CN111092052A - 集成电路器件和形成集成电路结构的方法 - Google Patents

集成电路器件和形成集成电路结构的方法 Download PDF

Info

Publication number
CN111092052A
CN111092052A CN201910870820.9A CN201910870820A CN111092052A CN 111092052 A CN111092052 A CN 111092052A CN 201910870820 A CN201910870820 A CN 201910870820A CN 111092052 A CN111092052 A CN 111092052A
Authority
CN
China
Prior art keywords
layer
silicon
forming
work function
over
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910870820.9A
Other languages
English (en)
Other versions
CN111092052B (zh
Inventor
王俊杰
黄国容
白岳青
杨怀德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN111092052A publication Critical patent/CN111092052A/zh
Application granted granted Critical
Publication of CN111092052B publication Critical patent/CN111092052B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种形成集成电路结构的方法包括：在晶圆上形成栅极电介质；在栅极电介质上方形成功函层；在功函层上方沉积覆盖层；将覆盖层浸泡在含硅气体中以形成含硅层；在形成含硅层之后，形成阻挡层；以及在阻挡层上方形成金属填充区。本发明的实施例还涉及集成电路器件。

Description

集成电路器件和形成集成电路结构的方法
技术领域
本发明的实施例涉及集成电路器件和形成集成电路结构的方法。
背景技术
金属氧化物半导体(MOS)器件是集成电路中的基本构建元件。现有的MOS器件通常具有使用诸如离子注入或热扩散的掺杂操作由掺杂有p型或n型杂质的多晶硅形成的栅电极。可以将栅电极的功函数调整到硅的带边缘。对于n型金属氧化物半导体(NMOS)器件，可以将功函数调节到接近硅的导带。对于P型金属氧化物半导体(PMOS)器件，可以将功函数调节到接近硅的价带。通过选择适当的杂质可以实现调整多晶硅栅电极的功函数。
具有多晶硅栅电极的MOS器件表现出载流子耗尽效应，这也称为多晶硅耗尽效应。当施加的电场从靠近栅极电介质的栅极区扫除载流子，从而形成耗尽层时，发生多晶硅耗尽效应。在n掺杂多晶硅层中，耗尽层包括离子化的非移动供体位点，其中在p掺杂多晶硅层中，耗尽层包括离子化的非移动受体位点。耗尽效应导致有效栅极电介质厚度的增加，使得更难以在半导体的表面处产生反型层。
可以通过形成金属栅电极来解决多晶硅耗尽问题，其中NMOS器件和PMOS器件中使用的金属栅极也可以具有带边缘功函数。因此，所得到的金属栅极包括多个层，以满足NMOS器件和PMOS器件的要求。
金属栅极的形成通常包括沉积金属层，然后进行化学机械抛光(CMP)以去除金属层的多余部分。金属层的剩余部分形成金属栅极。
发明内容
本发明的实施例提供了一种形成集成电路结构的方法，所述方法包括：在衬底上形成栅极电介质；在所述栅极电介质上方形成功函层；在所述功函层上方沉积覆盖层；将所述覆盖层浸泡在含硅气体中以形成含硅层；在形成所述含硅层之后，形成阻挡层；以及在所述阻挡层上方形成金属填充区。
本发明的另一实施例提供了一种形成集成电路结构的方法，所述方法包括：在半导体区上形成栅极电介质；在生产工具的第一工艺室中，在所述栅极电介质上方形成功函层；在所述生产工具的第二工艺室中，在所述功函层上方沉积第一氮化钛层；在所述生产工具的第二工艺室中，将所述第一氮化钛层浸泡在含硅气体中以形成含硅层，其中，所述含硅气体选自由SiH4、Si2H6、二氯硅烷(DCS)和它们的组合组成的组；将所述含硅层暴露于氧气以将一部分所述含硅层转化为含氧化硅层；在所述含氧化硅层上方形成第二氮化钛层；以及在所述第二氮化钛层上方形成金属填充区。
本发明的又一实施例提供了一种集成电路器件，包括：半导体区；和栅极堆叠件，位于所述半导体区上，所述栅极堆叠件包括：栅极电介质；功函层，位于所述栅极电介质上方；第一钛层，位于所述功函层上方；含硅层，位于所述第一钛层上方；第二钛层，位于所述含硅层上方；以及金属填充区，位于所述第二钛层上方。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图9B、图16和图17示出了根据一些实施例的鳍式场效应晶体管(FinFET)的形成中的中间阶段的立体图和截面图。
图10至图15示出了根据一些实施例的晶体管的栅极堆叠件的形成中的中间阶段的立体图和截面图。
图18示意性地示出了根据一些实施例的SiH4分子附接到TiN层，所述TiN层的形成以NH3循环结束。
图19示意性地示出了根据一些实施例的SiH4分子附接到TiN层，所述TiN层的形成以TiCl4循环结束。
图20示意性地示出了根据一些实施例的多晶TiN层中的扩散路径。
图21示出了根据一些实施例的晶体管的栅极堆叠件中的不同元件的分布。
图22示意性地示出了根据一些实施例的生产工具，其中栅极堆叠件中的多个层原位形成。
图23示出了根据一些实施例的附接到TiN层的表面的标准化量的硅，TiN层的形成以NH3循环或TiCl4循环结束。
图24示出了根据一些实施例的用于形成FinFET的工艺流程。
图25示出了根据一些实施例的用于在FinFET中形成栅极堆叠件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征不同的实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然这些仅是实例而不旨在限制。例如，元件的尺寸不限于所公开的范围或值，但可能依赖于工艺条件和/或器件所需的性能。此外，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。为了简单和清楚的目的，各个部件可以以不同的比例任意地绘制。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
根据各种实施例提供了具有替换栅极的晶体管及其形成方法。根据一些实施例示出了形成晶体管的中间阶段。讨论了一些实施例的一些变型。在各种视图和说明性实施例中，相同的附图标记用于表示相同的元件。在所示实施例中，鳍式场效应晶体管(FinFET)的形成用作解释本发明的概念的示例。平面晶体管也可以采用本发明的概念。根据本发明的一些实施例，在形成功函层和金属覆盖层之后，并且在沉积金属栅极的填充金属之前，执行含硅浸泡(处理)工艺。此外，可以在TiCl4脉冲和净化工艺之后执行含硅浸泡工艺，以提高浸泡工艺的效率。由含硅浸泡工艺产生的含硅混合层具有防止功函层中的金属向上扩散而对功函数产生不利影响的功能以及防止氧向下扩散到功函层中的功能。
图1至图9B、图16和图17示出了根据本发明的一些实施例的鳍式场效应晶体管(FinFET)的形成中的中间阶段的截面图和立体图。这些图中所示的工艺也在图24中所示的工艺流程200中示意性地反映。
在图1中，提供了衬底20。衬底20可以是半导体衬底，例如体半导体衬底、绝缘体上半导体(SOI)衬底等，其可以是掺杂的(例如，具有p型或n型掺杂剂)或未掺杂的。半导体衬底20可以是晶圆10的一部分，例如硅晶圆。通常，SOI衬底是在绝缘层上形成的半导体材料层。绝缘层可以是例如掩埋氧化物(BOX)层、氧化硅层等。绝缘层设置在衬底上，通常是硅或玻璃衬底。也可以使用其他衬底，例如多层或梯度衬底。在一些实施例中，半导体衬底20的半导体材料可以包括硅；锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。
进一步参考图1，阱区22形成在衬底20中。相应的工艺示出为图24中所示的工艺流程200中的工艺202。根据本发明的一些实施例，阱区22是通过将p型杂质(可以是硼、铟等)注入到衬底20中而形成的p型阱区。根据本发明的其他实施例，阱区22是通过将n型杂质(可以是磷、砷、锑等)注入到衬底20中而形成的n型阱区。所得到的阱区22可以延伸到衬底20的顶面。n型或p型杂质浓度可以等于或小于1018cm-3，诸如在约1017cm-3和约1018cm-3之间的范围内。
参考图2，隔离区24形成为从衬底20的顶面延伸到衬底20中。在下文中，隔离区24可选地称为浅沟槽隔离(STI)区。相应的工艺示出为图24中所示的工艺流程200中的工艺204。相邻STI区24之间的衬底20的部分称为半导体条26。为了形成STI区24，衬垫氧化物层28和硬掩模层30形成在半导体衬底20上，并且然后将衬垫氧化物层28和硬掩模层30图案化。衬垫氧化物层28可以是由氧化硅形成的薄膜。根据本发明的一些实施例，衬垫氧化物层28在热氧化工艺中形成，其中半导体衬底20的顶面层被氧化。衬垫氧化物层28用作半导体衬底20和硬掩模层30之间的粘附层。衬垫氧化物层28还可以用作蚀刻硬掩模层30的蚀刻停止层。根据本发明的一些实施例，例如，使用低压化学气相沉积(LPCVD)由氮化硅形成硬掩模层30。根据本发明的其他实施例，通过硅的热氮化或等离子体增强化学气相沉积(PECVD)形成硬掩模层30。在硬掩模层30上形成光刻胶(未示出)，然后将光刻胶图案化。然后使用图案化的光刻胶作为蚀刻掩模来图案化硬掩模层30，以形成如图2所示的硬掩模30。
接下来，图案化的硬掩模层30用作蚀刻掩模以蚀刻衬垫氧化物层28和衬底20，接着用介电材料填充衬底20中的所得沟槽。执行诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺以去除介电材料的多余部分，并且介电材料的剩余部分是STI区24。STI区24可以包括衬里电介质(未示出)，衬里电介质可以是通过衬底20的表面层的热氧化形成的热氧化物。衬里电介质也可以是使用以下方法形成的沉积的氧化硅层、氮化硅层等：例如，原子层沉积(ALD)、高密度等离子体化学气相沉积(HDPCVD)或化学气相沉积(CVD)。STI区24还可以包括衬里氧化物上方的介电材料，其中介电材料可以使用可流动化学气相沉积(FCVD)、旋涂等形成。根据一些实施例，衬里电介质上方的介电材料可以包括氧化硅。
硬掩模30的顶面和STI区24的顶面可以基本上彼此齐平。半导体条26位于相邻的STI区24之间。根据本发明的一些实施例，半导体条26是原始衬底20的一部分，因此半导体条26的材料与衬底20的材料相同。根据本发明的替代实施例，半导体条26是通过蚀刻STI区24之间的衬底20的部分以形成凹槽，并且执行外延以在凹槽中再生长另一半导体材料而形成的替换条。因此，半导体条26由不同于衬底20的半导体材料形成。根据一些实施例，半导体条26由硅锗、硅碳或III-V族化合物半导体材料形成。
参考图3，使STI区24凹陷，使得半导体条26的顶部比STI区24的剩余部分的顶面24A突出得更高，以形成突出的鳍36。相应的工艺示出为图24所示的工艺流程200中的工艺206。可以使用干蚀刻工艺执行蚀刻，其中例如HF3和NH3用作蚀刻气体。在蚀刻工艺期间，可以产生等离子体。也可以包括氩气。根据本发明的替代实施例，使用湿蚀刻工艺执行STI区24的凹陷。例如，蚀刻化学品可以包括HF。
在上面所示的实施例中，可以通过任何合适的方法图案化鳍。例如，可以使用一个或多个光刻工艺来图案化鳍，光刻工艺包括双重图案化或多重图案化工艺。通常，双重图案化或多重图案化工艺组合光刻和自对准工艺，允许创建具有例如比使用单个直接光刻工艺可获得的间距更小的间距的图案。例如，在一个实施例中，在衬底上方形成牺牲层并使用光刻工艺图案化牺牲层。使用自对准工艺在图案化的牺牲层旁边形成间隔件。然后去除牺牲层，然后可以使用剩余的间隔件或心轴来图案化鳍。
参考图4，伪栅极堆叠件38形成为在(突出的)鳍36的顶面和侧壁上延伸。相应的工艺示出为图24中所示的工艺流程200中的工艺208。伪栅极堆叠件38可以包括伪栅极电介质40和位于伪栅极电介质40上方的伪栅电极42。伪栅电极42可以例如使用多晶硅形成，并且也可以使用其他材料。每个伪栅极堆叠件38还可以包括位于伪栅电极42上方的一个(或多个)硬掩模层44。硬掩模层44可以由氮化硅、氧化硅、碳氮化硅或它们的多层形成。伪栅极堆叠件38可以跨过单个一个或多个突出的鳍36和/或STI区24。伪栅极堆叠件38也具有与突出鳍36的纵向方向垂直的纵向方向。
接下来，在伪栅极堆叠件38的侧壁上形成栅极间隔件46。相应的工艺也在图24中所示的工艺流程200中示出为工艺208。根据本发明的一些实施例，栅极间隔件46由诸如氮化硅、碳氮化硅等的介电材料形成，并且可以具有单层结构或包括多个介电层的多层结构。
然后执行蚀刻工艺以蚀刻未被伪栅极堆叠件38和栅极间隔件46覆盖的突出鳍36的部分，从而产生图5中所示的结构。相应的工艺示出为图24中所示的工艺流程200中的工艺210。凹陷可以是各向异性的，因此直接位于伪栅极堆叠件38和栅极间隔件46下面的鳍36的部分受到保护，并且不被蚀刻。根据一些实施例，凹陷的半导体条26的顶面可以低于STI区24的顶面24A。因此形成凹槽50。凹槽50包括位于伪栅极堆叠件38的相对侧上的部分，以及位于突出鳍36的剩余部分之间的部分。
接下来，通过在凹槽50中选择性地生长(通过外延)半导体材料来形成外延区(源极/漏极区)54，得到图6中的结构。相应的工艺示出为图24中所示的在工艺流程200中的工艺212。根据所得到的FinFET是p型FinFET还是n型FinFET，可以随着外延的进行原位掺杂p型或n型杂质。例如，当得到的FinFET是p型FinFET时，可以生长硅锗硼(SiGeB)或硅硼(SiB)。相反，当得到的FinFET是n型FinFET时，可以生长硅磷(SiP)或硅碳磷(SiCP)。根据本发明的替代实施例，外延区54包括III-V族化合物半导体，例如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、它们的组合或它们的多层。在用外延区54填充凹槽50之后，外延区54的进一步外延生长导致外延区54水平扩展，并且可以形成小平面。外延区54的进一步生长还可以使相邻的外延区54彼此合并。可以生成空隙(气隙)56。根据本发明的一些实施例，当外延区54的顶面仍然是波浪形时，或者当合并的外延区54的顶面变为平面时，可以完成外延区54的形成，这通过以下方式实现：如图6所示，在外延区54上进一步生长。
在外延步骤之后，可以用p型或n型杂质进一步注入外延区54以形成源极区和漏极区，源极区和漏极区也使用附图标记54表示。根据本发明的替代实施例，当在外延期间用p型或n型杂质原位掺杂外延区54时，跳过注入步骤。
图7A示出了在形成接触蚀刻停止层(CESL)58和层间电介质(ILD)60之后的结构的立体图。相应的工艺示出为图2中所示的工艺流程200中的工艺214。CESL 58可以由氧化硅、氮化硅、碳氮化硅等形成，并且可以使用CVD、ALD等形成。ILD 60可以包括使用例如FCVD、旋涂、CVD或其他沉积方法形成的介电材料。ILD 60可以由含氧介电材料形成，含氧介电材料可以是基于氧化硅的材料，例如正硅酸乙酯(TEOS)氧化物、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等。可以执行诸如CMP工艺或机械研磨工艺的平坦化工艺以使ILD 60、伪栅极堆叠件38和栅极间隔件46的顶面彼此平坦。
图7B示出图7A中的参考横截面7B-7B，其中示出伪栅极堆叠件38。接下来，蚀刻包括硬掩模层44、伪栅电极42和伪栅极电介质40的伪栅极堆叠件38，在栅极间隔件46之间形成沟槽62，如图8所示。相应的工艺示出为图24中所示的工艺流程200中的工艺216。突出的鳍36的顶面和侧壁暴露于沟槽62。接下来，如图9A和图9B所示，在沟槽62(图8)中形成替换栅极堆叠件72。相应的工艺示出为图24中所示的工艺流程200中的工艺218。图9B示出了图9A中的参考横截面9B-9B。替换栅极堆叠件72包括栅极电介质68和相应的栅电极70。
根据本发明的一些实施例，栅极电介质68包括界面层(IL)64作为其下部，如图9B所示。IL 64形成在突出的鳍36的暴露表面上。IL 64可以包括氧化物层，例如氧化硅层，通过突出的鳍36的热氧化、化学氧化工艺或沉积工艺形成。栅极电介质68还可以包括在IL 64上形成的高k介电层66。高k介电层66包括高k介电材料，例如氧化铪、氧化镧、氧化铝、氧化锆等。高k介电材料的介电常数(k值)高于3.9，并且可以高于约7.0，有时高达21.0或更高。高k介电层66位于IL 64上面并且可以接触IL 64。高k介电层66形成为共形层，并且在突出的鳍36的侧壁以及栅极间隔件46的顶面和侧壁上延伸。根据本发明的一些实施例，使用ALD、CVD、PECVD、分子束沉积(MBD)等形成高k介电层66。
进一步参考图9B，栅电极70形成在栅极电介质68上。栅电极70可以包括多个堆叠层74以及填充金属区76，堆叠层74可以形成为共形层，填充金属区76填充未由多层堆叠层74填充的沟槽的剩余部分。堆叠层74可以包括阻挡层、位于阻挡层上方的功函层以及位于功函层上方的一个或多个金属覆盖层。参照图10至15讨论堆叠层74的详细结构和形成方法。
图9B示意性地示出了区78，其中包括鳍36的一部分、栅极电介质68的一部分、堆叠层74的一部分和填充金属区76的一部分。图10至图15示出了根据一些实施例的延伸到区78中的部件的形成。相应的工艺示出为如图25中所示的工艺流程300。如图24中所示的工艺218通过工艺流程300来实现。
参考图10，形成包括IL 64和高k介电层的栅极电介质68。相应的工艺示出为图25中所示的工艺流程300中的工艺302。IL 64形成在突出的鳍36上。在IL 64上方形成高k介电层66。根据一些实施例，粘合层(也是也是扩散阻挡层)118形成在高k介电层66上。相应的工艺示出为图25所示的工艺流程300中的工艺304。粘合层118可以由TiN或氮化钛硅(TSN)形成。可以使用ALD或CVD形成TiN层，并且TSN层可以包括交替沉积的TiN层和SiN层，例如使用ALD形成TiN层和SiN层。由于TiN层和SiN层非常薄，因此这些层可能无法彼此区分，因此称为TSN层。
功函层120形成在粘合层118上方。相应的工艺示出为图25中所示的工艺流程300中的工艺306。功函层120确定栅极的功函数，并且包括至少一层，或由不同材料形成的多个层。根据相应的FinFET是n型FinFET还是p型FinFET来选择功函层的材料。例如，当FinFET是n型FinFET时，功函层120可以包括位于TaN层上的钛铝(TiAl)层。当FinFET是p型FinFET时，功函层120可以包括TaN层、位于TaN层上方的TiN层，并且可以包括或不包括位于TiN层上方的TiAl层。应理解，功函层可以包括不同的材料，这些材料也是可预期的。
根据本发明的一些实施例，在功函层120上方形成覆盖层122，如图11所示。相应的工艺示出为图25中所示的工艺流程300中的工艺308。根据一些实施例，覆盖层122可以由TiN形成，并且可以使用诸如TaN的其他材料。根据一些实施例，使用ALD形成覆盖层122。覆盖层122的厚度可以在约10nm和约50nm之间的范围内。
根据一些实施例，覆盖层122的形成包括将TiCl4气体脉冲进入相应的工艺ALD室(例如，图22中的室404)，以及净化TiCl4。相应的工艺分别示出为图25所示的工艺流程300中的工艺310和312。脉冲持续时间(TiCl4与晶圆10接触的时间)可以在约0.1秒至约10秒的范围内。TiCl4的流量可以在约50sccm和约150sccm之间的范围内。在整个说明书中，TiCl4的脉冲和净化统称为TiCl4循环。
接下来，将氨(NH3)脉冲到ALD室中，然后净化。相应的工艺分别示出为图25所示的工艺流程300中的工艺314和316。脉冲持续时间(NH3与晶圆10接触的时间)可以在约0.1秒至约10秒的范围内。在整个说明书中，NH3的脉冲和净化统称为NH3循环。NH3的流量可以在约50sccm和约100sccm之间的范围内。在形成覆盖层122期间，晶圆10的温度在约400℃至约600℃的范围内。TiCl4和NH3的每种的压力可以在约4托至约20托之间的范围内。
TiCl4循环和NH3循环组合导致形成TiN(原子)层，因此TiCl4循环和NH3循环组合称为ALD环。覆盖层122的形成可以包括多个ALD环，并且工艺流程300包括回到工艺310的环。覆盖层122的所得厚度可以在约10nm和约50nm之间的范围内。
根据一些实施例，覆盖层122的形成以NH3循环结束，通过以工艺316结束以进行到图25中的工艺322来指示。根据本发明的其他实施例，覆盖层122的形成以TiCl4循环结束，TiCl4循环包括TiCl4的脉冲和净化，如图25所示的工艺流程300中的工艺318和320所示。如将在后面的段落中讨论的，以TiCl4循环结束覆盖层122的形成导致改善的结果。当以TiCl4循环结束覆盖层122的形成时，最终的TiCl4脉冲的第二脉冲持续时间(图25中的工艺318)可以延长到比先前的ALD循环中的TiCl4脉冲的第一持续时间(图25中的工艺310)更长。例如，最终的TiCl4脉冲的脉冲持续时间可以在约0.1秒和约10秒之间的范围内。第二持续时间与第一持续时间的比率大于1.0，并且可以在约2.0和约5.0之间的范围内。
在最终的TiCl4脉冲318期间，晶圆10也被加热，例如，加热到约400℃和约600℃之间的温度。根据一些实施例，不产生等离子体。最终的TiCl4脉冲导致所得分子(例如TixCly分子，其中x和y为整数)暴露并连接到下面的覆盖层122。最终的TiCl4脉冲工艺用于改善覆盖层122与随后提供的硅的接合，如后续段落所讨论的。
图12示出了使用含硅气体的浸泡工艺(由箭头123表示)，含硅气体可以是SiH4、Si2H6、二氯硅烷(DCS)等或它们的组合。相应的工艺示出为图25所示的工艺流程300中的工艺322。在含硅气体浸泡期间，将晶圆10加热至例如约400℃至约600℃之间的范围内的温度。含硅气体的流量可以在约300sccm和约500sccm之间的范围内。含硅气体的压力可以在约4托至约20托之间的范围内。根据一些实施例，不产生等离子体。浸泡持续时间可以在约180秒至约600秒的范围内。
图12示意性地示出了由于含硅气体浸泡而形成硅层124。根据本发明的一些实施例，硅层124的厚度在约1埃至约15埃的范围内，而厚度可以更大或更小。
功函层120的形成、覆盖层122的形成、最终的TiCl4脉冲工艺和含硅气体浸泡工艺可以在相同的真空环境中原位执行，从而在这些工艺之间不发生真空破坏。这些工艺连续进行，并且可以在具有相同真空环境的同一平台中的不同工艺室中执行。例如，图22示出了生产工具400，其包括负载锁402和多个工艺室，工艺室包括共享相同真空环境的真空室404和406。根据一些实施例，功函层120在工艺室404中沉积，而覆盖层122的形成、最终的TiCl4脉冲工艺和含硅气体浸泡工艺在工艺室406中执行，工艺室406被设计用于ALD工艺。
图18示意性地示出了覆盖层122的顶面，覆盖层122以NH3循环结束。在覆盖层122的表面上存在一些TiClx分子。TiClx分子具有悬空键，悬空键可用于硅原子附接。然而，由于该工艺以NH3循环结束，因此大部分TiClx分子可以被NH3分子终止(示出为不具有TiClx的空白)，留下有限数量的悬空键。因此可以附接的硅原子的量是有限的。
图19示意性地示出了覆盖层122的顶面，覆盖层122以TiCl4循环结束。结果，更多的TiClx分子位于覆盖层122的表面上。与以NH3循环结束的覆盖层形成相比，可以附接的硅原子的量因此增加。
图23示出了结果的比较，其中附接至覆盖层的表面的标准化量的硅示出为浸泡时间的函数。实心圆是附接到使用NH3最终循环形成的覆盖层的硅的量的结果。空心圆和正方形是附接到使用TiCl4最终循环形成的覆盖层的硅的量的结果。数据显示，通过使用TiCl4最终循环，可以附接更多的硅。
返回参考图13，在含硅气体浸泡之后，可以执行真空破坏，并且硅层124暴露于空气。相应的工艺示出为图25所示的工艺流程300中的工艺324。将硅层124暴露于空气(洁净空气，其在室温下，例如，在约20℃和约25℃之间的范围内)，硅层124(图12)被氧化以形成含硅层126，如图13所示。
在硅层124的暴露中，空气中的氧与硅层124反应以形成氧化硅层126C。氧化硅层126C富含氧和硅，并且还可以包括其他元素，例如氮和钛。因此，氧化硅层126C实际上是这些元素的混合层，并且在下文中也称为氧化硅混合层126C。氧化硅混合层126C的厚度可以在约0.1nm和约10nm之间的范围内。另一方面，由于硅层124接触包括TiN的覆盖层122，部分地由于含硅气体浸泡中的高温，所以可以形成氮化硅混合层126A。氮化硅混合层126A富含硅和氮，并且还可以包括其他元素，例如氧和钛。来自功函层120的一部分铝也可以扩散到氮化硅混合层126A中。氮化硅混合层126A的厚度可以在约0.1nm和约10nm之间的范围内。
取决于硅层124(图12)的厚度，可以存在或不存在硅混合层126B，硅混合层126B富含硅并且可以包含其他元素，例如氮、氧、钛等，并且可以含有少量铝。下文将氮化硅混合层126A、硅混合层126B和氧化硅混合层126C组合称为含硅层126。含硅层126的厚度可以在约0.1nm和约1.5nm之间的范围内。
尽管非常薄，但含硅层126具有阻挡氧气向下扩散而氧化功函层120的功能，并且阻挡金属(例如铝)扩散出功函层120以引起相应的FinFET的阈值电压偏移。图20示意性地示出了覆盖层122的多晶粒结构，多晶粒结构包括多个晶粒。氧和金属原子可以通过覆盖层122的晶粒之间的路径扩散。位于覆盖层122上方的含硅层126(图20中未示出)用作阻止阻挡件以阻挡扩散。
返回参考图13，可以理解，由于元素的扩散，在诸如氮化硅混合层126A、硅混合层126B和氧化硅混合层126C的子层之间可能没有清晰的边界。图21示出了作为距离Z(图13)的函数的一些元素的量，距离Z是从图13中的突出鳍36的顶面测量的。X轴(图21)表示距离Z，并且Y轴表示元素氧(O)、氮(N)、铝(Al)、钛(Ti)和铪(Hf)的标准化量。简要标记突出鳍36(包括Si)、高k介电层66(包括Hf)、功函层120(包括TiAl)、覆盖层122(包括TiN)、含硅层126和阻挡层TiN(在后续步骤中形成的)。将如图21所示的结果与形成工艺不包括含硅气体浸泡工艺的样品(未示出)的结果进行比较，发现氧气扩散到覆盖层122以及铝通过含硅层126的扩散减少。
图14示出了阻挡层128的形成。相应的工艺示出为图25中所示的工艺流程300中的工艺326。阻挡层128的形成方法、材料、厚度等可以选自用于形成覆盖层122的候选方法、候选材料、候选厚度等。因此不再重复细节。例如，阻挡层128可以由TiN形成，可以使用ALD形成。扩散阻挡层118、功函层120、含硅层126和阻挡层128组合对应于图9B中的堆叠层74。
图15示出了填充金属区76的沉积。相应的工艺示出为图25中所示的工艺流程300中的工艺328。根据一些实施例，填充金属区76由钨或钴形成，可以使用化学气相沉积形成。根据一些实施例，WF6和SiH4用作沉积钨的工艺气体。在形成填充金属区76之后，可以执行平坦化工艺以去除沉积层的多余部分，如图15所示，从而产生如图9A和图9B所示的栅极堆叠件72。相应的平坦化工艺示出为图25中所示的工艺流程300中的工艺330。
图16示出了根据一些实施例的硬掩模80的形成。相应的工艺示出为图24中所示的工艺流程200中的工艺220。硬掩模80的形成可以包括执行蚀刻工艺以使栅极堆叠件72凹陷，使得在栅极间隔件46之间形成凹槽，用介电材料填充凹槽，以及然后执行平坦化工艺，例如CMP工艺或机械研磨工艺，以去除介电材料的多余部分。硬掩模80可以由氮化硅、氮氧化硅、碳氮氧化硅等形成。
图17示出了源极/漏极接触插塞82的形成。相应的工艺示出为图24中所示的工艺流程200中的工艺222。源极/漏极接触插塞82的形成包括蚀刻ILD 60以暴露下面的CESL 58的部分，然后蚀刻CESL 58的暴露部分以露出源/漏极区54。在随后的工艺中，沉积金属层(例如Ti层)并延伸到接触开口中。可以形成金属氮化物覆盖层。然后执行退火工艺以使金属层与源极/漏极区54的顶部反应以形成硅化物区84，如图17所示。接下来，保留先前形成的金属氮化物层而不去除，或者去除先前形成的金属氮化物层，然后沉积新的金属氮化物层(例如氮化钛层)。然后将诸如钨、钴等的填充金属材料填充到接触开口中，接着进行平坦化以去除多余的材料，从而产生源极/漏极接触插塞82。栅极接触插塞(未示出)也形成为穿透每个硬掩模80的一部分以接触栅电极70。由此形成FinFET 86，FinFET 86可以作为一个FinFET并联连接。
本发明的实施例具有一些有利特征。通过含硅气体浸泡工艺，在功函层上方形成含硅层。含硅层是薄的，并且是包括富含氧化硅的部分和富含氮化硅的部分的混合层。含硅层有效地防止氧气向下渗透到达功函层，因此可以防止功函层的氧化。此外，含硅层可以防止功函层中的金属向上扩散，因此可以帮助保持功函层的组成稳定，并且防止所得FinFET的阈值电压的偏移。结果，减小了阈值累积问题，即不同区(例如晶体管密集区和晶体管稀疏区)中的晶体管之间的阈值电压差的扩大。
根据本发明的一些实施例，一种形成集成电路结构的方法包括：在晶圆上形成栅极电介质；在栅极电介质上方形成功函层；在功函层上方沉积覆盖层；将覆盖层浸泡在含硅气体中以形成含硅层；在形成含硅层之后，形成阻挡层；在阻挡层上方形成金属填充区。在一个实施例中，沉积覆盖层包括多个循环，每个循环包括：TiCl4循环，包括脉冲和净化TiCl4；和NH3循环，包括脉冲和净化NH3，并且用额外的TiCl4循环结束沉积覆盖层。在一个实施例中，沉积覆盖层包括多个循环，每个循环包括：TiCl4循环，包括脉冲和净化TiCl4；和NH3循环，包括脉冲和净化NH3，并且用额外的NH3循环结束沉积覆盖层。在一个实施例中，在浸泡覆盖层时，将覆盖层浸泡在含硅气体中，所述含硅气体包含选自SiH4、Si2H6、二氯硅烷及它们的组合组成的组的气体。在一个实施例中，在浸泡工艺中，将晶圆加热至约400℃至约600℃之间的范围内的温度。在一个实施例中，该方法还包括真空破坏以将含硅层暴露于空气。在一个实施例中，在相同的真空环境中原位执行形成功函层、沉积覆盖层和浸泡覆盖层。在一个实施例中，沉积覆盖层和浸泡覆盖层是在相同的工艺室中进行的。在一个实施例中，该方法还包括在半导体鳍的侧壁和顶面上形成伪栅极堆叠件；在伪栅极堆叠件的相对侧上形成栅极间隔件；形成层间电介质，其中伪栅极堆叠件和栅极间隔件位于层间电介质中；以及去除伪栅极堆叠件以在堆叠间隔件之间形成沟槽，其中栅极堆叠件形成为延伸到沟槽中。
根据本发明的一些实施例，一种形成集成电路结构的方法包括：在半导体区上形成栅极电介质；在生产工具的第一工艺室中，在栅极电介质上方形成功函层；在生产工具的第二工艺室中，在功函层上方沉积第一氮化钛层；在所述生产工具的第二工艺室中，将所述第一氮化钛层浸泡在含硅气体中以形成含硅层，其中所述含硅气体选自由SiH4、Si2H6、二氯硅烷和它们的组合组成的组；将含硅层暴露于氧气以将一部分含硅层转化为含氧化硅层；在含氧化硅层上方形成第二氮化钛层；以及在第二氮化钛层上方形成金属填充区。在一个实施例中，第一工艺室和第二工艺室共享相同的真空环境。在一个实施例中，浸泡第一氮化钛层持续约180秒至约600秒的一段时间。在一个实施例中，将含硅层暴露于氧气包括将含硅层暴露于空气。在一个实施例中，将含硅层暴露于氧气在室温下进行。
根据本发明的一些实施例，集成电路包括：半导体区；和栅极堆叠件，位于半导体区上。栅极堆叠件包括栅极电介质；功函层，位于栅极电介质上方；第一钛层，位于功函层上方；含硅层，位于第一钛层上方；第二钛层，位于含硅层上方；以及金属填充区，位于第二钛层上方。在一个实施例中，含硅层包含硅、氧、氮和钛。在一个实施例中，含硅层包括氧化硅。在一个实施例中，含硅层包括氮化硅。在一个实施例中，功函层都包括TiAl。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并且不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成集成电路结构的方法，所述方法包括：
在衬底上形成栅极电介质；
在所述栅极电介质上方形成功函层；
在所述功函层上方沉积覆盖层；
将所述覆盖层浸泡在含硅气体中以形成含硅层；
在形成所述含硅层之后，形成阻挡层；以及
在所述阻挡层上方形成金属填充区。
2.根据权利要求1所述的方法，其中，沉积所述覆盖层包括多个循环，每个所述循环包括：
TiCl4循环，包括脉冲和净化TiCl4；和
NH3循环，包括脉冲和净化NH3，并且用额外的TiCl4循环结束沉积所述覆盖层。
3.根据权利要求1所述的方法，其中，沉积所述覆盖层包括多个循环，每个所述循环包括：
TiCl4循环，包括脉冲和净化TiCl4；和
NH3循环，包括脉冲和净化NH3，并且除了多个循环中的NH3循环，用额外的NH3循环结束沉积所述覆盖层。
4.根据权利要求1所述的方法，其中，在浸泡所述覆盖层时，将所述覆盖层浸泡在所述含硅气体中，所述含硅气体包含选自SiH4、Si2H6、二氯硅烷(DCS)及它们的组合组成的组的气体。
5.根据权利要求1所述的方法，其中，在浸泡所述覆盖层时，将衬底加热至400℃至600℃之间的范围内的温度。
6.根据权利要求1所述的方法，还包括真空破坏以将所述含硅层暴露于空气。
7.根据权利要求1所述的方法，其中，在相同的真空环境中原位执行形成所述功函层、沉积所述覆盖层和浸泡所述覆盖层。
8.根据权利要求7所述的方法，其中，沉积所述覆盖层和浸泡所述覆盖层是在相同的工艺室中进行的。
9.一种形成集成电路结构的方法，所述方法包括：
在半导体区上形成栅极电介质；
在生产工具的第一工艺室中，在所述栅极电介质上方形成功函层；
在所述生产工具的第二工艺室中，在所述功函层上方沉积第一氮化钛层；
在所述生产工具的第二工艺室中，将所述第一氮化钛层浸泡在含硅气体中以形成含硅层，其中，所述含硅气体选自由SiH4、Si2H6、二氯硅烷(DCS)和它们的组合组成的组；
将所述含硅层暴露于氧气以将一部分所述含硅层转化为含氧化硅层；
在所述含氧化硅层上方形成第二氮化钛层；以及
在所述第二氮化钛层上方形成金属填充区。
10.一种集成电路器件，包括：
半导体区；和
栅极堆叠件，位于所述半导体区上，所述栅极堆叠件包括：
栅极电介质；
功函层，位于所述栅极电介质上方；
第一钛层，位于所述功函层上方；
含硅层，位于所述第一钛层上方；
第二钛层，位于所述含硅层上方；以及
金属填充区，位于所述第二钛层上方。
CN201910870820.9A 2018-10-23 2019-09-16 集成电路器件和形成集成电路结构的方法 Active CN111092052B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862749195P 2018-10-23 2018-10-23
US62/749,195 2018-10-23
US16/290,118 US11587791B2 (en) 2018-10-23 2019-03-01 Silicon intermixing layer for blocking diffusion
US16/290,118 2019-03-01

Publications (2)

Publication Number Publication Date
CN111092052A true CN111092052A (zh) 2020-05-01
CN111092052B CN111092052B (zh) 2023-03-28

Family

ID=70280955

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910870820.9A Active CN111092052B (zh) 2018-10-23 2019-09-16 集成电路器件和形成集成电路结构的方法

Country Status (5)

Country Link
US (2) US11587791B2 (zh)
KR (1) KR102272121B1 (zh)
CN (1) CN111092052B (zh)
DE (1) DE102019117322A1 (zh)
TW (1) TWI737007B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023102679A1 (zh) * 2021-12-06 2023-06-15 华为技术有限公司 半导体芯片、其制备方法及电子设备

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10943829B2 (en) * 2018-10-23 2021-03-09 Taiwan Semiconductor Manufacturing Company, Ltd. Slot contacts and method forming same
US11658216B2 (en) 2021-01-14 2023-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for metal gate boundary isolation
US20220293422A1 (en) * 2021-03-11 2022-09-15 Changxin Memory Technologies, Inc. Semiconductor structure and preparation method for semiconductor structure
US20230020099A1 (en) * 2021-07-15 2023-01-19 Taiwan Semiconductor Manufacturing Co., Ltd. NFET with Aluminum-Free Work-Function Layer and Method Forming Same

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579006A (zh) * 2012-07-23 2014-02-12 南亚科技股份有限公司 具有垂直栅极的半导体元件及其制造方法
US20140239419A1 (en) * 2013-02-27 2014-08-28 United Microelectronics Corp. Semiconductor device and method of manufacturing the same
US20160027639A1 (en) * 2011-08-01 2016-01-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a semiconductor device comprising titanium silicon oxynitride
CN105810735A (zh) * 2015-01-20 2016-07-27 台湾积体电路制造股份有限公司 金属栅极及其制造方法
CN107017290A (zh) * 2015-10-20 2017-08-04 台湾积体电路制造股份有限公司 栅极结构、半导体器件以及形成半导体器件的方法
CN107689396A (zh) * 2016-08-03 2018-02-13 台湾积体电路制造股份有限公司 晶体管及其形成方法
CN107993933A (zh) * 2011-07-28 2018-05-04 台湾积体电路制造股份有限公司 半导体器件及其制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7135408B2 (en) * 2002-10-30 2006-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Metal barrier integrity via use of a novel two step PVD-ALD deposition procedure
JP2007243105A (ja) 2006-03-13 2007-09-20 Sony Corp 半導体装置およびその製造方法
US8114722B2 (en) * 2007-08-24 2012-02-14 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
KR101211043B1 (ko) * 2010-04-05 2012-12-12 에스케이하이닉스 주식회사 매립게이트를 구비한 반도체 장치 제조방법
KR102271202B1 (ko) 2013-09-27 2021-06-30 어플라이드 머티어리얼스, 인코포레이티드 심리스 코발트 갭-충전을 가능하게 하는 방법
CN105097474B (zh) 2014-05-09 2018-03-06 中国科学院微电子研究所 一种半导体器件的制造方法
JP2016058676A (ja) 2014-09-12 2016-04-21 株式会社日立国際電気 半導体装置の製造方法、基板処理装置およびプログラム
US9425317B1 (en) 2015-02-26 2016-08-23 Taiwan Semiconductor Manufacturing Co., Ltd Fin field effect transistor (FinFET) device structure with Ge-doped inter-layer dielectric (ILD) structure
US9941111B2 (en) * 2015-05-29 2018-04-10 Infineon Technologies Ag Method for processing a semiconductor layer, method for processing a silicon substrate, and method for processing a silicon layer
US11282938B2 (en) * 2018-09-28 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Capping layers in metal gates of transistors

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107993933A (zh) * 2011-07-28 2018-05-04 台湾积体电路制造股份有限公司 半导体器件及其制造方法
US20160027639A1 (en) * 2011-08-01 2016-01-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a semiconductor device comprising titanium silicon oxynitride
CN103579006A (zh) * 2012-07-23 2014-02-12 南亚科技股份有限公司 具有垂直栅极的半导体元件及其制造方法
US20140239419A1 (en) * 2013-02-27 2014-08-28 United Microelectronics Corp. Semiconductor device and method of manufacturing the same
CN105810735A (zh) * 2015-01-20 2016-07-27 台湾积体电路制造股份有限公司 金属栅极及其制造方法
CN107017290A (zh) * 2015-10-20 2017-08-04 台湾积体电路制造股份有限公司 栅极结构、半导体器件以及形成半导体器件的方法
CN107689396A (zh) * 2016-08-03 2018-02-13 台湾积体电路制造股份有限公司 晶体管及其形成方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023102679A1 (zh) * 2021-12-06 2023-06-15 华为技术有限公司 半导体芯片、其制备方法及电子设备

Also Published As

Publication number Publication date
US20200126797A1 (en) 2020-04-23
DE102019117322A1 (de) 2020-04-23
CN111092052B (zh) 2023-03-28
US20230116357A1 (en) 2023-04-13
KR20200047295A (ko) 2020-05-07
KR102272121B1 (ko) 2021-07-06
TW202034378A (zh) 2020-09-16
US11587791B2 (en) 2023-02-21
TWI737007B (zh) 2021-08-21

Similar Documents

Publication Publication Date Title
US11282938B2 (en) Capping layers in metal gates of transistors
CN111092052B (zh) 集成电路器件和形成集成电路结构的方法
US11742395B2 (en) Selective etching to increase threshold voltage spread
KR102495788B1 (ko) 콘택트 플러그의 상향식 형성
CN111834297A (zh) 集成电路器件及用于制作集成电路器件的方法
US11342188B2 (en) Methods for doping high-k metal gates for tuning threshold voltages
KR102267889B1 (ko) 트랜지스터의 금속 게이트에서의 캡핑 층
US20220181463A1 (en) Transistors with Reduced Defect and Methods of Forming Same
US20220359193A1 (en) Controlling Threshold Voltages Through Blocking Layers
US20240063061A1 (en) In-situ formation of metal gate modulators
US11532509B2 (en) Selective hybrid capping layer for metal gates of transistors
US20230253256A1 (en) Multiple Threshold Voltage Implementation Through Lanthanum Incorporation
US20220336640A1 (en) Undoped Region Under Source/Drain And Method Forming Same
US20230238241A1 (en) Method Forming Gate Stacks Adopting Thin Silicon Cap
US20220367261A1 (en) Selective Hybrid Capping Layer for Metal Gates of Transistors
US20230034854A1 (en) Semiconductor structure and method for forming the same
CN113284950A (zh) 形成半导体器件的方法及半导体器件

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant