CN107689396A - 晶体管及其形成方法 - Google Patents

晶体管及其形成方法 Download PDF

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CN107689396A
CN107689396A CN201710475469.4A CN201710475469A CN107689396A CN 107689396 A CN107689396 A CN 107689396A CN 201710475469 A CN201710475469 A CN 201710475469A CN 107689396 A CN107689396 A CN 107689396A
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layer
metal
opening
metal level
dielectric
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CN107689396B (zh
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张哲诚
林志翰
曾鸿辉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

方法包括在半导体区上方形成伪栅极堆叠件，在与伪栅极堆叠件相同的层级处形成介电层，去除伪栅极堆叠件以在介电层中形成开口，填充延伸至开口内的金属层，以及回蚀刻金属层，金属层的剩余部分的边缘低于介电层的顶面。开口填充有导电材料，并且导电材料位于金属层上方。金属层和导电材料组合形成替换栅极。在替换栅极的相对两侧上形成源极区和漏极区。本发明的实施例还涉及晶体管及其形成方法。

Description

晶体管及其形成方法
技术领域
本发明的实施例涉及晶体管及其形成方法。
背景技术
金属氧化物半导体(MOS)器件是集成电路中的基本构建元件。现有的MOS器件通常具有由使用诸如离子注入或热扩散的掺杂操作掺杂有p型或n型杂质的多晶硅形成的栅电极。栅电极的功函数可以调整至硅的带边缘。对于n型金属氧化物半导体(NMOS)器件，功函数可以调整至接近硅的导电带。对于p型金属氧化物半导体(PMOS)器件，功函数可以调整至接近硅的价带。可以通过选择适当的杂质实现多晶硅栅电极的功函数的调整。
具有多晶硅栅电极的MOS器件展现出载流子耗尽效应，其也称为多晶硅耗尽效应。当施加的电场从接近栅极电介质的栅极区清除载流子时，发生多晶硅耗尽效应，形成耗尽层。在n掺杂的多晶硅层中，耗尽层包括离子化的非移动供体位点，其中，在p掺杂的多晶硅层中，耗尽层包括离子化的非移动受体位点。耗尽效应导致有效栅极电介质厚度的增加，使得在半导体的表面处更加难以产生反转层。
可以通过形成金属栅电极解决多晶硅耗尽问题，其中，在NMOS器件和PMOS器件中使用的金属栅极也可以具有带边缘功函数。因此，产生的金属栅极包括多个层以适应NMOS器件和PMOS器件的需求。
发明内容
本发明的实施例提供了一种形成晶体管的方法，包括：在半导体区上方形成伪栅极堆叠件；在与所述伪栅极堆叠件相同的层级处形成介电层；去除所述伪栅极堆叠件以在所述介电层中形成开口；填充延伸至所述开口内的金属层；回蚀刻所述金属层，其中，所述金属层的剩余部分的边缘低于所述介电层的顶面；用导电材料填充所述开口，其中，所述导电材料位于所述金属层上方，其中，所述金属层和所述导电材料组合形成替换栅极；以及形成源极区和漏极区，其中，所述源极区和漏极区位于所述替换栅极的相对两侧上。
本发明的另一实施例提供了一种形成晶体管的方法，包括：在半导体区上形成伪栅极堆叠件；在所述伪栅极堆叠件的侧壁上形成栅极间隔件；在所述伪栅极堆叠件的相对两侧上形成源极区和漏极区；形成层间电介质以覆盖所述源极区和漏极区；去除所述伪栅极堆叠件以形成开口；形成延伸至所述开口内的栅极介电层；在所述栅极介电层上方形成含金属层，其中，所述含金属层包括位于所述开口中的第一部分和位于所述开口外部的第二部分；去除所述第二部分并且回蚀刻所述含金属层的所述第一部分；以及用导电材料填充剩余的开口。
本发明的又一实施例提供了一种晶体管器件，包括：栅极间隔件；位于所述栅极间隔件之间的开口；栅极电介质，内衬于所述开口；含金属层，位于所述栅极电介质的底部上方，其中，所述含金属层包括位于所述开口的底部处的底部和连接至所述底部的端部的侧壁部，其中，所述侧壁部的顶部边缘低于所述栅极间隔件的顶部边缘；以及导电材料，位于所述含金属层上方，其中，所述导电材料位于所述开口中，并且所述导电材料的顶面高于所述含金属层的所述侧壁部的顶部边缘。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图17示出了根据一些实施例的在鳍式场效应晶体管(FinFET)的形成中的中间阶段的截面图和立体图。
图 18至图20示出了根据一些实施例的FinEFT的截面图，其中从FinFET的沟道长度方向获得截面图。
图21A、图21B、图21C和图21D是根据一些实施例的FinEFT的截面图，其中金属层的顶端具有不同的高度和形状。
图22示出了根据一些实施例的用于形成FinFET的工艺的流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作相应的解释。
根据各个示例性实施例提供了晶体管及其形成方法。根据一些实施例示出了形成晶体管的中间阶段。讨论了一些实施例的一些变化。贯穿各个视图和示例性实施例，相同的参考数字用于表示相同的元件。在示出的示例性实施例中，鳍式场效应晶体管(FinFET)的形成使用实例来解释本发明的实施例。平面晶体管可以采用本发明的构思。
图1至图17示出了根据本发明的一些实施例的在FinFET的形成中的中间阶段的截面图和立体图。图1至图17中示出的步骤也在图22中示出的工艺流程中示意性地反映。
图1示出了初始结构的立体图。初始结构包括晶圆100，晶圆100还包括衬底20。衬底20可以是半导体衬底，其可以进一步为硅衬底、硅锗衬底或由其他半导体材料形成的衬底。衬底20可以掺杂有p型或n型杂质。诸如浅沟槽隔离(STI)区的隔离区22可以形成为从衬底20的顶面延伸至衬底20内，其中，衬底20的顶面是晶圆100的主表面100A。位于相邻的STI区22之间的衬底20的部分称为半导体条24。根据一些示例性实施例，半导体条24的顶面和STI区22的顶面可以彼此基本齐平。
STI区22可以包括衬垫氧化物(未示出)。衬垫氧化物可以由通过衬底20的表面层的热氧化形成的热氧化物形成。衬垫氧化物也可以是使用例如原子层沉积(ALD)、高密度等离子体化学汽相沉积(HDPCVD)或化学汽相沉积(CVD)形成的沉积的氧化硅层。STI区22也可以包括位于衬垫氧化物上方的介电材料，其中，该介电材料可以由可流动化学汽相沉积(FCVD)、旋涂等形成。
参照图2，使STI区22凹进，使得半导体条24的顶部突出为高于STI区22的顶面以形成突出鳍24’。相应的步骤示出为图22中示出的工艺流程中的步骤202。可以使用干蚀刻工艺实施蚀刻，其中，HF3和NH3用作蚀刻气体。在蚀刻工艺期间，可以生成等离子体。也可以包括氩气。根据本发明的可选实施例，使用湿蚀刻工艺实施STI区22的凹进。例如，蚀刻化学物可以包括稀释的HF。
参照图3，在突出鳍24’的顶面和侧壁上形成伪栅极堆叠件30。相应的步骤示出为图22中示出的工艺流程中的步骤204。伪栅极堆叠件30可以包括栅极电介质32和位于栅极电介质32上方的伪栅电极34。例如，可以使用多晶硅形成伪栅电极34，并且也可以使用其他材料。伪栅极堆叠件30也可以包括位于伪栅电极34上方的一个(或多个)硬掩模层36。硬掩模层36可以由氮化硅、碳氮化硅等形成。伪栅极堆叠件30可以横跨单个或多个突出鳍24’和/或STI区22。伪栅极堆叠件30也可以具有与突出鳍24’的纵向方向基本上垂直的纵向方向。
接下来，在伪栅极堆叠件30的侧壁上形成栅极间隔件38。根据本发明的一些实施例，栅极间隔件38由诸如碳氮化硅(SiCN)、氮化硅等的介电材料形成，并且可以具有单层结构或包括多个介电层的多层结构。
然后实施蚀刻步骤(此后称为源极/漏极凹进)以蚀刻未被伪栅极堆叠件30和栅极间隔件38覆盖的突出鳍24’的部分，产生图4中示出的结构。凹进可以是各向异性的，并且因此直接位于伪栅极堆叠件30和栅极间隔件38下方的鳍24’的部分受到保护并且不被蚀刻。根据一些实施例，凹进的半导体条24的顶面24A可以低于STI区22的顶面22A。因此在STI区22之间形成凹槽40。凹槽40位于伪栅极堆叠件30的相对两侧上。
接下来，通过在凹槽40中选择性地生长半导体材料形成外延区(源极/漏极区)，产生图5中的结构。相应的步骤示出为图22中示出的工艺流程中的步骤206。根据一些示例性实施例，外延区42包括硅锗或硅。取决于产生的FinFET是p型FinFET还是n型FinFET，随着外延的进行，可以原位掺杂p型或n型杂质。例如，当产生的FinFET是p型FinFET时，可以生长硅锗硼(SiGeB)。相反地，当产生的FinFET是n型FinFET时，可以生长硅磷(SiP)或硅碳磷(SiCP)。根据本发明的可选实施例，外延区42包括诸如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、它们的组合或它们的多层的III-V化合物半导体。在用外延区42填充凹槽40之后，外延区42的进一步外延生长使得外延区42横向扩展，并且可以形成小平面。
在外延步骤之后，外延区42可以进一步注入有p型或n型杂质以形成源极区和漏极区，其也使用参照标号42标记。根据本发明的可选实施例，由于在外延期间用p型或n型杂质原位掺杂外延区42，跳过注入步骤。外延区42包括在STI区22中形成的下部42A以及在STI区22的顶面22A上方形成的上部42B。下部42A的侧壁的形状为凹槽40(图4)的形状，下部42A可以具有(基本上)直的边缘，其也可以是与衬底20的主表面(诸如底面20B)基本上垂直的基本上垂直的边缘。
图6示出了在形成层间电介质(ILD)46之后的结构的立体图。相应的步骤示出为图22中示出的工艺流程中的步骤208。根据本发明的一些实施例，在形成ILD 46之前，在源极区和漏极区42上形成缓冲氧化物层(未示出)和接触蚀刻停止层(CESL，未示出)。缓冲氧化物层可以由氧化硅形成，并且CESL可以由氮化硅、碳氮化硅等形成。例如，可以使用诸如原子层沉积(ALD)的共形沉积方法形成缓冲氧化物层和CESL。ILD 46可以包括使用例如FCVD、旋涂、CVD或其他沉积方法形成的介电材料。ILD 46也可以由磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、正硅酸乙酯(TEOS)氧化物等形成。可以实施化学机械抛光(CMP)以使ILD 46、伪栅极堆叠件30和栅极间隔件38彼此齐平。
在随后的步骤中，去除ILD 46的部分46A以形成接触开口。然后在外延区42的表面上形成源极/漏极硅化物区48(图7A)。形成工艺包括在接触开口内沉积金属层，以及实施退火以使金属层与外延区42的暴露表面部分反应，使得形成硅化物区48。根据一些实施例，去除金属层的未反应部分。根据可选实施例，金属层的未反应部分保留未被去除。如图7A所示，然后在接触开口内填充诸如钨的导电材料以形成接触插塞50。
图7B中示出了图7A中所示的结构的截面图，其中，从图7A中的包含线A-A的垂直平面获得该截面图。接下来，如图8至图16所示，用金属栅极和替换栅极电介质替换包括硬掩模层36、伪栅电极34和伪栅极电介质32的伪栅极堆叠件30。从图7A中的包含线A-A的相同垂直平面获得图8至图16中所示的截面图。在图8至图16中，示出了STI区22的顶面22A，并且半导体鳍24’位于顶面22A上方。
然后去除如图7A和图7B所示的硬掩模层36、伪栅电极34和伪栅极电介质32，形成如图8所示的开口47。相应的步骤示出为图22中示出的工艺流程中的步骤210。突出鳍24’的顶面和侧壁暴露于开口47。
接下来，参照图9，形成延伸至开口47内的栅极电介质。相应的步骤示出为图22中示出的工艺流程中的步骤212。根据本发明的一些实施例，栅极电介质58包括作为其下部的界面层(IL)54。IL 54形成在突出鳍24’的暴露表面上。IL 54可以包括通过突出鳍24’的热氧化、化学氧化工艺或沉积工艺形成的诸如氧化硅层的氧化物层。栅极电介质58也可以包括形成在IL 54上方的高k介电层56。高k介电层56包括诸如氧化铪、氧化镧、氧化铝、氧化锆等的高k介电材料。高k介电材料的介电常数(k值)高于3.9，并且可以高于约7.0，并且有时高达21.0或更高。高k介电层56位于IL 54上面并且可以接触IL 54。高k介电层56形成为共形层，并且在突出鳍24’的侧壁上以及栅极间隔件38的顶面和侧壁上延伸。根据本发明的一些实施例，使用ALD或CVD形成高k介电层56。
参照图10，通过沉积形成含金属导电层62。相应的步骤示出为图22中示出的工艺流程中的步骤214。可以使用诸如ALD或CVD的共形沉积方法实施沉积，使得含金属层62(和每个子层)的横向部分的横向厚度T1和垂直部分的垂直厚度T2具有彼此基本相等的厚度。例如，横向厚度T1和垂直厚度T2可以具有小于厚度T1的约20％或10％的差。根据本发明的一些实施例，比率T1/W1可以小于约1/4，并且在约1/10和约1/5之间的范围内，其中，W1是开口47(图8)的宽度。例如，厚度T1可以在约和约的范围内，并且开口47的宽度W1可以在约和约的范围内。含金属层62延伸至开口47内，并且包括位于ILD 46上方的一些部分。
含金属层62包括至少一个层，并且可以包括由不同材料形成的多个层(诸如62A、62B和62C)。可以根据相应的FinFET是n型FinFET还是p型FinFET来选择含金属层62中的层的具体材料。例如，当FinFET是n型FinFET时，层62A、62B和62C可以分别包括氮化钛(TiN)层、氮化钽(TaN)层和钛铝(TiAl)层。当FinFET是p型FinFET时，层62A、62B和62C可以分别包括TiN层、TaN层和另一TiN层。根据本发明的一些实施例，层62包括层62A但没有层62B和62C，或可以包括层62A和62B但没有层62C。层62也可以包括多于三个层。
在沉积含金属层62之后，形成牺牲层64以填充开口47的剩余部分(图10)。根据一些实施例，牺牲层64由光刻胶形成。根据可选实施例，牺牲层64由与下面的层56和62(62A、62B和62C)的材料不同的另一材料形成。例如，牺牲层64可以由氧化硅、氮化硅、碳化硅等形成。牺牲层64可以具有基本上平坦的顶面，当牺牲层64由光刻胶形成时，这是由旋涂引起的。如果需要，可以实施诸如CMP的平坦化步骤。
图10也示出牺牲层64的回蚀刻，由箭头67表示。相应的步骤示出为图22中示出的工艺流程中的步骤216。蚀刻可以包括干蚀刻和/或湿蚀刻。此外，蚀刻可以是各项同性或各向异性的。根据本发明的一些实施例，使用侵袭牺牲层64和含金属层62而不侵袭高k介电层56的蚀刻剂实施回蚀刻。
图11示出蚀刻的中间步骤，其中，牺牲层64被回蚀刻，并且因此层62暴露。接下来，如图12所示，继续回蚀刻，在回蚀刻期间，蚀刻牺牲层64和含金属层62。结果，高k介电层56暴露。根据本发明的一些实施例，高k介电层56用作蚀刻的蚀刻停止层。因此，在随后的回蚀刻工艺中未蚀刻高k介电层56的暴露的横向部分。因此高k介电层56暴露下面的包括栅极间隔件38、ILD 46和金属接触插塞50的结构。
图13示出了在完成回蚀刻之后的产生的结构。由于蚀刻剂在回蚀刻期间侵袭牺牲层64和含金属层62，牺牲层64和含金属层62的顶面降低。应该理解，牺牲层64的蚀刻速率可以与含金属层62的蚀刻速率不同，这使得剩余的牺牲层64的顶面高于或低于剩余的含金属层62的顶部边缘。含金属层62的凹进深度(H2-H1)大于约大于约或在约和约之间的范围内，其中，H1是剩余的含金属层62的高度，并且H2是开口47的高度/深度。根据本发明的一些实施例，比率H1/H2小于约0.8，并且可以在约0.3和约0.8之间的范围内。例如，高度H2可以在约和约之间的范围内，并且高度H1可以在约和约之间的范围内。
在完成回蚀刻之后，例如，在湿蚀刻工艺或灰化工艺中去除牺牲层64的剩余部分。图14A示出根据一些实施例的产生的结构。由于层62A、62B和62C的材料差别，层62A、62B和62C的顶部边缘可以处于相同的层级或不同的层级，取决于层62A、62B和62C的材料、选择的蚀刻剂和蚀刻工艺条件(诸如温度、压力、浓度等)。因此，层62A、62B和62C的顶部边缘62A’、62B’和62C’分别与任意组合中的层62A、62B和62C的其他层齐平、高于或低于任意组合中的层62A、62B和62C的其他层(例如，参见图21A至图21D)。图14B示出了根据一些示例性实施例的产生的层62A、62B和62C，其中，62A、62B和62C的上层具有逐渐低于62A、62B和62C的相应的下层的顶部边缘62A’、62B’和62C’。这可以通过使用具有关系ER64≥ER62C≥ER62B≥ER62A的蚀刻剂实施回蚀刻来实现，其中，ER64、ER62C、ER62B和ER62A分别是牺牲层64、层62C、层62B和层62A的蚀刻速率。由于开口47的底部逐渐窄于上部，图14B中示出的轮廓是有利的，并且容易填充开口47，而不在填充材料中生成缝隙。图14B也示出顶部边缘62A’、62B’和62C’形成一些阶梯。
根据一些实施例，如图15所示，然后用导电(可以是含金属的)材料填充如图14A或图14B所示的剩余的开口47。相应的步骤示出为图22中示出的工艺流程中的步骤218。根据一些示例性实施例，填充金属包括金属层66、金属层68和金属层70。至少金属层66是功函金属，并且金属层68和金属层70可以是非功函金属或功函金属。贯穿说明书，当金属层称为功函金属时，表示它具有适合相应的FinFET的类型的功函数，并且它在金属栅极中的位置允许它的功函数影响或确定相应的FinFET的功函数。例如，当FinFET时n型FinFET时，功函金属优选具有低的功函数，其低于中间禁带功函数(约4.5eV)。相应的功函金属的功函数可以称为n功函数，其低于约4.3eV，并且可以在约3.9eV和约4.3eV之间的范围内。当FinFET时p型FinFET时，功函金属具有高的功函数，其高于中间禁带功函数。相应的功函金属的功函数可以称为p功函数，其高于约4.5eV，并且可以在约4.7eV和约5.1eV之间的范围内。
根据本发明的一些实施例，当FinFET时n型FinFET时，含金属层66可以包括TiAl，并且当FinFET时p型FinFET时，含金属层66可以包括TiN。根据一些实施例，当FinFET时n型FinFET时，层68和70可以包括TiN层/钴层以及钨层或铝层。根据一些实施例，当FinFET时p型FinFET时，层68和70可以包括TiAl层、TiN层、钴层和钨层或铝层。可以使用物理汽相沉积、ALD、CVD等形成层66、68和70。
接下来，实施平坦化步骤(例如，CMP)以去除位于ILD 46上方的层66、68和70的过量部分。相应的步骤示出为图22中示出的工艺流程中的步骤220。也去除位于ILD 46上方的高k介电层56的横向部分。层54、56、62、66、68和70的剩余部分组合形成替换栅极堆叠件74。层56、62、66和68的剩余部分的每个包括底部、位于底部上方并且连接至底部的侧壁部。因此形成FinFET 76。接下来，如图16所示，使金属层66、68和70凹进，并且用硬掩模72填充相应的凹槽，硬掩模72是由氮化硅、氮氧化硅、碳氧化硅等形成的介电硬掩模。也平坦化硬掩模72，使得它的顶面与ILD 46的顶面共面。
在示出的实施例中，在形成替换栅极堆叠件74之前形成源极/漏极接触插塞50。根据本发明的可选实施例，在形成替换栅极堆叠件74之后形成源极/漏极接触插塞50。
参照图17，在替换栅极堆叠件74上方形成蚀刻停止层78。蚀刻停止层78由介电材料形成，介电材料可以包括碳化硅、氮化硅、氮氧化硅等。在蚀刻停止层78上方形成ILD 80，并且在ILD 80中形成接触插塞82。形成工艺可以包括在ILD 80中形成接触插塞开口以暴露替换栅极堆叠件74和源极/漏极接触插塞50，并且用导电材料填充接触插塞开口以形成接触插塞82。在示出的平面中，也去除硬掩模72(图12)，使得栅极接触插塞82延伸至由去除的硬掩模72留下的凹槽内。
图18示出根据一些实施例的FinFET 76，其中，含金属层62包括层62A和62B，并且不包括如图17所示的层62C。根据一些实施例，图17和图18中示出的FinFET是形成在相同衬底20上的不同类型的FinFET。例如，图17中示出的FinFET可以是p型FinFET，并且图18中示出的FinFET可以是n型FinFET。根据一些实施例，图17和图18中的替换栅极堆叠件具有相同的宽度W1。
图19和图20示出，金属层的厚度的改变和/或宽度W1的改变引起金属层70的形状的改变。例如，如图19所示，当层68的厚度增加时，金属层70的宽度减小。进一步增加层66、层68和/或层62的厚度，含金属层70仅将具有高于含金属层62的顶部边缘的部分，并且将不具有延伸在含金属层62的顶部边缘下方的部分。根据本发明的一些实施例，图19中示出的结构可以由n型FinFET采用，并且图20中示出的结构可以由p型FinFET采用，其中，p型FinFET和n型FinFET形成在相同的衬底上。
在图17中，未示出层62A、62B和62C的顶部边缘轮廓的细节。图21A、图21B、图21C和图21D示出根据一些实施例的层62A、62B和62C的顶部边缘轮廓。如在前的段落中讨论的，通过调整牺牲层64以及层62C、62B和62A的蚀刻速率ER64、ER62C、ER62B和ER62A，顶部边缘62A’、62B’和62C’可以具有不同的高度和形状。例如，如图21A所示，顶部边缘62A’、62B’和62C’可以形成连续降低的边缘，没有形成阶梯。在图21B中，顶部边缘62A’和62C’低于顶部边缘62B’，顶部边缘的最高点是顶部边缘62B’的部分。在图21C中，顶部边缘62B’高于顶部边缘62C’，顶部边缘62C’进一步高于顶部边缘62A’。在图21D中，顶部边缘62B’低于顶部边缘62A’和62C’，其中，顶部边缘62A’可以高于或低于顶部边缘62C’。还应该注意，如图18至图20所示，顶部边缘62A’、62B’和62C’的顶部边缘轮廓也可以与层66、68和70的轮廓组合为任意组合。
本发明的实施例具有一些有利特征。通过形成一个或多个含金属层并且然后实施回蚀刻，用于形成替换栅极的凹槽的底部变窄。因此栅极间隙填充变得更容易，并且消除了可能在含金属层70中生成的缝隙。这有利地改进产品良率。而且，也消除了可以由缝隙引起的泄漏路径。
根据本发明的一些实施例，方法包括在半导体区上方形成伪栅极堆叠件，在与伪栅极堆叠件相同的层级处形成介电层，去除伪栅极堆叠件以在介电层中形成开口，填充延伸至开口内的金属层，以及回蚀刻金属层，金属层的剩余部分的边缘低于介电层的顶面。开口填充有导电材料，并且导电材料位于金属层上方。金属层和导电材料组合形成替换栅极。在替换栅极的相对两侧上形成源极区和漏极区。
在上述方法中，其中，所述回蚀刻包括：在所述金属层填充牺牲层，其中，所述牺牲层填充至所述开口内；以及当回蚀刻所述金属层时同时蚀刻所述牺牲层。
在上述方法中，其中，所述回蚀刻包括：在所述金属层填充牺牲层，其中，所述牺牲层填充至所述开口内；以及当回蚀刻所述金属层时同时蚀刻所述牺牲层，其中，填充所述牺牲层包括施加光刻胶。
在上述方法中，其中，用所述导电材料填充所述开口包括沉积与所述金属层接触的功函层。
在上述方法中，其中，蚀刻所述金属层所剩余的高度小于所述开口的深度的80％。
在上述方法中，其中，形成所述金属层包括形成多个金属层，并且所述多个金属层由不同的材料形成。
在上述方法中，其中，形成所述金属层包括形成多个金属层，并且所述多个金属层由不同的材料形成，在回蚀刻所述金属层之后，所述多个金属层中的上层的顶部边缘低于所述金属层中的相应的下面的层的顶部边缘。
在上述方法中，还包括在所述伪栅极堆叠件的相对两侧上形成栅极间隔件。
根据本发明的一些实施例，方法包括在半导体区上形成伪栅极堆叠件，在伪栅极堆叠件的侧壁上形成栅极间隔件，以及在伪栅极堆叠件的相对两侧上形成源极区和漏极区，该方法还包括形成层间电介质以覆盖源极区和漏极区，去除伪栅极堆叠件以形成开口，形成延伸至开口内的栅极介电层，以及在栅极介电层上方形成含金属层。含金属层具有位于开口中的第一部分以及位于开口外部的第二部分。该方法还包括去除第二部分并且回蚀刻含金属层的第一部分，以及用导电材料填充剩余的开口。
在上述方法中，其中，形成所述含金属层包括沉积多个金属层。
在上述方法中，其中，使用原子层沉积实施形成所述含金属层。
在上述方法中，其中，通过蚀刻实施去除所述第二部分。
在上述方法中，还包括：在所述含金属层上方形成牺牲层，其中，所述牺牲层填充入所述开口内，并且同时蚀刻所述牺牲层和所述含金属层。
在上述方法中，还包括：在所述含金属层上方形成牺牲层，其中，所述牺牲层填充入所述开口内，并且同时蚀刻所述牺牲层和所述含金属层，还包括，在蚀刻所述含金属层之后，去除所述牺牲层的剩余部分。
根据本发明的一些实施例，器件包括栅极间隔件、位于栅极间隔件之间的开口、内衬于开口的栅极电介质以及位于栅极电介质的底部上方的含金属层。含金属层具有位于开口的底部处的底部以及连接至底部的端部的侧壁部。侧壁部的顶部边缘低于栅极间隔件的顶部边缘。导电材料位于含金属层上方和开口中。导电材料的顶面高于含金属层的侧壁部的顶部边缘。
在上述器件中，其中，所述含金属层是共形层，并且其中，所述含金属层的所述底部和所述侧壁部具有相同的厚度。
在上述器件中，其中，所述导电材料包括功函金属，所述导电材料决定相应的晶体管的功函数。
在上述器件中，其中，所述导电材料包括功函金属，所述导电材料决定相应的晶体管的功函数，所述功函金属的顶部边缘与所述栅极间隔件的顶部边缘共面。
在上述器件中，其中，所述含金属层包括由不同的材料形成的多个金属层。
在上述器件中，其中，所述含金属层包括由不同的材料形成的多个金属层，所述多个金属层中的上层的顶部边缘低于所述多个金属层中的相应的下面的层的顶部边缘。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成晶体管的方法，包括：
在半导体区上方形成伪栅极堆叠件；
在与所述伪栅极堆叠件相同的层级处形成介电层；
去除所述伪栅极堆叠件以在所述介电层中形成开口；
填充延伸至所述开口内的金属层；
回蚀刻所述金属层，其中，所述金属层的剩余部分的边缘低于所述介电层的顶面；
用导电材料填充所述开口，其中，所述导电材料位于所述金属层上方，其中，所述金属层和所述导电材料组合形成替换栅极；以及
形成源极区和漏极区，其中，所述源极区和漏极区位于所述替换栅极的相对两侧上。
2.根据权利要求1所述的方法，其中，所述回蚀刻包括：
在所述金属层填充牺牲层，其中，所述牺牲层填充至所述开口内；以及
当回蚀刻所述金属层时同时蚀刻所述牺牲层。
3.根据权利要求2所述的方法，其中，填充所述牺牲层包括施加光刻胶。
4.根据权利要求1所述的方法，其中，用所述导电材料填充所述开口包括沉积与所述金属层接触的功函层。
5.根据权利要求1所述的方法，其中，蚀刻所述金属层所剩余的高度小于所述开口的深度的80％。
6.根据权利要求1所述的方法，其中，形成所述金属层包括形成多个金属层，并且所述多个金属层由不同的材料形成。
7.根据权利要求6所述的方法，其中，在回蚀刻所述金属层之后，所述多个金属层中的上层的顶部边缘低于所述金属层中的相应的下面的层的顶部边缘。
8.根据权利要求1所述的方法，还包括在所述伪栅极堆叠件的相对两侧上形成栅极间隔件。
9.一种形成晶体管的方法，包括：
在半导体区上形成伪栅极堆叠件；
在所述伪栅极堆叠件的侧壁上形成栅极间隔件；
在所述伪栅极堆叠件的相对两侧上形成源极区和漏极区；
形成层间电介质以覆盖所述源极区和漏极区；
去除所述伪栅极堆叠件以形成开口；
形成延伸至所述开口内的栅极介电层；
在所述栅极介电层上方形成含金属层，其中，所述含金属层包括位于所述开口中的第一部分和位于所述开口外部的第二部分；
去除所述第二部分并且回蚀刻所述含金属层的所述第一部分；以及
用导电材料填充剩余的开口。
10.一种晶体管器件，包括：
栅极间隔件；
位于所述栅极间隔件之间的开口；
栅极电介质，内衬于所述开口；
含金属层，位于所述栅极电介质的底部上方，其中，所述含金属层包括位于所述开口的底部处的底部和连接至所述底部的端部的侧壁部，其中，所述侧壁部的顶部边缘低于所述栅极间隔件的顶部边缘；以及
导电材料，位于所述含金属层上方，其中，所述导电材料位于所述开口中，并且所述导电材料的顶面高于所述含金属层的所述侧壁部的顶部边缘。
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