US20130221413A1 - Divot-free planarization dielectric layer for replacement gate - Google Patents
Divot-free planarization dielectric layer for replacement gate Download PDFInfo
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- US20130221413A1 US20130221413A1 US13/405,939 US201213405939A US2013221413A1 US 20130221413 A1 US20130221413 A1 US 20130221413A1 US 201213405939 A US201213405939 A US 201213405939A US 2013221413 A1 US2013221413 A1 US 2013221413A1
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- silicon nitride
- dielectric layer
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- dielectric
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Definitions
- the present disclosure relates to semiconductor structures, and particularly to replacement gate semiconductor structures employing a planarization dielectric layer that is planarized without formation of divots or recesses on a top surface thereof, and methods of manufacturing the same.
- silicon oxide as gate spacers and/or a planarization dielectric layer results in formation of recesses and divots on the planarized top surfaces of the silicon oxide material.
- removal of a disposable gate material in a replacement gate processing scheme results in collateral etch of the top portions of the silicon oxide gate spacer and top portions of the silicon oxide planarization dielectric layer relative to a top surface of another planarization dielectric material such as silicon nitride. Divots and/or recesses are formed above the top surfaces of the recessed portions of the oxide material.
- Such divots and/or recesses are filled with the conductive material.
- Such residual conductive material filling divots and/or recesses provide a spurious conductive path, causing electrical shorts between various semiconductor devices.
- the residual conductive material is a concern for reliability and yield.
- a dielectric material layer is deposited, which includes a dielectric material that is not prone to material loss during subsequent exposure to dry or wet etch chemicals employed to remove disposable gate materials in the disposable gate structure.
- the dielectric material can be a spin-on dielectric material or can be a dielectric metal oxide material.
- the dielectric material layer and the silicon nitride liner are planarized to provide a planarized dielectric surface in which the disposable gate materials are physically exposed. Surfaces of the planarized dielectric layer is not recessed relative to surfaces of the silicon nitride layer during removal of the disposable gate materials and prior to formation of replacement gate structures, thereby preventing formation of metallic stringers.
- a method of forming a semiconductor structure includes: forming a disposable gate structure including at least a disposable gate material portion on a semiconductor substrate; forming a silicon nitride gate spacer on sidewalls of the disposable gate structure; forming a silicon nitride liner on the silicon nitride gate spacer and over the disposable gate structure; forming a planarization dielectric layer including a dielectric material on the silicon nitride liner; physically exposing a top surface of the disposable gate material portion by planarizing the planarization dielectric layer and the silicon nitride liner; forming a gate cavity by removing at least the disposable gate material portion, wherein all topmost surfaces of the silicon nitride spacer, the silicon nitride liner, and the planarization dielectric layer are within a horizontal plane; and forming a replacement gate structure by filling the gate cavity with a gate dielectric layer and at least one conductive material and removing portions of the
- a semiconductor structure which includes a gate-level layer located on a semiconductor substrate and complementarily occupied with at least one gate cavity and dielectric material portions, wherein the dielectric material portions include at least one silicon nitride gate spacer laterally surrounding each of the at least one gate cavity, a silicon nitride liner in contact with all outer surfaces of the at least one silicon nitride gate spacer, and a planarization dielectric layer having one or more portions, wherein each portion of the planarization dielectric layer is embedded within a recessed portion of the silicon nitride liner, and wherein all topmost surfaces of the at least one silicon nitride gate spacer, the silicon nitride liner, and the planarization dielectric layer are within a horizontal plane overlying the semiconductor substrate.
- FIG. 1 is a vertical cross-sectional view of a first exemplary semiconductor structure after formation of a disposable dielectric layer, a disposable gate material layer, and an optional disposable gate cap dielectric layer according to a first embodiment of the present disclosure.
- FIG. 2 is vertical cross-sectional view of the first exemplary semiconductor structure after formation of disposable gate structures and silicon nitride gate spacers according to the first embodiment of the present disclosure.
- FIG. 3 is vertical cross-sectional view of the first exemplary semiconductor structure after formation of a silicon nitride liner according to the first embodiment of the present disclosure.
- FIG. 4 is a vertical cross-sectional view of the first exemplary semiconductor structure after formation of a planarization dielectric layer including a spin-on dielectric material according to the first embodiment of the present disclosure.
- FIG. 5 is a vertical cross-sectional view of the first exemplary semiconductor structure after planarization of the planarization dielectric layer to a topmost surface of the silicon nitride liner according to the first embodiment of the present disclosure.
- FIG. 6 is a vertical cross-sectional view of the first exemplary semiconductor structure after planarization of the planarization dielectric layer, silicon nitride liner, and gate cap dielectric portions according to the first embodiment of the present disclosure.
- FIG. 7 is a vertical cross-sectional view of the first exemplary semiconductor structure after removal of the disposable gate structures according to the first embodiment of the present disclosure.
- FIG. 8 is a vertical cross-sectional view of the first exemplary semiconductor structure after deposition of a contiguous gate dielectric layer and a first work function metallic layer and patterning of the first work function metallic layer according to the first embodiment of the present disclosure.
- FIG. 9 is a vertical cross-sectional view of the first exemplary semiconductor structure after deposition of a second work function metallic layer and a gate conductor layer according to the first embodiment of the present disclosure.
- FIG. 10 is a vertical cross-sectional view of the first exemplary semiconductor structure after formation of replacement gate structures according to the first embodiment of the present disclosure.
- FIG. 11 is a vertical cross-sectional view of the first exemplary semiconductor structure after formation of a contact-level dielectric layer and various contact structures according to the first embodiment of the present disclosure.
- FIG. 12 is a vertical cross-sectional view of a second exemplary semiconductor structure after formation of planarization dielectric layer including a dielectric metal oxide material according to a second embodiment of the present disclosure.
- the present disclosure relates to replacement gate semiconductor structures employing a planarization dielectric layer that is planarized without formation of divots or recesses on a top surface thereof, and methods of manufacturing the same, which are now described in detail with accompanying figures.
- Like and corresponding elements mentioned herein and illustrated in the drawings are referred to by like reference numerals. The drawings are not necessarily drawn to scale.
- a first exemplary semiconductor structure includes a semiconductor substrate 8 that includes a semiconductor material layer 10 .
- Various semiconductor devices including at least one field effect transistor can be subsequently formed on the semiconductor material layer 10 .
- the semiconductor substrate 8 can be a bulk substrate including a bulk semiconductor material constituting the semiconductor material layer 10 throughout, or a semiconductor-on-insulator (SOI) substrate (not shown) containing a top semiconductor layer that constitutes a semiconductor material layer, a buried insulator layer (not shown) located under the top semiconductor layer, and a bottom semiconductor layer (not shown) located under the buried insulator layer.
- SOI semiconductor-on-insulator
- the semiconductor substrate 8 can be doped with electrical dopants of p-type or n-type at different dopant concentration levels.
- the semiconductor substrate 8 may include at least one p-type well (not shown) and/or at least one n-type well (not shown).
- At least one shallow trench isolation structure (not shown) can be formed to laterally separate various surface regions of the semiconductor substrate 8 .
- a disposable dielectric layer 25 L, a disposable gate material layer 27 L, and an optional disposable gate cap dielectric layer 29 L are deposited on the top surface of the semiconductor substrate 8 .
- the disposable dielectric layer 25 L includes a dielectric material such as a semiconductor oxide, a semiconductor nitride, or a semiconductor oxynitride.
- the disposable dielectric layer 25 L can include silicon oxide, silicon nitride, or silicon oxynitride.
- the disposable gate material layer 27 L includes a material that can be subsequently removed selective to silicon nitride and selective to dielectric materials of gate spacers and a planarization dielectric layer to be subsequently deposited above the top surface of the substrate 8 .
- the disposable gate material layer 27 L can include a semiconductor material such as silicon, germanium, a silicon germanium alloy, or a compound semiconductor material.
- the disposable gate material layer 27 L can include any dielectric material or any metallic material that can be removed selective to the dielectric materials of the gate spacer and the dielectric layer to be subsequently deposited.
- a disposable gate cap dielectric layer 29 L can be deposited on the disposable gate material layer.
- the disposable gate cap dielectric layer 29 L includes a dielectric material such as silicon nitride.
- the total thickness of the stack of the disposable dielectric layer 25 L, the disposable gate material layer 27 L, and the optional disposable gate cap dielectric layer 29 L can be from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed.
- each disposable gate structure includes a disposable dielectric portion 25 , which is a remaining portion of the disposable dielectric layer 25 L, and a disposable gate material portion 27 , which is a remaining portion of the disposable gate material layer 27 L.
- Each disposable gate structure may optionally include a disposable gate cap dielectric portion 29 , which is a remaining portion of the disposable gate cap dielectric layer 29 L.
- the disposable gate dielectrics 25 can include at least one of silicon oxide and silicon oxynitride and/or the disposable gate material portions 27 can include a semiconductor material.
- Silicon nitride gate spacers 52 are formed on sidewalls of each of the disposable gate structures ( 25 , 27 , 29 ), for example, by deposition of a conformal dielectric material layer and an anisotropic etch. Silicon nitride can be deposited, for example, by chemical vapor deposition (CVD) or atomic layer deposition (ALD).
- CVD chemical vapor deposition
- ALD atomic layer deposition
- Masked ion implantation can be performed before and/or after formation of the silicon nitride gate spacers 52 .
- a masking structure including a combination of a patterned photoresist layer (not shown) and at least one disposable gate structure ( 25 , 27 , 29 ) is employed for each masked ion implantation prior to formation of the gate spacers 52 .
- a masking structure including a combination of a patterned photoresist layer (not shown) and at least one disposable gate structure ( 25 , 27 , 29 ) and at least one silicon nitride gate spacer 52 laterally surrounding each of the at least one disposable gate structure ( 25 , 27 , 29 ) is employed for each masked ion implantation after formation of the gate spacers 52 .
- source and drain regions 16 include any source region, any drain region, any source extension region, or any drain extension region as known in the art.
- the disposable gate material portions 27 include a semiconductor material, and the silicon nitride gate spacers 52 are formed directly on sidewalls of the semiconductor material in the disposable gate structures 27 .
- the disposable gate structures ( 25 , 27 , 29 ) can employ materials other than semiconductor oxide and semiconductor oxynitride. In this case, semiconductor oxide or semiconductor oxynitride is not present above the bottom surface of the disposable gate material portions 27 after the forming of the disposable gate structures ( 25 , 27 , 29 ).
- a silicon nitride liner 60 is deposited on the silicon nitride gate spacers 52 and over the disposable gate structures ( 25 , 27 , 29 ).
- the silicon nitride liner 60 is a contiguous layer that contacts the entirety of outer sidewall surfaces of the silicon nitride gate spacers 52 , the entirety of top surfaces of the disposable gate structures ( 25 , 27 , 29 ), and the entirety of the top surface of the semiconductor substrate 8 that is not contacted by the silicon nitride gate spacers 52 or the disposable gate structures ( 25 , 27 , 29 ).
- the silicon nitride liner 60 can be deposited, for example, by chemical vapor deposition (CVD).
- the thickness of the silicon nitride liner 60 can be from 20 nm to 200 nm, although lesser and greater thicknesses can also be employed.
- a planarization dielectric layer 70 is formed above the silicon nitride liner 60 .
- the planarization dielectric layer 70 includes a dielectric material other than semiconductor oxide, silicon nitride, and semiconductor oxynitride. If the disposable gate structures ( 25 , 27 , 29 ) can employ materials other than semiconductor oxide and semiconductor oxynitride, no semiconductor oxide or semiconductor oxynitride is present above the plane of the top surface of the disposable gate dielectrics 25 .
- the planarization dielectric layer 70 including a spin-on dielectric material that is etch-resistant to hydrofluoric acid, i.e., a spin-on dielectric material that is not etched by hydrofluoric acid.
- the spin-on dielectric material of the planarization dielectric layer 70 can be applied by spin-coating, and is self-planarizing, i.e., forms a planar top surface without application of external force other than gravity.
- Exemplary spin-on dielectric materials include hydrogen silsesquioxane (HSQ) and methyl silsesquioxane (MSQ).
- the thickness of the planarization dielectric layer 70 as measured from above the topmost portions of the silicon nitride liner 60 can be from 20 nm to 300 nm, although lesser and greater thicknesses can also be employed.
- the planarization dielectric layer 70 is planarized to a topmost surface of the silicon nitride liner 60 .
- the planarization of the planarization dielectric layer 70 can be effected, for example, by a recess etch or chemical mechanical planarization (CMP).
- CMP chemical mechanical planarization
- the top surface of the silicon nitride liner 60 can be employed as a stopping layer for the recess etch or for CMP.
- the planarization dielectric layer 70 , the silicon nitride liner 60 , and the disposable gate cap dielectric portions 29 are planarized, for example, by chemical mechanical planarization or a non-selective recess etch, to a level at which a top surface of the disposable gate material portions 27 are physically exposed.
- the physically exposed top surface of the disposable gate material portions 27 may be located at, or below, the topmost surfaces of the disposable gate material portions 27 prior to the planarization of the planarization dielectric layer 70 , the silicon nitride liner 60 , and the disposable gate cap dielectric portions 29 .
- the remaining portions of the disposable gate structures ( 25 , 27 ) are removed selective to the materials of the planarization dielectric layer 70 , the silicon nitride liner 60 , and the silicon nitride gate spacers 52 .
- a gate cavity 39 is formed within each volume from which a disposable gate structure ( 25 , 27 ) is removed.
- the formation of the gate cavities 39 can be effected by at least one etch that does not remove any material from the silicon nitride liner 60 , the silicon nitride gate spacer 52 , or the planarization dielectric layer 70 , while removing an entirety of the disposable gate structures ( 25 , 27 ).
- a semiconductor surface of the semiconductor substrate 8 is physically exposed at the bottom of each gate cavity 39 .
- the at least one etch can be at least one wet etch that employs hydrofluoric acid (HF) and/or ammonium hydroxide (NH 4 OH). Silicon nitride or the dielectric material of the planarization dielectric layer 70 is not removed during the formation of the gate cavities 39 .
- all topmost surfaces of the silicon nitride spacers 52 , the silicon nitride liner 60 , and the planarization dielectric layer 70 are within a horizontal plane that is parallel to the topmost surface of the semiconductor substrate 8 .
- Inner sidewall surfaces of each silicon nitride gate spacer 52 are physically exposed within a gate cavity 39 .
- the first exemplary semiconductor structure includes a gate-level layer 12 located on the semiconductor substrate.
- the gate-level layer 12 is complementarily occupied with at least one gate cavity 39 and dielectric material portions.
- the gate-level layer 12 consists of the at least one gate cavity 39 and the dielectric material portions.
- the dielectric material portions include at least one silicon nitride gate spacer 52 laterally surrounding each of the at least one gate cavity 39 , the silicon nitride liner 60 in contact with all outer surfaces of the at least one silicon nitride gate spacer 52 , and the planarization dielectric layer 70 having one or more portions, i.e., in the form of a single contiguous portion or in the form of a plurality of non-contiguous portions that are laterally spaced by at least one of the silicon nitride liner 60 and one or more silicon nitride gate spacers 52 .
- Each portion of the planarization dielectric layer 70 is embedded within a recessed portion of the silicon nitride liner 60 , and is laterally contacted by upper portions of the silicon nitride liner 60 . All topmost surfaces of the at least one silicon nitride gate spacer 52 , the silicon nitride liner 60 , and the planarization dielectric layer 70 are within a horizontal plane overlying the semiconductor substrate 8 and parallel to the top surface of the semiconductor substrate 8 .
- the planarization dielectric layer 70 includes a spin-on dielectric material such as hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ).
- HSQ hydrogen silsesquioxane
- MSQ methyl silsesquioxane
- Each of the at least one gate cavity 39 can overlie a channel of a field effect transistor that includes the various portions of the source and drain regions 16 as the source and the drain of the field effect transistor.
- the dielectric material portions can consist of the at least one silicon nitride gate spacer 52 , the silicon nitride liner 60 , and the planarization dielectric layer 70 .
- a contiguous gate dielectric layer 32 L is deposited in the gate cavities 39 and over the top surfaces of the silicon nitride gate spacers 52 , the silicon nitride liners 60 , and the planarization dielectric layer 70 .
- the contiguous gate dielectric layer 32 L can be a high dielectric constant (high-k) material layer having a dielectric constant greater than 3.9.
- the contiguous gate dielectric layer 32 L can include a dielectric metal oxide, which is a high-k material containing a metal and oxygen, and is known in the art as high-k gate dielectric materials.
- Dielectric metal oxides can be deposited by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), atomic layer deposition (ALD), etc.
- CVD chemical vapor deposition
- PVD physical vapor deposition
- MLD molecular beam deposition
- PLD pulsed laser deposition
- LSMCD liquid source misted chemical deposition
- ALD atomic layer deposition
- Exemplary high-k dielectric material include HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO x N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , a silicate thereof, and an alloy thereof.
- Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2.
- the thickness of the contiguous gate dielectric layer 32 L can be from 0.9 nm to 6 nm, and preferably from 1.0 nm to 3 nm.
- the contiguous gate dielectric layer 32 L may have an effective oxide thickness on the order of or less than 2 nm.
- the entirety of the interface between the contiguous dielectric layer 32 L and the horizontal surfaces of the silicon nitride gate spacers 52 , the silicon nitride liners 60 , and the planarization dielectric layer 70 is planar.
- an optional interfacial dielectric material layer (not shown) can be formed at the interface layer between the contiguous gate dielectric layer 32 L and the semiconductor material layer 10 .
- the interfacial dielectric material layer can include, for example, silicon oxide and/or silicon oxynitride.
- a first work function metallic layer 34 L is deposited on the contiguous gate dielectric layer 32 L, and is lithographically patterned to be present with at least one gate cavity 39 , while being absent within at least another gate cavity 39 .
- the first work function metallic layer 34 L includes a metallic material that can optimize the threshold voltages of transistors.
- the first work function metallic layer 34 L can include metallic materials such as Pt, Rh, Ir, Ru, Cu, Os, Be, Co, Pd, Te, Cr, Ni, TiN, Hf, Ti, Zr, Cd, La, Tl, Yb, Al, Ce, Eu, Li, Pb, Tb, Bi, In, Lu, Nb, Sm, V, Zr, Ga, Mg, Gd, Y, and TiAl, conductive nitrides thereof, and alloys thereof.
- the first work function metallic layer 34 L can be formed, for example, by physical vapor deposition, chemical vapor deposition, or atomic layer deposition (ALD).
- the thickness of the first work function metallic layer 34 L can be from 2 nm to 40 nm, although lesser and greater thicknesses can also be employed.
- a second work function metallic layer 36 L is deposited on the physically exposed surfaces of the first work function metallic layer 34 L and the contiguous gate dielectric layer 32 L.
- the second work function metallic layer 36 L includes a metallic material that can optimize the threshold voltages of transistors.
- the metallic material of the second work function metallic layer 36 L can be different from the metallic material of the first work function metallic layer 34 L.
- the second work function metallic layer 36 L can include any metallic material that can be selected for the metallic material of the first work function metallic layer 34 L.
- the second work function metallic layer 36 L can be formed, for example, by physical vapor deposition, chemical vapor deposition, or atomic layer deposition (ALD).
- the thickness of the second work function metallic layer 36 L can be from 2 nm to 40 nm, although lesser and greater thicknesses can also be employed.
- a gate conductor layer 40 L is deposited over the first and second work function metallic layers ( 34 L, 36 L).
- the gate conductor layer 40 L includes a conductive material, which can be deposited by physical vapor deposition or chemical vapor deposition.
- the gate conductor layer 40 L can be an aluminum layer, an aluminum alloy layer, a tungsten layer, and/or a tungsten alloy layer deposited by physical vapor deposition.
- the thickness of the gate conductor layer 40 L as measured in a planar region of the conductive metal layer 40 L above the topmost surface of the second work function metallic layer 36 L, can be from 100 nm to 500 nm, although lesser and greater thicknesses can also be employed.
- the gate conductor layer 40 L can include a single elemental metal such as Al or W or alloys thereof.
- portions of the gate conductor layer 40 L, portions of the first and second work function metallic layers ( 34 L, 36 L), and portions the contiguous gate dielectric layer 32 L are removed from above the top planar surface of the planarization dielectric layer 70 by performing a planarization process such as chemical mechanical planarization (CMP) and/or a non-selective recess etch.
- CMP chemical mechanical planarization
- Replacement gate structures are formed within volumes that are previously occupied by disposable gate structures ( 25 , 27 , 29 ; See FIGS. 2-6 ). Each replacement gate structure is a gate stack that remains permanently on the semiconductor substrate 8 , i.e., is not disposable.
- a gate dielectric 32 , at least one work function metal portion ( 34 , 36 ), and a gate conductor 40 are present with each replacement gate structure.
- Each gate dielectric 32 is a remaining portion of the contiguous gate dielectric layer 32 L after the planarization process.
- an optional interfacial dielectric material layer (not shown) can be present at the interface layer between the contiguous gate dielectric layer 32 L and the semiconductor material layer 10 .
- Each first work function metal portion 34 is a remaining portion of the first work function metallic layer 34 L after the planarization process.
- Each second work function metal portion 36 is a remaining portion of the second work function metallic layer 36 L after the planarization process.
- Each gate conductor 40 is a remaining portion of the gate conductor layer 40 L after the planarization process.
- Each replacement gate structure ( 32 , optionally 34 , 36 , 40 ) can overlie a channel region of a field effect transistor.
- a stack of at least one work function metal portion ( 36 and optionally 34 ) and a gate conductor 40 constitutes a gate electrode ( 36 , optionally 34 , 40 ).
- Each gate dielectric 32 can be a U-shaped gate dielectric contacting the semiconductor material of the semiconductor material layer 10 and the inner surfaces of a silicon nitride gate spacer 52 . Because the gate dielectrics 32 include the same material as the contiguous gate dielectric layer 32 L (See FIGS. 8 and 9 ), the gate dielectrics 32 can be U-shaped gate dielectrics including a dielectric material having a dielectric constant greater than 3.9. The U-shaped gate dielectrics include vertical portions, which have top surfaces that are coplanar with the top surfaces of the silicon nitride spacer 52 , the silicon nitride liner 60 , and the planarization dielectric layer 70 .
- Each work function metal portion ( 34 , 36 ) can be a U-shaped work function metal portion.
- a work function metal portion ( 34 , 36 ) may contact inner surfaces of the vertical portions of the gate dielectrics 32 and the top surfaces of the horizontal portions of the gate dielectrics 32 .
- a second work function metal portion 36 may contact inner sidewalls of vertical portions of a first work function metal portion 34 and a top surface of a horizontal portion of the first work function metal portion 34 .
- Each U-shaped work function metal portion includes vertical portions, which have top surfaces that are coplanar with the top surfaces of the silicon nitride spacer 52 , the silicon nitride liner 60 , and the planarization dielectric layer 70 and the top surfaces of the vertical portions of the U-shaped gate dielectrics.
- Each gate conductor 40 has a top surface that is coplanar with the top surface of the silicon nitride spacer 52 , the silicon nitride liner 60 , and the planarization dielectric layer 70 , and with the top surfaces of the vertical portions of the U-shaped gate dielectrics, and with the top surfaces of the vertical portions of the U-shaped work function metal portions.
- each replacement gate structure ( 32 , optionally 34 , 36 , 40 ) can be formed by filling a gate cavity 39 with a contiguous gate dielectric layer 32 L and at least one conductive material, and removing portions of the contiguous gate dielectric layer 32 L and the at least one conductive material from above a horizontal plane that is located at, or below, a plane including top surfaces of the top surfaces of the silicon nitride spacer 52 , the silicon nitride liner 60 , and the planarization dielectric layer 70 .
- the replacement gate structure ( 32 , optionally 34 , 36 , 40 ) includes a U-shaped gate dielectric, i.e., a gate dielectric 32 , which is in contact with inner sidewalls of a silicon nitride gate spacer 52 .
- the replacement gate structure ( 32 , optionally 34 , 36 , 40 ) further includes a gate electrode, which includes at least one conductive material, i.e., the conductive materials of a second work function metal portion 36 , the conductive material of the gate conductor 40 , and optionally the conductive material of a first work function metal portion 34 .
- the gate electrode ( 36 , 40 , and optionally 34 ) is in contact with inner sidewalls of the U-shaped gate dielectric.
- a contact-level dielectric layer 90 and various contact structures are formed.
- the contact-level dielectric layer 90 is deposited on a planar horizontal surface of the replacement gate structures ( 32 , 34 , 36 , 40 ), the silicon nitride spacers 52 , the silicon nitride liner 60 , and the planarization dielectric layer 70 , as a blanket layer, i.e., a layer without a pattern.
- the contact-level dielectric layer 90 includes a dielectric material such as silicon oxide, silicon nitride, and/or porous or non-porous organosilicate glass.
- the contact-level dielectric layer 90 can be deposited, for example, by chemical vapor deposition (CVD) or spin coating.
- the thickness of the contact-level dielectric layer 90 can be from 30 nm to 600 nm, although lesser and greater thicknesses can also be employed.
- Various contact via holes are formed through the contact-level dielectric layer 90 , for example, by applying and patterning a photoresist (not shown), and transferring the pattern in the photoresist into through the contact-level dielectric layer 90 and optionally through a stack of the planarization dielectric layer 70 and the silicon nitride liner 60 .
- the various contact via holes are filled with a conductive material to form various contact via structures, which can include at least one gate-contact via structure 94 and at least one substrate-contact via structure 96 .
- a second exemplary semiconductor structure according to a second embodiment of the present disclosure can be derived from the first exemplary semiconductor structure of FIG. 3 by formation of planarization dielectric layer 70 that is not self-planarized.
- the planarization dielectric layer 70 includes a dielectric material other than semiconductor oxide, silicon nitride, and semiconductor oxynitride.
- a semiconductor oxide or a semiconductor oxynitride is not present above the plane of the top surface of the disposable gate dielectrics 25 at this processing step.
- the planarization dielectric layer 70 including a dielectric material that is etch-resistant to hydrofluoric acid and/or ammonium hydroxide, i.e., a dielectric material that is not etched by the etchant to be subsequently employed.
- the dielectric material of the planarization dielectric layer 70 can be deposited by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), atomic layer deposition (ALD), etc.
- the dielectric material of the planarization dielectric layer 70 can be formed by a conformal deposition process, i.e., a deposition process that forms a film having a same thickness on a vertical surface as on a horizontal surface.
- Exemplary dielectric materials that can be employed for the planarization dielectric layer 70 include dielectric metal oxides such as HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TlO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO x N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , a silicate thereof, and an alloy thereof.
- Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2.
- the thickness of the planarization dielectric layer 70 as measured from above the topmost portions of the silicon nitride liner 60 can be from 20 nm to 300 nm, although lesser and greater thicknesses can also be employed.
- the dielectric material of the planarization dielectric layer 70 is deposited as an amorphous material.
- the second exemplary semiconductor structure is subsequently annealed at an elevated temperature to crystallize the amorphous material of the planarization dielectric layer 70 .
- the amorphous material of the planarization dielectric layer 70 as deposited is converted into a polycrystalline dielectric metal oxide during the anneal.
- the temperature of the anneal can be from 700 degrees Celsius to 1,100 degrees Celsius. In one embodiment, the temperature of the anneal can be greater than 800 degrees Celsius. In one embodiment, the temperature of the anneal can be greater than 900 degrees Celsius. In one embodiment, the temperature of the anneal can be greater than 1,000 degrees Celsius.
- the temperature of the anneal can be less than 1,000 degrees Celsius. In one embodiment, the temperature of the anneal can be less than 900 degrees Celsius. In one embodiment, the temperature of the anneal can be less than 800 degrees Celsius.
- the duration of the anneal at the elevated temperature can be from 1 second to 24 hours, although lesser and greater durations can also be employed.
- the entirety of the planarization dielectric layer 70 includes a polycrystalline dielectric metal oxide material after the anneal.
- the average grain size of the polycrystalline dielectric metal oxide material in the planarization dielectric layer 70 after the anneal can be metal oxide material in the planarization dielectric layer 70 can be in a range from 3 nm to 100 nm, although lesser and greater average grain sizes can also be employed.
- an “average grain size” refers to the average lateral dimensions in a random cross-sectional view such as a transmission electron micrographs (TEMs).
- FIGS. 6-11 are subsequently as in the first embodiment to provide a structure that is the same as the first exemplary structure of FIG. 11 except for the differences in the composition of the planarization dielectric layer 70 .
- the planarization dielectric layer 70 includes a polycrystalline dielectric metal oxide instead of an amorphous dielectric metal oxide, the planarization dielectric layer 70 provides greater etch resistance to chemicals employed to remove the disposable gate structures ( 25 , 26 ; See FIG. 6 ) during the at least one etch that forms the at least one gate cavity 39 at the processing step of FIG. 7 .
- silicon nitride or the dielectric material of the planarization dielectric layer 70 is not removed during the formation of the gate cavities 39 at the processing step of FIG.
- the polycrystalline dielectric metal oxide of the planarization dielectric layer 70 is resistant to most etch chemicals including hydrofluoric acid.
- all topmost surfaces of the silicon nitride spacers 52 , the silicon nitride liner 60 , and the planarization dielectric layer 70 are within a horizontal plane that is parallel to the topmost surface of the semiconductor substrate 8 after formation of gate cavities 39 (See FIG. 7 ).
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Abstract
After formation of a silicon nitride gate spacer and a silicon nitride liner overlying a disposable gate structure, a dielectric material layer is deposited, which includes a dielectric material that is not prone to material loss during subsequent exposure to wet or dry etch chemicals employed to remove disposable gate materials in the disposable gate structure. The dielectric material can be a spin-on dielectric material or can be a dielectric metal oxide material. The dielectric material layer and the silicon nitride liner are planarized to provide a planarized dielectric surface in which the disposable gate materials are physically exposed. Surfaces of the planarized dielectric layer is not recessed relative to surfaces of the silicon nitride layer during removal of the disposable gate materials and prior to formation of replacement gate structures, thereby preventing formation of metallic stringers.
Description
- The present disclosure relates to semiconductor structures, and particularly to replacement gate semiconductor structures employing a planarization dielectric layer that is planarized without formation of divots or recesses on a top surface thereof, and methods of manufacturing the same.
- The use of silicon oxide as gate spacers and/or a planarization dielectric layer results in formation of recesses and divots on the planarized top surfaces of the silicon oxide material. For example, in a semiconductor structure employing a silicon oxide gate spacer and a silicon oxide planarization dielectric layer, removal of a disposable gate material in a replacement gate processing scheme results in collateral etch of the top portions of the silicon oxide gate spacer and top portions of the silicon oxide planarization dielectric layer relative to a top surface of another planarization dielectric material such as silicon nitride. Divots and/or recesses are formed above the top surfaces of the recessed portions of the oxide material.
- During deposition of a conductive material for formation of metallic gate structures, such divots and/or recesses are filled with the conductive material. Such residual conductive material filling divots and/or recesses provide a spurious conductive path, causing electrical shorts between various semiconductor devices. Thus, the residual conductive material is a concern for reliability and yield.
- After formation of a silicon nitride gate spacer and a silicon nitride liner overlying a disposable gate structure, a dielectric material layer is deposited, which includes a dielectric material that is not prone to material loss during subsequent exposure to dry or wet etch chemicals employed to remove disposable gate materials in the disposable gate structure. The dielectric material can be a spin-on dielectric material or can be a dielectric metal oxide material. The dielectric material layer and the silicon nitride liner are planarized to provide a planarized dielectric surface in which the disposable gate materials are physically exposed. Surfaces of the planarized dielectric layer is not recessed relative to surfaces of the silicon nitride layer during removal of the disposable gate materials and prior to formation of replacement gate structures, thereby preventing formation of metallic stringers.
- According to an aspect of the present disclosure, a method of forming a semiconductor structure is provided, which includes: forming a disposable gate structure including at least a disposable gate material portion on a semiconductor substrate; forming a silicon nitride gate spacer on sidewalls of the disposable gate structure; forming a silicon nitride liner on the silicon nitride gate spacer and over the disposable gate structure; forming a planarization dielectric layer including a dielectric material on the silicon nitride liner; physically exposing a top surface of the disposable gate material portion by planarizing the planarization dielectric layer and the silicon nitride liner; forming a gate cavity by removing at least the disposable gate material portion, wherein all topmost surfaces of the silicon nitride spacer, the silicon nitride liner, and the planarization dielectric layer are within a horizontal plane; and forming a replacement gate structure by filling the gate cavity with a gate dielectric layer and at least one conductive material and removing portions of the gate dielectric layer and the at least one conductive material from above the horizontal plane.
- According to another aspect of the present disclosure, a semiconductor structure is provided, which includes a gate-level layer located on a semiconductor substrate and complementarily occupied with at least one gate cavity and dielectric material portions, wherein the dielectric material portions include at least one silicon nitride gate spacer laterally surrounding each of the at least one gate cavity, a silicon nitride liner in contact with all outer surfaces of the at least one silicon nitride gate spacer, and a planarization dielectric layer having one or more portions, wherein each portion of the planarization dielectric layer is embedded within a recessed portion of the silicon nitride liner, and wherein all topmost surfaces of the at least one silicon nitride gate spacer, the silicon nitride liner, and the planarization dielectric layer are within a horizontal plane overlying the semiconductor substrate.
-
FIG. 1 is a vertical cross-sectional view of a first exemplary semiconductor structure after formation of a disposable dielectric layer, a disposable gate material layer, and an optional disposable gate cap dielectric layer according to a first embodiment of the present disclosure. -
FIG. 2 is vertical cross-sectional view of the first exemplary semiconductor structure after formation of disposable gate structures and silicon nitride gate spacers according to the first embodiment of the present disclosure. -
FIG. 3 is vertical cross-sectional view of the first exemplary semiconductor structure after formation of a silicon nitride liner according to the first embodiment of the present disclosure. -
FIG. 4 is a vertical cross-sectional view of the first exemplary semiconductor structure after formation of a planarization dielectric layer including a spin-on dielectric material according to the first embodiment of the present disclosure. -
FIG. 5 is a vertical cross-sectional view of the first exemplary semiconductor structure after planarization of the planarization dielectric layer to a topmost surface of the silicon nitride liner according to the first embodiment of the present disclosure. -
FIG. 6 is a vertical cross-sectional view of the first exemplary semiconductor structure after planarization of the planarization dielectric layer, silicon nitride liner, and gate cap dielectric portions according to the first embodiment of the present disclosure. -
FIG. 7 is a vertical cross-sectional view of the first exemplary semiconductor structure after removal of the disposable gate structures according to the first embodiment of the present disclosure. -
FIG. 8 is a vertical cross-sectional view of the first exemplary semiconductor structure after deposition of a contiguous gate dielectric layer and a first work function metallic layer and patterning of the first work function metallic layer according to the first embodiment of the present disclosure. -
FIG. 9 is a vertical cross-sectional view of the first exemplary semiconductor structure after deposition of a second work function metallic layer and a gate conductor layer according to the first embodiment of the present disclosure. -
FIG. 10 is a vertical cross-sectional view of the first exemplary semiconductor structure after formation of replacement gate structures according to the first embodiment of the present disclosure. -
FIG. 11 is a vertical cross-sectional view of the first exemplary semiconductor structure after formation of a contact-level dielectric layer and various contact structures according to the first embodiment of the present disclosure. -
FIG. 12 is a vertical cross-sectional view of a second exemplary semiconductor structure after formation of planarization dielectric layer including a dielectric metal oxide material according to a second embodiment of the present disclosure. - As stated above, the present disclosure relates to replacement gate semiconductor structures employing a planarization dielectric layer that is planarized without formation of divots or recesses on a top surface thereof, and methods of manufacturing the same, which are now described in detail with accompanying figures. Like and corresponding elements mentioned herein and illustrated in the drawings are referred to by like reference numerals. The drawings are not necessarily drawn to scale.
- Referring to
FIG. 1 , a first exemplary semiconductor structure according to a first embodiment of the present disclosure includes asemiconductor substrate 8 that includes asemiconductor material layer 10. Various semiconductor devices including at least one field effect transistor can be subsequently formed on thesemiconductor material layer 10. Thesemiconductor substrate 8 can be a bulk substrate including a bulk semiconductor material constituting thesemiconductor material layer 10 throughout, or a semiconductor-on-insulator (SOI) substrate (not shown) containing a top semiconductor layer that constitutes a semiconductor material layer, a buried insulator layer (not shown) located under the top semiconductor layer, and a bottom semiconductor layer (not shown) located under the buried insulator layer. - Various portions of the semiconductor material in the
semiconductor substrate 8 can be doped with electrical dopants of p-type or n-type at different dopant concentration levels. For example, thesemiconductor substrate 8 may include at least one p-type well (not shown) and/or at least one n-type well (not shown). At least one shallow trench isolation structure (not shown) can be formed to laterally separate various surface regions of thesemiconductor substrate 8. - A
disposable dielectric layer 25L, a disposable gate material layer 27L, and an optional disposable gate cap dielectric layer 29L are deposited on the top surface of thesemiconductor substrate 8. The disposabledielectric layer 25L includes a dielectric material such as a semiconductor oxide, a semiconductor nitride, or a semiconductor oxynitride. For example, the disposabledielectric layer 25L can include silicon oxide, silicon nitride, or silicon oxynitride. - The disposable gate material layer 27L includes a material that can be subsequently removed selective to silicon nitride and selective to dielectric materials of gate spacers and a planarization dielectric layer to be subsequently deposited above the top surface of the
substrate 8. For example, the disposable gate material layer 27L can include a semiconductor material such as silicon, germanium, a silicon germanium alloy, or a compound semiconductor material. Alternately, the disposable gate material layer 27L can include any dielectric material or any metallic material that can be removed selective to the dielectric materials of the gate spacer and the dielectric layer to be subsequently deposited. - Optionally, a disposable gate cap dielectric layer 29L can be deposited on the disposable gate material layer. The disposable gate cap dielectric layer 29L includes a dielectric material such as silicon nitride. The total thickness of the stack of the disposable
dielectric layer 25L, the disposable gate material layer 27L, and the optional disposable gate cap dielectric layer 29L can be from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed. - Referring to
FIG. 2 , the stack of the disposabledielectric layer 25L, the disposable gate material layer 27L, and the optional disposable gate cap dielectric layer 29L is subsequently lithographically patterned to form disposable gate structures. Each disposable gate structure includes adisposable dielectric portion 25, which is a remaining portion of the disposabledielectric layer 25L, and a disposablegate material portion 27, which is a remaining portion of the disposable gate material layer 27L. Each disposable gate structure may optionally include a disposable gate capdielectric portion 29, which is a remaining portion of the disposable gate cap dielectric layer 29L. In one embodiment, thedisposable gate dielectrics 25 can include at least one of silicon oxide and silicon oxynitride and/or the disposablegate material portions 27 can include a semiconductor material. - Silicon
nitride gate spacers 52 are formed on sidewalls of each of the disposable gate structures (25, 27, 29), for example, by deposition of a conformal dielectric material layer and an anisotropic etch. Silicon nitride can be deposited, for example, by chemical vapor deposition (CVD) or atomic layer deposition (ALD). - Masked ion implantation can be performed before and/or after formation of the silicon
nitride gate spacers 52. A masking structure including a combination of a patterned photoresist layer (not shown) and at least one disposable gate structure (25, 27, 29) is employed for each masked ion implantation prior to formation of thegate spacers 52. A masking structure including a combination of a patterned photoresist layer (not shown) and at least one disposable gate structure (25, 27, 29) and at least one siliconnitride gate spacer 52 laterally surrounding each of the at least one disposable gate structure (25, 27, 29) is employed for each masked ion implantation after formation of thegate spacers 52. Multiple patterned photoresists can be employed in combination with multiple ion implantation steps to form various source and drainregions 16, i.e., source regions and drain regions, having different dopant types and/or different dopant concentrations. As used herein, source and drainregions 16 include any source region, any drain region, any source extension region, or any drain extension region as known in the art. - In one embodiment, the disposable
gate material portions 27 include a semiconductor material, and the siliconnitride gate spacers 52 are formed directly on sidewalls of the semiconductor material in thedisposable gate structures 27. - In one embodiment, the disposable gate structures (25, 27, 29) can employ materials other than semiconductor oxide and semiconductor oxynitride. In this case, semiconductor oxide or semiconductor oxynitride is not present above the bottom surface of the disposable
gate material portions 27 after the forming of the disposable gate structures (25, 27, 29). - Referring to
FIG. 3 , asilicon nitride liner 60 is deposited on the siliconnitride gate spacers 52 and over the disposable gate structures (25, 27, 29). Thesilicon nitride liner 60 is a contiguous layer that contacts the entirety of outer sidewall surfaces of the siliconnitride gate spacers 52, the entirety of top surfaces of the disposable gate structures (25, 27, 29), and the entirety of the top surface of thesemiconductor substrate 8 that is not contacted by the siliconnitride gate spacers 52 or the disposable gate structures (25, 27, 29). Thesilicon nitride liner 60 can be deposited, for example, by chemical vapor deposition (CVD). The thickness of thesilicon nitride liner 60 can be from 20 nm to 200 nm, although lesser and greater thicknesses can also be employed. - Referring to
FIG. 4 , aplanarization dielectric layer 70 is formed above thesilicon nitride liner 60. Theplanarization dielectric layer 70 includes a dielectric material other than semiconductor oxide, silicon nitride, and semiconductor oxynitride. If the disposable gate structures (25, 27, 29) can employ materials other than semiconductor oxide and semiconductor oxynitride, no semiconductor oxide or semiconductor oxynitride is present above the plane of the top surface of thedisposable gate dielectrics 25. - The
planarization dielectric layer 70 including a spin-on dielectric material that is etch-resistant to hydrofluoric acid, i.e., a spin-on dielectric material that is not etched by hydrofluoric acid. The spin-on dielectric material of theplanarization dielectric layer 70 can be applied by spin-coating, and is self-planarizing, i.e., forms a planar top surface without application of external force other than gravity. Exemplary spin-on dielectric materials include hydrogen silsesquioxane (HSQ) and methyl silsesquioxane (MSQ). The thickness of theplanarization dielectric layer 70 as measured from above the topmost portions of thesilicon nitride liner 60 can be from 20 nm to 300 nm, although lesser and greater thicknesses can also be employed. - Referring to
FIG. 5 , theplanarization dielectric layer 70 is planarized to a topmost surface of thesilicon nitride liner 60. The planarization of theplanarization dielectric layer 70 can be effected, for example, by a recess etch or chemical mechanical planarization (CMP). The top surface of thesilicon nitride liner 60 can be employed as a stopping layer for the recess etch or for CMP. - Referring to
FIG. 6 . theplanarization dielectric layer 70, thesilicon nitride liner 60, and the disposable gate capdielectric portions 29, if present, are planarized, for example, by chemical mechanical planarization or a non-selective recess etch, to a level at which a top surface of the disposablegate material portions 27 are physically exposed. The physically exposed top surface of the disposablegate material portions 27 may be located at, or below, the topmost surfaces of the disposablegate material portions 27 prior to the planarization of theplanarization dielectric layer 70, thesilicon nitride liner 60, and the disposable gate capdielectric portions 29. - Referring to
FIG. 7 , the remaining portions of the disposable gate structures (25, 27) are removed selective to the materials of theplanarization dielectric layer 70, thesilicon nitride liner 60, and the siliconnitride gate spacers 52. Agate cavity 39 is formed within each volume from which a disposable gate structure (25, 27) is removed. - The formation of the
gate cavities 39 can be effected by at least one etch that does not remove any material from thesilicon nitride liner 60, the siliconnitride gate spacer 52, or theplanarization dielectric layer 70, while removing an entirety of the disposable gate structures (25, 27). A semiconductor surface of thesemiconductor substrate 8 is physically exposed at the bottom of eachgate cavity 39. In one embodiment, the at least one etch can be at least one wet etch that employs hydrofluoric acid (HF) and/or ammonium hydroxide (NH4OH). Silicon nitride or the dielectric material of theplanarization dielectric layer 70 is not removed during the formation of thegate cavities 39. Thus, all topmost surfaces of thesilicon nitride spacers 52, thesilicon nitride liner 60, and theplanarization dielectric layer 70 are within a horizontal plane that is parallel to the topmost surface of thesemiconductor substrate 8. Inner sidewall surfaces of each siliconnitride gate spacer 52 are physically exposed within agate cavity 39. - The first exemplary semiconductor structure includes a gate-level layer 12 located on the semiconductor substrate. The gate-level layer 12 is complementarily occupied with at least one
gate cavity 39 and dielectric material portions. In other words, the gate-level layer 12 consists of the at least onegate cavity 39 and the dielectric material portions. The dielectric material portions include at least one siliconnitride gate spacer 52 laterally surrounding each of the at least onegate cavity 39, thesilicon nitride liner 60 in contact with all outer surfaces of the at least one siliconnitride gate spacer 52, and theplanarization dielectric layer 70 having one or more portions, i.e., in the form of a single contiguous portion or in the form of a plurality of non-contiguous portions that are laterally spaced by at least one of thesilicon nitride liner 60 and one or more siliconnitride gate spacers 52. Each portion of theplanarization dielectric layer 70 is embedded within a recessed portion of thesilicon nitride liner 60, and is laterally contacted by upper portions of thesilicon nitride liner 60. All topmost surfaces of the at least one siliconnitride gate spacer 52, thesilicon nitride liner 60, and theplanarization dielectric layer 70 are within a horizontal plane overlying thesemiconductor substrate 8 and parallel to the top surface of thesemiconductor substrate 8. - Semiconductor oxide or semiconductor oxynitride is not present above the horizontal plane of the bottommost surface of the at least one
gate cavity 39, which coincides with the top surface of thesemiconductor substrate 8. As discussed above, theplanarization dielectric layer 70 includes a spin-on dielectric material such as hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ). - Each of the at least one
gate cavity 39 can overlie a channel of a field effect transistor that includes the various portions of the source and drainregions 16 as the source and the drain of the field effect transistor. In one embodiment, the dielectric material portions can consist of the at least one siliconnitride gate spacer 52, thesilicon nitride liner 60, and theplanarization dielectric layer 70. - Referring to
FIG. 8 , a contiguousgate dielectric layer 32L is deposited in thegate cavities 39 and over the top surfaces of the siliconnitride gate spacers 52, thesilicon nitride liners 60, and theplanarization dielectric layer 70. The contiguousgate dielectric layer 32L can be a high dielectric constant (high-k) material layer having a dielectric constant greater than 3.9. The contiguousgate dielectric layer 32L can include a dielectric metal oxide, which is a high-k material containing a metal and oxygen, and is known in the art as high-k gate dielectric materials. Dielectric metal oxides can be deposited by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), atomic layer deposition (ALD), etc. Exemplary high-k dielectric material include HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfOxNy, ZrOxNy, La2OxNy, Al2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2. The thickness of the contiguousgate dielectric layer 32L, as measured at horizontal portions, can be from 0.9 nm to 6 nm, and preferably from 1.0 nm to 3 nm. The contiguousgate dielectric layer 32L may have an effective oxide thickness on the order of or less than 2 nm. The entirety of the interface between thecontiguous dielectric layer 32L and the horizontal surfaces of the siliconnitride gate spacers 52, thesilicon nitride liners 60, and theplanarization dielectric layer 70 is planar. In one embodiment, an optional interfacial dielectric material layer (not shown) can be formed at the interface layer between the contiguousgate dielectric layer 32L and thesemiconductor material layer 10. The interfacial dielectric material layer can include, for example, silicon oxide and/or silicon oxynitride. - A first work function
metallic layer 34L is deposited on the contiguousgate dielectric layer 32L, and is lithographically patterned to be present with at least onegate cavity 39, while being absent within at least anothergate cavity 39. The first work functionmetallic layer 34L includes a metallic material that can optimize the threshold voltages of transistors. For example, the first work functionmetallic layer 34L can include metallic materials such as Pt, Rh, Ir, Ru, Cu, Os, Be, Co, Pd, Te, Cr, Ni, TiN, Hf, Ti, Zr, Cd, La, Tl, Yb, Al, Ce, Eu, Li, Pb, Tb, Bi, In, Lu, Nb, Sm, V, Zr, Ga, Mg, Gd, Y, and TiAl, conductive nitrides thereof, and alloys thereof. The first work functionmetallic layer 34L can be formed, for example, by physical vapor deposition, chemical vapor deposition, or atomic layer deposition (ALD). The thickness of the first work functionmetallic layer 34L can be from 2 nm to 40 nm, although lesser and greater thicknesses can also be employed. - Referring to
FIG. 9 , a second work functionmetallic layer 36L is deposited on the physically exposed surfaces of the first work functionmetallic layer 34L and the contiguousgate dielectric layer 32L. The second work functionmetallic layer 36L includes a metallic material that can optimize the threshold voltages of transistors. The metallic material of the second work functionmetallic layer 36L can be different from the metallic material of the first work functionmetallic layer 34L. For example, the second work functionmetallic layer 36L can include any metallic material that can be selected for the metallic material of the first work functionmetallic layer 34L. The second work functionmetallic layer 36L can be formed, for example, by physical vapor deposition, chemical vapor deposition, or atomic layer deposition (ALD). The thickness of the second work functionmetallic layer 36L can be from 2 nm to 40 nm, although lesser and greater thicknesses can also be employed. - A
gate conductor layer 40L is deposited over the first and second work function metallic layers (34L, 36L). Thegate conductor layer 40L includes a conductive material, which can be deposited by physical vapor deposition or chemical vapor deposition. For example, thegate conductor layer 40L can be an aluminum layer, an aluminum alloy layer, a tungsten layer, and/or a tungsten alloy layer deposited by physical vapor deposition. The thickness of thegate conductor layer 40L, as measured in a planar region of theconductive metal layer 40L above the topmost surface of the second work functionmetallic layer 36L, can be from 100 nm to 500 nm, although lesser and greater thicknesses can also be employed. In one embodiment, thegate conductor layer 40L can include a single elemental metal such as Al or W or alloys thereof. - Referring to
FIG. 10 , portions of thegate conductor layer 40L, portions of the first and second work function metallic layers (34L, 36L), and portions the contiguousgate dielectric layer 32L are removed from above the top planar surface of theplanarization dielectric layer 70 by performing a planarization process such as chemical mechanical planarization (CMP) and/or a non-selective recess etch. Replacement gate structures are formed within volumes that are previously occupied by disposable gate structures (25, 27, 29; SeeFIGS. 2-6 ). Each replacement gate structure is a gate stack that remains permanently on thesemiconductor substrate 8, i.e., is not disposable. - A
gate dielectric 32, at least one work function metal portion (34, 36), and agate conductor 40 are present with each replacement gate structure. Eachgate dielectric 32 is a remaining portion of the contiguousgate dielectric layer 32L after the planarization process. As discussed above, an optional interfacial dielectric material layer (not shown) can be present at the interface layer between the contiguousgate dielectric layer 32L and thesemiconductor material layer 10. Each first workfunction metal portion 34 is a remaining portion of the first work functionmetallic layer 34L after the planarization process. Each second workfunction metal portion 36 is a remaining portion of the second work functionmetallic layer 36L after the planarization process. Eachgate conductor 40 is a remaining portion of thegate conductor layer 40L after the planarization process. Each replacement gate structure (32, optionally 34, 36, 40) can overlie a channel region of a field effect transistor. A stack of at least one work function metal portion (36 and optionally 34) and agate conductor 40 constitutes a gate electrode (36, optionally 34, 40). - Each
gate dielectric 32 can be a U-shaped gate dielectric contacting the semiconductor material of thesemiconductor material layer 10 and the inner surfaces of a siliconnitride gate spacer 52. Because thegate dielectrics 32 include the same material as the contiguousgate dielectric layer 32L (SeeFIGS. 8 and 9 ), thegate dielectrics 32 can be U-shaped gate dielectrics including a dielectric material having a dielectric constant greater than 3.9. The U-shaped gate dielectrics include vertical portions, which have top surfaces that are coplanar with the top surfaces of thesilicon nitride spacer 52, thesilicon nitride liner 60, and theplanarization dielectric layer 70. - Each work function metal portion (34, 36) can be a U-shaped work function metal portion. A work function metal portion (34, 36) may contact inner surfaces of the vertical portions of the
gate dielectrics 32 and the top surfaces of the horizontal portions of thegate dielectrics 32. Alternately, a second workfunction metal portion 36 may contact inner sidewalls of vertical portions of a first workfunction metal portion 34 and a top surface of a horizontal portion of the first workfunction metal portion 34. Each U-shaped work function metal portion includes vertical portions, which have top surfaces that are coplanar with the top surfaces of thesilicon nitride spacer 52, thesilicon nitride liner 60, and theplanarization dielectric layer 70 and the top surfaces of the vertical portions of the U-shaped gate dielectrics. - Each
gate conductor 40 has a top surface that is coplanar with the top surface of thesilicon nitride spacer 52, thesilicon nitride liner 60, and theplanarization dielectric layer 70, and with the top surfaces of the vertical portions of the U-shaped gate dielectrics, and with the top surfaces of the vertical portions of the U-shaped work function metal portions. - Thus, each replacement gate structure (32, optionally 34, 36, 40) can be formed by filling a
gate cavity 39 with a contiguousgate dielectric layer 32L and at least one conductive material, and removing portions of the contiguousgate dielectric layer 32L and the at least one conductive material from above a horizontal plane that is located at, or below, a plane including top surfaces of the top surfaces of thesilicon nitride spacer 52, thesilicon nitride liner 60, and theplanarization dielectric layer 70. The replacement gate structure (32, optionally 34, 36, 40) includes a U-shaped gate dielectric, i.e., agate dielectric 32, which is in contact with inner sidewalls of a siliconnitride gate spacer 52. The replacement gate structure (32, optionally 34, 36, 40) further includes a gate electrode, which includes at least one conductive material, i.e., the conductive materials of a second workfunction metal portion 36, the conductive material of thegate conductor 40, and optionally the conductive material of a first workfunction metal portion 34. The gate electrode (36, 40, and optionally 34) is in contact with inner sidewalls of the U-shaped gate dielectric. - Referring to
FIG. 11 , a contact-level dielectric layer 90 and various contact structures (94, 96) are formed. The contact-level dielectric layer 90 is deposited on a planar horizontal surface of the replacement gate structures (32, 34, 36, 40), thesilicon nitride spacers 52, thesilicon nitride liner 60, and theplanarization dielectric layer 70, as a blanket layer, i.e., a layer without a pattern. The contact-level dielectric layer 90 includes a dielectric material such as silicon oxide, silicon nitride, and/or porous or non-porous organosilicate glass. The contact-level dielectric layer 90 can be deposited, for example, by chemical vapor deposition (CVD) or spin coating. The thickness of the contact-level dielectric layer 90 can be from 30 nm to 600 nm, although lesser and greater thicknesses can also be employed. - Various contact via holes are formed through the contact-
level dielectric layer 90, for example, by applying and patterning a photoresist (not shown), and transferring the pattern in the photoresist into through the contact-level dielectric layer 90 and optionally through a stack of theplanarization dielectric layer 70 and thesilicon nitride liner 60. The various contact via holes are filled with a conductive material to form various contact via structures, which can include at least one gate-contact viastructure 94 and at least one substrate-contact viastructure 96. - Referring to
FIG. 12 , a second exemplary semiconductor structure according to a second embodiment of the present disclosure can be derived from the first exemplary semiconductor structure ofFIG. 3 by formation ofplanarization dielectric layer 70 that is not self-planarized. Theplanarization dielectric layer 70 includes a dielectric material other than semiconductor oxide, silicon nitride, and semiconductor oxynitride. Thus, a semiconductor oxide or a semiconductor oxynitride is not present above the plane of the top surface of thedisposable gate dielectrics 25 at this processing step. - The
planarization dielectric layer 70 including a dielectric material that is etch-resistant to hydrofluoric acid and/or ammonium hydroxide, i.e., a dielectric material that is not etched by the etchant to be subsequently employed. The dielectric material of theplanarization dielectric layer 70 can be deposited by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), atomic layer deposition (ALD), etc. The dielectric material of theplanarization dielectric layer 70 can be formed by a conformal deposition process, i.e., a deposition process that forms a film having a same thickness on a vertical surface as on a horizontal surface. Exemplary dielectric materials that can be employed for theplanarization dielectric layer 70 include dielectric metal oxides such as HfO2, ZrO2, La2O3, Al2O3, TlO2, SrTiO3, LaAlO3, Y2O3, HfOxNy, ZrOxNy, La2OxNy, Al2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, a silicate thereof, and an alloy thereof. Each value of x is independently from 0.5 to 3 and each value of y is independently from 0 to 2. The thickness of theplanarization dielectric layer 70 as measured from above the topmost portions of thesilicon nitride liner 60 can be from 20 nm to 300 nm, although lesser and greater thicknesses can also be employed. - The dielectric material of the
planarization dielectric layer 70 is deposited as an amorphous material. The second exemplary semiconductor structure is subsequently annealed at an elevated temperature to crystallize the amorphous material of theplanarization dielectric layer 70. The amorphous material of theplanarization dielectric layer 70 as deposited is converted into a polycrystalline dielectric metal oxide during the anneal. The temperature of the anneal can be from 700 degrees Celsius to 1,100 degrees Celsius. In one embodiment, the temperature of the anneal can be greater than 800 degrees Celsius. In one embodiment, the temperature of the anneal can be greater than 900 degrees Celsius. In one embodiment, the temperature of the anneal can be greater than 1,000 degrees Celsius. In one embodiment, the temperature of the anneal can be less than 1,000 degrees Celsius. In one embodiment, the temperature of the anneal can be less than 900 degrees Celsius. In one embodiment, the temperature of the anneal can be less than 800 degrees Celsius. The duration of the anneal at the elevated temperature can be from 1 second to 24 hours, although lesser and greater durations can also be employed. - The entirety of the
planarization dielectric layer 70 includes a polycrystalline dielectric metal oxide material after the anneal. The average grain size of the polycrystalline dielectric metal oxide material in theplanarization dielectric layer 70 after the anneal can be metal oxide material in theplanarization dielectric layer 70 can be in a range from 3 nm to 100 nm, although lesser and greater average grain sizes can also be employed. As used herein, an “average grain size” refers to the average lateral dimensions in a random cross-sectional view such as a transmission electron micrographs (TEMs). - The processing steps of
FIGS. 6-11 are subsequently as in the first embodiment to provide a structure that is the same as the first exemplary structure ofFIG. 11 except for the differences in the composition of theplanarization dielectric layer 70. Because theplanarization dielectric layer 70 includes a polycrystalline dielectric metal oxide instead of an amorphous dielectric metal oxide, theplanarization dielectric layer 70 provides greater etch resistance to chemicals employed to remove the disposable gate structures (25, 26; SeeFIG. 6 ) during the at least one etch that forms the at least onegate cavity 39 at the processing step ofFIG. 7 . As in the first embodiment, silicon nitride or the dielectric material of theplanarization dielectric layer 70 is not removed during the formation of thegate cavities 39 at the processing step ofFIG. 7 because the polycrystalline dielectric metal oxide of theplanarization dielectric layer 70 is resistant to most etch chemicals including hydrofluoric acid. Thus, all topmost surfaces of thesilicon nitride spacers 52, thesilicon nitride liner 60, and theplanarization dielectric layer 70 are within a horizontal plane that is parallel to the topmost surface of thesemiconductor substrate 8 after formation of gate cavities 39 (SeeFIG. 7 ). - While the disclosure has been described in terms of specific embodiments, it is evident in view of the foregoing description that numerous alternatives, modifications and variations will be apparent to those skilled in the art. Each of the various embodiments of the present disclosure can be implemented alone, or in combination with any other embodiments of the present disclosure unless expressly disclosed otherwise or otherwise impossible as would be known to one of ordinary skill in the art. Accordingly, the disclosure is intended to encompass all such alternatives, modifications and variations which fall within the scope and spirit of the disclosure and the following claims.
Claims (18)
1. A method of forming a semiconductor structure comprising:
forming a disposable gate structure comprising at least a disposable gate material portion on a semiconductor substrate;
forming a silicon nitride gate spacer on sidewalls of said disposable gate structure;
forming a silicon nitride liner on said silicon nitride gate spacer and over said disposable gate structure;
forming a planarization dielectric layer on said silicon nitride liner;
physically exposing a top surface of said disposable gate material portion by planarizing said planarization dielectric layer and said silicon nitride liner;
forming a gate cavity by removing at least said disposable gate material portion, wherein all topmost surfaces of said silicon nitride spacer, said silicon nitride liner, and said planarization dielectric layer are within a horizontal plane; and
forming a replacement gate structure by filling said gate cavity with a gate dielectric layer and at least one conductive material and removing portions of said gate dielectric layer and said at least one conductive material from above said horizontal plane.
2. The method of claim 1 , wherein formation of said gate cavity is effected by at least one etch that does not remove any material from said silicon nitride liner or said planarization dielectric layer, while removing an entirety of said disposable gate structure.
3. The method of claim 1 , wherein formation of said gate cavity is effected by at least one wet etch that employs at least one of hydrofluoric acid and ammonium hydroxide.
4. The method of claim 1 , wherein, after said forming of said disposable gate structure and prior to said forming of said gate cavity, no semiconductor oxide is present above a bottom surface of said disposable gate material portion, and no semiconductor oxynitride is present above said bottom surface of said disposable gate material portion.
5. The method of claim 1 , further comprising planarizing said planarization dielectric layer employing a top surface of said silicon nitride liner as a stopping layer prior to said physically exposing said top surface of said disposable gate material portion.
6. The method of claim 1 , wherein said disposable gate material portion comprises a semiconductor material, and said silicon nitride gate spacer is formed directly on sidewalls of said semiconductor material in said disposable gate structure.
7. The method of claim 1 , wherein said planarization dielectric layer comprises a dielectric material other than semiconductor oxide, silicon nitride, and semiconductor oxynitride.
8. The method of claim 7 , wherein said planarization dielectric layer is formed by spin-coating of said dielectric material.
9. The method of claim 8 , wherein said planarization dielectric layer comprises hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ).
10. The method of claim 7 , wherein said planarization dielectric layer is formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).
11. The method of claim 10 , wherein said planarization dielectric layer comprises a dielectric metal oxide material.
12. The method of claim 11 , wherein said dielectric metal oxide material is a polycrystalline dielectric metal oxide material having an average grain size in a range from 3 nm to 100 nm.
13. The method of claim 1 , wherein said disposable gate structure includes a disposable gate dielectric comprising at least one of silicon oxide and silicon oxynitride.
14. The method of claim 13 , wherein said disposable gate material portion comprises a semiconducting material.
15. The method of claim 1 , wherein, after forming of said gate cavity and prior to said forming of said replacement gate structure, no semiconductor oxide is present above a bottommost surface of said silicon nitride liner, and no semiconductor oxynitride is present above said bottommost surface of said silicon nitride liner.
16. The method of claim 1 , wherein said replacement gate structure comprises:
a U-shaped gate dielectric in contact with inner sidewalls of one of said at least one silicon nitride gate spacer; and
a gate electrode comprising said at least one conductive material and in contact with inner sidewalls of said U-shaped gate dielectric.
17. The method of claim 1 , wherein inner sidewall surfaces of said silicon nitride gate spacer are physically exposed within said gate cavity.
18.-25. (canceled)
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Cited By (10)
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US8735272B2 (en) * | 2012-07-31 | 2014-05-27 | GlobalFoundries, Inc. | Integrated circuit having a replacement gate structure and method for fabricating the same |
US8841726B2 (en) * | 2013-01-31 | 2014-09-23 | International Business Machines Corporation | Self-adjusting gate hard mask |
US20150024584A1 (en) * | 2013-07-17 | 2015-01-22 | Global Foundries, Inc. | Methods for forming integrated circuits with reduced replacement metal gate height variability |
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US20180342599A1 (en) * | 2016-08-03 | 2018-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal Gate Formation Through Etch Back Process |
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JP6194516B2 (en) * | 2014-08-29 | 2017-09-13 | 豊田合成株式会社 | MIS type semiconductor device |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6392280B1 (en) * | 2000-10-19 | 2002-05-21 | Advanced Micro Devices, Inc. | Metal gate with PVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process |
US7026256B2 (en) * | 2003-07-24 | 2006-04-11 | Hynix Semiconductor Inc. | Method for forming flowable dielectric layer in semiconductor device |
US20070228425A1 (en) * | 2006-04-04 | 2007-10-04 | Miller Gayle W | Method and manufacturing low leakage MOSFETs and FinFETs |
US20090186458A1 (en) * | 2008-01-23 | 2009-07-23 | Chih-Hao Yu | Method for manufacturing a cmos device having dual metal gate |
US20120264281A1 (en) * | 2011-04-12 | 2012-10-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a plurality of gate structures |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5494700A (en) * | 1994-04-05 | 1996-02-27 | The Curators Of The University Of Missouri | Method of coating a substrate with a metal oxide film from an aqueous solution comprising a metal cation and a polymerizable organic solvent |
US6124640A (en) | 1998-08-31 | 2000-09-26 | Advanced Micro Devices, Inc. | Scalable and reliable integrated circuit inter-level dielectric |
KR100632467B1 (en) | 2005-08-12 | 2006-10-09 | 삼성전자주식회사 | Semiconductor memory device and method for fabricating the same |
US7452766B2 (en) | 2006-08-31 | 2008-11-18 | Micron Technology, Inc. | Finned memory cells and the fabrication thereof |
US8062966B2 (en) | 2008-12-31 | 2011-11-22 | Texas Instruments Incorporated | Method for integration of replacement gate in CMOS flow |
US8367563B2 (en) | 2009-10-07 | 2013-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for a gate replacement process |
US8940388B2 (en) * | 2011-03-02 | 2015-01-27 | Micron Technology, Inc. | Insulative elements |
US9129985B2 (en) * | 2013-03-05 | 2015-09-08 | United Microelectronics Corp. | Semiconductor device having metal gate and manufacturing method thereof |
-
2012
- 2012-02-27 US US13/405,939 patent/US20130221413A1/en not_active Abandoned
-
2014
- 2014-09-15 US US14/486,128 patent/US9356121B2/en not_active Expired - Fee Related
-
2016
- 2016-05-27 US US15/167,013 patent/US9876091B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6392280B1 (en) * | 2000-10-19 | 2002-05-21 | Advanced Micro Devices, Inc. | Metal gate with PVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process |
US7026256B2 (en) * | 2003-07-24 | 2006-04-11 | Hynix Semiconductor Inc. | Method for forming flowable dielectric layer in semiconductor device |
US20070228425A1 (en) * | 2006-04-04 | 2007-10-04 | Miller Gayle W | Method and manufacturing low leakage MOSFETs and FinFETs |
US20090186458A1 (en) * | 2008-01-23 | 2009-07-23 | Chih-Hao Yu | Method for manufacturing a cmos device having dual metal gate |
US20120264281A1 (en) * | 2011-04-12 | 2012-10-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating a plurality of gate structures |
Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8735272B2 (en) * | 2012-07-31 | 2014-05-27 | GlobalFoundries, Inc. | Integrated circuit having a replacement gate structure and method for fabricating the same |
US8841726B2 (en) * | 2013-01-31 | 2014-09-23 | International Business Machines Corporation | Self-adjusting gate hard mask |
US8853084B2 (en) * | 2013-01-31 | 2014-10-07 | International Business Machines Corporation | Self-adjusting gate hard mask |
US20150024584A1 (en) * | 2013-07-17 | 2015-01-22 | Global Foundries, Inc. | Methods for forming integrated circuits with reduced replacement metal gate height variability |
US9653573B2 (en) | 2014-01-30 | 2017-05-16 | International Business Machines Corporation | Replacement metal gate including dielectric gate material |
US9490253B1 (en) | 2015-09-23 | 2016-11-08 | International Business Machines Corporation | Gate planarity for finFET using dummy polish stop |
US9576954B1 (en) | 2015-09-23 | 2017-02-21 | International Business Machines Corporation | POC process flow for conformal recess fill |
US9634005B2 (en) | 2015-09-23 | 2017-04-25 | International Business Machines Corporation | Gate planarity for FinFET using dummy polish stop |
US9941392B2 (en) | 2015-09-23 | 2018-04-10 | International Business Machines Corporation | Gate planarity for FinFET using dummy polish stop |
US10403740B2 (en) | 2015-09-23 | 2019-09-03 | International Business Machines Corporation | Gate planarity for FinFET using dummy polish stop |
US9640633B1 (en) | 2015-12-18 | 2017-05-02 | International Business Machines Corporation | Self aligned gate shape preventing void formation |
US9773885B2 (en) | 2015-12-18 | 2017-09-26 | International Business Machines Corporation | Self aligned gate shape preventing void formation |
US10505016B2 (en) | 2015-12-18 | 2019-12-10 | International Business Machines Corporation | Self aligned gate shape preventing void formation |
US10868138B2 (en) * | 2016-08-03 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate formation through etch back process |
US20180342599A1 (en) * | 2016-08-03 | 2018-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal Gate Formation Through Etch Back Process |
US9704991B1 (en) | 2016-10-31 | 2017-07-11 | International Business Machines Corporation | Gate height and spacer uniformity |
US10586741B2 (en) | 2016-10-31 | 2020-03-10 | International Business Machines Corporation | Gate height and spacer uniformity |
US11031508B2 (en) * | 2017-11-30 | 2021-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with treated interfacial layer on silicon germanium |
US11688812B2 (en) | 2017-11-30 | 2023-06-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with treated interfacial layer on silicon germanium |
Also Published As
Publication number | Publication date |
---|---|
US9876091B2 (en) | 2018-01-23 |
US9356121B2 (en) | 2016-05-31 |
US20150001598A1 (en) | 2015-01-01 |
US20160276457A1 (en) | 2016-09-22 |
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