CN112750818A - 半导体器件及其形成方法 - Google Patents
半导体器件及其形成方法 Download PDFInfo
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- CN112750818A CN112750818A CN202011118370.7A CN202011118370A CN112750818A CN 112750818 A CN112750818 A CN 112750818A CN 202011118370 A CN202011118370 A CN 202011118370A CN 112750818 A CN112750818 A CN 112750818A
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- germanium
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- silicon
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
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Abstract
一种器件包括:半导体区;界面层,位于半导体区上方,该界面层包括半导体氧化物;高k介电层,位于界面层上方;混合层,位于高k介电层上方。混合层包括氧、高k介电层中的金属、以及另外的金属。功函层位于混合层上方。填充金属区位于功函层上方。本申请的实施例还提供半导体器件及其制造方法。
Description
技术领域
本申请的实施例涉及半导体领域,具体地,涉及半导体器件及其形成方法。
背景技术
金属氧化物半导体(MOS)器件是集成电路中的基本构建元件。MOS器件可以具有栅极电极,该栅极电极通过掺杂有p型或者n型杂质的多晶硅形成,该p型或者n型杂质使用诸如离子注入或者热扩散的掺杂工艺来掺杂。栅极电极的功函数可以调整至硅的带边缘。对于n型金属氧化物半导体(NMOS)器件,功函数可以调整至接近硅的导带。对于P型金属氧化物半导体(PMOS)器件,功函数可以调整至接近硅的价带。可以通过选择适当的杂质来实现多晶硅栅极电极的功函数的调整。
具有多晶硅栅极电极的MOS器件呈现出载流子耗尽效应,其也称为多晶硅耗尽效应。当所施加的电场从靠近栅极电介质的栅极区扫除载流子、形成耗尽层时,就会发生多晶硅耗尽效应。在n掺杂的多晶硅层中,耗尽层包括电离的非移动供体位点,其中,在p掺杂的多晶硅层中,耗尽层包括电离的非移动受体位点。耗尽效应导致有效栅极电介质厚度的增加,使得更难以在半导体表面上形成反型层。
可以通过形成金属栅极电极来解决多晶硅耗尽问题,其中,在NMOS器件和PMOS器件中使用的金属栅极也可以具有带边缘功函数。因此,所得到的金属栅极包括多层,以满足NMOS器件和PMOS器件的要求。
金属栅极的形成通常涉及使金属层沉积,然后实施化学机械抛光(CMP)工艺以去除金属层的多余部分。金属层的所剩部分形成金属栅极。
发明内容
本申请的实施例提供了一种器件,包括:半导体区;界面层,位于半导体区上方,界面层包括半导体氧化物;高k介电层,位于界面层上方;混合层,位于高k介电层上方,其中,混合层包括氧、高k介电层中的金属、以及另外的金属;功函层,位于混合层上方;以及填充金属区,位于功函层上方。
本申请的实施例另外提供了一种器件,包括:硅锗鳍部;栅极堆叠件,位于硅锗鳍部上,其中,栅极堆叠件包括:界面层,接触硅锗鳍部;高k介电层,位于界面层上方;混合层,位于高k介电层上方并且接触高k介电层,其中,高k介电层具有第一介电常数,混合层具有第二介电常数,第二介电常数大于第一介电常数;以及氮化钛层,位于混合层上方并且接触混合层;以及源极/漏极区,位于栅极堆叠件的侧部上。
本申请的实施例还提供一种方法,包括:在半导体区上方形成界面层,其中,界面层包括半导体氧化物;在界面层上方沉积高k介电层;在高k介电层上方沉积阻挡层;在阻挡层上沉积金属层;当金属层位于阻挡层上方时实施退火工艺;以及去除金属层。
本申请的实施例提供了缺陷减少的晶体管及其形成方法。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该指出,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1-图6、图7A、图7B、图8A、图8B、图9、图10A、图10B、图11-图18、图23和图24示出了根据一些实施例的在鳍式场效应晶体管(FinFET)的形成中的中间阶段的立体图和截面图;
图19和图20示出了根据一些实施例的FinFET的栅极堆叠件的一些部分的截面图;
图21和图22示出了根据一些实施例的在FinFET的栅极堆叠件的形成中的中间阶段的截面图;
图25至图30示出了根据一些实施例的样品FinFET的结果;
图31和图32分别示出了根据一些实施例的p型和n型晶体管的栅极堆叠件的比较;
图33示出了根据一些实施例的用于形成栅极堆叠件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。另外,本发明可以在各个实例中重复参考数字和/或字母。该重复是出于简化和清楚的目的,其本身并不指示所讨论的各种实施例和/或结构之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以容易地描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
根据各种实施例,提供了具有替换栅极的晶体管及其形成方法。根据一些实施例,示出了晶体管的形成的中间阶段。讨论了一些实施例的一些变型。贯穿各种视图和说明性实施例,相似的附图标记用于指示相似的元件。在示出的示例实施例中,鳍式场效应晶体管(FinFET)的形成用作示例,用以解释本发明的理念。诸如平面晶体管和全栅极(GAA)晶体管的其他类型的晶体管也可以采用本发明的理念。根据本发明的一些实施例,形成硅锗鳍部。在硅锗鳍部上形成包括硅氧化物和锗氧化物的界面层(IL),然后沉积高k介电层。金属层形成在高k介电层上方。实施退火工艺。退火工艺使得IL中的氧原子扩散至金属层中的金属中并且与之键合。另一方面,IL中的锗原子向下扩散至硅锗鳍部中。因此,由于去除了锗氧化物,使得IL变得富含硅。IL也变薄,并且栅极电介质的有效氧化物厚度(EOT)减小。下面的含锗的鳍部变得富含锗,这使得沟道迁移率增加。
图1-图6、图7A、图7B、图8A、图8B、图9、图10A、图10B、图11-图18、图23和图24示出了根据本发明的一些实施例的在鳍式场效应晶体管(FinFET)的形成中的中间阶段的截面图和立体图。这些图所示的工艺也示意性地反映在图33所示的工艺流程200中。
在图1中,提供了衬底20。衬底20可以是半导体衬底,例如体半导体衬底、绝缘体上半导体(SOI)衬底等,其可以是掺杂的(例如,用p型或者n型掺杂剂)或者未掺杂的。半导体衬底20可以是诸如硅晶圆的晶圆10的一部分。通常,SOI衬底是在绝缘体层上形成的半导体材料层。绝缘体层可以是例如氧化物掩埋(BOX)层、氧化硅层等。绝缘层设置在衬底上,该衬底通常为硅衬底或者玻璃衬底。也可以使用其他衬底,例如多层衬底或者梯度衬底。在一些实施例中,半导体衬底20的半导体材料可以包括:硅;锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、和/或GaInAsP;或其组合。
进一步参考图1,在衬底20中形成阱区22。在图33所示的工艺流程200中,相应的工艺示出为工艺202。根据本发明的一些实施例,阱区是n型阱区,其通过将n型杂质注入至衬底20中而形成,n型杂质可以是磷、砷、锑等。根据本发明的其他实施例,阱区22是p型阱区,其通过将p型杂质注入至衬底20中而形成,p型杂质可以是硼、铟等。所得的阱区22可以延伸至衬底20的顶面。n型或者p型杂质浓度可以等于或者小于1018cm-3,例如在约1017cm-3和约1018cm-3之间的范围内。
参考图2,隔离区24形成为从衬底20的顶面延伸至衬底20中。在下文中,隔离区24可替代地称为浅沟槽隔离(STI)区。在图33所示的工艺流程200中,相应的工艺示出为工艺204。在相邻的STI区24之间的衬底20的部分称为半导体条带26。为了形成STI区24,在半导体衬底20上形成衬垫氧化层28和硬掩模层30,然后进行图案化。衬垫氧化物层28可以是通过氧化硅形成的薄膜。根据本发明的一些实施例,在热氧化工艺中形成衬垫氧化物层28,其中氧化了半导体衬底20的顶面层。衬垫氧化物层28充当半导体衬底20和硬掩模层30之间的粘附层。衬垫氧化物层28还可以充当用于蚀刻硬掩模层30的蚀刻停止层。根据本发明的一些实施例,硬掩模层30例如使用低压化学气相沉积(LPCVD)通过氮化硅来形成。根据本发明的其他实施例,硬掩模层30通过硅的热氮化或者等离子体增强化学气相沉积(PECVD)来形成。在硬掩模层30上形成光刻胶(未示出),然后进行图案化。然后,使用图案化的光刻胶作为蚀刻掩模对硬掩模层30进行图案化,以形成如图2所示的硬掩模30。
接下来,将图案化的硬掩模层30用作蚀刻掩模,以蚀刻衬垫氧化物层28和衬底20,然后用(一些)介电材料填充衬底20中的所得沟槽。实施诸如化学机械抛光(CMP)工艺或者机械研磨工艺的平坦化工艺,以去除介电材料的多余部分,并且(一些)介电材料的所剩部分成为STI区24。STI区24可以包括衬垫电介质(未示出),其可以是通过衬底20的表面层的热氧化形成的热氧化物。衬垫电介质还可以是沉积的氧化硅层、氮化硅层等,其使用例如原子层沉积(ALD)、高密度等离子体化学气相沉积(HDPCVD)、或者化学气相沉积(CVD)来形成。STI区24还可以包括位于衬垫氧化物上方的介电材料,其中可以使用可流动化学气相沉积(FCVD)、旋涂等形成介电材料。根据一些实施例,衬垫电介质上方的介电材料可以包括氧化硅。
硬掩模30的顶面和STI区24的顶面可以基本上彼此齐平。半导体条带26位于相邻的STI区24之间。根据本发明的一些实施例,半导体条带26是原始衬底20的一部分,因此半导体条带26的材料与衬底20的材料相同。根据本发明的可替代的实施例,半导体条带26是通过蚀刻STI区24之间的衬底20的部分以形成凹进、以及实施外延以在凹进中再生长另一半导体材料而形成的替换条带。因此,半导体条带26通过与衬底20的材料不同的半导体材料来形成。根据一些实施例,半导体条带26通过诸如硅锗的含锗材料形成。根据一些实施例,突出的鳍部36中的锗原子百分比可以在约30%和约70%之间的范围内。
参考图3,STI区24凹进,以使得半导体条带26的顶部突出为高于STI区24的所剩部分的顶面24A,以形成突出的鳍部36。在图33所示的工艺流程200中,相应的工艺示出为工艺206。可以使用干蚀刻工艺来实施蚀刻,其中,例如将HF3和NH3用作蚀刻气体。在蚀刻工艺期间,可能产生等离子体。也可以包括氩气。根据本发明的可替代的实施例,使用湿蚀刻工艺实施STI区24的凹进。蚀刻化学品可以包括例如HF。
根据本发明的一些实施例,突出的鳍部36通过诸如硅锗的含锗材料来形成。根据可替代的实施例,突出的鳍部36包括硅并且不含锗。可以在同一晶圆中形成包括锗的半导体鳍部和不含锗的半导体鳍部。例如,参考图8B,在晶圆10中,可以存在其中分别要形成n型FinFET和p型FinFET的n型FinFET区21N和p型FinFET区21P。突出的鳍部36A可以是含硅鳍部(不含锗),而突出的鳍部36B可以是硅锗鳍部。在下面的讨论中,除非另有说明,否则突出的鳍部指的是可以通过硅锗形成的突出的鳍部36B。
在如上所示的实施例中,可以通过任何合适的方法来图案化鳍部。例如,可以使用一种或者多种包括双重图案化或者多重图案化工艺的光刻工艺来图案化鳍部。通常,双重图案化或者多重图案化工艺将光刻和自对准工艺相结合,从而允许创建的图案可以是例如所具有的间距小于使用单个直接光刻工艺可获得的间距。例如,在一个实施例中,在衬底上方形成牺牲层,并且使用光刻工艺进行图案化。使用自对准工艺沿着图案化的牺牲层形成间隔件。然后去除牺牲层,然后可以使用所剩的间隔件或者心轴来图案化鳍部。
参考图4,伪栅极堆叠件38形成为在(突出的)鳍部36的顶面和侧壁上延伸。在图33所示的工艺流程200中,相应的工艺示出为工艺208。伪栅极堆叠件38可以包括伪栅极电介质40和位于伪栅极电介质40上方的伪栅极电极42。伪栅极电极42可以例如使用多晶硅形成,并且也可以使用其他材料。每个伪栅极堆叠件38还可以包括位于伪栅极电极42上方的一个(或者多个)硬掩模层44。硬掩模层44可以通过氮化硅、氧化硅、碳氮化硅、或其多层形成。伪栅极堆叠件38可以横跨单个或者多个突出的鳍部36和/或STI区24。伪栅极堆叠件38还具有垂直于突出的鳍部36的长度方向的长度方向。
接下来,在伪栅极堆叠件38的侧壁上形成栅极间隔件46。在图33所示的工艺流程200中,相应的工艺也示出为工艺208。根据本发明的一些实施例,栅极间隔件46通过诸如氮化硅、碳氮化硅等的(一些)介电材料形成,并且可以具有单层结构或者包括多个介电层的多层结构。
然后,实施蚀刻工艺,以蚀刻伪栅极堆叠件38和栅极间隔件46未覆盖的突出的鳍部36的部分,从而得到图5所示的结构。在图33所示的工艺流程200中,相应的工艺示出为工艺210。凹进可以是各向异性的,因此位于伪栅极堆叠件38和栅极间隔件46正下方的鳍部36的部分受到保护,并且未受到蚀刻。根据一些实施例,经过凹进的半导体条带26的顶面可以低于STI区24的顶面24A。相应地形成凹进50。凹进50包括位于伪栅极堆叠件38的相对侧上的部分,以及位于突出的鳍部36的所剩部分之间的部分。
接下来,通过在凹进50中选择性地生长(通过外延)半导体材料来形成外延区(源极/漏极区)54,得到图6的结构。在图33所示的工艺流程200中,相应的工艺示出为工艺212。根据所得的FinFET是p型FinFET还是n型FinFET,随着外延的进行,可以原位掺杂p型或者n型杂质。例如,当所得的FinFET是p型FinFET时,可以生长硅锗硼(SiGeB)、硅硼(SiB)等。相反,当所得的FinFET是n型FinFET时,可以生长硅磷(SiP)、硅碳磷(SiCP)等。根据本发明的可替代的实施例,外延区54包括III-V族化合物半导体,例如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、其组合、或者其多层。在用外延区54填充凹进50之后,外延区54的进一步外延生长使得外延区54水平扩展,并且可以形成小平面。外延区54的进一步生长还可以使得相邻的外延区54彼此融合。可能产生空隙(气隙)56。
图7A示出了在形成接触蚀刻停止层(CESL)58和层间电介质(ILD)60之后的结构的立体图。在图33所示的工艺流程200中,相应的工艺示出为工艺214。CESL 58可以通过氧化硅、氮化硅、碳氮化硅等形成,并且可以使用CVD、ALD等形成。ILD 60可以包括使用例如FCVD、旋涂、CVD、或者另一种沉积方法而形成的介电材料。ILD 60可以通过含氧的介电材料形成,该含氧的介电材料可以是基于诸如氧化硅、磷硅玻璃(PSG)、硼硅玻璃(BSG)、掺硼磷硅玻璃(BPSG)等的材料的硅氧化物。可以实施诸如CMP工艺或者机械研磨工艺的平坦化工艺,以使ILD 60、伪栅极堆叠件38、以及栅极间隔件46的顶面彼此齐平。
图7B示出了图7A中的参考截面7B-7B,其中示出了伪栅极堆叠件38。接下来,如图8A所示,在(一些)蚀刻工艺中去除包括硬掩模层44、伪栅极电极42和伪栅极电介质40的伪栅极堆叠件38,以在栅极间隔件46之间形成沟槽62。在图33所示的工艺流程200中,相应的工艺示出为工艺216。如图8B所示,突出的鳍部36的顶面和侧壁暴露于沟槽62。图8B示出了从图8A中的参考截面8B-8B获得的截面图,其中示出了N型晶体管区21N和p型晶体管区21P二者。另外,如前所述,突出的鳍部36可以包括位于n型FinFET区21N中的含硅鳍部36A(可以不含锗),以及位于p型FinFET区21P中的含锗鳍部36B(可以包括硅锗)。
图9示出了通过氧化工艺分别在突出的鳍部36A和36B上形成IL 64A和64B。在图33所示的工艺流程200中,相应的工艺示出为工艺218。根据一些实施例,氧化工艺包括化学氧化工艺,其通过在化学溶液中接触晶圆来实施,该化学溶液包括臭氧化(O3)去离子化(DI)水、过氧化氢(H2O2)硫酸(H2SO4)、氢氧化铵(NH4OH)等或其组合的一种或者多种的混合物。氧化工艺可以在从室温(例如约21℃)至约80℃的温度范围实施。根据可替代的实施例,氧化工艺包括热氧化工艺,其中晶圆10在包括氧(O2)、臭氧(O3)等的含氧环境中进行退火。IL64A可以包括硅氧化物(SiO2),并且可以不含锗氧化物。IL 64B可以包括硅氧化物和锗氧化物(其也称为硅锗氧化物)。
接下来,如图10A和图10B所示,形成另外的组件以获得填充在沟槽62中(图8A)的替换栅极堆叠件72。图10B示出了图10A中的参考截面10B-10B。替换栅极堆叠件72包括栅极电介质67和相应的栅极电极70。
如图10B所示,栅极电介质67包括IL 64和在IL 64上方形成的高k介电层66。在图33所示的工艺流程200中,高k介电层66的形成工艺示出为工艺220。高k介电层66包括高k介电材料,例如氧化铪、氧化镧、氧化铝、氧化锆等。高k介电材料的介电常数(k值)高于3.9,并且可以高于约7.0,有时高达21.0或者更高。高k介电层66形成为保形层,并且在突出的鳍部36的侧壁以及栅极间隔件46的顶面和侧壁上延伸。根据本发明的一些实施例,高k介电层66使用ALD、CVD、PECVD、分子束沉积(MBD)等形成。
进一步参考图10A和图10B,栅极电极70形成在栅电介质67上。栅极电极70可以包括多个含金属层74和填充金属区76,多个含金属层74可以形成为保形层,填充金属区76填充多个含金属层74未填充的沟槽的其余部分。含金属层74可以包括阻挡层、位于阻挡层上方的一个或者多个功函层、以及位于功函层上方的一个或者多个金属覆盖层。参考图11至图18讨论含金属层74的详细结构,图11至图18示出了根据一些实施例的用于p型FinFET的栅极结构。
图10B示意性地示出了区域78,其中包括鳍部36的一部分、IL 64B的一部分、高k介电层66的一部分、含金属层74的一部分、以及填充金属区76的一部分。图11至图18示出了根据一些实施例的延伸至区域78中的特征的形成。应该理解,高k介电层66、含金属层74、以及填充金属区76可以包括ILD 60和栅极间隔件46的顶部上的水平部分,在平坦化工艺中去除该水平部分以得到图10B所示的结构。
参考图11,IL 64B(也参考图8B)位于突出的鳍部36上。高k介电层66位于IL 64B上方并且接触IL 64B。根据一些实施例,氮化钛硅(TSN)120形成在高k介电层66上方。在图33所示的工艺流程200中,相应的工艺示出为工艺222。TSN层120可以使用ALD或者CVD形成,并且TSN层120可以包括交替沉积的TiN层和SiN层。由于TiN层和SiN层非常薄,因此可能无法将这些层彼此区分开,因此结合起来形成了TSN层。
实施金属化后退火(PMA)工艺122。在图33所示的工艺流程200中,相应的工艺也示出为工艺222。PMA工艺122可以使用炉子退火、快速退火等来实施。PMA工艺122的温度可以在约600℃和约900℃之间的范围内。退火持续时间可以在约2秒和约120秒之间的范围内。PMA工艺122可以用包括NH3、N2、H2、O2等的工艺气体来实施。
图12示出了硅覆盖层124的沉积。在图33所示的工艺流程200中,相应的工艺示出为工艺224。根据一些实施例,硅覆盖层124使用包含硅烷、乙硅烷、二氯硅烷(DCS)等的含硅前体来沉积。在沉积之后,实施封盖后退火(PCA)工艺126。在图33所示的工艺流程200中,相应的工艺也示出为工艺224。PCA工艺可以使用炉子退火、快速退火等来实施。PCA工艺126的温度可以在约650℃和约1,100℃之间的范围内。退火持续时间可以在约2秒和约120秒之间的范围内。PCA工艺126可以用包括NH3、N2、H2、O2等的工艺气体来实施。
接下来,在(一些)蚀刻工艺中去除TSN层120和硅覆盖层124。在图33所示的工艺流程200中,相应的工艺示出为工艺226。所得的结构示出于图13中。TSN层120和硅覆盖层124的沉积、退火和随后的去除可以提高高k介电层66的可靠性及其热稳定性。根据本发明的可替代的实施例,跳过TSN层120和硅覆盖层124的沉积、退火和随后的去除。
图14示出了阻挡层128和金属层130的沉积。在图33所示的工艺流程200中,相应的工艺示出为工艺228和230。根据一些实施例,阻挡层128包括或者可以是TiN层、TaN层、或其复合层。沉积工艺可以包括CVD、ALD等。对金属层130中的金属进行选择,以使其在退火时能够穿透阻挡层128,并且能够形成具有期望特性的混合层,如随后的段落中所述。对金属层130中的金属进行选择,以能够从界面层清除氧而不会在高k介电层中产生额外的空位,从而使得所选择的金属层130的氧化物与SiOx和GeOx相比具有更高的稳定性,而与高k氧化物相比则具有较低的稳定性。根据一些实施例,金属层130包括Al、Ti、Hf、Zr、Ta、Cr、W、V、Mo、或其合金。沉积方法可以包括例如物理气相沉积(PVD)、或者原子层沉积(ALD)、或者等离子体增强原子层沉积(PEALD)、或者化学气相沉积(CVD)。
对阻挡层128的厚度Tl进行选择,从而使得在随后的如图15所示的退火工艺中,阻挡层128的厚度Tl可以起到阻挡金属层130中的金属过度扩散至高k介电层66中的作用,同时允许金属层130中足够量的金属到达阻挡层128和高k介电层66之间的界面以形成混合层。阻挡层128还允许IL 64B和IL 64A中的氧原子向上穿透以到达金属层130。根据一些实施例,厚度T1在约5埃和约40埃之间的范围内。如果厚度T1太大,例如大于约则氧原子不能通过阻挡层128向上扩散,导致破坏随后实施的退火工艺的目的。如果厚度T1太小,例如小于约5埃,则金属层130中的过量金属原子将向下扩散,穿透阻挡层128,并且扩散至高k介电层66中。高k介电层中的金属原子的扩散将因此不利地影响高k介电层66的性能。金属层130的厚度T2可以在约5埃和约150埃之间的范围内。
图15示出了沉积后退火(PDA)工艺132。在图33所示的工艺流程200中,相应的工艺示出为工艺232。PDA工艺可以使用炉子退火、快速退火等来实施。如随后段落中所讨论的,对温度和退火持续时间进行控制,从而实现期望的效果,而不会产生不利影响。例如,如果温度太高和/或退火持续时间太长,则金属层130中的金属会扩散至整个高k介电层66中,从而降低其性能,并且高k膜也会结晶。如果温度太低或者退火时间太短,则不能获得理想的效果。因此,PDA工艺132可以在约400℃和约535℃之间的温度范围内实施。退火持续时间可以在约15秒和约45秒之间的范围内。PDA工艺132可以用包括NH3、N2、H2、O2等的工艺气体来实施。
在PDA工艺132中,IL64B中的锗氧化物在PMOS器件区21P中分解,而IL64A中的硅氧化物在NMOS器件区21N中分解。IL64B中的硅氧化物比锗氧化物更稳定,并且不会分解。IL64B中锗氧化物的这种优先分解导致IL64B中锗原子百分比与硅原子百分比的比值降低。分解的锗氧化物中的氧原子向上扩散至金属层130中,并且与金属层130的底部(或者全部)形成金属氧化物层136。例如,根据金属层130是否包含Al、Ti、Hf、Ta、Cr、W、V、Mo、或者Zr,金属氧化物层136可以分别包括氧化铝、氧化钛、氧化铪或者氧化锆。
在PDA工艺132中,分解的锗氧化物中的锗原子向下扩散至突出的鳍部36的顶面部分中,并且形成富锗层36-S,该富锗层形成相应的晶体管的沟道区的至少一部分。由于额外的锗原子添加至突出的鳍部36的顶面部分中,因此富锗层36-S中的锗原子百分比比突出的鳍部36的原始顶面部分中的锗原子百分比高出ΔC,并且也比突出的鳍部36的下部中的锗原子百分比高出ΔC。原子百分比差ΔC可以在约1%和约4%之间的范围内。富锗层36-S的厚度T3可以在约0.5nm和约1nm之间的范围内。
由于锗氧化物的分解以及锗原子和氧原子的向外扩散,PMOS器件区21P中IL64B的厚度减小。另外,由于硅氧化物的分解和氧原子的向外扩散,NMOS器件区21N中IL64A的厚度减小。例如,在沉积金属层130之前,IL64B或者IL64A(图13)的厚度为T4。在PDA工艺132之后,IL64B和/或IL64A之一或两者的厚度减小至T4′(图15),其在约25%*T4和约80%*T4之间的范围内。例如,T4可以在约10埃和约120埃之间的范围内,而厚度T4′可以在约2埃和约80埃之间的范围内。因此所得栅极电介质的EOT降低。
在PDA工艺132中,混合层134也形成在高k介电层66和阻挡层128的边界区域。混合层134包括来自高k介电层66的金属(例如Hf)、从IL64B扩散的氧、从金属层130扩散的金属、以及来自阻挡层128的金属(例如Ti)。来自金属层130的金属可以与来自高k介电层66中的(一些)金属相同或者不同,并且可以与来自层142A、142B、144、146、和148(图18)中的(一些)金属相同或者不同。根据一些实施例,混合层134包括Mx-Ti-Hf-O,其中Mx是金属层130中的金属。混合层134是介电层,并且可以是富钛、富锆、富铝、或者富铪,取决于金属层130中的金属。混合层134具有一些有利的特征。例如,富钛和富锆的混合层134具有高于高k介电层66的介电常数kHK的介电常数kIM,例如,k值差(kIMkHK)为大于约1,并且可以在约1和8之间的范围内。混合层134具有阻止上覆功函金属层(随后形成)扩散至高k介电层66中的功能,因此改善了高k膜质量、泄漏、以及相应器件的可靠性。而且,富铝的混合层134有助于增强p型偶极子,并且可以降低p型晶体管的电压阈值。富锆的混合层134可以稳定高k介电层66中的四方相,并且可以改善高k介电层66的热稳定性。
图25示出了根据一些实施例的如图15所示的各个层中的一些元素的组成分布。组成分布测量自样品晶圆,其上具有图15中形成的结构。为了便于理解,标记了图示各层中的示例元素。例如,样品结构具有通过Hf形成的金属层130和通过TiN形成的阻挡层128。在图24中,线338、340、342、344、346、348和350分别代表Ge、Si、O、Hf、N、Ti和Al的原子百分比。富锗的SiGe层36-S中的Ge原子百分比(线338)高于SiGe突出的鳍部36中的Ge原子百分比,因此命名为富锗。相应地,富锗的SiGe层36-S中的Si原子百分比(线340)低于SiGe突出的鳍部36中的Si原子百分比。
图25进一步说明,与富锗的SiGe层36-S和突出的鳍部36二者相比,IL层64B的锗硅比明显较低,这清楚地表明锗原子已经向外扩散至富锗的SiGe层36-S。还清楚地显示出,混合层134具有Hf、O、Ti、和Al的高原子百分比。
图26示出了混合层134、高k介电层66和IL 64B、以及突出的鳍部36(包括富锗的SiGe层36-S)中某些元素的原子百分比,其中X轴表示测量自晶圆10的顶面的深度,Y轴表示原子百分比。对元素进行标记。而且,也可以清楚地观察到混合层134。
接下来,蚀刻如图15所示的阻挡层128、金属氧化物层136、和金属层130,并且所得的结构示出于图16中。在图33所示的工艺流程200中,相应的工艺示出为工艺234。蚀刻化学品可以根据金属层130和阻挡层128的材料来选择,并且可以选自NH4OH、HCl、HF、H3PO4、H2O2、H2O、及其组合。例如,当金属层130包括Al、Ti、Hf、和/或Zr时,并且当阻挡层28包括TiN时,蚀刻化学品可以包括NH4OH和HCl中的一者或者两者,并且还包括H2O2和H2O。当金属层130包括Al、Ti、Hf、Ta、Cr、W、V、Mo、和/或Zr时,并且当阻挡层28包括TaN时,蚀刻化学品可以包括HF、NH4OH、H2O2、和H2O的混合物。蚀刻之后,露出混合层134。
图17示出了根据一些实施例的阻挡层142A的沉积。在图33所示的工艺流程200中,相应的工艺示出为工艺236。阻挡层142A有时也称为粘附层,其可以通过TiN、TaN等形成。
在形成阻挡层142A之后,在阻挡层142A上可以存在(或者可以不存在)另一沉积的阻挡层142B。根据其他实施例,没有形成层142A和142B,并且随后形成的功函层144与混合层134接触。
接下来,还如图18所示,功函层144形成在阻挡层142B上方(如果形成)。在图33所示的工艺流程200中,相应的工艺示出为工艺238。功函层144确定栅极的功函数,并且包括至少一层或者通过不同材料形成的多层。根据一些实施例,功函层144可以包括TaN层、位于TaN层上方的TiN层、以及位于TiN层上方的TiAl层。应该理解,功函层可以包括不同的材料,这也是可以预期的。
根据本发明的一些实施例,如图18所示,金属覆盖层146形成在功函层144上方。在图33所示的工艺流程200中,相应的工艺示出为工艺240。根据一些实施例,金属覆盖层146可以通过诸如TiN的金属氮化物形成,并且可以使用诸如TaN的其他材料。层142A、142B、144、和146共同对应于图10B中的堆叠件层74。
图18示出了填充金属区148的形成,其对应于图10B中的填充金属区76。在图33所示的工艺流程200中,相应的工艺示出为工艺242。堆叠件包括混合层134和对应于图10B中的堆叠件层74的上覆层。根据一些实施例,填充金属区148通过钨或者钴形成,其可以使用ALD、CVD等形成。在形成填充金属区148之后,可以实施平坦化工艺,以去除如图18所示的沉积的层的多余部分,从而得到如图10A和图10B所示的栅极堆叠件72。
如上所述,可以形成或者可以不形成扩散阻挡层142A和142B。当不形成扩散阻挡层142A和142B时,所得的栅极堆叠件72如图19所示,其中功函层144位于混合层134上方并且与混合层134物理接触。根据其他实施例,可以形成扩散阻挡层142B,而不形成扩散阻挡层142A。相应的栅极堆叠件72示出于图20,其中功函层144位于扩散阻挡层142B上方并且与扩散阻挡层142B物理接触。
图21和图22示出了根据可替代的实施例的栅极堆叠件72的形成中的中间阶段。除非另有说明,否则这些实施例中的组件的材料和形成工艺与在图1至图18所示的前述实施例中以相同的附图标记表示的相同的组件基本相同。因此,在前面的实施例的讨论中可以找到图21和图22所示的关于组件的形成工艺和材料的细节。
这些实施例的初始步骤基本上与图1-图6、图7A、图7B、图8A、图8B、图9、图10A、图10B、以及图11-图15所示相同。在随后的工艺中,如图15所示,在蚀刻工艺中去除如图15所示的金属层130和金属氧化物层136,而如图21所示,未蚀刻阻挡层128。因此,相应的蚀刻工艺称为局部蚀刻工艺。根据一些实施例,当金属层130包括Al、Ti、Hf、Ta、Cr、W、V、Mo、和/或Zr时,并且当阻挡层128包括TiN时,局部蚀刻化学品可以包括HF、NH4OH、H2O2、和H2O的混合物。当金属层130包括Al、Ti、Hf、Ta,Cr、W、V、Mo、和/或Zr时,并且当阻挡层128包括TaN时,蚀刻化学品可以选自H2O2、H3PO4和H2O的混合物、NH4OH、H2O2和H2O的混合物、HCl、H2O2和H2O的混合物、或者NH4OH、HCl、H2O2和H2O的混合物。在局部蚀刻工艺之后,如图21所示,保留阻挡层128。阻挡层128通过与图18所示的扩散阻挡层142A类似的材料形成,并且具有与扩散阻挡层142A相同的功能。图22示出了上面的扩散阻挡层142B、功函层144、覆盖层146和填充金属148。类似地,可以形成或者可以不形成扩散阻挡层142B。
图23示出了根据一些实施例的硬掩模80的形成。硬掩模80的形成可以包括:实施蚀刻工艺以使栅极堆叠件72凹进从而在栅极间隔件46之间形成凹进、用介电材料填充凹进、然后实施诸如CMP工艺或者机械研磨工艺的平坦化工艺以去除介电材料的多余部分。硬掩模80可以通过氮化硅、氧氮化硅、氧碳氮化硅等形成。
图24示出了源极/漏极接触插塞82的形成。源极/漏极接触插塞82的形成包括:蚀刻ILD60以暴露下面的CESL58的部分、然后蚀刻CESL58的暴露的部分以露出源极/漏极区54。在随后的工艺中,沉积金属层(例如Ti层)并且使其延伸至接触开口中。可以实施金属氮化物覆盖层。然后实施退火工艺,以使金属层与源极/漏极区54的顶部反应,以形成硅化物区84,如图24所示。接下来,要么保留先前形成的金属氮化物层而不将其去除,要么去除先前形成的金属氮化物层,然后沉积新的金属氮化物层(例如氮化钛层)。然后将诸如钨、钴等的填充金属材料填充至接触开口中,随后进行平坦化以去除多余的材料,得到源极/漏极接触插塞82。还将栅极接触插塞(未示出)形成为穿过每个硬掩模80的一部分以接触栅极电极70。从而形成FinFET86,其可以作为一个FinFET并联连接。
图27示出了PMOS器件区21P中的硅的键合能。接近102.8eV的键合能的峰值表示Si-O键,其对应于IL64B。接近于100eV的键合能的峰值表示Si-Si键和/或Si-Ge键,其对应于沟道区。信号强度线152得自使用常规方法形成的第一样品,其中未形成金属层130(图15),并且未实施退火工艺132(图15)。信号强度线154得自根据本发明的一些实施例形成的第二样品,其中形成金属层130(图15),并且实施退火工艺132(图15)。实验结果表明,在接近于102.8eV的键合能的峰值处(图27),线154的信号强度高于线152的信号强度,表明在第二样品的IL中,硅原子百分比与第一样品中的相比增加了,这也意味着由于锗的扩散,IL64B中的锗原子百分比降低了。在接近100eV的键合能的峰值处(图27),线154的信号强度低于线152的信号强度,表明在富锗的SiGe层36-S中,硅原子百分比在第二样品中比在第一样品中降低了,这也意味着锗原子百分比在沟道中增加了。
图28和图29示出了锗的键合能。接近图28中33.5eV和图29中1,222eV的键合能的信号强度表示Ge-O键,其对应于IL64B。接近图28中30eV和图29中1,218eV的键合能的峰值分别表示Ge-Si键和Ge-Ge键,其对应于沟道区。信号强度线156得自使用常规方法形成的第一样品。信号强度线158得自根据本发明的一些实施例形成的第二样品。实验结果表明,接近33.5eV(图28)和1,222eV(图29)的键合能,线158的信号强度低于信号强度线156的信号强度,表明在第二样品的IL中,锗原子百分比降低,表明IL64B中的Ge-O键较少,这是由于从IL中的锗氧化物清除的氧进入金属层130中、以及锗向外扩散至沟道中所致。在接近30eV(图28)和1,218eV(图29)的键合能的峰值处,线158的信号强度高于线156的信号强度,表明在富锗的SiGe层36-S中,锗原子百分比增加。
图30示出了NMOS器件区21N中的硅的键合能。接近102.8eV的键合能的峰值表示Si-O键,其对应于IL64A。接近100eV的键合能的峰值表示Si-Si键,其对应于Si沟道区。信号强度线160得自使用常规方法形成的第一样品,其中未形成金属层130(图15),并且未实施退火工艺132(图15)。信号强度线162得自根据本发明的一些实施例形成的第二样品,其中形成金属层130(图15),并且实施退火工艺132(图15)。实验结果表明,在接近102.8eV的键合能的峰值处(图30),线162的信号强度低于线160的信号强度,表明在第二样品的IL 64A中,硅原子百分比与第一样品中的相比减少了,这也意味着IL64A的厚度减小了。
图31示出了根据一些实施例的低电压p型晶体管、标准电压p型晶体管和高电压p型晶体管的堆叠方案的比较。这些器件的不同之处在于其是否包括扩散阻挡层142A(或者128)和142B。这些晶体管的形成可以共享用于形成富锗的SiGe层64、IL 66、混合层134、和功函层144的通用工艺。为了针对不同的晶体管不同地形成扩散阻挡层142A和142B,第一扩散阻挡层142A可以形成在所有三个晶体管区域中,然后将其从低电压和标准电压晶体管区域中去除。接下来,第二扩散阻挡层142B可以形成在所有三个晶体管区域中,然后将其从低电压晶体管区域中去除。薄IL层64B包括富硅和锗缺乏氧化物,并且功函层144包括P型功函金属。另外,富锗的SiGe层36-S形成在所有三个晶体管区域中。
图32示出了根据一些实施例的低电压n型晶体管、标准电压n型晶体管和高电压n型晶体管的堆叠方案的比较。这些器件的不同之处在于其是否包括扩散阻挡层142A(或者128)和142B。对应的IL包括薄的硅氧化物64A,并且功函层包括n型功函金属。在所有三个晶体管区域的沟道中没有形成富锗层。
本发明的实施例具有一些有利特征。通过在n型晶体管的栅极的形成期间形成金属层并且对该金属层进行退火,可以从包括硅氧化物的IL中去除氧。通过在p型晶体管的栅极的形成期间形成金属层并且对该金属层进行退火,可以从包括硅氧化物和锗氧化物的IL中去除氧。锗也扩散至下面的沟道中。因此,IL中锗氧化物的量减少了。锗氧化物的稳定性不如硅氧化物,并且容易与氧结合形成一氧化锗,并且呈气态并且可能蒸发,导致在IL中留下空位。另外,与硅氧化物或者高k氧化物相比,锗氧化物中的氧空位形成能更低。因此,IL中的锗氧化物会导致过多的缺陷。因此,锗氧化物的减少使得IL中的缺陷减少以及p型晶体管中的界面陷阱的密度减少。IL也在n型晶体管和p型晶体管二者中变薄,并且栅极电介质的EOT降低。扩散至沟道区中的锗使得对于p型晶体管迁移率在沟道中达到理想的增长。另外,形成具有高k值和其他有利特征的混合层。
根据本发明的一些实施例,一种器件包括:半导体区;界面层,位于半导体区上方,该界面层包括半导体氧化物;高k介电层,位于界面层上方;混合层,位于高k介电层上方,其中,该混合层包括氧、高k介电层中的金属、以及另外的金属;功函层,位于混合层上方;以及填充金属区,位于功函层上方。在一个实施例中,另外的金属选自铝、钛、铪、锆、铬、钽、钨、钒、钼、及其组合组成的组。在一个实施例中,半导体区包括:下部,包括具有第一锗原子百分比的硅锗;以及上部,位于下部上方并且接触下部,其中,上部包括具有第二锗原子百分比的硅锗,第二锗原子百分比大于第一锗原子百分比。在一个实施例中,上部具有在约0.5nm和约1nm之间的范围内的厚度。在一个实施例中,第二锗原子百分比大于第一锗原子百分比一个差值,并且该差值在约1%和约4%之间的范围内。在一个实施例中,功函层接触混合层。在一个实施例中,该器件还包括:氮化钛层,位于混合层和填充金属区之间。在一个实施例中,界面层、高k介电层、混合层、功函层、以及填充金属区形成晶体管的栅极堆叠件。
根据本发明的一些实施例,一种器件,包括:半导体区;界面层,位于半导体区上方,界面层包括半导体氧化物;高k介电层,位于界面层上方;混合层,位于高k介电层上方,其中,混合层包括氧、高k介电层中的金属、以及另外的金属;功函层,位于混合层上方;以及填充金属区,位于功函层上方。在一个实施例中,半导体区包括:下部,包括具有第一锗原子百分比的硅锗;以及上部,位于下部上方并且接触下部,其中,上部包括具有第二锗原子百分比的硅锗,第二锗原子百分比大于第一锗原子百分比。在一个实施例中,界面层中的锗原子百分比与硅原子百分比的第一比值低于半导体区的上部中的锗原子百分比与硅原子百分比的第二比值,并且低于半导体区的下部中的锗原子百分比与硅原子百分比的第三比值。
根据本发明的一些实施例,一种器件包括:硅锗鳍部;栅极堆叠件,位于硅锗鳍部上,其中,栅极堆叠件包括:界面层,接触硅锗鳍部;高k介电层,位于界面层上方;混合层,位于高k介电层上方并且接触高k介电层,其中,高k介电层具有第一介电常数,混合层具有第二介电常数,第二介电常数大于第一介电常数;氮化钛层,位于混合层上方并且接触混合层;以及源极/漏极区,位于栅极堆叠件的侧部上。在一个实施例中,混合层包括的金属不同于高k介电层中的以及栅极堆叠件中和混合层上覆的层中的金属。在一个实施例中,混合层包括氧和金属,该金属选自铝、钛、铪、锆、及其组合组成的组。在一个实施例中,硅锗鳍部包括:下部,具有第一锗原子百分比;以及上部,位于下部上方并且接触下部,其中,上部具有第二锗原子百分比,该第二锗原子百分比高于第一锗原子百分比。在一个实施例中,在下部和上部之间的界面处,存在从第一锗原子百分比至第二锗原子百分比的突然增加。在一个实施例中,硅锗鳍部、栅极堆叠件、以及源极/漏极区是p型晶体管的一部分。
根据本发明的一些实施例,一种方法包括:在半导体区上方形成界面层,其中,界面层包括半导体氧化物;在界面层上方沉积高k介电层;在高k介电层上方沉积阻挡层;在阻挡层上沉积金属层;当金属层位于阻挡层上方时实施退火工艺;以及去除金属层。在一个实施例中,通过退火工艺在阻挡层和高k介电层之间形成混合层。在一个实施例中,该方法还包括:去除阻挡层;在去除阻挡层之后形成功函层;以及在功函层上方形成含金属的覆盖层。在一个实施例中,该方法还包括:在阻挡层上方形成功函层。在一个实施例中,沉积金属层包括:沉积的金属选自铝、钛、铪、锆、及其组合组成的组。在一个实施例中,退火工艺在约400℃和约535℃之间的温度范围内实施。
前面概述了若干实施例的特征,使得本领域的技术人员可以更好地理解本公开的各个方面。本领域的技术人员应该理解,他们可以容易地使用本公开作为用于设计或修改用于执行与本公开相同或类似的目的和/或实现相同或类似优点的其他工艺和结构的基础。本领域的技术人员还应该意识到,这种等效结构不背离本公开的精神和范围,并且可以进行各种改变、替换和变更而不背离本公开的精神和范围。
Claims (10)
1.一种半导体器件,包括:
半导体区;
界面层,位于所述半导体区上方,所述界面层包括半导体氧化物;
高k介电层,位于所述界面层上方;
混合层,位于所述高k介电层上方,其中,所述混合层包括氧、所述高k介电层中的金属、以及另外的金属;
功函层,位于所述混合层上方;以及
填充金属区,位于所述功函层上方。
2.根据权利要求1所述的半导体器件,其中,所述另外的金属选自铝、钛、铪、锆、铬、钨、钒、钼、及其组合组成的组。
3.根据权利要求1所述的半导体器件,其中,所述半导体区包括:
下部,包括具有第一锗原子百分比的硅锗;以及
上部,位于所述下部上方并且接触所述下部,其中,所述上部包括具有第二锗原子百分比的硅锗,所述第二锗原子百分比大于所述第一锗原子百分比。
4.根据权利要求3所述的半导体器件,其中,所述上部具有在0.5nm和1nm之间的范围内的厚度。
5.根据权利要求3所述的半导体器件,其中,所述第二锗原子百分比大于所述第一锗原子百分比一个差值,并且所述差值在1%和4%之间的范围内。
6.根据权利要求3所述的半导体器件,其中,所述界面层中的锗原子百分比与硅原子百分比的第一比值低于所述半导体区的所述上部中的锗原子百分比与硅原子百分比的第二比值,并且低于所述半导体区的所述下部中的锗原子百分比与硅原子百分比的第三比值。
7.根据权利要求1所述的半导体器件,其中,所述功函层接触所述混合层。
8.根据权利要求1所述的半导体器件,还包括:氮化钛层,位于所述混合层和所述填充金属区之间。
9.一种半导体器件,包括:
硅锗鳍部;
栅极堆叠件,位于所述硅锗鳍部上,其中,所述栅极堆叠件包括:
界面层,接触所述硅锗鳍部;
高k介电层,位于所述界面层上方;
混合层,位于所述高k介电层上方并且接触所述高k介电层,其中,所述高k介电层具有第一介电常数,所述混合层具有第二介电常数,所述第二介电常数大于所述第一介电常数;以及
氮化钛层,位于所述混合层上方并且接触所述混合层;以及源极/漏极区,位于所述栅极堆叠件的侧部上。
10.一种形成半导体器件的方法,包括:
在半导体区上方形成界面层,其中,所述界面层包括半导体氧化物;
在所述界面层上方沉积高k介电层;
在所述高k介电层上方沉积阻挡层;
在所述阻挡层上沉积金属层;
当所述金属层位于所述阻挡层上方时实施退火工艺;以及
去除所述金属层。
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KR20210053118A (ko) | 2021-05-11 |
US20210134974A1 (en) | 2021-05-06 |
KR102373065B1 (ko) | 2022-03-11 |
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