CN115346915A - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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CN115346915A
CN115346915A CN202110527033.1A CN202110527033A CN115346915A CN 115346915 A CN115346915 A CN 115346915A CN 202110527033 A CN202110527033 A CN 202110527033A CN 115346915 A CN115346915 A CN 115346915A
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layer
semiconductor device
manufacturing
surface treatment
substrate
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林雨谦
赖威壮
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN202110527033.1A priority Critical patent/CN115346915A/zh
Priority to US17/353,547 priority patent/US20220367182A1/en
Publication of CN115346915A publication Critical patent/CN115346915A/zh
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Abstract

本发明提供一种半导体器件的制造方法，包括：对第一氧化硅层进行化学机械抛光工艺，以形成平坦表面层；对所述平坦表面层进行表面处理，以形成经处理的平坦层；以及在所述经处理的平坦层上形成第二氧化硅层。

Description

半导体器件的制造方法
技术领域
本发明涉及一种集成电路的制造方法，尤其是涉及一种半导体器件的制造方法。
背景技术
化学机械抛光工艺是半导体工艺中非常重要的平坦化技术。然而，介电层经由平坦化之后，其与上覆层之间的粘着性不佳，常有膜龟裂或是脱层的问题。
发明内容
本发明是针对一种半导体器件的制造方法，可以提升经化学机械抛光工艺平坦化的平坦表面层与上覆层之间的粘着性，改善膜龟裂或是脱层的问题。
根据本发明的实施例，一种半导体器件的制造方法，包括：对第一氧化硅层进行化学机械抛光工艺，以形成平坦表面层；对所述平坦表面层进行表面处理，以形成经处理的平坦层；以及在所述经处理的平坦层上形成第二氧化硅层。
在根据本发明的实施例中，所述表面处理包括氧气、氢气或是氨气等离子处理。
在根据本发明的实施例中，对所述平坦表面层进行所述表面处理以及在所述经处理的平坦层上形成所述第二氧化硅层是在原位进行。
在根据本发明的实施例中，对所述平坦表面层进行所述表面处理以及在所述经处理的平坦层上形成所述第二氧化硅层是在非原位进行。
本发明的另一实施例还针对一种半导体器件的制造方法，包括在第一衬底上形成内连结构；在所述内连上形成第一材料层；在第一材料层上形成第一介电层；对所述第一介电层进行平坦化工艺，以形成平坦表面层；对所述平坦表面层进行第一表面处理，以形成经处理的平坦层；在所述经处理的平坦层上形成第二介电层，其中所述第一衬底、所述内连结构、所述第一材料层、所述第一介电层、所述经处理的平坦层以及所述第二介电层形成第一半导体晶片；以及将第二半导体晶片结合到所述第一半导体晶片。
在根据本发明的实施例中，所述平坦化工艺含有氢氧化四甲基铵(TMAH)以及富含氨的研浆的化学机械抛光工艺。
在根据本发明的实施例中，所述第一表面处理包括氧气、氢气或是氨气等离子处理。
在根据本发明的实施例中，所述的半导体器件的制造方法还包括在所述内连上形成所述第一材料层之前对所述内连进行第二表面处理。
在根据本发明的实施例中，所述第二表面处理包括使用氢气等离子处理。
在根据本发明的实施例中，将所述第二衬底结合到所述第一衬底包括将所述第二衬底上的第二材料层结合到所述第一衬底上的所述第二介电层。
在根据本发明的实施例中，所述的第一介电层与所述第二介电层包括氧化硅层，所述第一材料层与所述第二材料层包括碳氮化硅层。
在根据本发明的实施例中，，对所述平坦表面层进行所述第一表面处理以及在所述经处理的平坦层上形成所述第二氧化硅层是在原位进行。
在根据本发明的实施例中，对所述平坦表面层进行所述第一表面处理以及在所述经处理的平坦层上形成所述第二氧化硅层是在非原位进行。
基于上述，本发明实施例的半导体器件的制造方法可以提升经化学机械抛光工艺平坦化的平坦表面层与上覆层之间的粘着性，避免脱层的问题。
附图说明
图1A至图1H是本发明的实施例的一种半导体器件的制造方法的截面示意图；
图2是本发明的实施例的一种半导体器件的局部截面示意图。
附图标记说明
10：器件层
11：接触件
13：内层介电层
12、28：导线
14、18、24：层间介电层
16：刻蚀停止层
20、22：硬掩模层
26：介层窗
30、32、34：阻障层
100：衬底
102：内连结构
103、108：表面处理
104、114：材料层
106、110：介电层
106a：平坦表面层
106b：表层
106c：经处理的平坦层
100W、200W：半导体晶片
100a、200a：管芯
300：堆叠结构
300a：堆叠的管芯
具体实施方式
现将详细地参考本发明的示范性实施例，示范性实施例的实例说明于附图中。只要有可能，相同元件符号在图式和描述中用来表示相同或相似部分。
请参照图1A与图2，提供衬底100。衬底100可以是掺杂硅衬底、未掺杂硅衬底、绝缘体上覆硅(SOI)衬底或外延衬底。掺杂硅的掺质可以为P型掺质、N型掺质或其组合。在衬底100内还可形成隔离结构(未示出)，以在衬底100中界定出有源区。衬底100上或衬底100中可形成器件层10。器件层10可以包括有源器件或无源器件。有源器件例如是PMOS、NMOS、CMOS、JFET、BJT或二极管等器件。无源器件例如是电感、电容等。
请参照图1A与图2，在衬底100上形成内连结构102。内连结构102包括内层介电层13、接触件11、导线12、刻蚀停止层16、层间介电层14、18、24、介层窗26、最顶层的导线28、硬掩模层20、22等构件。在一些实施例中，导线12与接触件11还包括其他的导线、层间介电层以及介层窗，但未示出。接触件11、导线12、28与介层窗26可以彼此电连接，且与器件层10之中的器件电连接。导线12、28与介层窗26的材料包括掺杂多晶硅或金属。金属例如是铜、钨或铜铝合金等。在一些实施例中，导线12、28与介层窗11、26还可以包括阻障层30、32、34。导线28与介层窗26可以经由双重金属镶嵌的工艺形成，但不以此为限。内层介电层13与层间介电层14、18、24可以例如是氧化硅，形成的方法例如是化学气相沉积法或旋涂法等。在一些实施例中，层间介电层14与层间介电层14可以采用介电常数低于4的低介电常数材料。内层介电层13与层间介电层14、18、24可以经由化学机械抛光法或回刻蚀法平坦化。刻蚀停止层16例如是氮化硅或氮氧化硅。硬掩模层20例如是氮氧化硅。硬掩模层22例如是氮化硅。刻蚀停止层16与硬掩模层20、20可以以化学气相沉积法来形成。
为了简要起见，在图1A至图1H中省略了器件层10并省略了内连结构102的部分构件。在图1A至图1H中示出内连结构102的最顶层的导线28以及层间介电层24。
请参照图1B，对内连结构102进行表面处理103。表面处理103可以移除最顶层的28的表面上的氧化物，例如氧化铜，或是杂质。表面处理103使用的气体包括氢气。表面处理103可以在沉积机台或是刻蚀机台中进行。在一实施例中，表面处理103是在含有等离子的机台中进行，例如是等离子增强型化学气相沉积机台。在一示例实施例中，使用氢气作为等离子的气体源，气体的流量为200sccm至500sccm，温度为350℃至450℃，压力为4托至7托，反应的时间为5秒至30秒。
请参照图1B，在内连结构102上形成材料层104。材料层104包括介电材料，例如是碳氮化硅(SiCN)、氮化硅(SiN)或氮氧化硅(SiON)。材料层104可以是单层或是多层。材料层104的形成方法例如是等离子增强型化学气相沉积法。材料层104与表面处理103可以在相同的机台中原位(in situ)进行，或是在不同的机台中非原位(ex situ)进行。材料层104的厚度例如是200埃至500埃。
之后，在材料层104上形成介电层106。介电层106的材料不同于材料层104。介电层106可以是单层或是多层。介电层106例如是氧化硅层，例如是未掺杂硅玻璃(USG)。介电层106的形成方法例如是等离子增强型化学气相沉积法。介电层106的厚度例如是12000埃至16000埃。
请参照图1C，对介电层106进行平坦化工艺，以形成平坦表面层106a。在一些实施例中，平坦表面层106a的厚度例如是6500埃至12500埃。平坦化工艺例如是化学机械平坦化工艺。在一实施例中，化学机械平坦化工艺采用具有氢氧化四甲基铵(TMAH)以及富含氨(NH3rich)的研浆。在一些情况下，这些研浆与介电层106作用，使得氮吸附在平坦表面层106a的表面或与平坦表面层106a的表面反应，而形成表层106b。因此，平坦表面层106a的表层106b的氮含量高于平坦表面层106a的内层的氮含量。
平坦表面层106a的表层106b的氮含量高，若不移除，很容易在后续堆叠结构(图1G)形成之后导致龟裂、脱层等问题。因此，在本发明实施例中，在进行平坦化工艺后，还进行表面处理108，以移除或减少平坦表面层106a的表层106b中所含的氮，以形成经处理的平坦层106c，如图1C所示。经处理的平坦层106c的表面的氮含量低于平坦表面层106a的表层106b的氮含量。
表面处理108可以在沉积机台或是刻蚀机台中进行。在一实施例中，表面处理108是在含有等离子的机台中进行，例如是等离子增强型化学气相沉积机台或是等离子刻蚀机台(例如lam机台)。在一示例实施例中，使用氧气、氢气或是氨气作为等离子的气体源，气体的流量为500sccm至1000sccm，温度为350℃至450℃，压力为4托至7托，反应的时间为5秒至30秒。表面处理108可以在后续用来形成介电层110(如图1E所示)的机台中原位进行，或是在不同的机台中非原位进行。
请参照图1E，在经处理的平坦层106c上形成介电层110。介电层110的材料包括可以是单层或是多层。介电层106例如是氧化硅层，例如是未掺杂硅玻璃。介电层106的厚度例如是800埃至1200埃。如上所述，介电层110与上述的表面处理108可以在相同的机台中原位进行，或是在不同的机台中非原位进行。
请参照图1F，在介电层110上形成材料层114。材料层114的材料包括介电材料，例如是碳氮化硅(SiCN)、氮化硅(SiN)或氮氧化硅(SiON)。材料层114可以是单层或是多层。材料层114的形成方法例如是等离子增强型化学气相沉积法。材料层114的材料与介电层110的材料相异。材料层114和材料层104具有相同或是相异材料。材料层114的厚度例如是200埃至500埃。
接着，请参照图1G，提供半导体晶片200W。半导体晶片200W包括衬底200与材料层204。衬底200可以包括可以是掺杂硅衬底、未掺杂硅衬底、绝缘体上覆硅(SOI)衬底或外延衬底。掺杂硅的掺质可以为P型掺质、N型掺质或其组合。在衬底200内还可形成隔离结构(未示出)，以在衬底200中界定出有源区。衬底200上或衬底200中可形成器件层(未示出)。器件层(未示出)可以包括有源器件或无源器件。有源器件例如是PMOS、NMOS、CMOS、JFET、BJT或二极管等器件。无源器件例如是电感、电容等。衬底200上还可以包括内连结构(未示出)。内连结构包括内层介电层、接触件、导线、刻蚀停止层、层间介电层、介层窗、最顶层的导线、硬掩模层等构件。
半导体晶片200W还包括材料层204位于衬底200的内连结构上。材料层204的材料包括介电材料，例如是碳氮化硅(SiCN)、氮化硅(SiN)、氮氧化硅(SiON)或氧化硅。材料层204可以是单层或是多层。材料层204的形成方法例如是化学气相沉积法。材料层204的材料与材料层114的材料可以相同或相异。
接着，以材料层204以及材料层114作为结合层，通过材料层204与材料层114的结合工艺，以使得半导体晶片200W与半导体晶片100W(包括衬底100、内连结构102、介电层106a、介电层110、材料层114)结合，以形成堆叠结构300。
请参照图1H，在一些实施例中，进一步将堆叠结构300切割成多个堆叠的管芯300a。堆叠的管芯300a包括管芯100a以及管芯200a。管芯100a例如是逻辑管芯，管芯200a例如是感测管芯或内存管芯。
以上的实施例是以晶片与晶片之间(wafer-to-wafer)的结合来说明。然而，本发明实施例并不限于此。本发明的实施例也可以包含管芯与晶片之间(die-to-wafer)的结合。
本发明实施例的半导体器件的制造方法，在化学机械抛光工艺平坦化之后，对平坦表面层进行表面处理，可以增加经处理的平坦层与上覆的介电层之间的粘着性，改善膜龟裂或是脱层的问题脱层的问题。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (14)

1.一种半导体器件的制造方法，其特征在于，所述方法包括：
对第一氧化硅层进行化学机械抛光工艺，以形成平坦表面层；
对所述平坦表面层进行表面处理，以形成经处理的平坦层；以及
在所述经处理的平坦层上形成第二氧化硅层。
2.根据权利要求1所述的半导体器件的制造方法，其中所述化学机械抛光工艺使用含有氢氧化四甲基铵以及富含氨的研浆。
3.根据权利要求2所述的半导体器件的制造方法，其中所述表面处理包括氧气、氢气或是氨气等离子处理。
4.根据权利要求1所述的半导体器件的制造方法，其中对所述平坦表面层进行所述表面处理以及在所述经处理的平坦层上形成所述第二氧化硅层是在原位进行。
5.根据权利要求1所述的半导体器件的制造方法，其中对所述平坦表面层进行所述表面处理以及在所述经处理的平坦层上形成所述第二氧化硅层是在非原位进行。
6.一种半导体器件的制造方法，其特征在于，所述方法包括：
在第一衬底上形成内连结构；
在所述内连结构上形成第一材料层；
在第一材料层上形成第一介电层；
对所述第一介电层进行平坦化工艺，以形成平坦表面层；
对所述平坦表面层进行第一表面处理，以形成经处理的平坦层；
在所述经处理的平坦层上形成第二介电层，其中所述第一衬底、所述内连结构、所述第一材料层、所述第一介电层、所述经处理的平坦层以及所述第二介电层形成第一半导体晶片；以及
将第二半导体晶片结合到所述第一半导体晶片。
7.根据权利要求6所述的半导体器件的制造方法，其中所述平坦化工艺包括使用含有氢氧化四甲基铵以及富含氨的研浆的化学机械抛光工艺。
8.根据权利要求7所述的半导体器件的制造方法，其中所述第一表面处理包括氧气、氢气或是氨气等离子处理。
9.根据权利要求8所述的半导体器件的制造方法，还包括在所述内连上形成所述第一材料层之前对所述内连进行第二表面处理。
10.根据权利要求9所述的半导体器件的制造方法，其中所述第二表面处理包括使用氢气等离子处理。
11.根据权利要求10所述的半导体器件的制造方法，其中将所述第二衬底结合到所述第一衬底包括将所述第二衬底上的第二材料层结合到所述第一衬底上的所述第二介电层。
12.根据权利要求11所述的半导体器件的制造方法，其中所述的第一介电层与所述第二介电层包括氧化硅层，所述第一材料层与所述第二材料层包括碳氮化硅层。
13.根据权利要求6所述的半导体器件的制造方法，其中对所述平坦表面层进行所述第一表面处理以及在所述经处理的平坦层上形成所述第二氧化硅层是在原位进行。
14.根据权利要求6所述的半导体器件的制造方法，其中对所述平坦表面层进行所述第一表面处理以及在所述经处理的平坦层上形成所述第二氧化硅层是在非原位进行。
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