CN105845725B - 一种半导体器件及其制造方法和电子装置 - Google Patents

一种半导体器件及其制造方法和电子装置 Download PDF

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CN105845725B
CN105845725B CN201510014336.8A CN201510014336A CN105845725B CN 105845725 B CN105845725 B CN 105845725B CN 201510014336 A CN201510014336 A CN 201510014336A CN 105845725 B CN105845725 B CN 105845725B
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layer
interlayer dielectric
dielectric layer
stressor layers
manufacturing
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CN105845725A (zh
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曾以志
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to US14/962,315 priority patent/US9768167B2/en
Publication of CN105845725A publication Critical patent/CN105845725A/zh
Priority to US15/676,354 priority patent/US10157919B2/en
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供一种半导体器件及其制造方法和电子装置，包括：提供半导体衬底，在所述半导体衬底上形成有多个鳍片，以及位于每个所述鳍片顶面上的应力层；沉积形成接触孔蚀刻停止层，以覆盖所述半导体衬底的表面、所述鳍片的侧壁以及所述应力层的顶面和侧壁；形成第一层间介电层，以填充相邻鳍片之间的间隙，在所述第一层间介电层中形成有填充空洞；回蚀刻所述第一层间介电层停止于所述填充空洞的上方；在剩余的所述第一层间介电层暴露的表面上形成阻挡衬垫层；在所述阻挡衬垫层上形成第二层间介电层。根据本发明的制造方法，避免了应力层对于器件的污染，提高了介电层的强度和致密性，同时增大了工艺窗口，进而提高了器件的良率和性能。

Description

一种半导体器件及其制造方法和电子装置
技术领域
本发明涉及半导体技术领域，具体而言涉及一种半导体器件及其制造方法和电子装置。
背景技术
随着半导体技术的不断发展，集成电路性能的提高主要是通过不断缩小集成电路器件的尺寸以提高它的速度来实现的。目前，由于在追求高器件密度、高性能和低成本中半导体工业已经进步到纳米技术工艺节点，特别是当半导体器件尺寸降到20nm或以下时，半导体器件的制备受到各种物理极限的限制。减小的特征结构尺寸造成器件上的结构特征的空间尺寸减小。器件上间隙与沟槽的宽度变窄到间隙深度对宽度的深宽比高到足以导致介电材料填充间隙相当不易的程度。
在FinFET制程中，一般采用流动式化学气相沉积法(Flowable CVD)形成层间介电层。然而在源漏区，形成于鳍片顶面上的SiGe或SiC应力层尺寸波动大，形状不规则，导致相邻鳍片之间的间隙变的更窄，对于FCVD层间介电材料的填充能力影响很大，导致填充空洞的出现，如图1所示，进而降低了层间介电层的致密性。
因此，为了解决上述技术问题，有必要提出一种新的制造方法。
发明内容
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
为了克服目前存在问题，本发明实施例一提供一种半导体器件的制造方法，包括：
提供半导体衬底，在所述半导体衬底上形成有多个鳍片，以及位于每个所述鳍片顶面上的应力层，在所述应力层的上方与所述鳍片延伸方向相垂直的方向上形成有若干条状栅极结构；
沉积形成接触孔蚀刻停止层，以覆盖所述半导体衬底的表面、所述鳍片的侧壁以及所述应力层的顶面和侧壁；
形成第一层间介电层，以填充相邻鳍片之间的间隙，其中，所述第一层间介电层的顶面高于所述应力层的顶面，在所述第一层间介电层中形成有填充空洞；
回蚀刻所述第一层间介电层停止于所述填充空洞的上方；
在剩余的所述第一层间介电层暴露的表面上形成阻挡衬垫层；
在所述阻挡衬垫层和接触孔蚀刻停止层上形成第二层间介电层。
可选地，所述应力层的材料为SiGe或者SiC。
可选地，在形成所述第一层间介电层之前，还包括在所述接触孔蚀刻停止层上形成高深宽比HARP衬垫层的步骤。
可选地，所述高深宽比HARP衬垫层为采用化学气相沉积或原子层沉积工艺形成的氧化物层。
可选地，在形成所述第一层间介电层之前还包括采用SiCoNi干法刻蚀工艺回蚀刻所述高深宽比HARP衬垫层的步骤或采用臭氧对所述高深宽比HARP衬垫层进行处理的步骤。
可选地，所述阻挡衬垫层的材料为氧化物或氮化物。
可选地，所述阻挡衬垫层的厚度为2nm～15nm。
可选地，形成所述第一层间介电层和所述第二层间介电层的步骤包括：
沉积可流动介电材料；
依次对所述可流动介电材料进行固化处理和退火处理。
可选地，采用去离子水结合臭氧进行所述固化处理。
可选地，所述退火处理为蒸气退火或干法退火或两者的组合。
本发明实施例二提供一种半导体器件，包括：
半导体衬底；
位于所述半导体衬底正面的间隔的若干鳍片，以及位于每个所述鳍片顶面上的应力层；
在所述应力层的上方与所述鳍片延伸方向相垂直的方向上形成有若干条状栅极结构；
覆盖所述半导体衬底的表面、所述鳍片的侧壁以及所述应力层的顶面和侧壁的接触孔蚀刻停止层；
位于所述接触孔蚀刻停止层上方的第一层间介电层，其中，在所述第一层间介电层中形成有填充空洞，所述第一层间介电层的顶面低于所述应力层的上表面；
位于所述第一层间介电层顶面上方的阻挡衬垫层；
位于所述阻挡衬垫层和所述接触孔蚀刻停止层上的第二层间介电层。
可选地，所述应力层的材料为SiGe或者SiC。
可选地，所述阻挡衬垫层的材料为氧化硅或氮化硅，用于保护所述填充空洞。
可选地，在所述第一层间介电层与所述接触孔蚀刻停止层之间还形成有高深宽比HARP衬垫层。
本发明实施例三提供一种电子装置，所述电子装置包括前述的半导体器件。
综上所述，根据本发明的制造方法，所述第一层间介电层、所述阻挡衬垫层和所述第二层间介电层组成的叠层作为器件的介电层，其中阻挡衬垫层对填充空洞起到保护作用，避免了应力层对于器件的污染，提高了介电层的强度和致密性，同时增大了工艺窗口，另外，整个制程的工艺温度低，提高了可流动介电材料的间隙填充能力，进而提高了器件的良率和性能。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1示出了现有的一种FinFET器件的剖面示意图；
图2A-2G为根据本发明一个具体实施方式依次实施的步骤所获得器件的示意图；
图3为根据本发明一个具体实施方式依次实施的步骤的工艺流程图；
图4为根据本发明实施例二中的半导体器件的剖面示意图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本发明，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
实施例一
下面，参照图2A-2G以及图3来描述根据本发明实施例一的方法依次实施的详细步骤。
如图2A所示，提供半导体衬底200，在所述半导体衬底200上形成有多个鳍片201，以及位于每个所述鳍片201顶面上的应力层202a、202b，在所述应力层202a、202b的上方与所述鳍片201延伸方向相垂直的方向上形成有若干条状栅极结构20。
所述半导体衬底200可以是以下所提到的材料中的至少一种：硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。此外，半导体衬底200上可以被定义有源区。
在所述半导体衬底200上形成有多个鳍片201，作为一实例，所述鳍片201的形成方法为在所述半导体衬底上形成硬掩膜层，例如氮化硅，接着在所述硬掩膜层上形成图案化的光刻胶层，所述光刻胶层定义了所述鳍片201，然后以所述光刻胶掩膜层为掩膜蚀刻所述硬掩膜层和所述半导体衬底，在所述半导体衬底上形成鳍片，然后去除所述光刻胶掩膜层，去除所述光刻胶掩膜层的方法可以为氧化灰化法。需要注意的是，所述鳍片201的形成仅仅是示例性的，并不局限于该方法。
在所述半导体衬底200上还形成有隔离结构21，例如在所述半导体衬底200上形成浅沟槽隔离或局部氧化物层，在本发明的一具体实施方式中，较佳地形成浅沟槽隔离结构，所述浅沟槽隔离的形成方法可以选用现有技术中常用的方法，例如首先，在半导体衬底上沉积氧化物层，接着回蚀刻所述氧化物层，形成顶部低于所述鳍片201的浅沟槽隔离结构。
应力层202a、202b位于每个所述鳍片201顶面上，对于PFET而言，所述应力层202a的材料为锗硅层；对于NFET而言，所述应力层202b的材料为碳硅层。示例性地，所述应力层202a、202b具有不规则形状，其尺寸变化波动大，如图2A中沿AA方向的剖面示意图所示，由于其尺寸的波动大，导致相邻鳍片201之间的间隙变的更窄，导致之后层间介电层的填充变的更加困难。
在所述应力层202a、202b的上方与所述鳍片201延伸方向相垂直的方向上形成有若干条状栅极结构20。作为示例，栅极结构20包括自下而上层叠的栅极介电层和栅极材料层。所述栅极介电层包括氮氧化物层，例如氮氧化硅(SiON)层，或者高k介电层，所述高k介电层的材料包括氧化铪、氧化铪硅、氮氧化铪硅、氧化镧、氧化锆、氧化锆硅、氧化钛、氧化钽、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化铝等，特别优选的是氧化铪、氧化锆或氧化铝。所述栅极材料层105包括多晶硅层、金属层、导电性金属氮化物层、导电性金属氧化物层和金属硅化物层中的一种或多种，其中，金属层的构成材料可以是钨(W)、镍(Ni)或钛(Ti)；导电性金属氮化物层可包括氮化钛(TiN)层；导电性金属氧化物层可包括氧化铱(IrO2)层；金属硅化物层可包括硅化钛(TiSi)层。
如图2B所示，沉积形成接触孔蚀刻停止层203，以覆盖所述半导体衬底200的表面、所述鳍片201的侧壁以及所述应力层202a、202b的顶面和侧壁。
可选地，所述接触孔蚀刻停止层203的材料为氮化硅或其他适合的材料。可以使用包括但不限于：通过物理气相沉积、化学气相沉积等合适的沉积工艺或者其他氮化工艺形成接触孔蚀刻停止层(CESL)。
如图2C所示，在所述接触孔蚀刻停止层203上形成高深宽比HARP衬垫层204。
可选地，所述高深宽比HARP衬垫层可以为采用化学气相沉积或原子层沉积工艺形成的氧化物层。
示例性地，还可以采用SiCoNi干法刻蚀工艺回蚀刻所述高深宽比HARP衬垫层204或采用臭氧对所述高深宽比HARP衬垫层204进行处理。
在一个示例中，可以采用包括氨水、双氧水和去离子水的混合溶液(SC1溶液)或臭氧气体或任何其他合适的气体或溶液清洗所述高深宽比HARP衬垫层204。采用富含氧的溶液或气体对高深宽比HARP衬垫层进行清洗/处理可以增加高深宽比HARP衬垫层中的氧含量，例如使硅与氧结合等。因此，可以使得高深宽比HARP衬垫层204转变为含有较多活性氧的富氧衬垫层。
如图2D所示，形成第一层间介电层205，以填充相邻鳍片201之间的间隙，其中，所述第一层间介电层205的顶面高于所述应力层202a、202b的顶面，在所述第一层间介电层205中形成有填充空洞。
第一层间介电层205的材料可以包括可流动二氧化硅或者氮氧化硅。
在一个示例中，形成所述第一层间介电层205的步骤包括：沉积可流动介电材料；依次对所述可流动介电材料进行固化处理和退火处理。
示例性地，可流动介电材料可以通过旋转涂覆电介质(SOD)形成，比如硅酸盐、硅氧烷、甲基倍半硅氧烷(methyl SilsesQuioxane，MSQ)、氢倍半硅氧烷(hydrogenSilseQuioxane,HSQ)、MSQ/HSQ、全氢硅氮烷(perhydrosilazane，TCPS)或者全氢聚硅氮烷(perhydro-polysilazane，PSZ)。在另一个示例中，以SiO2作为层间介电层，其中可流动介电材料的形成方法选用流动式化学气相沉积法(Flowable CVD，FCVD)，采用含硅前驱物(例如有机硅烷)和含氧前驱物(例如氧气、臭氧或氮氧化合物等)反应，在衬底上形成氧化硅层，形成的氧化硅层含有高浓度的硅-氢氧键(Si-OH)，这些键可增加氧化硅的流动性，使氧化硅层具有绝佳的流动性，并可快速移入衬底上的间隙或沟槽内。
对可流动介电材料实施固化处理步骤。在一个实施例中，在使用去离子水并结合O3的条件下实施固化处理，其中，O3的流量范围为100～5000sccm，实施固化处理的温度处于10℃到500℃的范围内。实施固化处理的压力范围为1torr～760torr。可以相信，固化可流动介电材料使得Si-O键网络能够进行转化，从而增加第一层间介电层的密度。
所述退火处理可采用蒸气退火或干法退火，也可单独或两者结合使用，也可结合其他退火技术来退火该可流动介电层，包括等离子体退火、紫外光退火、电子束退火及/或微波退火等。干法退火的气氛可为干燥氮气、氦气或氩气等。可选地，退火温度范围为400～600℃，或者其它能提高可流动介电材料质量的温度均可适用于本发明。
通过上述步骤获得最终的第一层间介电层205，然而由于应力层202a、202b尺寸的波动大，导致相邻鳍片201之间的间隙变的更窄，以至于使得第一层间介电层的填充能力变差，产生填充空洞，而填充空洞的影响器件的可靠性和稳定性。
如图2E所示，回蚀刻所述第一层间介电层205停止于所述填充空洞的上方。
回蚀刻工艺可以采用SiCoNi刻蚀或干法刻蚀等。回蚀刻工艺具有第一层间介电层205对接触孔蚀刻停止层203的高蚀刻选择比。其中，在进行SiCoNi刻蚀时，可以选用原位SiCoNi刻蚀或非原位SiCoNi刻蚀来去除氧化硅。在本发明的一具体实施例中，可以采用干法刻蚀执行回刻蚀工艺，干法蚀刻工艺包括但不限于：反应离子蚀刻(RIE)、离子束蚀刻、等离子体蚀刻或者激光切割。例如采用等离子体刻蚀，刻蚀气体可以采用基于氧气(O2-based)的气体。
所述回蚀刻工艺使得剩余所述第一层间介电层205的顶面低于所述应力层202a、202b的顶面，或者与所述应力层202a、202b的顶面齐平。
如图2F所示，在剩余所述第一层间介电层205暴露的表面上形成阻挡衬垫层206。
阻挡衬垫层206可以包括数种衬垫材料的任何一种，包括但不限于：氧化物衬垫材料或氮化物衬垫材料，示例性地，阻挡衬垫层206包括氧化物衬垫材料。可选地，所述氮化物可以为氮化硅。可以使用包括但不限于：化学气相沉积方法或原子层沉积方法形成的阻挡衬垫层206。在一个示例中，使用化学气相沉积方法形成氧化物衬垫层，因其具有足够高的致密性。可选地，所述阻挡衬垫层206的厚度范围为2～15nm，例如5nm、7nm或10nm，但并不限于上述厚度，可根据制程能力进行适当调整。由于阻挡衬垫层的致密性及强度更高，可以对第一层间介电层内的填充空洞提供保护作用，以降低填充空洞对器件性能的影响程度。
如图2G所示，在所述阻挡衬垫层206上形成第二层间介电层207。
第二层间介电层207的材料可以包括可流动二氧化硅或者氮氧化硅。可采用与形成所述第一层间介电层205相类似的方法形成所述第二层间介电层207，在此不作赘述。
示例性地，所述第二层间介电层207的顶面高于所述应力层202a、202b的顶面。
至此完成了器件的介电层的制作过程。上述半导体器件的制造方法可以适用于各种采用可流动的介电材料进行间隙填充的工艺，尤其是具有填充空洞的介电材料，例如可适用于任何技术节点(例如45nm及以下)的后高k/金属栅极工艺或鳍式场效应晶体管(FinFET)工艺中的层间介电层的形成。
综上所述，根据本发明的制造方法，所述第一层间介电层、所述阻挡衬垫层和所述第二层间介电层组成的叠层作为器件的介电层，其中阻挡衬垫层对填充空洞起到保护作用，避免了应力层对于器件的污染，提高了介电层的强度和致密性，同时增大了工艺窗口，另外，整个制程的工艺温度低，提高了可流动介电材料的间隙填充能力，进而提高了器件的良率和性能。
参照图3，示出了本发明一个具体实施方式依次实施的步骤的工艺流程图，用于简要示出整个制造工艺的流程。
在步骤301中，提供半导体衬底，在所述半导体衬底上形成有多个鳍片，以及位于每个所述鳍片顶面上的应力层，在所述应力层的上方与所述鳍片延伸方向相垂直的方向上形成有若干条状栅极结构；
在步骤302中，沉积形成接触孔蚀刻停止层，以覆盖所述半导体衬底的表面、所述鳍片的侧壁以及所述应力层的顶面和侧壁；
在步骤303中，形成第一层间介电层，以填充相邻鳍片之间的间隙，其中，所述第一层间介电层的顶面高于所述应力层的顶面，在所述第一层间介电层中形成有填充空洞；
在步骤304中，回蚀刻所述第一层间介电层停止于所述填充空洞的上方；
在步骤305中，在暴露的所述第一层间介电层表面上形成阻挡衬垫层；
在步骤306中，在所述阻挡衬垫层和接触孔蚀刻停止层上形成第二层间介电层。
实施例二
参考图4，本实施例提供一种采用实施例一中方法制作的半导体器件，包括：
半导体衬底400，所述半导体衬底400可以是以下所提到的材料中的至少一种：硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。此外，半导体衬底上可以被定义有源区。
在所述半导体衬底400上还形成有隔离结构41，例如在所述半导体衬底400上形成浅沟槽隔离或局部氧化物层，在本发明的一具体实施方式中，较佳地所述隔离结构41为浅沟槽隔离结构。
位于所述半导体衬底400正面的间隔的若干鳍片401，以及位于每个所述鳍片401顶面上的应力层402a、402b。示例性地，对于PFET而言，所述应力层402a的材料为锗硅层；对于NFET而言，所述应力层402b的材料为碳硅层。示例性地，所述应力层402a、402b具有不规则形状，其尺寸变化波动大。
在所述应力层402a、402b的上方与所述鳍片401延伸方向相垂直的方向上形成有若干条状栅极结构。作为示例，栅极结构包括自下而上层叠的栅极介电层和栅极材料层。
覆盖所述半导体衬底400的表面、所述鳍片401的侧壁以及所述应力层402a、402b的顶面和侧壁的接触孔蚀刻停止层403。可选地，所述接触孔蚀刻停止层403的材料为氮化硅或其他适合的材料。可以使用包括但不限于：通过物理气相沉积、化学气相沉积等合适的沉积工艺或者其他氮化工艺形成接触孔蚀刻停止层(CESL)。
位于所述接触孔蚀刻停止层403上方的第一层间介电层404，其中，在所述第一层间介电层404中形成有填充空洞。第一层间介电层404的材料可以包括可流动二氧化硅或者氮氧化硅。在一个示例中，第一层间介电层404的形成方法选用流动式化学气相沉积法(Flowable CVD，FCVD)。所述第一层间介电层404的顶面低于所述应力层402a、402b的顶面，或者与所述应力层402a、402b的顶面齐平。
较佳地，在所述第一层间介电层404与所述接触孔蚀刻停止层403之间还形成有高深宽比HARP衬垫层(未示出)。
位于所述第一层间介电层404顶面上方的阻挡衬垫层405。阻挡衬垫层405可以包括数种衬垫材料的任何一种，包括但不限于：氧化物衬垫材料或氮化物衬垫材料，示例性地，阻挡衬垫层405包括氧化物衬垫材料。可选地，所述氮化物可以为氮化硅可选地，所述阻挡衬垫层405的厚度范围为2～15nm，例如5nm、7nm或10nm，但并不限于上述厚度，可根据制程能力进行适当调整。由于阻挡衬垫层405的致密性及强度更高，可以对第一层间介电层404内的填充空洞提供保护作用，以降低填充空洞对器件性能的影响程度。
位于所述阻挡衬垫层405和所述接触孔蚀刻停止层403上的第二层间介电层406。较佳地，所述第二层间介电层406的顶面高于所述应力层402a、402b的顶面。第二层间介电层406的材料可以包括可流动二氧化硅或者氮氧化硅。较佳地，所述第二层间介电层406与所述第一层间介电层404的材料相同。
综上所述，根据本发明的半导体器件，所述第一层间介电层、所述阻挡衬垫层和所述第二层间介电层组成的叠层作为器件的介电层，其中阻挡衬垫层对填充空洞起到保护作用，避免了应力层对于器件的污染，提高了介电层的强度和致密性，进而使得器件具有优异的性能。
实施例三
本发明还提供了一种电子装置，包括半导体器件。其中，半导体器件为实施例二所述的半导体器件，或根据实施例一所述的制造方法得到的半导体器件。
本实施例的电子装置，可以是手机、平板电脑、笔记本电脑、上网本、游戏机、电视机、VCD、DVD、导航仪、照相机、摄像机、录音笔、MP3、MP4、PSP等任何电子产品或设备，也可为任何包括所述半导体器件的中间产品。本发明实施例的电子装置，由于使用了上述的半导体器件，因而具有更好的性能。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (13)

1.一种半导体器件的制造方法，包括：
提供半导体衬底，在所述半导体衬底上形成有多个鳍片，以及位于每个所述鳍片顶面上的应力层，在所述应力层的上方与所述鳍片延伸方向相垂直的方向上形成有若干条状栅极结构；
沉积形成接触孔蚀刻停止层，以覆盖所述半导体衬底的表面、所述鳍片的侧壁以及所述应力层的顶面和侧壁；
在所述接触孔蚀刻停止层上形成高深宽比HARP衬垫层；
采用富含氧的溶液对所述高深宽比HARP衬垫层进行清洗，或采用富含氧的气体对所述高深宽比HARP衬垫层进行处理，以增加所述高深宽比HARP衬垫层中的氧含量；
形成第一层间介电层，以填充相邻鳍片之间的间隙，其中，所述第一层间介电层的顶面高于所述应力层的顶面，在所述第一层间介电层中形成有填充空洞；
回蚀刻所述第一层间介电层停止于所述填充空洞的上方；
在剩余的所述第一层间介电层暴露的表面上形成阻挡衬垫层；
在所述阻挡衬垫层和接触孔蚀刻停止层上形成第二层间介电层。
2.根据权利要求1所述的制造方法，其特征在于，所述应力层的材料为SiGe或者SiC。
3.根据权利要求1所述的制造方法，其特征在于，所述高深宽比HARP衬垫层为采用化学气相沉积或原子层沉积工艺形成的氧化物层。
4.根据权利要求1所述的制造方法，其特征在于，在形成所述第一层间介电层之前还包括采用SiCoNi干法刻蚀工艺回蚀刻所述高深宽比HARP衬垫层的步骤或采用臭氧对所述高深宽比HARP衬垫层进行处理的步骤。
5.根据权利要求1所述的制造方法，其特征在于，所述阻挡衬垫层的材料为氧化物或氮化物。
6.根据权利要求1所述的制造方法，其特征在于，所述阻挡衬垫层的厚度为2nm～15nm。
7.根据权利要求1所述的制造方法，其特征在于，形成所述第一层间介电层和所述第二层间介电层的步骤包括：
沉积可流动介电材料；
依次对所述可流动介电材料进行固化处理和退火处理。
8.根据权利要求7所述的制造方法，其特征在于，采用去离子水结合臭氧进行所述固化处理。
9.根据权利要求7所述的制造方法，其特征在于，所述退火处理为蒸气退火或干法退火或两者的组合。
10.一种半导体器件，包括：
半导体衬底；
位于所述半导体衬底正面的间隔的若干鳍片，以及位于每个所述鳍片顶面上的应力层；
在所述应力层的上方与所述鳍片延伸方向相垂直的方向上形成有若干条状栅极结构；
覆盖所述半导体衬底的表面、所述鳍片的侧壁以及所述应力层的顶面和侧壁的接触孔蚀刻停止层；
位于所述接触孔蚀刻停止层上方的第一层间介电层，在所述第一层间介电层与所述接触孔蚀刻停止层之间还形成有高深宽比HARP衬垫层，其中，在所述第一层间介电层中形成有填充空洞，所述第一层间介电层的顶面低于所述应力层的上表面，所述高深宽比HARP衬垫层为含有活性氧的富氧衬垫层；
位于所述第一层间介电层顶面上方的阻挡衬垫层；
位于所述阻挡衬垫层和所述接触孔蚀刻停止层上的第二层间介电层。
11.根据权利要求10所述的半导体器件，其特征在于，所述应力层的材料为SiGe或者SiC。
12.根据权利要求10所述的半导体器件，其特征在于，所述阻挡衬垫层的材料为氧化硅或氮化硅，用于保护所述填充空洞。
13.一种电子装置，所述电子装置包括权利要求10所述的半导体器件。
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