CN109427890A - 半导体元件 - Google Patents

半导体元件 Download PDF

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Publication number
CN109427890A
CN109427890A CN201711162406.XA CN201711162406A CN109427890A CN 109427890 A CN109427890 A CN 109427890A CN 201711162406 A CN201711162406 A CN 201711162406A CN 109427890 A CN109427890 A CN 109427890A
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China
Prior art keywords
contact trench
layer
depth
dielectric layer
insulating layer
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CN201711162406.XA
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English (en)
Inventor
蔡伩哲
谢旻谚
陈华丰
潘国华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN109427890A publication Critical patent/CN109427890A/zh
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    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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Abstract

本揭露的实施例提供一种半导体元件包含基板、绝缘层形成于基板之上；多个鳍状物垂直地形成自基板的表面，这些鳍状物延伸穿过绝缘层且于绝缘层的顶面之上；栅极结构形成于这些鳍状物的一部分之上且于绝缘层的顶面之上；源极/漏极结构配置相邻于栅极结构的相对两侧，源极/漏极结构接触鳍状物；介电层形成于绝缘层之上；第一接触沟槽以第一深度延伸穿过介电层以暴露源极/漏极结构，第一接触沟槽含有导电材料；以及第二接触沟槽以第二深度延伸穿过介电层，第二接触沟槽包含导电材料，且第二深度大于第一深度。

Description

半导体元件
技术领域
本发明实施例是关于一种半导体元件及其制造方法，特别是一种具有较浅沟槽的半导体元件及其制造方法。
背景技术
随着半导体产业已进入纳米技术制程节点以寻求更高的元件密度及较佳的表现，诸如鳍式场效晶体管(fin-like field-effect transistor,FinFET)元件的三维设计已被导入多种逻辑及应用之中。其中一种鳍式场效晶体管元件的类型是以多个鳍状结构自基板表面垂直地扩展以进行制造。这些鳍状结构通过浅沟槽隔离(shallow trench isolation,STI)区彼此分隔开来。鳍状结构各具有源极/漏极区以及在源极/漏极区之间形成的通道区。金属栅极缠绕于各鳍状结构的通道区从而更好控制来自通道区三侧的电流。
与上述鳍式场效晶体管元件有关的问题是，在浅沟槽隔离区用于形成源极/漏极接触(为了层间连接而电性耦合至源极/漏极区)的沟槽深度与在主动区(包含源极/漏极区及通道区)用于形成源极/漏极接触的沟槽深度由于图案负载效应(pattern-loadingeffect)的关系而有所差异，其发生于当浅沟槽隔离区与主动区之间的图案密度有所不同时。此种深度上的差异可能会在沟槽填充导电材料后造成沟槽轮廓的变形。因此，元件的表现会有所降低。
发明内容
本揭露的一态样为一种半导体元件包含基板、绝缘层、多个鳍状物、栅极结构、源极/漏极结构、介电层、第一接触沟槽以及第二接触沟槽。绝缘层形成于基板之上。多个鳍状物垂直地形成自基板的表面，这些鳍状物延伸穿过绝缘层且于绝缘层的顶面之上。栅极结构形成于这些鳍状物的一部分之上及绝缘层的顶面之上。源极/漏极结构配置相邻于栅极结构的相对两侧，源极/漏极结构接触鳍状物的一部分。介电层形成于绝缘层之上。第一接触沟槽以第一深度延伸穿过介电层以暴露源极/漏极结构，第一接触沟槽含有导电材料。第二接触沟槽以第二深度延伸穿过介电层，第二接触沟槽包含导电材料，且第二深度大于第一深度。
附图说明
当结合附图阅读以下详细描述时将更好地理解本揭露内容的态样。但须注意依照本产业的标准做法，各种特征未按照比例绘制。事实上，各种特征的尺寸为了清楚的讨论而可被任意放大或缩小。
图1是根据本揭露各种实施方式，绘示制造半导体元件例示性的方法流程图；
图2A至图2P是根据图1的流程图，绘示半导体元件在各种制造阶段的剖视图。
具体实施方式
本揭露接下来将会提供许多不同的实施方式或实施例以实施本揭露中不同的特征。各特定实施例中的组成及配置将会在以下作描述以简化本揭露。这些为实施例仅作为式范并非用于限定本揭露。例如，一第一元件形成于一第二元件“上方”或“之上”可包含实施例中的第一元件与第二元件直接接触，亦可包含第一元件与第二元件之间更有其他额外元件使第一元件与第二元件无直接接触。此外，在本揭露各种不同的范例中，将重复地使用元件符号及/或字母。此重复乃为了简化与清晰的目的，而其本身并不决定各种实施例及/或结构配置之间的关系。此外，各种特征乃为了简化与清晰可能会依不同比例做绘制。
更进一步，像是“之下”、“下面”、“较低”、“上面”、“较高”、以及其他类似的相对空间关系的用语，可用于此处以便描述附图中一元件或特征与另一元件或特征之间的关系。该等相对空间关系的用语乃为了涵盖除了附图所描述的方向以外，装置于使用或操作中的各种不同的方向。举例来说，若于图中的装置被翻转过来，原先被描述为在其他元件或特征“之下”或“下面”的元件则变成在其他元件或特征“上面”。因此，范例用语“之下”皆能包含上面及之下的方位。上述装置可另有其他导向方式(旋转90度或朝其他方向)，此时的空间相对关系也可依上述方式解读。
图1是根据本揭露各种实施方式，绘示制造半导体元件例示性的方法流程图100。图2A至图2P是根据图1的流程图，绘示半导体元件在各种制造阶段的剖视图。本领域技术人员应知用于形成半导体元件及相关结构的全部制程并未绘示或在此讨论。虽然各种操作绘示于附图中并在此讨论，关于步骤的顺序或步骤的介入的存在与否并无限制。操作依序做描绘或描述，除非明确指定，否则仅是为了解释的目的而进行，而非排除各步骤(至少部分地，若非全部)以同时或重迭的方式执行的可能性。
如图2A所示，流程图100始于操作102，提供基板202。基板202可为半导体晶圆例如硅晶圆。供选择地或额外地，基板202可包含基本半导体材料、复合半导体材料及/或合金半导体材料。举例而言，基本半导体材料可包含但不限于结晶硅、多晶硅、非晶硅及/或锗。举例而言，复合半导体材料可包含但不限于碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟。举例而言，合金半导体材料可包含但不限于SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP。
根据一些实施例，如图2A所示，介电层204及遮罩层206形成于基板202之上，及感光层208形成于遮罩层206之上。图2A显示感光层208已被图案化。介电层204可作为基板202与遮罩层206之间的粘着层。此外，介电层204亦可作为用于蚀刻遮罩层206的蚀刻停止层。在一些实施例中，介电层204可由氧化硅所制成。介电层204可通过热氧化制程来形成，而在一些其他实施例中可采用其他沉积制程。
在后续光微影制程期间，遮罩层206可作为硬遮罩。在一些实施例中，遮罩层206由氮化硅制成。遮罩层206可通过低压化学气相沉积(low-pressure chemical vapordeposition,LPCVD)或等离子增强化学气相沉积(plasma enhanced chemical vapordeposition,PECVD)来形成，而在一些其他实施例中可采用其他沉积制程。
接着，根据一些实施例，如图2B所示，透过感光层208依序对遮罩层206、介电层204及基板的一部分进行蚀刻而形成鳍状物210。鳍状物210为基板202的一部分。感光层208接着被移除。根据一些实施例，如图2C所示，在感光层被208被移除之后，绝缘层212形成以覆盖鳍状物210于基板202之上。绝缘层可为浅沟槽隔离(shallow trench isolation,STI)结构。绝缘层212可由氧化硅、氮化硅、氮氧化硅、氟化物掺杂硅酸盐玻璃(fluoride-dopedsilicate glass,FSG)或其他介电常数小于3.9的低介电常数材料(例如约莫或小于3.2)而制成。绝缘层212可利用高密度等离子(high-density-plasma,HDP)、亚大气压化学气相沉积(sub-atmospheric pressure CVD,SACVD)，低压化学气相沉积(LPCVD)、原子层沉积(atomic layer deposition,ALD)、等离子增强原子层沉积(PEALD)、等离子增强化学气相沉积(PECVD)、单层沉积(monolayer deposition,MLD)、等离子脉冲化学气相沉积(plasmaimpulse CVD,PICVD)、旋涂沉积或类似方式来形成。
根据一些实施例，如图2D所示，在绝缘层212形成之后，可执行化学机械研磨(chemical mechanical polishing,CMP)制程以暴露出鳍状物210的顶面。如图2D所示，遮罩层206及介电层204已被移除。
接着，根据一些实施例，如图2E所示，对绝缘层212进行凹陷以暴露出鳍状物210的顶部。绝缘层212可通过湿式蚀刻制程或干式蚀刻制程进行凹陷。如上述所提，绝缘层212可被视为围绕在鳍状物210的浅沟槽隔离(STI)结构。绝缘层212定义出基板202的隔离区域。
之后，根据一些实施例，如图2F所示，栅极介电层214形成于基板202之上以覆盖鳍状物210及绝缘层212。栅极介电层214可以由高介电常数材料制成，例如金属氧化物，过渡金属氧化物或类似物等。举例而言，高介电常数材料可包含但不限于氧化铪(HfO2)、氧化铪铪(HfSiO)、氧化钽铪(HfTaO)、铪钛氧化物(HfTiO)、铪氧化锆(HfZrO)、氧化锆、氧化钛、氧化铝、二氧化铪矾土(HfO2-Al2O3)合金或其他适合的介电材料。在一些实施例中，栅极介电层214为氧化层。栅极介电层214可通过沉积制程来形成，例如化学气相沉积(CVD)、物理气相沉积(physical vapor deposition,PVD)、原子层沉积(ALD)、高密度等离子化学气相沉积(high density plasma CVD,HDPCVD)、金属有机化学气相沉积(metal organic CVD,MOCVD)或等离子增强化学气相沉积(PECVD)。
根据一些实施例，如图2F所示，在栅极介电层214形成之后，牺牲层216形成于栅极介电层214之上。牺牲层216可通过沉积制程来形成，例如化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)、高密度等离子化学气相沉积(HDPCVD)、金属有机化学气相沉积(MOCVD)或等离子增强化学气相沉积(PECVD)。牺牲层216可由导电或非导电材料制成，例如金属、含硅材料或介电材料。在一些实施例中，牺牲层216由多晶硅制成。
接着，根据一些实施例，如图2G所示，遮罩结构218形成于牺牲层216的一部分上。遮罩结构218可视为在后续光微影制程期间用于保护牺牲层216及栅极介电层214的硬遮罩。遮罩结构218可通过包含沉积、光微影图案化及蚀刻制程的程序来形成。光微影图案化制程可包含光阻涂布(例如：旋转涂布)、软烤、遮罩对准、曝光、曝光后烘烤、光阻显影、洗净、干燥(例如：硬烤)及/或其他适合的制程。蚀刻制程可包含干式蚀刻、湿式蚀刻及/或其他的蚀刻方法(例如：反应性离子蚀刻)。
根据一些实施例，如图2H所示，在遮罩结构218形成之后，利用蚀刻制程对牺牲层216及栅极介电层214进行图案化以形成多个栅极结构220a至220e。通过蚀刻制程的执行，牺牲层216及栅极介电层214未被遮罩结构218覆盖的部分被移除。接着利用任何适合的制程诸如灰化制程或蚀刻制程对遮罩结构218进行移除。栅极结构220a至220e可被视为包含位于遮罩结构218下方的牺牲层216及栅极介电层214的部分。如下述图2I所示，所得到的栅极结构220a至220e形成于鳍状物210的一部分上并缠绕鳍状物的顶面207及相对两侧边209、211。
应了解到所呈现的两个鳍状物及五个栅极结构仅为绘示之用。在应用上，鳍状物及栅极结构视需求可为任何数量。此外，尽管在此讨论的栅极结构220a至220e是利用后栅极制程进行制造，可想而知的是，本领域技术人员应理解栅极结构可利用先栅极制程进行制造。
根据一些实施例，如图2I所示，在栅极结构220a至220e形成之后，间隔物222形成于栅极结构220a至220e的侧壁上。在一些实施例中，间隔物222可由氮化硅、碳化硅、氮氧化硅、硅碳、氧化硅、硅氢、其他适合的材料或其组合。在一些实施例中，间隔物222由氮化物所制成。间隔物222可由沉积及蚀刻制程形成。
如同前述，根据一些实施例，通过蚀刻制程的执行，牺牲层216及栅极介电层214未被遮罩结构218覆盖的部分被移除。因此，当间隔物222形成于鳍状物210及绝缘层212上的栅极结构220a至220e的侧壁时，间隔物222直接接触鳍状物210及绝缘层212。意即，栅极介电层214并未位于间隔物222及鳍状物210之间。
接着，如图2J所示，绘示图2I中的结构沿线段A-A’的剖视图，利用蚀刻制程使鳍状物210(除了上方有栅极结构220a至220e所形成之处)的部分凹陷以形成源极及漏极(源/漏极)沟槽224。沿X轴的方向来看时，源/漏极沟槽224(以实线表示)相邻于栅极结构220b、220c、220d各自的相对两侧，而绝缘层212(即，浅沟槽隔离区)保留在源/漏极沟槽224内的鳍状物210的两侧。鳍状物210暴露的部分及介于源/漏极沟槽224(被栅极结构220a至220e所覆盖)的鳍状物210定义为基板202的主动区217。主动区217相邻或毗邻隔离区219(即，浅沟槽隔离区)。在一实施例中，主动区217被隔离区219所包围或围绕。
根据一些实施例，如图2K所示，在源/漏极沟槽224形成于鳍状物210中之后，源/漏极结构226形成于源/漏极沟槽224中。下面欲进行讨论的图2K及图2L至图2P为图2I中的结构沿线段A-A’并带有各种额外特征的剖视示意图。沿X轴的方向来看，源/漏极结构226可包含顶部226a(配置于源/漏极沟槽224中的绝缘层212之间)及顶部226b(配置于源/漏极沟槽224之外)。源/漏极结构226之间连接的鳍状物210形成半导体元件的通道区(未绘示)。应理解的是，源/漏极沟槽224之外的源/漏极结构226(即，顶部226b)可具有不同的形状，取决于源/漏极结构226的材料及/或欲进行成长的基板202的表面。举例而言，源/漏极结构226的顶部226b可磊晶成长并平行扩展以形成多个刻面。这些刻面可形成各种轮廓，例如，由于基板的不同平面(或表面)上成长速率的差异，沿X轴的方向来看时，有菱形的剖面轮廓。
举例而言，源/漏极结构226的材料可包含但不限于锗(Ge)、硅(Si)、砷化镓(GaAs)、砷化铝镓(AlGaAs)、硅锗(SiGe)、砷化镓磷化物(GaAsP)、镓锑(GaSb)、铟锑(InSb)砷化物(InGaAs)、砷化铟(InAs)或其组合。源/漏极结构226可用p型掺杂剂进行掺杂以形成p型鳍式场效晶体管或用n型掺杂剂进行掺杂以形成n型鳍式场效晶体管。源/漏极结构226可通过磊晶成长制程来形成，例如化学气相沉积技术(如气相磊晶(vapor-phase epitaxy,VPE)及/或超高真空化学气相沉积(ultra-high vaccum CVD,UHVCVD))、分子束磊晶及/或其他适合的制程。
根据一些实施例，如图2K所示，在形成源/漏极结构226之后，接触蚀刻停止层228形成以覆盖基板202的表面，其可包含栅极结构220a至220e、侧壁间隔物222、源/漏极结构226及绝缘层212暴露的表面。接触蚀刻停止层228可由氮化硅、氧化硅、氧氮化硅、碳化硅、碳氮化硅、氮化硼、硅氮化硼、硅碳氮化硼、或其组合或其他适合的材料所制成。在一实施例中，接触蚀刻停止层228为氮化硅。接触蚀刻停止层228可利用任何适合的技术来形成，例如化学气相沉积(CVD)、等离子增强化学气相沉积(PECVD)、高密度等离子化学气相沉积(HDPCVD)或旋转涂布制程等。
其后，根据一些实施例，如图2L所示，第一层间介电层230(标记为ILD1)形成于基板202上的接触蚀刻停止层228上。可看到第一层间介电层230为横向地穿过主动区217及隔离区219。第一层间介电层230可包含多层由多种介电材料所制成，例如氧化硅、氮化硅、氮氧化硅、碳化硅、硅氮化硼(SiBN)、硅碳氮化硼(SiCBN)、四乙氧基硅烷(TEOS)、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、低介电常数材料及/或其他适合的低介电常数材料。举例而言，低介电常数材料可包含但不限于氟硅玻璃(FSG)、碳掺杂氧化硅、非晶氟化碳、聚对二甲苯、双苯基环丁烯(BCB)或聚酰亚胺。第一层间电介质层230可通过化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)、旋转涂布或其他适合的制程来形成。
根据一些实施例，如图2L所示，在第一层间介电层230形成之后，执行平坦化制程于第一层间介电层230上。如图2L所示，第一层间介电层230可通过化学机械研磨(CMP)制程进行平坦化直到栅极结构220a至220e的顶面221暴露出来。层间介电层230的顶面与栅极结构220a至220e的顶面实质上共平面。
在平坦化制程执行之后，诸如栅极结构220b及220d的一些栅极结构可被移除以提供用以填充金属栅极材料的沟槽。残留的栅极结构220a、220c及220e其包含多晶硅，可做为虚设栅极。栅极结构220b及220d可以任何适合的移除制程进行移除。举例而言，栅极结构220b及220d的牺牲层216及栅极介电层214随后可利用干式蚀刻制程及/或湿式蚀刻制程进行移除。
如图2M所示，在栅极结构220b及220d被移除之后，对图2L栅极结构220b及220d移除后所形成的沟槽填充金属栅极材料并形成金属栅极232b及232d。在一些实施例中，金属栅极232b及232d各自可包含高介电常数(high-k)介电层234、功函数层236以及金属栅极电极层238。
如图2M所示，在金属栅极232b及232d形成之后，多余的材料可利用平坦化制程(例如：化学机械研磨制程)移除以暴露出高介电常数介电层234的顶面241、功函数层236的顶面243、金属栅极电极层238的顶面245、间隔物222的顶面247、接触蚀刻停止层228的顶面249以及第一层间介电层230的顶面251。高介电常数介电层234的顶面241、功函数层236的顶面243、金属栅极电极层238的顶面245、间隔物222的顶面247、接触蚀刻停止层228的顶面249以及第一层间介电层230的顶面251实质上共平面。
在一些实施例中，高介电常数介电层234保角地形成于沟槽所暴露的表面上。高介电常数介电层234可由金属氧化物、金属氮化物、金属硅酸盐、过渡金属氧化物、过渡金属氮化物、过渡金属硅酸盐或金属的氮氧化物所制成。举例而言，高介电常数材料可包含但不限于氧化铪(HfO2)、氧化铪铪(HfSiO)、铪硅氮化物(HfSiON)、铪钽氧化物(HfTaO)、铪钛氧化物(HfTiO)、铪锆氧化物(HfZrO)、氮化硅、氮氧化硅、氧化锆、氧化钛、氧化铝、二氧化铪矾土(HfO2-Al2O3)合金或其他具有介电常数高于约3.9的适合的高介电常数材料及/或其组合。取决于所欲形成的材料，适合的制程如原子层沉积(ALD)技术、化学气相沉积(CVD)技术、等离子增强化学气相沉积(PECVD)技术、物理气相沉积(PVD)技术或组合可用于形成栅极介电质。
在一些实施例中，功函数层236保角地形成于高介电常数介电层234上。功函数层236可被调整为具有适当的功函数。举例而言，若需要用于PMOS元件的P型功函数金属(P金属)时，则可采用P型功函数材料。举例而言，P型功函数材料可包含但不限于氮化钛(TiN)、氮化钨(WN)、钨(W)、钌(Ru)、钯(Pd)、铂(Pt)、钴(Co)、镍(Ni)及/或其他适合的材料。
另一方面，若需要用于NMOS元件的N型功函数金属(N金属)时，则可采用N型功函数材料。举例而言，N型功函数材料可包含但不限于钛化铝(TiAl)、氮化钛铝(TiAlN)、碳氮化钽(TaCN)、铪(Hf)、锆(Zr)、钛(Ti)、钽(Ta)、铝(Al)、碳化铪(HfC)、碳化锆(ZrC)、碳化钛(TiC)、碳化铝(AlC)、铝化物及/或其他适合的材料。
在一些实施例中，金属栅极电极层238形成于功函数层236上。在一些实施例中，金属栅极电极层238可由导电材料所制成，例如铝(Al)、铜(Cu)、钛(Ti)、钽(Ta)、钛铝(AlTi)、氮化铝钛(TiAlN)、钛(Ti)、氮化钛(TiN)、钽氮化物(TaN)、钽铝(AlTa)、钽(Ta)、硅化镍、硅化钴、碳化钽(TaC)、氮化硅(TaSiN)、钨(W)、氮化钨(WN)铂(Pt)、钌(Ru)、其他适合的导电材料及其组合。取决于所欲形成的层体材料，适合的制程如化学气相沉积(CVD)技术、物理气相沉积(PVD或溅镀)技术、原子层沉积(ALD)技术、等离子增强化学气相沉积(PECVD)技术及/或镀覆可用于形成金属栅极电极层238。
其后，如图2N所示，第二层间介电层260(标记为ILD2)形成以覆盖结构所暴露的顶面，意即，高介电常数介电层234的顶面241、功函数层236的顶面243、金属栅极电极层238的顶面245、间隔物222的顶面247、接触蚀刻停止层228的顶面249以及第一层间介电层230的顶面251。可看到第二层间介电层260为横向穿过主动区217及隔离区219(图2P)。在应用上，第二层间介电层260可由同于或异于第一层间介电层230的材料所制成。
来到操作104，如图2O所示，在第二层间介电层260形成之后，对基板202进行蚀刻制程以同时形成第一接触沟槽262及第二接触沟槽264分别于主动区217及隔离区219。第一接触沟槽262穿过第二层间介电层260、第一层间介电层230及接触蚀刻停止层228而形成以暴露出源/汲结构226的一部分。同样地，第二接触沟槽264穿过第二层间介电层260及部分进入第一层间介电层230而形成。在此所用的术语“沟槽”可广泛地涵盖任何形貌特征，例如“开口”、“孔”、“通道”、“凹陷”、“插塞”等，其水平地及/或垂直地于结构中延伸，适合用于提供导电或接触途径。
将第一接触沟槽262及第二接触沟槽264填充导电材料(将于下述操作106详细讨论)。第一接触沟槽262提供与随后将形成的导电通道/插塞的电性接触，其是用于多层半导体结构中的层间互连结构。第二接触沟槽264可提供两相邻MOS晶体管间的电性连接，或提供与随后将形成的电性连接结构(例如：接触、导孔、局部互连结构)的电性连接以耦接源/漏极结构226至外部电源及/或其他多层半导体结构中的层间互连结构。
第一接触沟槽262及第二接触沟槽264可由微影制程及蚀刻制程来形成，例如等离子干式蚀刻制程。在微影制程期间，用于定义第一接触沟槽262及第二接触沟槽264区域而带有开口的图案化光阻层(未绘示)形成于第二层间介电层260上。接着以图案化光阻层做为蚀刻遮罩层移除部分的第二层间介电层260、第一层间介电层230及接触蚀刻停止层228以形成第一接触沟槽262以暴露出部分的源/漏极结构226。同时，以图案化光阻层做为蚀刻遮罩层移除部分的第二层间介电层260及部分的第一层间介电层230以形成第二接触沟槽264。
待蚀刻制程完成后，第一接触沟槽262形成并具有长度或深度"D1"及第二接触沟槽264形成并具有长度或深度"D2"。深度"D1"在此定义为从第二层间介电层260的顶面266至第一接触沟槽262的底面268的量测距离。深度"D2"在此定义为从第二层间介电层260的顶面266至第二接触沟槽264的底面270的量测距离。在一定时间内进行蚀刻时，深度"D2"大于深度"D1"。原因在于主动区217及隔离区219之间的不同特征密度(即，图案负载效应)，以及源/漏极结构226之间存在接触蚀刻停止层228，其导致在主动区217的蚀刻速率比在隔离区219慢。
如下文将更详尽地讨论到，本揭露的发明人提出一种改良的蚀刻制程以控制第一接触沟槽262的深度"D1"及第二接触沟槽264的深度"D2"。特别在于，此蚀刻制程优化蚀刻气体混合物，使其能有效地以比移除隔离区219的材料更快的速率移除主动区217的接触蚀刻停止层228。由于主动区217及隔离区219皆同时暴露于蚀刻制程的化学作用中，故在一特定时间内于隔离区219穿过第二层间介电层260及第一层间介电层230以蚀刻出第二接触沟槽264所需的时间可被缩短。
透过此种改良的蚀刻制程，与未采用改良蚀刻气体混合物为蚀刻剂来进行蚀刻制程的传统较深接触沟槽相比，第二接触沟槽264在隔离区219的深度"D2"较浅。较浅的第二接触沟槽264有所助益的原因在于，他们可在第二接触沟槽264填充导电材料之后，使得沿第二接触沟槽264深度的沟槽轮廓的变形或弯曲最小化。当第二接触沟槽264为较浅时，填入第二接触沟槽264的导电材料的量可减少。由于第二接触沟槽264具有较少量的导电材料，较浅的第二接触沟槽264不会变形或弯曲，因此可保持沟槽轮廓的完整性。即使第二接触沟槽264变形或弯曲，由于其具有较浅轮廓的关系，可防止第二接触沟槽264接触邻近的结构(例如：于栅极结构220a、220e下方的鳍状物210)。相对而言，在隔离区219较深的第二接触沟槽有可能会弯曲并与邻近结构桥接，导致电性短路及元件故障。利用下文将讨论的改良的蚀刻制程，在隔离区219的第二接触沟槽264的深度可减少多于12％，例如约16％或更多。在一些实施例中，在隔离区219的第二接触沟槽264的深度减少25％或更多，例如37.5％。
图2O所绘示的实施例中，第一层间介电层230具有厚度"T1"且第二接触沟槽264延伸进入第一层间介电层230至深度"D3"。厚度"T1"在此定义为第一层间介电层230的顶面251至第一层间介电层230的底面282的量测距离。深度"D3"在此定义为第一层间介电层230的顶面251至第二接触沟槽264的底面270的量测距离。在各种实施例中，深度"D3"及厚度"T1"的比例为约1:1.1至约1:1.6，如约1:1.2至约1:1.5，举例来说，约1:1.3。
第一层间介电层230、第二层间介电层260及绝缘层212具有组合厚度或深度"D4"。深度"D4"在此定义为第二层间介电层260的顶面266至绝缘层212的底面284的量测距离。在各种实施例中，第二接触沟槽264的深度"D2"与第一层间介电层230、第二层间介电层260及绝缘层212的组合深度"D4"比例为约1:1.1至约1:1.6，如约1:1.2至约1:1.4，举例来说，约1:1.3。
第一接触沟槽262的高宽比(aspect ratio)可为约2:1至约50:1，例如约5:1至约30:1，举例来说，约20:1。第二接触沟槽264的高宽比可为约2:1至约50:1，例如约10:1至约30:1，举例来说，约20:1。在此所用的术语“高宽比”是指一特定特征的高度尺寸与宽度尺寸的比例，例如：第一接触沟槽262或第二接触沟槽264的沟槽高度比上沟槽宽度。在各种实施例中，第二接触沟槽264的深度"D2"与第一接触沟槽262的深度"D1"的比例为约1:0.3至约1:1，如约1:0.4至约1:0.9，举例来说，约1:0.7。
在一些实施例中，第一接触沟槽262及第二接触沟槽264形成从顶端至底端带有实质固定的的剖面。较浅的第二接触沟槽264带有实质固定的剖面轮廓使他们得以导电材料的可控制收缩性填充导电材料，从而在第二接触沟槽264的底部有可控制的气隙(在操作106会有更详细的讨论)。
在一些实施例中，第一接触沟槽262及/或第二接触沟槽264沿第一接触沟槽262及/或第二接触沟槽264的深度形成带有略微锥形的剖面。意即，第一接触沟槽262及/或第二接触沟槽264顶端的沟槽宽度(或内径)略大于第一接触沟槽262及/或第二接触沟槽264底端的沟槽宽度。此沟槽宽度的差异部分来自于第一接触沟槽262及/或第二接触沟槽264的高宽比为约2:1或更大。因此，第一接触沟槽262及/或第二接触沟槽264的顶部暴露于蚀刻剂的时间较第一接触沟槽262及/或第二接触沟槽264的底部长，导致第一接触沟槽262及/或第二接触沟槽264在顶部有较宽的沟槽及在底部有较窄的沟槽。在大部分例子中，第一接触沟槽262及/或第二接触沟槽264的顶部至少2％大于第一接触沟槽262及/或第二接触沟槽264的底部，例如约5％、约10％或更大、约20％或更大、约30％或更大、约35％或更大。
蚀刻制程可为湿式蚀刻制程或干式蚀刻制程。在一实施例中，蚀刻制程为干式蚀刻制程，例如等离子源蚀刻制程。在蚀刻制程期间，图案化的光阻层可配置于第二层间介电层260之上使得未被光阻层覆盖的主动区217及隔离层219同时以来自蚀刻制程中一或多个化学物质的等离子种类轰击并移除。等离子源蚀刻制程可用电容耦合等离子或感应耦合等离子。在一些实施例中，蚀刻制程可采用中性种类，例如自由基，其可通过与基板所在的处理室所分隔开来的远距等离子系统(remote plasma system,RPS)来产生。
适用于蚀刻制程的化合物可包含含氟化合物，例如具有结构式为CxFy的氟碳化合物，其中x及y为正整数，及/或具有结构式为CxHyFz的氢氟碳化合物，其中x、y、z为正整数。举例而言，氟碳化合物可包含但不限于六氟丁二烯(C4F6)、四氟甲烷(CF4)、六氟甲烷(C2F6)、八氟丙烷(C3F8)、八氟环丁烷(C4F8)及其任何组合。氢氟烃化学的实例可以包括但不限于三氟甲烷(CHF3)、二氟甲烷(CH2F2)、氟甲烷(CH3F)、四氟乙烷(C2H2F4)、三氟乙烷(C2H3F3)及任其组合。
在一些此处所讨论的实施例中，蚀刻制程进一步包含第二气体包含惰性气体、含氧气体或其组合。适合的惰性气体可包含但不限于氦(He)、氖(Ne)、氩(Ar)、氪(Kr)、氙(Xe)及任其组合。在一实施例中，惰性气体为氩。适合的含氧气体可包含但不限于氧(O2)、臭氧(O3)、二氧化碳(CO2)、一氧化碳(CO)及任其组合。在一实施例中，含氧气体为氧。
在本揭露的各种实施例中，氟碳化合物以第一体积流速通入处理室中(例如等离子蚀刻处理室)以及氢氟碳化合物以第二体积流速通入处理室中。第一体积流速与第二体积流速的比例可控制在为约5:1至约40:1，例如约10:1至约25:1，举例来说，为15:1至20:1。含氧气体可以第三体积流速通入处理室，并且第一体积流速与第三体积流速的比例可控制在为约1:1至约10:1，例如约2:1至约8:1，举例来说，为4:1至6:1。第二体积流速与第三体积流速的比例可控制在为约1:1至约1:8，例如约1:2至约1:6，举例来说，为1:3至1:5。惰性气体可以第四体积流速通入处理室，并且第一体积流速与第四体积流速的比例可控制在为约1:10至约1:200，例如约1:15至约1:60，举例来说，为1:20至1:40。第二体积流速与第四体积流速的比例可控制在为约1:20至约1:500，例如约1:40至约1:300，举例来说，为1:60至1:250。
在一例示性的实施例中，其接触蚀刻停止层228为氮化硅，而蚀刻制程使用具有C4F6、O2、CH2F2及Ar的蚀刻气体混合物；具有C4F8、O2、CH2F2及Ar的蚀刻气体混合物；具有C4F6、O2、CH3F及Ar的蚀刻气体混合物；具有C4F8、O2、CH3F及Ar的蚀刻气体混合物。
在一些实施例中，可结合本揭露中任一实施例，蚀刻制程为两步骤的等离子源蚀刻制程，第一步骤使用氟碳化合物及第二步骤使用氢氟碳化合物。可供选择地，第一步骤可使用氢氟碳化合物而第二步骤则使用氟碳化合物。在任一例子中，第一步骤及/或第二步骤可进一步包含如前述所提的第二气体其包含惰性气体、含氧气体或其组合。
举例而言，较浅的源/漏极连接沟槽264可通过两步骤的蚀刻制程来获得，第一步骤使用含有C4F6及O2的蚀刻气体混合物，而第二步骤则使用含有CH2F2及Ar的蚀刻气体混合物。在另一实施例中，蚀刻制程包含第一步骤使用含有C4F8及O2的蚀刻气体混合物，而第二步骤则使用含有CH2F2及Ar的蚀刻气体混合物。在一实施例中，蚀刻制程包含第一步骤使用含有C4F6及O2的蚀刻气体混合物，而第二步骤则使用含有CH3F及Ar的蚀刻气体混合物。在一实施例中，蚀刻制程包含第一步骤使用含有C4F8及O2的蚀刻气体混合物，而第二步骤则使用含有CH3F及Ar的蚀刻气体混合物。
在蚀刻制程期间，处理室可维持在室压为约1mTorr至约300mTorr，例如约10mTorr至约80mTorr，举例来说，可为约20mTorr。室温可维持在为约5摄氏温度至约200摄氏温度，例如约10摄氏温度至约120摄氏温度，举例来说，可为约20摄氏温度至约60摄氏温度。用于产生等离子的射频功率可介于50watts至约3000watts之间，举例来说，可为约100watts至约1000watts，以及射频可为约50kHz至约150MHz，举例来说，可为约400kHz至约60MHz。蚀刻制程次数可倍增以在主动区217及隔离区219达理想的沟槽深度。举例来说，在蚀刻制程期间，源/漏极连接沟槽264的深度"D2"及第一接触沟槽262的深度"D1"可通过调整基板暴露于蚀刻化合物的时间长短而获得控制。在一实施例中，蚀刻制程执行时间为约10秒至约15分钟，例如为约20秒至约5分钟，举例来说，可为约30秒至约1分钟。应理解的是，蚀刻时间可取决于所需深度而有所变化，惟如第二接触沟槽264的深度"D2"与第一层间介电层230、第二层间介电层260及绝缘层212的组合深度"D4"的比例为约1:1.2至约1:1.7，例如为约1:1.3至约1:1.6，举例来说可为约1:1.5。此处所讨论的制程参数是基于300毫米(mm)的基板。
操作106，根据一些实施例，如图2P所示，在第一接触沟槽262及第二接触沟槽264各于主动区217及隔离区219中形成理想的深度后，将第一接触沟槽262及第二接触沟槽264填充导电材料276并随后进行平坦化以暴露出第二层间介电层260的顶面266。第二接触沟槽264因而提供两相邻MOS晶体管间的电性连接，或提供与随后将形成的电性连接结构(例如：接触、导孔、局部互连结构)的电性连接以耦接源/漏极结构226至外部电源及/或其他多层半导体结构中的层间互连结构。另一方面，第一接触沟槽262提供与随后将形成的导电通道/插塞的电性接触，其是用于多层半导体结构中的层间互连结构。
用于导电材料276的适合材料可包含但不限于钴、铜、钌、钯、铂、镍、氧化钌、钨、铝、钛、钽、铪锆、金属碳化物、导电金属氧化物及任其组合。在一实施例中，导电材料276可为钴。第一接触沟槽262及第二接触沟槽264可通过任何适合的技术来形成，例如PVD、电镀、化学气相沉积(CVD)、等离子增强化学气相沉积(PECVD)、脉冲CVD、ALD、PE-ALD或其组合。
在一些实施例中，气隙278形成于导电材料276的底面280与第二接触沟槽264的底面270之间。气隙278的形成部分来自于导电材料276冷却至室温时在体积上的收缩。另一方面，因为主动区217的第一接触沟槽262比隔离区219的第二接触沟槽264还浅，故主动区217的第一接触沟槽262可不具有气隙。由于第二接触沟槽264较深，在一特定时间内，导电材料276不易以如同到达第一接触沟槽262底面一般的情形到达第二接触沟槽264的底面。因此，气隙278较易形成于第二接触沟槽264的底面。
本发明人注意到气隙278有助于防止第二接触沟槽264变形或弯曲时与相邻结构(例如：栅极结构272a或272e下的鳍状物210)发生电性短路的情形。在一些应用上，气隙278有助于防止或使第二接触沟槽264与相邻结构之间的寄生电容最小化。
在一些实施例中，在第二接触沟槽264填充导电材料276之后，可对基板202进行热处理，例如回焊制程或退火制程，借以控制气隙278的尺寸。气隙278的尺寸可通过调整导电材料的回焊温度加以控制。在一些例子中，导电材料276为钴，可执行沉积制程将第二接触沟槽264填充钴。基板202接着冷却至第一温度范围(可介于室温与低于钴的回焊温度之间)以形成气隙278于第二接触沟槽264的底部。其后，基板202可逐渐加热至接近或在回焊温度之上(例如：约200摄氏温度至约500摄氏温度)的第二温度范围以在第二接触沟槽264回焊钴。在第二接触沟槽264回焊钴改变了在第二接触沟槽264底部的气隙278尺寸。
如图2P所示，气隙278具有深度"D5"，定义为导电材料276的底部280至第二接触沟槽264的底面270的量测距离。在各种实施例中，气隙278的深度"D5"与第二接触沟槽264的深度"D2"的比例为约1:3至约1:40，例如为约1:4至约1:20，举例来说可为约1:5至约1:10。
在第一接触沟槽262及第二接触沟槽264填充导电材料276之后，可对基板202进行额外的制程，例如制造多层互连结构所需的金属化制程。
本揭露的实施例使用改良的蚀刻制程通过同时将基板暴露于由碳氟化合物、氢氟碳化合物、含氧气体和惰性气体所组成的等离子种类，从而在基板的主动区域形成第一接触沟槽以及在围绕主动区域的隔离区域形成第二接触沟槽。等离子种类使第一接触沟槽穿过介电层及蚀刻停止层得以形成，并以比隔离区的材料还快的速率暴露出部分源/漏极接触，导致与未采用改良制程的蚀刻制程而在隔离区形成的传统较深的接触沟槽相比，第二接触沟槽深度有所减少。具有减少深度的第二接触沟槽使得在填充导电材料时沿第二接触沟槽深度的沟槽轮廓的变形或弯曲最小化。即使第二接触沟槽有所变形或弯曲，第二接触沟槽的较浅沟槽轮廓亦可防止第二接触沟槽接触相邻的栅极结构。在一些实施例中，第二接触沟槽可具有气隙形成于第二接触沟槽的底部以防止第二接触沟槽与相邻栅极结构电性短路。因此，第二接触沟槽与相邻栅极结构之间的寄生电容可被预防或最小化。
在一实施例中，半导体元件包含基板、绝缘层形成于基板之上、多个鳍状物垂直地形成自基板的表面，这些鳍状物延伸穿过绝缘层且于绝缘层的顶面之上、栅极结构形成于这些鳍状物的一部分之上及绝缘层的顶面之上、源极/漏极结构配置相邻于栅极结构的相对两侧，源极/漏极结构接触鳍状物的一部分、介电层形成于绝缘层之上、第一接触沟槽以第一深度延伸穿过介电层以暴露源极/漏极结构，第一接触沟槽含有导电材料以及第二接触沟槽以第二深度延伸穿过介电层，第二接触沟槽包含导电材料，且第二深度大于第一深度。在一些实施例中，半导体元件进一步包含气隙配置于第二接触沟槽的底面。在一些实施例中，气隙的深度与第二接触沟槽的深度的比例为约1:5至约1:10。在一些实施例中，第二深度与介电层的厚度的比例为约1:1.2至约1:1.5。在一些实施例中，蚀刻停止层包含氮化硅、氧化硅、氮氧化硅、碳化硅、碳氮化硅、氮化硅硼、碳氮化硅硼及其组合。在一些实施例中，导电材料包含钴、铜、钌、钯、铂、镍、氧化钌、钨、铝、钛、钽、铪锆、金属碳化物、导电金属氧化物或任其组合。
在另一实施例中，半导体元件包含基板、鳍状物垂直地形成自基板的表面、绝缘层形成于基板之上，绝缘层覆盖该鳍状物的一底部的两侧、栅极结构形成于鳍状物之上且于绝缘层之上、源极/漏极结构配置于栅极结构的相对两侧，源极/漏极结构接触鳍状物的顶部、第一介电层具有第一部分形成于绝缘层之上且具有第二部分形成于源极/漏极结构之上，第一介电层的顶面与栅极结构的顶面实质上共平面、第二介电层形成于第一介电层之上、第一接触沟槽延伸穿过第二介电层及第一介电层的第二部分以暴露出源极/漏极结构的一部分，第一接触沟槽含有导电材料以及第二接触沟槽延伸穿过第二介电层并以一深度穿入第一介电层的第一部分，第二接触沟槽被部分填入导电材料以提供气隙介于导电材料与第二接触沟槽的底面之间。在一些实施例中，半导体元件进一步包含蚀刻停止层配置于第一介电层的第二部分与源极/漏极结构之间。在一些实施例中，第二接触沟槽的深度与绝缘层、第一介电层的第一部分及第二介电层的结合厚度的比例为约1:1.1至约1:1.6。在一些实施例中，第二接触沟槽的深度与第一接触沟槽的深度的比例为约1:0.4至约1:0.9。在一些实施例中，蚀刻停止层包含氮化硅、氧化硅、氮氧化硅、碳化硅、碳氮化硅、氮化硅硼、碳氮化硅硼及其组合。在一些实施例中，导电材料包含钴、铜、钌、钯、铂、镍、氧化钌、钨、铝、钛、钽、铪锆、金属碳化物、导电金属氧化物或任其组合。在一些实施例中，第一及第二接触沟槽各具有高宽比为约5:1至约30:1。
尚有另一实施例中，半导体元件的制造方法包含形成绝缘层于基板之上、自基板的表面形成多个鳍状物，这些鳍状物垂直地延伸穿过绝缘层且在绝缘层的顶面的上方、形成栅极结构于这些鳍状物的部分之上及绝缘层的顶面之上、形成源极/漏极结构在栅极结构的相对两侧，源极/漏极结构接触鳍状物的一部分、形成蚀刻停止层于源极/漏极结构之上、形成介电层于绝缘层之上、形成第一接触沟槽穿过介电层及蚀刻停止层以暴露出源极/漏极结构、形成第二接触沟槽于介电层中至一深度，其中第一及第二接触沟槽是通过将基板同时暴露于由氟碳化合物、氢氟碳化合物、含氧气体及惰性气体所形成的等离子种类来形成以及以导电材料填充第一及第二接触沟槽。在一些实施例中，深度与介电层的厚度的比例为约1:1.2至约1:1.5。在一些实施例中，氟碳化合物具有CxFy的结构，其中x及y为正整数，氢氟碳化合物具有CxHyFz的结构，其中x、y、z为正整数。在一些实施例中，氟碳化合物以第一体积流速通入设有基板的处理室中、氢氟碳化合物以第二体积流速通入处理室中以及含氧气体以第三体积流速通入处理室中，其中第一体积流速与第二体积流速的比例为约5:1至约10:1，而第一体积流速与第三体积流速的比例为约2:1至约8:1。在一些实施例中，氟碳化合物为六氟丁二烯(C4F6)、氢氟碳化合物为二氟甲烷(CH2F2)、含氧气体为氧以及惰性气体为氩。在一些实施例中，第一接触沟槽及该第二接触沟槽的形成是通过将基板同时暴露于由氟碳化合物及含氧气体所形成的等离子种类，其中氟碳化合物具有CxFy的结构，其中x及y为正整数，且将基板同时暴露于由氢氟碳化合物及惰性气体所形成的等离子种类，其中氢氟碳化合物具有CxHyFz的结构，其中x、y、z为正整数。在一些实施例中，半导体元件的制造方法进一步包含形成气隙于第二接触沟槽的底面，并且气隙的深度与第二接触沟槽的深度比例为约1:5至约1:10。
前文概述数个实施例的特征以使得熟悉该项技术者可更好地理解本揭露的态样。熟悉该项技术者应了解，可容易地将本揭露内容用作设计或修改用于实现相同目的及/或达成本文引入的实施例的相同优点的其他制程及结构的基础。熟悉该项技术者亦应认识到，此类等效物构造不违背本揭露内容的精神及范畴，且可在不违背本揭露内容的精神及范畴的情况下于此作出各种变化、替代以及变更。

Claims (1)

1.一种半导体元件，其特征在于，包含：
一基板；
一绝缘层，形成于该基板之上；
多个鳍状物，垂直地形成自该基板的一表面，所述多个鳍状物延伸穿过该绝缘层且于该绝缘层的一顶面之上；
一栅极结构，形成于所述多个鳍状物的一部分之上及该绝缘层的该顶面之上；
一源极/漏极结构，配置相邻于该栅极结构的相对两侧，该源极/漏极结构接触该鳍状物的一部分；
一介电层，形成于该绝缘层之上；
一第一接触沟槽，以一第一深度延伸穿过该介电层以暴露该源极/漏极结构，该第一接触沟槽含有一导电材料；以及
一第二接触沟槽，以一第二深度延伸穿过该介电层，该第二接触沟槽包含该导电材料，且该第二深度大于该第一深度。
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