CN108231563A - 制造半导体装置的方法 - Google Patents

制造半导体装置的方法 Download PDF

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Publication number
CN108231563A
CN108231563A CN201711035734.3A CN201711035734A CN108231563A CN 108231563 A CN108231563 A CN 108231563A CN 201711035734 A CN201711035734 A CN 201711035734A CN 108231563 A CN108231563 A CN 108231563A
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China
Prior art keywords
layer
gate electrode
height
semiconductor device
electrode structure
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CN201711035734.3A
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罗伊辰
林立德
黄玉莲
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种制造半导体装置的方法，包括形成栅极电极结构于半导体基板的第一区域之上，和通过使卤化物与氧气反应，选择性地形成覆盖栅极电极结构的氧化物层，以增加栅极电极结构的高度。卤化物可以是四氯化硅，而氧化物层可以是二氧化硅。栅极电极结构可以是虚设栅极电极，其在随后被移除，并且被另一个栅极电极结构取代。

Description

制造半导体装置的方法
技术领域
本发明实施例是有关一种制造半导体装置的方法；特别是关于一种在半导体装置处理期间，增加半导体装置的各种元件的水平高度的方法。
背景技术
因为半导体工业已经进入纳米科技制程阶段，以追求较高的装置密度、较高的性能、以及较低的成本，从而导致制造和设计等问题需要克服。尤其，增加装置密度已产生了非常高的栅极高度和栅极高宽比。高的栅极高度和栅极高宽比往往导致栅极倾斜或倒塌。此外，随着在半导体装置上执行更多的步骤以增加装置密度，越来越多的制程步骤暴露出栅极电极，其可能劣化(degrade)栅极电极并导致栅极电极的高度收缩变矮。如果栅极高度太矮，则在形成覆盖层期间，装置可能会受到损害。所以，期望一种能在整个半导体处理操作中，保持适当的栅极高度的方法。
发明内容
一种制造半导体装置的方法，包括形成一栅极电极结构于一半导体基板的一第一区域之上；以及通过使一卤化物与一氧气反应，选择性地形成覆盖栅极电极结构的一氧化物层，以增加栅极电极结构的一高度。
附图说明
当结合附图阅读时，从以下详细描述中可以更好地理解本揭示内容的各个方面。应注意，依据工业中的标准实务，多个特征并未按比例绘制。实际上，多个特征的尺寸可任意增大或缩小，以便使论述明晰。
图1为根据本揭示内容的一实施例的半导体装置的平面示意图；
图2揭示根据本揭示内容的一实施例的用于制造半导体装置的连续制程的一个阶段的示意图；
图3揭示根据本揭示内容的一实施例的用于制造半导体装置的连续制程的一个阶段中，沿着图1的A-A线的剖面示意图，此连续制程是在图2的装置上执行的；
图4揭示根据本揭示内容的一实施例的用于制造半导体装置的连续制程的一个阶段的示意图，此连续制程是在图3的装置上执行的；
图5揭示根据本揭示内容的一实施例的用于制造半导体装置的连续制程的一个阶段的示意图，此连续制程是在图4的装置上执行的；
图6揭示根据本揭示内容的一实施例的用于制造半导体装置的连续制程的一个阶段中，沿着图1的B-B线的剖面示意图，此连续制程是在图5的装置上执行的；
图7揭示根据本揭示内容的一实施例的连续制程的一个阶段的示意图，此连续制程是在图6的装置上执行的；
图8揭示根据本揭示内容的一实施例的用于制造半导体装置的连续制程的一个阶段的示意图，此连续制程是在图7的装置上执行的；
图9揭示根据本揭示内容的一实施例的图8的半导体装置沿着图1的A-A线的剖面示意图的一个阶段的示意图；
图10揭示根据本揭示内容的一实施例的用于制造半导体装置的连续制程的沿着图1的B-B线的剖面示意图一个阶段的示意图，此连续制程是在图8的装置上执行的；
图11揭示根据本揭示内容的一实施例的用于制造半导体装置的连续制程的一个阶段的示意图，此连续制程是在图10的装置上执行的；
图12揭示根据本揭示内容的另一实施例的用于制造半导体装置的连续制程的一个阶段的示意图，此连续制程是在图11的装置上执行的；
图13揭示根据本揭示内容的一实施例的用于制造半导体装置的连续制程的一个阶段的示意图，此连续制程是在图12的装置上执行的；
图14揭示根据本揭示内容的一实施例的用于制造半导体装置的连续制程的一个阶段的示意图，此连续制程是在图13的装置上执行的；
图15揭示根据本揭示内容的一实施例的用于制造半导体装置的连续制程的一个阶段的示意图，此连续制程是在图14的装置上执行的；
图16揭示根据本揭示内容的一实施例的用于制造半导体装置的连续制程的一个阶段的示意图，此连续制程是在图14的装置上执行的；
图17揭示根据本揭示内容的一实施例的用于制造半导体装置的连续制程的一个阶段的示意图，此连续制程是在图16的装置上执行的；
图18揭示根据本揭示内容的一实施例的用于制造半导体装置的连续制程的一个阶段的示意图，此连续制程是在图17的装置上执行的；
图19揭示根据本揭示内容的一实施例的用于制造半导体装置的连续制程的一个阶段的示意图，此连续制程是在图18的装置上执行的。
具体实施方式
应当理解，以下揭示案提供许多不同实施例或实例以用于实现所提供标的物的不同的特征。下文描述组件及排列的特定实例以简化本揭示内容。当然，此等仅仅为实例，并不旨在限制本揭示内容。例如，元件的尺寸不限于所揭示的范围或值，而是可以取决于装置的制程条件和/或所需性质。此外，在随后描述中的在第二特征之上或在第二特征上形成第一特征可包括形成直接接触的第一特征和第二特征的实施例，还可以包括在第一特征和第二特征之间形成额外特征，从而使第一特征和第二特征不直接接触的实施例。出于简化及清楚的目的，可以以不同的尺度任意绘制各种特征。
另外，空间相对用语，诸如“下方”、“以下”、“下部”、“上方”、“上部”及类似者，在此用于简化描述附图所示的一个元件或特征与另一元件(或多个元件)或特征(或多个特征)的关系。除附图中描绘的方向外，空间相对用语旨在包含于使用或操作中的装置的不同方向。装置可为不同的方向(旋转90度或在其他的方向)，并且在此使用的空间相关描述词也可相应地被解释。此外，用语“由...制成”可能意味着“包括”或“由...组成”。
为了防止半导体装置在半导体装置的建构制程期间被损坏，保持半导体装置的各种组件的适当的水平高度是重要的。水平高度可能会因为多种半导体处理步骤(包括各种蚀刻操作)而降低。根据本揭示内容的一些实施例，为了抵消水平高度收缩，在半导体处理期间，增加了栅极电极高度或层间介电层的高度。
图1是根据本揭示内容的半导体装置的一实施例的平面示意图。
图2至图11揭示了根据本揭示内容的多个实施例的用于制造半导体装置的多个示例性连续制程。应当理解，可以在图2至图11所示的多个处理之前、期间、以及之后，提供额外的多个操作，并且对于方法中的特定实施例，可以替换或排除下面描述的一些操作。多个操作/制程的顺序是可以互换的。
图1绘示半导体装置的平面示意图。如图1所示，形成多个栅极电极结构65覆盖多个鳍状结构15。虽然是揭示了三个鳍状结构和三个栅极电极结构，根据本揭示内容的多个方法和装置可以包括一个、两个、四个或更多个的鳍状结构和一个、两个、四个或更多个的栅极电极结构。
在本揭示内容的一些实施例中，提供半导体基板10。基板10包括至少在其表面部分上的单晶半导体层。基板10可以包括单晶半导体材料，例如但不限于Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb、InP或其任何组合。在一特定实施例中，基板10由Si制成。
如图3所示，在一些实施例中，图案化半导体基板10，以形成多个鳍状结构15。在一些实施例中，通过多个光微影和蚀刻操作，图案化半导体基板10。在其他实施例中，通过多个半导体材料沉积操作，形成鳍状结构15于基板10上。如图1所示，鳍状结构15在第一方向(例如Y方向)上延伸，并且多个鳍状结构15沿着第二方向(例如X方向)排列，第二方向大致上垂直于第一方向。
可以通过任何合适的方法图案化鳍片。例如，可以使用一个或多个光微影制程来图案化鳍片，包括双重图案化或多重图案化制程。通常，双重图案化或多重图案化制程结合多个光微影和自对准(self-aligned)制程，从而允许所产生的多个图案具有例如多个间距(pitches)，此多个间距小于使用单个、直接的光微影制程所得到的多个图案的间距。例如，在一实施例中，形成牺牲层于基板之上，并且使用光微影制程图案化牺牲层。使用自对准制程形成与图案化的牺牲层并排靠着的间隔件。接着，移除牺牲层，并且可以使用剩余的间隔件来图案化多个鳍片。
在一些实施例中，如图4所示，隔离绝缘层20(例如浅沟槽隔离区)填充于鳍状结构15之间的空间。
隔离绝缘层20包括一层或多层绝缘材料。用于绝缘层20的绝缘材料可以包括氧化硅、氮化硅、氮氧化硅(SiON)、SiOCN、氟掺杂硅酸盐玻璃(fluorine-doped silicateglass，FSG)、低k介电材料或通过低压化学气相沉积(low pressure chemical vapordeposition，LPCVD)、等离子辅助化学气相沉积(plasma enhanced chemical vapordeposition，PECVD)或可流动式化学气相沉积(flowable CVD)所形成的任何其他合适的介电材料。在形成隔离绝缘层20之后，可以执行退火操作。
在一些实施例中，如图4所示，隔离绝缘材料在鳍状结构的最高表面之上延伸，并且随后执行诸如化学机械研磨(chemical mechanical polishing，CMP)法和/或回蚀刻(etch-back)法的平坦化操作，以移除隔离绝缘层20的上部。进一步地，如图5所示，进行额外的回蚀操作或蚀刻操作，以减少隔离绝缘层20的高度。在特定实施例中，从隔离绝缘层20突出的鳍状结构15的多个部分，将成为半导体装置的通道区，而嵌入隔离绝缘层20的鳍状结构15的多个部分，将成为半导体装置的井区。
在一些实施例中，如图6(沿着图1的B-B线的剖面示意图)所示，形成栅极堆叠结构于鳍状结构15上。栅极堆叠结构包括在鳍状结构15上形成的栅极介电层25、在栅极介电层25上形成的栅极电极层30、以及在栅极电极层30上形成的硬罩幕层35。在一些实施例中，栅极堆叠结构是虚设栅极堆叠结构，栅极介电层25是虚设栅极介电层，并且栅极电极层30是虚设栅极电极层。
在特定实施例中，栅极介电层25包括一层或多层介电材料(例如氧化硅、氮化硅)、高k介电材料、其他合适的介电材料和/或其组合。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高k介电材料和/或其组合。在一些实施例中，栅极介电层25包括在鳍状结构15和介电材料之间形成的界面层(未绘示)。
栅极介电层25可以通过化学气相沉积、原子层沉积(atomic layer deposition，ALD)或任何合适的方法来形成。在一些实施例中，栅极介电层25的厚度范围为约1nm至约6nm。
栅极电极层30形成于栅极介电层25上。栅极电极层30包括一层或多层导电材料，例如多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其他合适的材料和/或其组合。栅极电极层30可以通过化学气相沉积、原子层沉积、电镀或其他合适的方法来形成。
在本揭示内容的特定实施例中，一个或多个功函数调整层(未绘示)夹置于栅极介电层25和栅极电极层30之间。功函数调整层由导电材料制成，导电材料例如为TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单层，或者这些材料的两种或多种的多层。对于N型场效晶体管(n-type field effect transistor,nFET)，使用TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi、以及TaSi中的一种或多种作为功函数调整层，而对于P型场效晶体管(p-type field effect transistor,pFET)，使用TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC、以及Co中的一种或多种作为功函数调整层。功函数调整层可以通过原子层沉积、物理气相沉积、化学气相沉积、电子束蒸镀(e-beam evaporation)或其他合适的制程来形成。进一步地，针对N型场效晶体管和P型场效晶体管，可以分别使用不同的金属层来形成功函数调整层。
在一些实施例中，当栅极堆叠是虚设栅极堆叠时，栅极介电层25是氧化硅，并且栅极电极层30是多晶硅。
在一些实施例中，硬罩幕层35可以包括一层或多层氮化硅或氧化硅，并且可以通过化学气相沉积、物理气相沉积、原子层沉积或任何其他合适的技术来形成。
如图7所示，随后通过图案化栅极堆叠结构形成栅极电极结构32。使用光微影和蚀刻技术图案化硬罩幕层35，然后硬罩幕中的图案延伸通过栅极电极层30和栅极介电层25，并且使用诸如非等向性蚀刻的适当蚀刻技术来暴露鳍状结构15。栅极电极结构32沿着与鳍状结构15延伸的第一方向(Y方向)大致垂直的第二方向(X方向)延伸。栅极电极结构32包括栅极介电层25和栅极电极层30。在一些实施例中，栅极电极结构32还包括设置在栅极电极层30和栅极介电层25的相对侧壁上的栅极侧壁45(参见图10)。在一些实施例中，在图案化栅极电极结构之后，移除硬罩幕层35。
在一些实施例中，如图7所示，栅极电极结构32具有高度H1，高度H1是从鳍状结构15的顶部到栅极电极层30的最上表面或到硬罩幕层35测量得到。在特定实施例中，高度H1的范围为30nm至300nm。
在半导体装置处理的过程中，因为各种蚀刻操作(例如多晶硅图案化操作)，降低了栅极电极层的高度。如图8所示，栅极电极层30和硬罩幕层35具有高度H2，高度H2是从鳍状结构15的顶部到栅极电极层30的最上表面或到硬罩幕层35测量得到，其中高度H2<H1。在一些实施例中，H2的范围为约30nm至约290nm。为了增加高度，如图8所示，随后选择性地形成氧化硅层40于栅极电极结构32上。
根据本揭示内容的一些实施例，执行氧化硅沉积操作，以增加栅极电极结构32的高度，从而形成氧化硅层40。在特定实施例中，氧化硅层40的高度H3的范围为约5nm至约20nm。在特定实施例中，(H2+H3)≥H1。
在一些实施例中，通过沉积由卤化硅和氧气反应所形成的二氧化硅，增加了栅极电极结构层32的高度。在特定实施例中，卤化硅是四氯化硅，并且根据下式进行氧化硅沉积：SiCl4+O2→SiO2+2Cl2。
在半导体装置制造期间，可以沉积氧化硅层40于多个位置。在特定实施例中，在图案化栅极电极层之后、在金属栅极回蚀之后或在自对准接触件形成之后，执行二氧化硅沉积，以增加水平高度(层间介电层高度或栅极高度)。
在一些实施例中，沉积氧化硅层是在约55℃至约110℃的温度和约1.9mT至约5mT的压力下，执行等离子沉积。在特定实施例中，使用具有约100sccm至约200sccm流速的氮气气体载体。在一些实施例中，SiCl4和O2流速范围为约4sccm至约16sccm。在特定实施例中，SiCl4流速和O2流速均为约8sccm。在一些实施例中，SiCl4流速与O2流速的比例为约4/1至约1/100。
根据本揭示内容，透过四氯化硅的氧化而沉积的二氧化硅，没有形成保形涂层(conformal coating)于半导体装置上。氧化硅层40是沉积于栅极电极层30或硬罩幕层35的顶表面上，或者是沉积在绝缘层的顶表面上，例如层间绝缘层的顶表面上，而不是在侧壁上。此外，相较于沉积于硅表面或金属表面上，根据上述操作所沉积的二氧化硅，优先地沉积于含氧的表面上，例如氧化硅。因为氧气等离子氧化硅和金属表面，一些二氧化硅也将沉积于硅和金属表面上。根据一些实施例，二氧化硅沉积增加了层间介电层的高度，而大致上没有形成氧化物层于硅或金属表面之上。在一些实施例中，沉积在硅或金属表面上的二氧化硅的量为沉积在层间介电层上的量的约1/10至约1/100。在一些实施例中，在二氧化硅表面上的二氧化硅的沉积速率是二氧化硅沉积于硅或金属表面上的速率的约10倍至约100倍。在一些实施例中，二氧化硅将以较低速率沉积于氮化物表面(例如氮化硅表面)上，此较低速率指的是比二氧化硅沉积于氧化物表面上的速率还低。在一些实施例中，在二氧化硅表面上的二氧化硅的沉积速率与沉积于氮化物表面上的速率相比，为大致相同至约三倍。然而，一旦形成氧化硅层40于氮化物表面上，则二氧化硅沉积的速率将增加，因为后来沉积的二氧化硅将沉积于氧化物表面上，而不是沉积于氮化物表面上。根据四氯化硅氧化操作而沉积的二氧化硅，与下表面(例如在沟槽中和在栅极电极结构32之间的表面)相比，优先地沉积于最上面的可接受表面(氧化物表面)上。
在一些实施例中，在二氧化硅的沉积期间，将Cl2/NF3的蚀刻剂气体混合物引入SiCl4和O2等离子中。在一些实施例中，二氧化硅沉积和蚀刻同时发生。在装置的较高部分，沉积速率大于蚀刻速率，而在装置的较低部分，例如在栅极之间的沟槽中，蚀刻速率大于二氧化硅沉积速率。其结果是，沉积在装置的较低部分的少量二氧化硅被蚀刻剂所移除。在一些实施例中，Cl2的流速范围为8sccm至20sccm，NF3的流速范围为10sccm至20sccm。在特定实施例中，Cl2的流速为13sccm，NF3的流速为16scccm。在一些实施例中，Cl2/NF3流速的比例范围为约3/1至约0(即不含Cl2流)。
图9是沿着图1的A-A线剖面示意图，其中绘示栅极电极层30、围绕鳍状结构15的栅极介电层25以及形成在栅极电极层30上的硬罩幕层35和氧化硅层40。
图10是沿着图1的B-B线的剖面示意图，绘示绝缘侧壁间隔件45形成于栅极电极层30的侧壁、栅极介电层25的侧壁、硬罩幕层35的侧壁、以及氧化硅层40的侧壁上；并且源极/漏极区域90形成于鳍状结构15中的栅极电极结构32的相对侧。可以通过合适的沉积和蚀刻技术来形成侧壁间隔件45，并且侧壁间隔件45可以包括一层或多层氮化硅、氧化硅、碳化硅、氮氧化硅、氮氧碳化硅、其他合适的材料或其组合。
侧壁绝缘材料的毯覆层可以通过化学气相沉积、物理气相沉积、原子层沉积或其他合适的技术来形成。然后，对侧壁绝缘材料执行非等向性蚀刻，以形成一对侧壁绝缘层(间隔件)45于栅极电极层30、栅极介电层25、硬罩幕层35、以及氧化硅层40的两个主侧面上。在一些实施例中，侧壁间隔件45的厚度范围为约5nm至约30nm，而在其他实施例中，则为约10nm至约20nm。
在一些实施例中，如图10所示，随后形成源极/漏极区域90于栅极电极结构32的相对侧上。在本揭示内容中使用源极/漏极来指明源极区域或漏极区域。在一些实施例中，可以通过注入掺杂剂到鳍状结构15中来形成源极/漏极区域90。在一些实施例中，掺杂剂选自磷、砷、锑、硼、氟化硼、铝或镓。在一些实施例中，掺杂剂以1×1017至1×1021atoms/cm3的浓度注入鳍状结构。
在一些实施例中，使即将形成源极/漏极区域90的鳍状结构15的部分凹陷或被蚀刻，并且随后通过一或多个磊晶成长制程来形成源极/漏极区域90，从而形成一个或多个Si、SiC、SiGe、SiP、SiCP或III-V族半导体材料的结晶层于鳍状结构15上。如上所述，结晶层掺杂有合适的掺杂剂。磊晶制程包括化学气相沉积技术(例如气相磊晶(vapor-phaseepitaxy，VPE)和/或超真空化学气相沉积(ultra-high vacuum CVD，UHV-CVD))、分子束磊晶和/或其他合适的制程。在其他实施例中，在没有形成凹陷的情况下，形成磊晶成长的源极/漏极区域90。
如图11所示，形成蚀刻停止层95和层间介电层50于图10的装置之上，而覆盖栅极电极结构32和源极/漏极区域90。层间介电层50具有从鳍状结构15的顶表面测量得到的高度H4。在一些实施例中，高度H4的范围为约80nm至约450nm。在一些实施例中，蚀刻停止层95包括一层或多层绝缘材料，例如包括SiN、SiCN、以及SiOCN的氮化硅基材料。在一些实施例中，蚀刻停止层95的厚度范围为约3nm至约15nm，在其他实施例中，则为约4nm至约8nm。在一些实施例中，层间介电层50是由绝缘材料制成的绝缘层，例如一层或多层氧化硅、氮化硅、低k介电材料或其组合。可以通过化学气相沉积来形成层间介电层50。在特定实施例中，层间介电层50的介电质是旋涂式玻璃(spin on glass，SOG)，包括磷硅酸盐玻璃(phosphosilicate glass，PSG)或硼磷硅玻璃(borophosphosilicate glass，BPSG)。
图12至图15揭示根据本揭示内容的另一实施例的用于制造半导体装置的连续制程的沿着图1的B-B线的剖面示意图。
在此实施例中，栅极电极层30和栅极介电层25是虚设栅极电极层和虚设栅极介电层。例如通过化学机械研磨来平坦化层间介电层50，并且移除硬罩幕层35和氧化硅层40(如果存在)。如图12所示，随后通过光微影以及蚀刻来移除虚设栅极电极层和虚设栅极介电层，以产生栅极空间55。
如图13所示，随后形成高k栅极介电层60和金属栅极电极层65于栅极空间55中。用于高k栅极介电层60的高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、氧化钛、二氧化铪-氧化铝(HfO2-Al2O3)合金、其他合适的高k介电材料或其任何组合。在一些实施例中，栅极介电层60包括在鳍状结构15和栅极介电层60之间形成的界面层(未绘示)。可以通过化学气相沉积、原子层沉积或任何合适的方法来形成栅极介电层60。
金属栅极电极层65包括一层或多层金属，例如铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其他合适的材料或其任何组合。可以通过化学气相沉积、原子层沉积、电镀或其他合适的方法来形成金属栅极电极层65。
在本揭示内容的特定实施例中，一个或多个功函数调整层(未绘示)可夹置于栅极介电层60与栅极电极层65之间。功函数调整层由导电材料制成，例如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi、TiAlC的单层、这些材料的两种或多种的多层或其任何组合。可以通过原子层沉积、物理气相沉积、化学气相沉积、电子束蒸镀或其他合适的方法来形成功函数调整层。
在一些实施例中，如图14所示，随后在金属栅极回蚀操作中，蚀刻而使金属栅极电极层65凹陷，以形成凹部70。在回蚀操作之后，层间介电层50具有高度H6，高度H6是从鳍状结构15的顶表面到层间介电层50的最上表面测量得到。在一些实施例中，层间介电层50的高度H6为约70nm至约300nm。
在特定实施例中，在图案化栅极电极层之后、在金属栅极回蚀之后或在自对准接触件形成之后，执行二氧化硅沉积，以增加水平高度(层间介电层高度)。例如，在金属栅极回蚀操作期间或在作为自对准接触件形成的一部分的氮化硅硬罩幕移除操作期间，层间介电层50的高度可能会损失，使得层间介电层50的高度H6小于在回蚀或硬罩幕移除操作之前的高度H5(参见图13)。
如图15所示，在一些实施例中，通过形成氧化硅层75于层间介电层50上，使层间介电层50的高度增加。在特定实施例中，氧化硅层75的高度H7为约5nm至约20nm。在特定实施例中，(H6+H7)≥H5。
在一些实施例中，通过沉积由卤化硅和氧气反应所形成的氧化硅层75，增加了层间介电层50的高度。在特定实施例中，卤化硅是四氯化硅，并且根据下式进行氧化硅沉积：SiCl4+O2→SiO2+2Cl2。
透过四氯化硅的氧化而沉积的二氧化硅，没有形成保形涂层于半导体装置上。如图15所示，与金属栅极电极层65的顶部相比，氧化硅层75优选地沉积于层间介电层50的顶表面上。根据一些实施例，二氧化硅沉积增加了层间介电层50的高度，而大致上没有形成氧化物层于金属栅极电极层65上。在一些实施例中，沉积在金属栅极电极层65的顶部上的二氧化硅的量为沉积在层间介电层50上的量的约1/10至约1/100。在一些实施例中，在二氧化硅表面上的二氧化硅沉积速率是在金属栅极电极层65的顶部上的二氧化硅沉积速率的约10倍至约100倍。
图16至图19揭示根据本揭示内容的另一实施例的用于制造半导体装置的连续制程的沿着图1的B-B线的剖面示意图。在一些实施例中，如图16所示，形成帽盖绝缘层80于图14的凹陷的金属栅极电极层65之上。帽盖绝缘层80包括一层或多层绝缘材料，例如包括SiN、SiCN、以及SiOCN的氮化硅基材料。可以通过化学气相沉积、包括溅镀的物理气相沉积、原子层沉积或其他合适的成膜方法来形成帽盖绝缘层80。在一些实施例中，形成帽盖绝缘层80于层间介电层50之上，并且执行平坦化操作，例如回蚀制程和/或化学机械研磨制程，从而获得图16的结构。在一些实施例中，帽盖绝缘层80的厚度范围为约10nm至约250nm，在其他实施例中，则为约15nm至约80nm。在一些实施例中，形成帽盖绝缘层80以作为自对准接触件形成操作的一部分。
如图17所示，在一些实施例中，随后蚀刻而使帽盖绝缘层80凹陷，以形成凹部110。由于各种蚀刻操作可能造成层间介电层50的高度降低，从而提供了高度H8，其中H8<H5。因此，在一些实施例中，通过形成氧化硅层85于层间介电层50上，以增加层间介电层50的高度。在特定实施例中，氧化硅层85的高度H9的范围为约5nm至约20nm。在特定实施例中，(H8+H9)≥H5。
在一些实施例中，通过沉积由卤化硅和氧气反应所形成的二氧化硅，增加了层间介电层50的高度。在特定实施例中，卤化硅是四氯化硅，并且根据下式进行氧化硅沉积：SiCl4+O2→SiO2+2Cl2。在一些实施例中，二氧化硅将以较低速率沉积于氮化物表面(例如帽盖绝缘层80)上，此较低速率指的是比二氧化硅沉积于氧化物表面上的速率还低。在一些实施例中，在二氧化硅表面上的二氧化硅的沉积速率与沉积于帽盖绝缘层80上的速率相比，为大致相同至约三倍。
图18绘示形成第二层间介电层115于图17的装置之上。在一些实施例中，第二层间介电层115是由绝缘材料制成的绝缘层，绝缘材料例如为一层或多层氧化硅、氮化硅、低k介电材料或其组合。可以通过化学气相沉积来形成层间介电层115。在特定实施例中，层间介电层115的介电质是旋涂式玻璃，包括磷硅酸盐玻璃或硼磷硅玻璃。
在一些实施例中，通过使用合适的光微影和蚀刻操作，形成多个通孔于层间介电层50和层间介电层115中。如图19所示，使用合适的材料沉积技术，形成源极/漏极接触件120于一些通孔中，提供了到源极/漏极区域90的电接触，并且形成栅极电极接触件125于一些通孔中，提供了到栅极电极层65的电接触。在一些实施例中，在形成接触件120和接触件125之前，形成接触阻挡内榇层于通孔中(未绘示)。在一些实施例中，由金属氮化物(如TaN或TiN)形成接触阻挡内榇层。可以通过原子层沉积、物理气相沉积、化学气相沉积或其他合适的制程来形成接触阻挡内榇层。在一些实施例中，接触件120和接触件125由铝、铜、钛、钽、钨、钴、钼、镍、其合金、以及其他合适的导电材料所形成。可以通过化学气相沉积、原子层沉积、电镀或其他合适的方法来形成接触件120和接触件125。
应当理解，半导体装置可经历进一步的制造制程，以形成各种特征，例如接触件/通孔、互连金属层、介电层、钝化层等。在半导体装置上执行的额外操作可以包括光微影、蚀刻、化学机械研磨、包括快速热退火的热处理、沉积、包括离子植入的掺杂、光阻灰化、以及液体溶剂清洗。
本揭示内容提供了增加栅极电极结构或层间介电层高度的方法。特定的半导体处理操作(例如栅极电极层的图案化、金属栅极回蚀、以及自对准接触件形成)可能导致栅极电极或层间介电质的损失。在特定实施例中，为了恢复栅极电极或层间介电层的原始高度，在图案化栅极电极层之后、在金属栅极回蚀之后或在自对准接触件形成之后，执行二氧化硅沉积，以增加水平高度(层间介电层高度或栅极高度)，从而提高半导体制造制程的产量。
本揭示内容有助于防止高的高宽比的栅极电极的多晶硅倒塌。本揭示内容还免除了使用表面活性剂的表面修饰技术，此使用表面活性剂的表面修饰技术用于防止高的高宽比的栅极电极的多晶硅倒塌，但在此表面修饰技术之后需要移除所使用的表面活性剂。
应当理解，并不是所有的优势都在本揭示内容中被讨论，对于所有的实施例或实例并不需要特别的优势，并且其他实施例或实例可以提供不同的优势。
本揭示内容的一实施例是一种制造半导体装置的方法，包括形成栅极电极结构于半导体基板的第一区域之上，以及通过使卤化物与氧气反应，选择性地形成覆盖栅极电极结构的氧化物层，以增加栅极电极结构的高度。在一实施例中，卤化物是四氯化硅。在一实施例中，氧化物层是二氧化硅。在一实施例中，覆盖栅极电极结构的氧化物层的高度为约5nm至约20nm。在一实施例中，在形成栅极电极结构之前，方法包括图案化基板以形成沿第一方向延伸的鳍片，和形成覆盖鳍片并沿第二方向延伸的栅极电极结构，第二方向基本上垂直于第一方向。在一实施例中，方法包括形成源极/漏极区域于半导体基板的第二区域上，其中半导体基板的第二区域位于栅极电极结构的相对侧。在一实施例中，形成栅极电极结构包括形成覆盖基板的栅极介电层、形成覆盖栅极介电层的栅极电极层、形成覆盖栅极电极层的硬罩幕层、图案化硬罩幕层以形成图案化的硬罩幕、以及移除没有被硬罩幕所覆盖的栅极电极层和栅极介电层的部分。在一实施例中，形成的氧化物覆盖硬罩幕。
本揭示内容的另一实施例是一种制造半导体装置的方法，包括形成虚设栅极电极结构于半导体基板的一区域之上。形成绝缘层于虚设栅极电极结构之上，并且移除虚设栅极电极结构。形成栅极电极结构于半导体基板的该区域之上，该区域是虚设栅极电极结构被移除的区域。通过使卤化物与氧气反应，形成覆盖绝缘层的氧化物层，以增加绝缘层的高度，而实质上没有形成氧化物层于栅极电极结构之上。在一实施例中，卤化物是四氯化硅。在一实施例中，氧化物层是二氧化硅。在一实施例中，覆盖绝缘层的氧化物层的高度为约5nm至约20nm。在一实施例中，栅极电极结构包括高k栅极介电层和在高k栅极介电层之上形成的金属栅极电极。在一实施例中，方法包括在形成覆盖绝缘层的氧化物层之前，执行金属栅极电极的回蚀。
本揭示内容的另一实施例是一种制造半导体装置的方法，包括形成虚设栅极电极结构于半导体基板的一区域之上。形成第一绝缘层于虚设栅极电极结构之上，并且移除虚设栅极电极结构。形成栅极电极结构于半导体基板的该区域之上，该区域是虚设栅极电极结构被移除的区域。形成第二绝缘层于栅极电极结构之上。通过使卤化物与氧气反应，形成覆盖第一绝缘层的氧化物层，以增加第一绝缘层的高度，而实质上没有形成氧化物层于第二绝缘层之上。形成通孔于第一绝缘层和第二绝缘层中，暴露出栅极电极结构。沉积导电材料于通孔中，以形成栅极电极接触件。在一实施例中，卤化物是四氯化硅。在一实施例中，氧化物层是二氧化硅。在一实施例中，栅极电极结构包括高k栅极介电层和在高k栅极介电层之上形成的金属栅极电极。在一实施例中，方法包括在形成第二绝缘层于栅极电极结构上之前，使金属栅极电极凹陷。在一实施例中，第二绝缘层是氮化物层。
上文概述若干实施例或实例的特征，使得熟悉此项技术者可更好地理解本揭示内容的态样。熟悉此项技术者应了解，可轻易使用本揭示内容作为设计或修改其他制程及结构的基础，以便实施本文所介绍的实施例或实例的相同目的和/或实现相同优势。熟悉此项技术者亦应认识到，此类等效结构并未脱离本揭示内容的精神及范畴，且可在不脱离本揭示内容的精神及范畴的情况下产生本文的各种变化、替代及更改。

Claims (1)

1.一种制造半导体装置的方法，其特征在于，包括：
形成一栅极电极结构于一半导体基板的一第一区域之上；以及
通过使一卤化物与一氧气反应，选择性地形成覆盖该栅极电极结构的一氧化物层，以增加该栅极电极结构的一高度。
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