CN1090775C - 产生内部电源电压的电路 - Google Patents
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Abstract
一个内部电源电压产生器接收外部电源电压,不管温度如何变化都能产生稳定且恒定的内部电源电压,并施加在半导体存储器器件上。为此,该产生器包括电压共用电路(80),该电路设有作为负载元件的较高阻值的第一可变电阻(R1′)和作为驱动元件的较低阻值的第二可变电阻(R2′)。当温度升高时,第一可变电阻(R1′)阻值增大,以降低通过它形成的电流。与电压共用电路(80)的输出端相连接的比较器(60)则使输出电路(70)增加该内部电源电压以响应温度的升高。
Description
本发明涉及一种在高密度半导体存储器器件中使用的、用以产生内部电源电压的电路,具体涉及这样的内部电源电压产生电路,它响应温度的升高,使其产生的输出电压也随之升高。
近来,在具有大存储容量的半导体存储器器件中要求给小于微米单位量级的MOS晶体管提供低于外部电源5V电压(该电压通常是由计算机系统提供的)的低电源电压。为此,在半导体芯片内除了存储器电路以外还必须设置一个内部电源电压产生器,以提供低的内部电源电压。例如,高于16兆比特量级的半导体DRAM(动态随机存储器)器件必需内含一个内部电源电压产生器,以成为一种高可靠性的存储器器件。
参照图1至图3,这些图公开了先有技术的内部电源电压产生器及其特性曲线。参照图1,这种传统的内部电源电压产生器100包括:参考电压产生器50、比较器60和输出电路70。图2示出了图1所示的内部电源电压产生器的特性曲线与外电源电压的对照图。图3示出了图1所示的参考电压产生器50的另一个实施例。
再参照图1,内部电源电压产生器100含有参考电压产生器50和输出电路70,输出电路70是由作为可变电阻的PMOS晶体管组成的。来自参考电压产生器50和输出电路70的输出电压随后在比较器60进行比较,比较器60是一个差分放大器,用以控制施加在PMOS晶体管10的栅极上的电压。参考电压产生器50具有第一电阻R1和第二电阻R2,它们串联连接在外部电源电压与地电平之间,在二者相连的节点3上产生参考电压Vref。比较器60具有构成一个差分放大器的第一NMOS晶体管6和第二NMOS晶体管7、作为恒流源的第三NMOS晶体管8、以及构成一个电流镜负载级的第一PMOS晶体管4和第二PMOS晶体管5。此外,PMOS晶体管10的源极与外部电源电压Vccext相连接。其漏极与输出节点11的内部电源电压Vccint相连接。在图中,将参考电压Vref施加在比较器60的第一NMOS晶体管6的栅极上。在从输出节点11到存储器电路(图中未示出)形成负载电流的情况下,在输出电路70的PMOS晶体管10上产生电压降,其结果是内部电源电压被设定为比该外部电源电压低的一个电压电平。与此同时,比较器60控制PMOS晶体管10的栅极电压,以使内部电源电压电平与参考电压Vref电平相同。
该内部电源电压产生器不管外部电源电压是否变化都必须保持恒定的内部电源电压,以使半导体存储器器件具有高度可靠性。然而,不希望的是,图1所示的这种传统的内部电源电压产生器100响应外部电压的升高,而具有如图2所示的电压差ΔV。上述这个问题是由于来自参考电压产生器50的参考电压
而引起的,因此,参考电压Vref随外部电源电压的升高而升高,于是内部电源电压也就升高了,从而降低了半导体器件的可靠性。
参照图3,参考电压产生器50是由相互串联连接的第一、第二和第三PMOS晶体管12、13、14和相互串连接的第四和第五PMOS晶体管15、16组成的,第一至第三PMOS晶体管与第四和第五PMOS晶体管并联连接。第一至第五PMOS晶体管12-16每个的栅极与漏极都是二极管式连接的,而且第四PMOS晶体管15的栅极与第三PMOS晶体管14的源极相连接。第三PMOS晶体管14的源极被耦合成使第四PMOS晶体管15的栅极电压电平被设定为Vccext/3,第四PMOS晶体管15的源极成为输出节点17,于是参考电压产生器50通过输出节点17产生参考电压Vref。然而,当温度升高时,图3中所示的参考电压产生器50中的各PMOS晶体管的阈值电压Vth下降,因此参考电压Vref也将下降。如果参考电压降低了,则内部电源电压也会降低,使半导体存储器器件以低速工作。
为此,本发明的一个目的是提供一种用以产生内部电源电压的电路,该电路不管温度如何变化都能使半导体存储器器件以稳定且恒定的速度工作,其中,该电路的输出电压随温度的升高而升高。
为实现本发明的上述的和其它的目的以及特点,本发明的内部电源电压发生器包括一个电压共用电路,这个电压共用电路具有第一和第二可变负载电阻,二者串联连接在内部电源电压输出与地电平之间,两个可变负载电阻的公共连接点变为该电路的输出节点,以响应温度的升高,使内部电源电压的输出也升高。
为了更好地理解本发明,现通过举例的方式并参照附图来说明如何实施本发明。
图1示出一种传统的内部电源电压产生器;
图2示出图1所示的内部电源电压产生器的输出特性曲线;
图3示出图1所示的参考电压产生器的另一个实施例;
图4示出本发明的一种内部电源电压产生器;
图5示出图4所示的内部电源电压产生器的输出特性曲线;
图6示出图4所示的内部电源电压产生器的一个实施例;
图7示出MOS晶体管的电流驱动功率响应温度变化的下降比。
参照图4,图4清楚示出电压共用电路80如何与比较器60及输出电路70相连接的。加有外部电源电压的参考电压产生器50产生参考电压Vref。与参考电压产生器50的输出端相连接的比较器60将耦合予参考电压Vref的第一输入电压与第二输入电压相比较。比较器60的输出与输出电路70的输入端相耦合,以产生内部电源电压。电压共用电路80与输出电路70相连接,在其输出节点上产生第二输入电压,借此响应温度的升高使输出电路70的输出电压电平升高。还应该注意到,电压共用电路80具有第一和第二可变负载电阻R1′和R2′,响应温度的升高,两电阻的阻值随之增加,其中第一可变负载电阻R1′的阻值比第二可变负载电阻R2′的阻值大。此外根据温度的升高,第一可变负载电阻R1′的电阻增长比要比第二可变负载电阻R2′的电阻增长比高些。
图4所示的内部电源电压产生器100的输出电压Vccint可以写为,其中电阻变化与温度变化之比是R1′的大于R2′的。因而从上可以看出,在温度升高时,第一可变负载电阻R1′的电阻增长比要比第二可变负载电阻R2′的电阻增长比高些,从而使内部电源电压Vccint增加。
如图5所示,可以理解,内部电源电压Vccint随着温度升高而稳定提高以使之保持恒定。据此,在传统电路中出现的问题是当温度升高时,参考电压产生器的参考电压Vref下降,导致不希望的低的内部电源电压,以及当外部电源电压升高时参考电压也升高从而产生不稳定的内部电源电压的问题,这两个问题都得到了解决。
下面参照图6详细描述图4所示的内部电源电压产生器50的一个实施例。参考电压产生器50具有:恒流源31,恒流源31的输入端与外部电源电压Vccext相耦合,,其输出端与一个输出节点38相耦合;和一个连接在该输出节点与地电位之间的电路,用以将输出节点38的电压电平降低到一预定的电平上。
该电压下降电路具有:第一电阻35,其一端与该输出节点38连接,其另一端与第一双极晶体管32的集电极和基极相连接,该晶体管的发射极耦合到地电位上;第二电阻36,其一端耦合到输出节点38上,其另一端与第二双极晶体管33的集电极相耦合,第二双极晶体管33的基极与第一双极晶体管32的集电极相耦合,其发射极经过第三电阻37接地电位;此外,输出节点38与第三双极晶体管34的集电极相连接,该晶体管的基极与第二双极晶体管33的集电极相连接,其发射极接地电位。
比较器60具有第一PMOS晶体管39,其源极接到外部电源电压;第二PMOS晶体管40,其源极也接到外部电源电压。第一PMOS晶体管39的栅极与第二PMOS晶体管40的栅极和漏极共同连接。此外,第一NMOS晶体管41的栅极与第一输入电压(亦即参考电压Vref)相耦合,其漏极与第一PMOS晶体管39的漏极相连接,其源极与第二NMOS晶体管43的源极相连接。第二NMOS晶体管43的漏极与第二PMOS晶体管40的漏极相连接,其栅极与第二输入电压相耦合。第一和第二NMOS晶体管41、43的源极都与第三NMOS晶体管42的漏极相连接。第三NMOS晶体管42的源极接地电位,其栅极与第一输入电压相耦合。第一PMOS晶体管39的漏极与第一NMOS晶体管41的漏极的连接节点44作为比较器60的输出节点。
输出电路70包括一个PMOS晶体管45,其源极与外部电源电压Vccext相连接,其栅极与比较器60的输出节点44相连接。PMOS晶体管45的漏极与输出节点49连接,内部电源电压Vccint通过该节点49而产生。
电压共用电路80包括第一PMOS晶体管46,其源极与输出电路70的输出节点49相连接,其栅极和漏极为二极管式连接;第二PMOS晶体管47,其源极与第一PMOS晶体管46的漏极连接,其栅极和漏极二极管式连接到地电位;此外,有一个输出节点48,第一和第二PMOS晶体管的漏极和源极分别与节点48连接,输出节点48与第二输入电压连接。
为了不管温度如何变化而产生恒定的参考电压Vref,参考电压产生器50包括多个双极晶极管。作为参考,本发明的参考电压产生器50的输出电压为
式中VBE为第三双极晶体管34的基极一发射极间电压;Vt为热电电压;Rb和Rc分别是第二和第三电阻36和37;以及Is1和Is2分别是第一和第二双极晶体管32和33的集电极饱和电流。该参考电压产生器50被制造得使该基极一发射极间电压VBE具有负温度系数为-2.2mV/℃,热电电压Vt具有正温度系数为0.085mV/℃,这二者相互结合,结果得到一个零温度系数。为此本发明的参考电压产生器50不像传统的参考电压产生器那样使用具有负温度系数为-3mV/℃的PMOS晶体管,本发明的参考电压产生器50不管温度如何变化都能产生一个稳定且恒定的参考电压Vref。
此外,电压共用电路80这样被连接,以根据温度的升高,使参考电压Vref增长,因此而提高内部电源电压Vccint。为此,第一PMOS晶体管46的沟道电导
要比第二PMOS晶体管47的沟道电导g2低些,因而第一PMOS晶体管46的沟道电阻要比第二PMOS晶体管47的沟道电阻大些。众所周知,电导是电阻倒数。从上面的描述可以理解,对于具有高沟道电阻的MOS晶体管而言,其电流驱动功率下降了。总的来说,沟道长度长的MOS晶体管受温度影响要比沟道短的MOS晶体管的要大些,因此沟道长度长的MOS晶体管的沟道电阻随温度的变化是比较大的。
现在讨论图6所示的内部电源电压产生器在25℃正常温度下工作的情况。来自参考电压产生器50的参考电压Vref施加在第一和第三NOMS晶体管41和42的基极上。这时如果该电压高于施加在比较器60的第二NMOS晶体管43基极上的电压,则在输出电路70的输出节点49上将充电到一给定电压。在这同时,在参考电压Vref的电平与电压共用电路80的输出电压电平相同的情况下,内部电源电压Vccint由电压共用电路80维持恒定。过一小会儿,如果温度上升直到83℃以上,则电压共用电路80的第一PMOS晶体管46中的电流将会下降,于是低于正常温度期间的电压就施加在比较器60的第二NMOS晶体管43的基极上。因此,比较器60的输出节点44上的电压被充电得低于正常温度期间的电压,因而输出电路70的输出节点49上的电压亦即内部电源电压Vccint就会升高。况且,随着温度越升越高,电压共用电路80的第一PMOS晶体管46沟道上形成的电流越来越减小,使得输出电路70的输出节点49上的内部电源电压随着温度的增长而增长。其结果是,由于温度变化而造成MOS晶体管的劣化得以防止,因此能使半导体存储器器件稳定地工作。
为了更好地理解本发明的电压共用电路80,现在对图7所示的格表作如下的讨论。表中详细列出栅极氧化层厚度为160的MOS晶体管的电流驱动功率下降比。为了方便起见,下文中将PMOS晶体管与NMOS晶体管一起描述,但将有关PMOS晶体管的情况用加括号的方式来描述。在该表中NMOS(PMOS)晶体管的电流驱动功率是在其栅极和漏极上施加的电压皆为+4.0V(-4.0V)、以及衬底源极电压为-2.0V(OV)的条件下测量的。85℃时电流驱动功率下降比是对照25℃时的电流驱动功率下降比来说明的。本领域中的技术人员可以理解,电流驱动功率的下降比高意味着MOS晶体管响应温度升高其沟道电阻比值增加得大,因此,在MOS晶体管的沟道电导下降时,其沟道电阻变大,从而使其电阻增长比也加大。
从上文所述的内容可以理解本发明的内部电源电压产生器可以补偿由于温度升高而引起的电流驱动功率的下降以及由于电流驱动功率的下降而引起的操作速度的下降。因而,使用本发明电路的半导体存储器器件不管温度如何变化都可以稳定地工作。
虽然在这里已经说明和描述了本发明的特定结构和操作过程,但是本发明并不限于已公开的这些元件和结构。本领域的技术人员不难理解,在不违背本发明的精神和范围的情况下还可以使用其它的特定的元件或其它的附属结构。
Claims (9)
1.一种内部电源电压产生电路,包括:
一个输出装置,用以利用可变电阻降低外部电源电压,从而在该输出装置的输出端子产生内部电源电压;
电压共用装置,由两个作为电阻器串联耦合的金属氧化物半导体(MOS)晶体管所组成,每个MOS晶体管具有不同的沟道长度,所述电压共用装置用以从具有较长沟道长度的所述MOS晶体管接收所述内部电源电压;然后将所述内部电压降压和输出;
参考电压产生电路,用以产生用来设定所述内部电源电压电平的参考电压;以及
比较器,其一个输入端与所述参考电压产生电路的输出端相连接,另一个输入端则与所述电压共用装置的输出端相连接,用以通过将所述电压共用装置的输出电压与所述参考电压作比较而控制所述输出端子的可变电阻;
其中,所述输出装置的输出具有随温度的上升而提高的趋向,从而补偿所述参考电压因温度上升而引起的下降,以提供基本上与温度无关的输出。
2.如权利要求1所述的电路,其特征在于,所述电压共用装置包括连接成二极管的p沟道金属氧化物半导体(MOS)晶体管。
3.如权利要求1所述的电路,其特征在于,
所述第一金属氧化物半导体晶体管,其源极与一内部电源电压端子相耦合,漏极和栅极接成二极管的形式连接所述输出端子;
所述第二金属氧化物半导体晶体管,其源极与所述输出端子相耦合,漏极和栅极接成二极管的形式接地;
所述第一金属氧化的半导体晶体管的沟道长度比所述第二金属氧化物半导体晶体管的沟道长度长。
4.如权利要求1所述的电路,其特征在于,所述输出装置包括:
一个PMOS晶体管,其源极耦合到外部电源电压,其栅极耦合到所述比较装置的输出节点;和
一个输出节点,耦合到所述PMOS晶体管的漏极。
5.如权利要求1所述的电路,其特征在于,所述电压共用装置会随温度的上升使所述内部电源电压提高,所述电压共用装置包括:
第一和第二可变电阻器装置,串联耦合在所述输出装置与地电平之间,且具有
一个输出节点,在所述第一和第二可变电阻器装置的连接点处形成。
6.如权利要求5所述的电路,其特征在于,所述第一可变电阻装置的电阻随温度的上升而提高的比例高于所述第二可变电阻器装置的。
7.如权利要求5或6所述的电路,其特征在于,所述第一和第二可变电阻装置包括:
第一MOS晶体管,其沟道的一端耦合到所述输出装置,沟道的另一端和其栅极以二极管形式连接;和
第二MOS晶体管,其沟道的一端耦合到所述输出节点,沟道的另一端和其栅极以一个二极管形式接地电平;
所述第一MOS晶体管的沟道比所述第二MOS晶体管的长。
8.如权利要求1至4任一项所述的电路,其特征在于,所述电压共用装置包括:
第一PMOS晶体管,其源极耦合到所述输出装置的输出节点,其栅极和源极以二极管形式连接;
第二MOS晶体管,其源极耦合到所述第一PMOS晶体管的漏极,其栅极和漏极以二极管形式接所述地电平;和
一个输出节点,在第一和第二PMOS晶体管的公用连接点处形成。
9.配备有如权利要求1所述的电路的半导体存储器装置。
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KR1019910009659A KR940003406B1 (ko) | 1991-06-12 | 1991-06-12 | 내부 전원전압 발생회로 |
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US4095164A (en) * | 1976-10-05 | 1978-06-13 | Rca Corporation | Voltage supply regulated in proportion to sum of positive- and negative-temperature-coefficient offset voltages |
JPS53103770A (en) * | 1977-02-22 | 1978-09-09 | Seiko Instr & Electronics Ltd | Electronic timepiece |
SU744513A1 (ru) * | 1978-03-06 | 1980-06-30 | Предприятие П/Я В-8450 | Стабилизатор напр жени посто нного тока |
JPS6029123B2 (ja) * | 1978-08-02 | 1985-07-09 | 富士通株式会社 | 電子回路 |
GB2046483A (en) * | 1979-04-06 | 1980-11-12 | Gen Electric | Voltage regulator |
US4298835A (en) * | 1979-08-27 | 1981-11-03 | Gte Products Corporation | Voltage regulator with temperature dependent output |
JPS56108258A (en) * | 1980-02-01 | 1981-08-27 | Seiko Instr & Electronics Ltd | Semiconductor device |
US4445083A (en) * | 1981-08-26 | 1984-04-24 | Honeywell Information Systems Inc. | Integrated circuit compensatory regulator apparatus |
JP2592234B2 (ja) * | 1985-08-16 | 1997-03-19 | 富士通株式会社 | 半導体装置 |
DE3682855D1 (de) * | 1985-09-17 | 1992-01-23 | Siemens Ag | Schaltungsanordnung zur erzeugung einer referenzspannung mit vorgebbarer temperaturdrift. |
JPH083766B2 (ja) * | 1986-05-31 | 1996-01-17 | 株式会社東芝 | 半導体集積回路の電源電圧降下回路 |
GB8630980D0 (en) * | 1986-12-29 | 1987-02-04 | Motorola Inc | Bandgap reference circuit |
JPH01124011A (ja) * | 1987-11-10 | 1989-05-16 | Furukawa Electric Co Ltd:The | Led駆動回路 |
KR900019026A (ko) * | 1989-05-11 | 1990-12-22 | 김광호 | 반도체 장치의 기준전압 발생회로 |
JP2674669B2 (ja) * | 1989-08-23 | 1997-11-12 | 株式会社東芝 | 半導体集積回路 |
KR920010633A (ko) * | 1990-11-30 | 1992-06-26 | 김광호 | 반도체 메모리 장치의 기준전압 발생회로 |
-
1991
- 1991-06-12 KR KR1019910009659A patent/KR940003406B1/ko not_active IP Right Cessation
- 1991-07-02 US US07/724,796 patent/US5146152A/en not_active Expired - Lifetime
- 1991-07-10 TW TW080105360A patent/TW238439B/zh not_active IP Right Cessation
- 1991-07-18 FR FR9109071A patent/FR2677793B1/fr not_active Expired - Lifetime
- 1991-07-23 DE DE4124427A patent/DE4124427C2/de not_active Expired - Lifetime
- 1991-08-12 NL NL9101377A patent/NL193703C/nl not_active IP Right Cessation
- 1991-08-26 IT ITMI912287A patent/IT1251297B/it active IP Right Grant
- 1991-08-29 RU SU5001410/A patent/RU2146388C1/ru active
- 1991-08-29 GB GB9118530A patent/GB2256731B/en not_active Expired - Fee Related
- 1991-08-30 JP JP3244106A patent/JPH0793006B2/ja not_active Expired - Fee Related
- 1991-08-30 CN CN91108584A patent/CN1090775C/zh not_active Expired - Fee Related
-
1997
- 1997-03-13 HK HK28597A patent/HK28597A/xx not_active IP Right Cessation
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US4746823A (en) * | 1986-07-02 | 1988-05-24 | Dallas Semiconductor Corporation | Voltage-insensitive and temperature-compensated delay circuit for a monolithic integrated circuit |
GB2231177A (en) * | 1989-05-01 | 1990-11-07 | Samsung Electronics Co Ltd | Supply voltage converter for semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
ITMI912287A1 (it) | 1992-12-13 |
IT1251297B (it) | 1995-05-08 |
GB2256731B (en) | 1996-01-10 |
DE4124427A1 (de) | 1992-12-17 |
TW238439B (zh) | 1995-01-11 |
FR2677793B1 (fr) | 1997-01-31 |
NL193703C (nl) | 2000-07-04 |
HK28597A (en) | 1997-03-21 |
KR930001574A (ko) | 1993-01-16 |
JPH0793006B2 (ja) | 1995-10-09 |
JPH04366492A (ja) | 1992-12-18 |
GB9118530D0 (en) | 1991-10-16 |
NL193703B (nl) | 2000-03-01 |
CN1067751A (zh) | 1993-01-06 |
GB2256731A (en) | 1992-12-16 |
DE4124427C2 (de) | 1994-06-30 |
US5146152A (en) | 1992-09-08 |
RU2146388C1 (ru) | 2000-03-10 |
ITMI912287A0 (it) | 1991-08-26 |
KR940003406B1 (ko) | 1994-04-21 |
NL9101377A (nl) | 1993-01-04 |
FR2677793A1 (fr) | 1992-12-18 |
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