CN108428663B - 静电夹盘 - Google Patents

静电夹盘 Download PDF

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CN108428663B
CN108428663B CN201810246829.8A CN201810246829A CN108428663B CN 108428663 B CN108428663 B CN 108428663B CN 201810246829 A CN201810246829 A CN 201810246829A CN 108428663 B CN108428663 B CN 108428663B
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electrostatic chuck
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capacitance
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CN108428663A (zh
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R·萨德贾迪
W·G·小博伊德
V·D·帕科
M·M·诺基诺夫
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Applied Materials Inc
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Abstract

本文所述的实现方式提供一种像素化静电夹盘，该像素化静电夹盘能够对静电夹盘与置于该静电夹盘上的基板之间的RF耦接进行侧向调谐和方位角调谐。在一个实施例中，像素化静电夹盘(ESC)可包括：电介质体，具有工件支撑表面，该工件支撑表面配置成在其上接受基板；一个或多个夹紧电极，安置在该像素化静电夹盘中；以及多个像素电极。该多个像素电极可在浮动状态与接地状态之间切换，具有对地的可变电容，或者既可在浮动状态与接地状态之间切换，又具有对地的可变电容。像素电极和夹紧电极形成电路，该电路可操作以将该基板静电地夹紧至该工件支撑表面。

Description

静电夹盘
本申请是申请日为“2015年2月9日”、申请号为“201580007797.0”、题为“像素化电容受控的ESC”的分案申请。
技术领域
本文所述的实现方式总体上关于半导体制造，并且更特定地关于静电夹盘以及使用该静电夹盘的方法。
背景技术
随着器件图案的特征尺寸变得更小，对这些特征的临界尺寸(criticaldimension；CD)的要求成为对于稳定且可重现的器件性能的更重要的准则。由于腔室的不对称性(诸如，腔室和基板温度、流导和RF场)，跨处理腔室内经处理的基板的可允许的CD变化难以达成。
在利用静电夹盘的工艺中，由于在基板下方的夹盘的非均质构造，跨基板的表面的蚀刻的均匀性具有挑战性。例如，静电夹盘中的一些区域具有气孔，而其他区域则具有从所述气孔侧向偏离的升举销孔。又一些其他区域具有夹紧电极，而其他区域则具有从夹紧电极侧向偏离的加热器电极。夹盘的非均质构造导致射频(radio frequency；RF)场的不均匀性，此不均匀性直接影响跨基板表面的蚀刻。
静电夹盘的结构可能在侧向上且在方位角上变化，这使夹盘与基板之间的RF场的均匀性复杂化且难以获得，从而导致跨夹盘表面的RF场中的局部变化性。基于等离子体的工艺可能对于至静电夹盘的小局部RF耦接变化非常敏感。由此，局部射频耦接变化导致沿基板的表面的处理结果的不均匀性。
因此，存在对改进的静电夹盘的需要。
发明内容
本文所述的实现方式提供一种像素化ESC，该像素化ESC允许对对ESC与置于该ESC上的基板之间的RF耦接进行侧向调谐和方位角调谐。在一个实施例中，像素化静电夹盘(pixelated electrostatic chuck；ESC)可包括：电介质体，具有工件支撑表面，所述工件支撑表面配置成在其上接受基板；一个或多个夹紧电极，安置于像素化ESC中；以及多个像素电极。多个像素电极可在浮动状态与接地状态之间切换，具有对地的可变电容，或者既可在浮动状态与接地状态之间切换，又具有对地的可变电容。像素电极和夹紧电极形成电路，该电路可操作以将基板静电地夹紧至工件支撑表面。
在另一实施例中，提供一种处理腔室。所述处理腔室包括腔室主体，该腔室主体中安置有像素化静电夹盘(ESC)。像素化ESC可如上所述那样配置。
在又一实施例中，提供一种用于处理基板的方法，该方法包括：向形成于像素化静电夹盘中的主夹紧电极施加功率；将侧向分布在像素化静电夹盘内的多个像素电极中的一个或多个选择性地耦接到地面以将基板紧固至像素化静电夹盘；以及在像素化静电夹盘上处理基板。
附图说明
因此，为了可详细地理解本发明的上述特征的方式，可通过参考实现方式对上文中简要概述的本发明进行更特定的描述，这些实现方式中的一些在附图中示出。然而，将注意的是，附图仅示出本发明的典型实现方式，因此附图将不被视作限制本发明的范围，因为本发明可承认其他同样有效的实现方式。
图1是处理腔室的示意性横剖面侧视图，该处理腔室中具有像素化静电夹盘的一个实施例；
图2是详细说明像素化静电夹盘和基板支撑组件的多个部分的部分示意性横剖面侧视图；
图3是示出在像素化静电夹盘中的可调电容器和电极的布局的部分平面顶视图；
图4是沿图3的剖面线A-A截取的横剖面视图，这些图示出电容器在像素化静电夹盘中的简化布线示意图；
图5是示出RF可变电容器的部分布线示意图；以及
图6是利用像素化静电夹盘处理基板的一个实施例的流程图。
为了便于理解，已在可能的情况下使用完全相同的附图标记指定诸图所共有的完全相同的元件。构想了在一个实现方式中公开的元件可有利地用于其他实现方式而无需特定的陈述。
具体实施方式
随着半导体工业正在将电子特征尺寸缩小至亚纳米水平，蚀刻速率和临界尺寸均匀性要求同样缩至接近原子尺寸的埃
Figure BDA0001606755880000031
水平。在这种情况下，基板温度必须非常均匀(例如对于小于20纳米的节点，小于约0.5℃)或能以使用非常精细的分辨率来调谐以定制跨基板的工艺均匀性。然而，对于小于10纳米的半导体技术节点而言，即使低至0.25℃或更低的温度均匀性也不足以维持工艺均匀性。影响工艺均匀性的一个因素是在静电夹盘的圆盘内的夹紧电极的电介质深度。电介质深度是圆盘的顶部与包括夹紧电极的高电压栅格之间的距离。圆盘的基板支撑表面地形与电介质深度都显著地影响基板对ESC的RF耦接。对基板的较强的射频(RF)耦接可增加蚀刻速率，反之亦然。由此，跨ESC侧向地控制工件对地的局部电容是重要的工艺控制参数，在本文中公开的本发明的所述工艺控制参数已经证实为有效的工艺控制属性，以用于定制对使用ESC执行的工艺的侧向和/或方位角蚀刻速率均匀性和/或CD控制。
本文所述的实现方式提供像素化静电夹盘(ESC)，该像素化ESC允许对像素化ESC与诸如基板之类的工件的RF耦接进行局部调谐、侧向调谐以及方位角调谐，进而允许对像素化ESC上的基板与地面的侧向RF耦接进行侧向调谐和方位角调谐。此外，针对基板与地面的耦接而对像素化ESC中的电容的局部变化的控制通过消除(或在一些情况下诱发)受RF耦接影响的工艺变化，来大幅增强在该像素化ESC上执行的工艺。由此，像素化ESC允许对在跨基板的几乎任何位置之间的埃
Figure BDA0001606755880000032
水平蚀刻速率和临界尺寸(CD)均匀性进行控制。本文还描述对在像素化ESC上处理的基板的RF耦接进行调谐的方法。尽管在下文中描述了像素化ESC处于蚀刻处理腔室中，但像素化ESC可用于其他类型的等离子体处理腔室中，所述腔室诸如物理气相沉积腔室、化学气相沉积腔室、离子注入腔室等，以及期望跨ESC的基板支撑表面的RF分布进行方位角调谐、侧向调谐和/或局部调谐中的至少一个调谐所在的其他系统。还构想到像素化电极也可用于控制其他表面(包括不用于半导体处理的那些表面)的RF偏置或耦接。
在一个或多个实施例中，像素化ESC允许在真空工艺(诸如，蚀刻、沉积、注入，等等)期间通过利用像素电极来补偿腔室不均匀性(诸如，温度、流导、电场、等离子体密度，等等)对边缘处或跨基板的其他位置处的临界尺寸(CD)变化进行校正。此外，一些实施例已证实将基板对地的电容控制到自约20pF至约数百pF范围中的任一电容的能力。
图1是示例性蚀刻处理腔室100的示意性横剖面视图，该蚀刻处理腔室100具有像素化ESC132。如上文所讨论，像素化ESC132可用于其他处理腔室中，例如等离子体处理腔室、退火腔室、物理气相沉积腔室、化学气相沉积腔室，以及离子注入腔室等等，以及期望有控制将表面或工件(诸如，基板)耦接至地面的RF分布的能力的其他系统中。对跨表面(即像素化ESC132的基板支撑表面)的许多离散区域的RF耦接进行独立控制和局部控制有益地允许RF分布的侧向调谐和/或方位角调谐以及局部RF不平度(诸如，高或低RF耦接)的减小RF，所述RF不平度可影响蚀刻处理腔室100中的局部工艺结果。
处理腔室100包括接地腔室主体102。腔室主体102包括壁104、底部106，以及盖108，上述各项围成内部体积124。基板支撑组件126安置于内部体积124中。像素化ESC132安置于基板支撑组件126上并且在处理期间在其上支撑基板134。
处理腔室100的壁104包括开口(未示出)，能以机器人方式将基板134经由该开口移送进出内部容积124。泵送口110形成在腔室主体102的壁104或底部106中的一个中并且流体地连接至泵送系统(未示出)。泵送系统用以在处理腔室100的内部体积124内维持真空环境，同时移除处理副产物。
气体面板112通过一个或多个进气端口114将工艺气体和/或其他气体提供至处理腔室100的内部容积124，该进气端口114穿过腔室主体102的盖108或壁104中的至少一个而形成。由气体面板112提供的工艺气体在内部体积124内被激励以形成等离子体122，该等离子体122用以处理安置在像素化ESC132上的基板134。可由感性耦接至处理气体的RF功率来激励此工艺气体，该RF功率来自定位在腔室主体102外部的等离子体施加器120。在图1中示出的实施例中，等离子体施加器120是经由匹配电路118耦接至RF功率源116的一对共轴线圈或容性耦接等离子体(capacitively coupled plasma；CCP)腔室。
控制器148耦接至处理腔室100以控制处理腔室100的操作和基板134的处理。控制器148可以是任何形式的通用数据处理系统中的一个，该处理系统可在工业设定中使用以用于控制多种子处理器和子控制器。总体上，控制器148包括与存储器174和输入/输出(I/O)电路176通信的中央处理单元(CPU)172及其他常见部件。由控制器148的CPU执行的软件命令使处理腔室：例如将蚀刻剂气体混合物(即处理气体)引入内部体积124，通过施加来自等离子体施加器120的RF功率由处理气体形成等离子体122，以及蚀刻存在于基板134上的材料的层。
基板支撑组件126总体上至少包括基板支撑件。在图1的实施例中，基板支撑件为ESC并且在下文中描述为像素化ESC132。基板支撑组件126可附加地包括加热器组件170。基板支撑组件126也可包括冷却基座130。或者，冷却基座可与基板支撑组件126分离。基板支撑组件126可以可移除地耦接至支撑台125。支撑台125安装至腔室主体102并且可包括台基座128。支撑台125可任选地包括设施盘180。可周期性地将基板支撑组件126从支撑台125移除以允许对基板支撑组件126的一个或多个部件进行整修。
设施盘180配置成容纳多个驱动机构，所述驱动机构配置成升高和降低多个升举销。此外，设施盘180还配置成容纳来自像素化ESC132和冷却基座130的多个流体连接。设施盘180还配置成容纳来自像素化ESC132和加热器组件170的多个电连接。许多连接可在基板支撑组件126外部或内部运行，而设施盘180为这些连接提供至相应终点的接口。
温度受控的冷却基座130耦接至热传递流体源144。热传递流体源144提供诸如液体、气体或其组合的热传递流体，该热传递流体循环通过安置于冷却基座130中的一个或多个导管160。流经相邻导管160的流体可被隔离以允许对在像素化ESC132与冷却基座130的不同区域之间的热传递进行局部控制，这辅助控制基板134的侧向温度分布。
在一个或多个实施例中，流体分配器可流体地耦接在热传递流体源144的出口与温度受控的冷却基座130之间。流体分配器操作以控制经提供至导管160的热传递流体的量。流体分配器可安置在处理腔室100的外部、基板支撑组件126内、台基座128内或其他适合的位置。
加热器组件170可包括嵌入在主体152中的一个或多个主电阻式加热器154和任选的多个二级加热器(未示出)。主电阻式加热器154可被提供以将基板支撑组件126的温度升高至用于执行腔室工艺的温度。二级加热器(当存在时)可对由主电阻式加热器154产生的像素化ESC132的温度分布提供几摄氏度的局部化调整。由此，主电阻式加热器154在全局化的大尺度上操作，而二级加热器则在局部化的小尺度上操作。主电阻式加热器154经由RF滤波器184耦接至主加热器功率源156。功率源156可向主电阻式加热器154提供500瓦特或更高的功率。控制器148可控制主加热器功率源156的操作，该主加热器功率源156的操作一般被设定为加热基板134。在一个或多个实施例中，主电阻式加热器154包括多个侧向分开的加热区，其中控制器148使主电阻式加热器154的一个区能够相对于位于其他区中一个或多个区中的主电阻式加热器154优先被加热。例如，主电阻式加热器154可同心地布置在多个分开的加热区中以实现边缘至中心温度控制。
或者，一个或多个主电阻式加热器154和/或二级加热器可形成在像素化ESC132中。在主电阻式加热器154和二级加热器都形成在像素化ESC132中的那些实施例中，基板支撑组件126可被形成为不具有加热器组件170并且像素化ESC132可直接安置于冷却基座130上。
处理腔室100中的基板134的表面的温度可受到由泵对工艺气体的抽空、狭缝阀门、等离子体122以及其他因素的影响。冷却基座130、一个或多个主电阻式加热器154以及二级加热器全都有助于控制基板134的表面温度。
像素化ESC132具有安装表面131和与安装表面131相对的工件表面133。像素化ESC132的工件表面133可包括气道(未示出)以用于将背侧热传递气体提供至限定在基板134与像素化ESC132的工件表面133之间的间隙空间。像素化ESC132还可包括升举销孔以用于容纳升举销(两者都未示出)，所述升举销用于将基板134升高至像素化ESC132的工件表面133上方以便于以机器人方式移送进和移送出处理腔室100。
像素化ESC132一般包括电介质体150，该电介质体150中嵌入有一个或多个夹紧电极136。电介质体150中还可嵌入有一个或多个像素电极140。像素电极140可与夹紧电极136共面。像素电极140可与夹紧电极136散布，例如像素电极140可以以栅格或极性阵列的方式布置(该栅格或极性阵列散布在形成于单个夹紧电极136中的孔径内)，或可在多个夹紧电极136之间散布。
使用MEMS技术可直接将像素电极140和夹紧电极136集成到圆盘228中。每一个像素电极140可通过夹紧电极136而与相邻像素电极140隔开。像素电极140和夹紧电极136可通过电镀、喷墨打印、丝网印刷、物理气相沉积、冲压、金属丝网或其他适合的方式形成。
往回参见电介质体150，电介质体150可具有配置成在直径上与基板相同或略大于基板的平盘形式。或者，电介质体150可具有其他形式，诸如，矩形、正方形或其他平面形式。电介质体150可由陶瓷材料(诸如，AlN或Al2O3)制成。当由陶瓷材料制成时，电介质体150可被称作圆盘(在图2中示为圆盘228)。或者，电介质体150可由聚合物制成，诸如聚酰亚胺、聚醚醚酮、聚芳醚酮，等等。当由聚合物制成时，电介质体150可被称作弯曲叠层。
像素化ESC132的主体150可由两层个或更多个层形成，这些层在压力下经加热以形成单块主体150。例如，主体152可由聚酰亚胺层形成，并且像素电极140和夹紧电极136在这些聚酰亚胺层之上或之间。在一些实施例中，主电阻式加热器154也可形成在聚酰亚胺层之上或之间。或者，像素化ESC132可由陶瓷材料形成。像素化ESC132可经烧结并且可包含嵌入其中的一个或多个夹紧电极136和像素电极140。
夹紧电极136可配置为双极性电极，或其他适合的布置。夹紧电极136经由RF滤波器182耦接至夹紧功率源138，该夹紧功率源138提供RF或DC电功率以将基板134静电地固定至像素化ESC132的上表面。RF滤波器182防止用于在处理腔室100内形成等离子体122的RF功率损害电气设备或在腔室外部造成电气危害。在一个实施例中，夹紧功率源138向一个或多个夹紧电极136提供高电压。
多个像素电极140可安置在像素化ESC132中并且紧邻夹紧电极136。像素电极140经由电引线146、经过像素电容器(图4和图5中示出)耦接至地面142。像素电容器可配置成具有固定的或可变的电容，其中每一个像素电容器的值被选择成独立地且局部地控制跨像素化ESC132的许多离散区域的RF耦接，以使得能够对基板与ESC132之间的功率耦接进行局部调谐、侧向调谐和/或方位角调谐，进而能够在蚀刻处理腔室100中调谐局部、侧向和/或方位角工艺结果。
在一个或多个实施例中，像素电容器可以是可变电容器，该可变电容器的电容能以机械方式或电子方式改变。像素控制器210可用于控制像素电容器的电容。像素电容器的电容的改变可用于通过一个或多个像素电极140来影响夹紧电极136通过基板134而至地面142之间的功率的耦接的亲和性(affinity)，由此将基板134静电地夹紧至像素化ESC132。
像素电容器与电阻器、电感器及忆阻器(memristor)都属于用于电子设备中的“被动部件”群组，这些被动部件用于传输夹持功率，同时允许对处理结果进行可调谐控制。像素电容器可具有固定电容值，和/或具有可变电容器，所述可变电容器具有可变(修整器(trimmer))或可调整的(可调谐的)电容值。像素电容器可以是电容可由像素控制器210控制的数字调谐电容器，诸如集成电路(IC)可变电容器。像素电容器的电容值可被配置成调谐RF信号以控制蚀刻处理腔室100中的蚀刻速率。
在一个或多个实施例中，像素电容器可被制造为固态场效应晶体管(field-effect transistor；FET)开关。像素电容器可以是微型机电系统(microelectromechanical system；MEMS)、基于钛酸锶钡(barium strontium titanate；BST)的器件、基于绝缘体上硅(silicon-on-insulator；SOI)的器件/基于蓝宝石上硅(silicon-on-sapphire；SOS)的器件、基于铁电体的器件，或其他适合的器件技术。MEMS器件是高度线性的，因此适合于天线孔径调谐、动态阻抗匹配、功率放大器负载匹配，以及可调滤波器。BST器件通过向该等器件施加高压来改变电容。调谐准确度仅受限于产生高压的D-A(直流-交流)转换器电路的准确度。在需求严格的应用中，BST器件具有在变化的温度上的优良稳定性和线性。SOI/SOS调谐器件使用以二进制加权值布置的金属-绝缘体-金属(metal-insulator-metal；MIM)覆层以获取不同电容值。SOI/SOS开关具有高度线性并且十分适合于不存在高电压的低功率应用。高电压耐受性要求串联的多个FET器件，这增加串联电阻并且降低质量因子。在一个实施例中，像素电极140是数字调谐的可变MEMS器件。
基于等离子体的工艺可能对ESC的小局部RF(RF)耦接变化非常敏感。像素化ESC132允许控制表面电容，以便对跨基板134的侧向剖面的离散位置处的蚀刻速率提供埃
Figure BDA0001606755880000091
水平CD控制。
图2是示出基板支撑组件126的多个部分的部分横剖面示意图。图2中包括像素化ESC132、加热器组件170、冷却基座130以及设施盘180的部分。
加热器组件170可以是任选的并且具有绝缘区域264。绝缘区域264可保护加热器组件170不接触电引线146，所述电引线146通过像素电容器和像素控制器210而将像素电极140连接至地面142。在主电阻式加热器154位于像素化ESC132中的实施例中，基板支撑组件126中可不存在加热器组件170。
可利用结合剂244将加热器组件170可耦接至像素化ESC132的安装表面131。结合剂244可以是粘合剂，诸如，丙烯酸基粘合剂、环氧树脂、硅基粘合剂、基于氯丁橡胶的粘合剂，或其他适合的粘合剂。在一个实施例中，结合剂244是环氧树脂。结合剂244可具有选自从0.01至200W/mK的范围中的热传导系数，且在一个示例性实施例中，具有选自从0.1至10W/mK的范围中的热传导系数。包括结合剂244的粘合剂材料可附加地包括至少一种热传导陶瓷填充物，例如氧化铝(Al2O3)、氮化铝(AlN)，及二硼化钛(TiB2)，等等。当整修像素化ESC132或加热器组件170时，可去除结合剂244。在其他实施例中，像素化ESC132利用紧固件或夹具(未示出)可移除地耦接至加热器组件170。
像素化ESC132的主体150一般可以是平面形式的圆柱形，但还能以其他几何形状来形成。主体150可以是陶瓷并且可烧结至图2中示出的圆盘228内。圆盘228具有工件表面133以在其上支撑基板134。此外，主体150可包括面对加热器组件170的安装表面131。
圆盘228的安置在电极136、140与基板134的顶表面之间的部分形成电介质226，该电介质226用于将功率容性地耦接至基板134。由电介质226的较厚深度或圆盘228的较平的地形而导致的耦接至基板134的较多功率可能降低蚀刻速率，反之亦然。由于甚至低至0.25℃的温度均匀性也不足以维持良好的侧向蚀刻均匀性，功率至基板134的耦接在形成小于10纳米的半导体技术节点时具有十分重要的作用。由此，已发现在侧向地跨像素化ESC 132的离散位置处对基板134与像素化ESC 132之间的功率耦接的独立控制允许在像素化ESC132中与像素电极140以及该像素电极140周围的夹紧电极136中的一个相关联的每一个位置处独立地控制蚀刻速率。
取决于ESC设计和所用的材料，常规ESC在基板与夹紧电极之间的离散位置处可具有不同的电容。例如，完全平坦的晶片与完全平坦的常规ESC之间的电容可以是约220pF。考虑到圆盘表面平坦度和粗糙度以及其他因素(诸如，电介质深度、夹紧电极与ESC表面的距离和圆盘的材料，以及其他因素)中的变化，ESCESC的一个区域中电容相比其他区域可能高得多。例如，一些常规ESC跨基板支撑表面可具有约数千皮(pico)法拉第的电容变化。
本文所述的像素化ESC132的实施例允许通过将跨像素化ESC132的基板支撑表面的局部电容变化控制为低于10％而允许将蚀刻速率均匀性控制在约
Figure BDA0001606755880000103
Figure BDA0001606755880000102
之内。例如，跨像素化ESC132的基板支撑表面的局部电容变化可被控制在约20pF至约数百皮法拉第之间。
在一个或多个实施例中，可通过充分地缩紧电介质226的深度容限来控制跨像素化ESC 132的基板支撑表面的局部电容变化以便获得小于10％的电容变化。例如，如果另外的5％与掺杂变化有关，则可将电介质226的深度容限缩紧至小于约5％，从而获得小于10％的电容变化。
附加于或替代于除缩紧电介质226的深度容限可通过充分改进圆盘228的表面的平坦度和地形均匀性来控制跨像素画ESC 132的基板支撑表面的局部电容变化。例如，圆盘228的平坦度的容限可小于约10μm。附加于或替代于改进圆盘228的平坦度，圆盘228的表面粗糙度变化可小于约10μm。
附加于或替代于改进电介质226和圆盘228的物理属性(即深度容限、平坦度、粗糙度，等等)中的一者或更多者，可通过为耦接至各个像素电极140的每一个像素电容器选择适当的电容来控制跨像素化ESC132的基板支撑表面的局部电容变化。通过为耦接至各个像素电极140的每一个像素电容器选择适当的电容，可补偿电介质226和圆盘228的物理属性的变化或处理环境中的变化以获得期望的处理结果，诸如将蚀刻速率均匀性维持在约
Figure BDA0001606755880000101
内。
像素控制器210可用于为耦接至各个像素电极140的每一个像素电容器选择适当的电容。例如，像素控制器210可利用由像素控制器210产生的控制信号来控制每一个像素电容器的电容。
使用可独立控制的像素电容器来平滑化或校正像素化ESC132的功率耦接分布能够将跨基板134的局部RF均匀性控制到非常小的容限。跨基板134的局部RF均匀性使得在处理基板134时允许精确处理和CD控制。此外，像素电极140的小尺寸和高密度使得能够在基板上不影响像素化ESC 132的相邻区域的功率耦接的情况下，允许通过基板134而在单个像素电极140与相邻夹紧电极136之间进行的功率耦接进行离散的局部控制，ESC耦接由此允许对功率耦接的局部控制。具有多个像素电极140的基板支撑组件126已经被证实具有如下能力：将在该基板支撑组件126上处理的基板134的电容均匀性控制到小于约10％，从而控制蚀刻均匀性的工艺偏差向下控制到约
Figure BDA0001606755880000111
图3是沿图2中的剖面线A-A截取的像素化ESC132的部分横剖面顶视平面图。ESC像素电极140和夹紧电极136在像素化ESC 132中的布局借助示例而提供并且以可选的方式排列。沿图2中穿过像素化ESC132的剖面线A-A的平面来安置像素电极140。示出的像素电极140和夹紧电极136的数量仅为了说明并且任何数量的实施例可具有大幅地更多(或更少)的像素电极140和夹紧电极136。此外，夹紧电极136可以是独立可偏置区段的形式，可作为多个共同偏置的区段，或其他配置。跨像素化ESC132的工件支撑表面的局部电容可由像素电容器来控制以提供蚀刻速率的埃
Figure BDA0001606755880000112
水平控制。
诸如图2中示出的像素控制器210的像素控制器可控制每一个像素电容器。在一个实施例中，像素电容器和用于将像素电容器耦接至选定像素电极140的开关安置于像素控制器210中。像素控制器210可将单个像素电极140耦接至电容器，该电容器具有与相邻像素电极140相同或不同的电容。在其他实施例中，像素控制器210可将一组相邻像素电极140耦接至具有相同电容的电容器(该电容可与相邻组的像素电极140的电容相同或不同)，由此限定可独立于其他区而受控的像素化ESC132中的一部分或一区。像素控制器210可耦接多个像素电极140，这些像素电极140经群组化以限定内楔、周边群组、饼状区域，或其他期望的几何形状配置，包括不毗邻的配置。由此，通过控制每一个像素电极140的局部电容，可在沿像素化ESC132的表面的独立位置处精确地控制RF耦接，这使得能够更精确地控制基板处理结果。尽管针对像素电极140示出的图案布置为小单元的栅格，但该图案可替代地具有更大和/或更小的单元，延伸至边缘，或处于其他布置。
像素电极140的数量可基板上等于夹紧电极136的数量。或者，像素电极140的数量可大幅超过或小于夹紧电极136的数量。跨基板支撑组件126而定位的像素电极140的数量可容易地超过数百个。在一个实施例中，对于每一个夹紧电极136，存在对应的像素电极140。在替代实施例中，对于一个或多个夹紧电极，存在对应的像素电极140的群组。
能以高效地生成基板与地面之间期望的RF耦接分布的图案来配置像素电极140。该图案可以是围绕中点而对称的栅格(如图所示)或其他适合的图案，所述其他适合的图案在孔中且围绕孔为升举销或其他机械连接、流体连接或电连接和端口(未示出)提供空隙。
图4是沿图3的B-B剖面线截取的像素化ESC132的横剖面视图。图4示出耦接至像素化ESC 132中的像素电极140的电容器的简化示例性布线示意图ESC。图4中的像素化ESC132示出在其中形成的像素电极140和夹紧电极136。像素电极140耦接至例如驻留在电容器组410中的一个或多个电容器440。电容器组410可安置在像素控制器210中或其他适合的位置。电容器440可具有固定的或可变的电容。在电容是可变的实施例中，可响应于来自像素控制器210的信号来选择电容器440的电容。
像素控制器210可具有控制器412以用于断开和/或闭合各电路，这些电路经由电引线141而选择性地将电容器440耦接至相应的像素电极140。当像素控制器210的电路处于闭合位置时，像素电极140经由电容器440中的至少一个耦接至地面142。在一个实施例中，控制器412可经由电引线141F将像素电极140F和电容器440F连接至地面142，而其他电容器440中的一个或多个则相对于地面142是浮动的(因为那些电路处于断开状态)。在此配置中，像素化ESC132中位于像素电极140F局部的区域可比例如像素化ESC132中位于电极140G具有的区域具有更强的RF耦接。控制器412可控制像素电极140F和电容器440F接至地面142或相对于地面处于浮动状态的持续时间或占空比。控制器412可附加地相对于像素电极140F或其他像素电极140控制其他像素电极140和电容器440接至地面142或相对于地面处于浮动状态的持续时间或占空比。以此方式，可随着时间的推移来控制跨像素化ESC132的基板支撑表面的每一个位置处的相对电容，由此允许对局部RF耦接进行控制，并且因此能够按需定制局部处理结果。
在另一实施例中，附加于或替代于控制像素电极140与地面之间的相对连接的占空比和持续时间，控制器412也可程序化地改变每一个电容器440的电容，以使得可控制跨像素化ESC132的基板支撑表面的每一个位置处的相对电容。像素电极140的数量和密度有助于将跨基板134的RF耦接的均匀性控制至非常小的容限的能力。由此，相对与另一个像素电极140在每一个像素电极140与地面之间的电容的单独控制允许对在基板134与像素化ESC132之间的特定位置处对RF耦接的局部和侧向控制，这进而允许在处理基板134时的精确的工艺和CD控制。
图5示出用于将像素电极140耦接至地面142的针对可变电容器500的部分布线示意图的一个实施例，。可变电容器500可例如通过替换图4中示出的电容器440而用于像素电极140中任一个与地面142之间的上述像素控制器210中。可变电容器500可包括可变电容器505和固定电容器570的混合，这两个电容器经由去耦电阻器506耦接至薄膜晶体管(TFT)508。可变电容器500一般用作电压受控的可变电容器(变容器(varactor))，并且可将MEMS控制元件用作可变电容器505。可变电容器500包括分支510、520、530、540、550、560，这些分支各自包括至少一个可变电容器505和至少一个固定电容器570。
当可变电容器505配置为MEMS控制元件时，可变电容器505为二进制(开/关)受控的，即可切换的。可变电容器505可向可变电容器500提供约0pF至约3.4pF之间的电容。每一个固定电容器570可向可变电容器500提供约0.5pF至约74pF之间的总电容。此外，安置在TFT 508与电容器505、570之间的去耦电阻器506可单独提供约5欧姆的电阻。
沿包括可变电容器500的一个或多个分支510、520、530、540、550、560，能以可选择的二进制加权电容来配置可变电容器500的电容。TFT 508可用于选择分支510、520、530、540、550、560中的哪一个或哪些为浮动的，以及分支510、520、530、540、550、560中的哪一个或哪些将像素电极140耦接至地面142。
每一个分支510、520、530、540、550、560的总电容是两组电容器(即可变电容器505与固定电容器570)的组合。每一个分支510、520、530、540、550、560可具有相同范围的电容或不同的电容。例如，分支560可配置最大总电容，分支550配置第二大总电容，以此类推，分支510具有最小总电容。分支560可由六个可切换的可变电容器505构成，每一个可切换的可变电容器具有设定为约3.4pF的电容(总电容为约20.4pF)，且每一个可切换的可变电容器与固定电容器576并联布置，该固定电容器576具有约74pF的电容。这对于分支560产生16pF的总电容。分支550、540、530、520、510以类似方式建构并且可分别具有8pF、4pF、2pF、1pF和0.5pF的总电容。具有小于3.4pF的总电容的分支530、520、510可使用与单个固定电容器570并联或串联的单个MEMS可变电容器505。固定电容器570可配置成将分支530、520、510的总电容降低至期望值。例如，最小分支510可具有与大约0.6pF的固定电容器570并联的单个可变电容器505。由此，当可变电容器505被激励(即接通)时，最小分支510可具有0.5pF的有效电容。因此，通过选择性地接通/关闭多个分支510、520、530、540、550、560中的可变电容器505，可获得约0.5pF至约31.5pF之间的总电容。
或者，固定电容器576可与诸如MEMS可变电容器505的RF MEMS电容器单元串联。一个或多个直列式电容器可与像素电极140串联连接。在该种配置中，与电容器576、505并联置放的配置中的电压相比，电容器576、505可经受更高的电压。由此，诸如MEMS可变电容器505的RFMEMS电容器单元的串联配置可配置成用于处理高电压。
图6是用于利用像素化静电夹盘(诸如上述像素化静电夹盘等等)处理基板的方法600的一个实施例的流程图。方法600通过向形成于像素化静电夹盘中的主电极施加功率而开始于框602。主电极可以是单个电极，或分段到多个区中。主电极在像素化ESC中的区可以是可独立控制的。
在框604处，选择性地将侧向分布在像素化ESC内的多个像素电极中的一个或多个耦接至地面，从而有效地将该基板夹紧至ESC的表面。可相对于安置在像素画静电夹盘内的其他像素电极来控制对每一个像素电极与地面的耦接的持续时间和/或占空比，从而控制对安置在ESC上的基板的RF耦接。在一些实施例中，可跨像素化ESC顺序扫描每一个像素电极至地面的耦接。在其他实施例中，任选地附加于每一个像素电极至地面的耦接的持续时间和/或占空比可相对于安置在像素化静电夹盘内的其他像素电极的接地路径可控地选择单个像素电极至地面之间的电容。通过定制像素电极与地面之间的局部电容，可实现对跨基板的处理结果的局部调谐、侧向调谐，和/或方位角调谐。
在框606处，可在像素化ESC上处理基板。例如，可在真空腔室中(例如使用等离子体工艺)来处理基板。真空工艺(任选地可在等离子体存在于处理腔室的情况下执行的真空工艺)可以是蚀刻、化学气相沉积、物理气相沉积、离子注入、等离子体处理、退火、氧化物去除、减排(abatement)或其他等离子体工艺之一。构想在用于其他应用的其他环境(例如在大气条件下)，可在像素化静电夹盘的RF受控的表面上处理工件。在一个实施例中，像素化静电夹盘上的基板经蚀刻以形成亚10纳米(sub 10nm)的半导体技术节点。
任选地，在框606处中，可响应于工艺条件的变化或工艺配方的变化而改变在像素化静电夹盘内侧向分布的多个像素电极中的一个或多个与地面之间的耦接。例如，可响应于工艺条件的变化或工艺配方的变化，利用来自像素控制器210的命令来改变像素电极中的一个或多个与地面之间的电容。在另一个示例中，可响应于工艺条件的变化或工艺配方的变化而利用来自像素控制器210的命令在浮动与接地之间切换像素电极中的一个或多个。
尽管前述内容针对本发明的实现方式，但可设计本发明的其他和进一步实现方式而不背离本发明的基本范围，且本发明的范围由所附权利要求书来确定。

Claims (10)

1.一种静电夹盘，包括：
电介质体，具有工件支撑表面，所述工件支撑表面配置成在其上接受基板；
多个夹紧电极，所述多个夹紧电极安置在所述电介质体中，所述多个夹紧电极配置为经由RF滤波器耦接至夹紧功率源；以及
多个像素电极，所述多个像素电极安置在所述电介质体中，所述像素电极可通过多个电容器接地，其中所述多个夹紧电极中的每一个夹紧电极通过所述多个像素电极中的一个与所述多个夹紧电极中的相邻夹紧电极分开。
2.如权利要求1所述的静电夹盘，其中每个电容器耦接至所述多个像素电极中的各个像素电极。
3.如权利要求2所述的静电夹盘，其中所述多个电容器进一步包括：
多个分支，所述多个分支具有去耦电阻器，所述分支包括：
多个可变电容器；和
多个固定电容器，所述多个固定电容器与各个分支上的所述可变电容器耦接；以及
耦接至所述多个分支的薄膜晶体管。
4.如权利要求2所述的静电夹盘，其中所述多个电容器中的至少一个是MEMS电容器。
5.如权利要求2所述的静电夹盘，其中所述多个电容器集成到所述电介质体中。
6.如权利要求2所述的静电夹盘，其中所述多个电容器是RF可变电容器。
7.如权利要求1所述的静电夹盘，其中所述夹紧电极以栅格的方式布置。
8.如权利要求1所述的静电夹盘，其中所述多个夹紧电极中的每一个夹紧电极都是独立可偏置的。
9.如权利要求1所述的静电夹盘，其中所述多个夹紧电极以一个或多个共同偏置区段的形式放置。
10.如权利要求3所述的静电夹盘，其中所述多个可变电容器中的每一个提供介于0 pF与3.4 pF之间的电容，且所述多个固定电容器中的每一个提供介于0.5 pF与74 pF之间的电容。
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