TWI596697B - 像素化電容控制的靜電夾盤 - Google Patents

像素化電容控制的靜電夾盤 Download PDF

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TWI596697B
TWI596697B TW104105345A TW104105345A TWI596697B TW I596697 B TWI596697 B TW I596697B TW 104105345 A TW104105345 A TW 104105345A TW 104105345 A TW104105345 A TW 104105345A TW I596697 B TWI596697 B TW I596697B
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electrostatic chuck
pixelated electrostatic
pixelated
substrate
capacitance
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TW201535588A (zh
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沙德加地雷沙
博德二世溫德爾格倫
帕克維傑Ｄ
諾吉諾夫麥斯曼米克黑洛維齊
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應用材料股份有限公司
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Description

像素化電容控制的靜電夾盤
本文所述之實施方式大體而言係關於半導體製造，且更特定而言係關於靜電夾盤及使用該靜電夾盤之方法。
隨著裝置圖案之特徵尺寸變得更小，該等特徵之臨界尺寸(critical dimension；CD)需求成為對於穩定及可重現裝置效能之更重要的準則。在處理腔室內處理之基板整體的可容許臨界尺寸變化由於腔室非對稱性而難以達成，該等腔室非對稱性如腔室及基板溫度、流動導率，及射頻場。
在利用靜電夾盤之製程中，整個基板表面之蝕刻均勻性由於在基板下方之夾盤之非均質構造而具有挑戰性。例如，靜電夾盤中之一些區域具有氣孔，而其他區域則具有側向偏離於氣孔之升舉銷孔。又一些其他區域具有夾緊電極，而其他區域則具有側向偏離於該等夾緊電極之加熱器電極。夾盤之非均質構造導致射頻(radio frequency；RF)場之不均勻性，此不均勻性直接影響整個基板表面之蝕刻。
靜電夾盤之結構可能在側向及方位角向皆為不同，夾盤與基板之間的射頻場均勻性十分複雜及難以獲得，從而 導致整個夾盤表面的射頻場中之局部變化性。基於電漿之製程可能對靜電夾盤之較小局部射頻耦合變化靈敏度極高。由此，局部射頻耦合變化導致沿基板表面之處理結果之不均勻性。
因此，需要改良之靜電夾盤。
本文所述之實施方式提供一種像素化靜電夾盤，該像素化靜電夾盤賦能對靜電夾盤與置於該靜電夾盤上之基板之間的射頻耦合進行側向及方位角向調諧。在一個實施例中，像素化靜電夾盤(pixelated electrostatic chuck；ESC)可包括：介電體，具有經配置以在其上接受基板之工件支撐表面；一或更多個夾緊電極，安置於像素化靜電夾盤中；及複數個像素電極。複數個像素電極可在浮動狀態與接地狀態之間切換，該等像素電極具有接地可變電容，或兩者兼有。像素電極及夾緊電極形成電路，該電路可操作以將基板以靜電方式夾緊至工件支撐表面。
在另一實施例中，提供處理腔室。處理腔室包括腔室主體，該腔室主體中安置有像素化靜電夾盤(pixelated electrostatic chuck；ESC)。像素化靜電夾盤可如上所述來配置。
在又一實施例中，提供用於處理基板之方法，該方法包括：向形成於像素化靜電夾盤中之主要夾緊電極施加功率；將側向分佈在像素化靜電夾盤內之複數個像素電極中之一或更多者選擇性地耦合接地，以將基板緊固至像素化靜電 夾盤；及在像素化靜電夾盤上處理基板。
100‧‧‧處理腔室
102‧‧‧腔室主體
104‧‧‧側壁
106‧‧‧底部
108‧‧‧蓋
110‧‧‧泵送口
112‧‧‧氣體分配盤
114‧‧‧入口端
116‧‧‧射頻功率來源
118‧‧‧匹配電路
120‧‧‧電漿施用器
122‧‧‧電漿
124‧‧‧內部體積
125‧‧‧支撐台座
126‧‧‧基板支撐組件
128‧‧‧台座基座
130‧‧‧冷卻基座
131‧‧‧安裝表面
132‧‧‧像素化靜電夾盤
133‧‧‧工件表面
134‧‧‧基板
136‧‧‧夾緊電極
136A‧‧‧夾緊電極
136B‧‧‧夾緊電極
138‧‧‧夾緊電源
140‧‧‧像素電極
140F‧‧‧像素電極
140G‧‧‧像素電極
141F‧‧‧電導線
141G‧‧‧電導線
142‧‧‧地面
144‧‧‧熱傳遞流體源
146‧‧‧電導線
148‧‧‧控制器
150‧‧‧介電體
152‧‧‧主體
154‧‧‧主要電阻加熱器
156‧‧‧主要加熱器電源
160‧‧‧導管
170‧‧‧加熱器組件
172‧‧‧中央處理單元
174‧‧‧記憶體
176‧‧‧輸入/輸出電路系統
180‧‧‧設施板件
182‧‧‧射頻濾波器
184‧‧‧射頻濾波器
210‧‧‧像素控制器
226‧‧‧介電質
228‧‧‧圓盤
244‧‧‧黏結劑
264‧‧‧絕緣區域
410‧‧‧電容器組
412‧‧‧控制器
440‧‧‧電容器
440F‧‧‧電容器
500‧‧‧可變電容器
505‧‧‧可變電容器
506‧‧‧去耦電阻器
508‧‧‧薄膜電晶體
510‧‧‧分支
520‧‧‧分支
530‧‧‧分支
540‧‧‧分支
550‧‧‧分支
560‧‧‧分支
570‧‧‧固定電容器
576‧‧‧固定電容器
600‧‧‧方法
602‧‧‧方塊
604‧‧‧方塊
606‧‧‧方塊
608‧‧‧方塊
為詳細理解本發明之上述特徵，可藉由參考實施方式對上文中簡短概述之本發明進行更為特定之描述，該等實施方式中之一些在附圖中圖示。然而，將注意，附圖僅圖示本發明之典型實施方式，因此附圖將不被視作限制本發明之範疇，因為本發明可承認其他同樣有效之實施方式。
第1圖是處理腔室之示意性橫剖面側視圖，該處理腔室中具有像素化靜電夾盤之一個實施例；第2圖是局部示意性橫剖面側視圖，該圖詳細圖示像素化靜電夾盤及基板支撐組件之部分；第3圖是局部平面頂視圖，該圖圖示在像素化靜電夾盤中之可調電容器及電極之佈局；第4圖是沿第3圖之剖面線A-A截取之橫剖面視圖，該圖圖示電容器在像素化靜電夾盤中之簡化佈線示意圖；第5圖是局部佈線示意圖，該圖圖示射頻可變電容器；及第6圖是利用像素化靜電夾盤處理基板之一個實施例之流程圖。
為便於理解，已在可能之情況下使用相同元件符號以指定諸圖中共有之相同元件。可以預期，在一個實施方式中揭示之元件可以有利方式用於其他實施方式而無需特定詳述。
隨著半導體工業正在將電子特徵尺寸縮小至亞奈米位準，蝕刻速率及臨界尺寸均勻性需求同樣縮至接近原子尺寸之埃(Å)位準。在此情況下，基板溫度必須極為均勻(例如小於20奈米之節點的溫度均勻性小於約0.5℃)或可進行極高解析度調諧以定製整個基板之製程均勻性。然而，對於小於10奈米之半導體技術節點而言，即使低至0.25℃或更低之溫度均勻性亦不足以維持製程均勻性。實現製程均勻性之一個因數為在靜電夾盤之圓盤內的夾緊電極之介電深度。介電深度是圓盤頂部與包括夾緊電極之高電壓柵格之間的距離。圓盤之基板支撐表面構形與介電深度皆顯著影響基板與靜電夾盤之射頻耦合。射頻(radio frequency；RF)與基板之更強耦合可增加蝕刻速率，且反之亦然。由此，控制工件之局部電容以在整個靜電夾盤側向接地是重要的製程控制參數，在本文中揭示之本發明之該參數已經證實為有效的製程控制屬性，該製程控制屬性用於為使用靜電夾盤執行之製程定製側向及/或方位角向蝕刻速率均勻性及/或臨界尺寸控制。
本文所述之實施方式提供像素化靜電夾盤(pixelated electrostatic chuck；ESC)，該像素化靜電夾盤賦能對像素化靜電夾盤與諸如基板之工件的射頻耦合進行局部、側向及方位角向調諧，從而由此容許對像素化靜電夾盤上之基板與地面之側向射頻耦合進行側向及方位角向調諧。此外，針對基板與地面之耦合而對像素化靜電夾盤中之電容的局部變化之控制藉由消除或，在一些情況下誘發受射頻耦合影響之製程變化，來大體上增強在該像素化靜電夾盤上執行 之製程。由此，像素化靜電夾盤賦能對整個基板上幾乎任何位置之間的埃(Å)位準的蝕刻速率及臨界尺寸(critical dimension；CD)均勻性進行控制。本文亦描述對在像素化靜電夾盤上處理之基板的射頻耦合進行調諧之方法。儘管像素化靜電夾盤在下文中經描述處於蝕刻處理腔室中，但像素化靜電夾盤可用於其他類型之電漿處理腔室中，該腔室諸如物理氣相沉積腔室、化學氣相沉積腔室、離子佈植腔室及其他腔室，及可用於需要對靜電夾盤之整個基板支撐表面的射頻輪廓進行方位角向調諧、側向調諧及/或局部調諧中之至少一個調諧之其他系統。可以預期，像素化電極亦可用以控制其他表面之射頻偏壓或耦合，該等表面包括不用於半導體處理之彼等表面。
在一或更多個實施例中，像素化靜電夾盤容許在真空製程期間藉由利用像素電極以補償腔室不均勻性(如溫度、流通導率、電場、電漿密度，等等)，來對基板邊緣或整個基板上其他位置處之臨界尺寸(critical dimension；CD)變化進行校正(如蝕刻、沉積、佈植，等等)。此外，一些實施例已證實控制基板接地之電容(自約20pF至約數百pF範圍中任一電容)的能力。
第1圖是示例性蝕刻處理腔室100之示意性橫剖面視圖，該蝕刻處理腔室100中具有像素化靜電夾盤132。如上文之論述，像素化靜電夾盤132可用於其他處理腔室中，例如電漿處理腔室、退火腔室、物理氣相沉積腔室、化學氣相沉積腔室，及離子佈植腔室，及其他腔室，亦可用於需要對 將表面或工件(如基板)耦合至地面之射頻輪廓進行控制之能力的其他系統中。對橫跨表面(亦即像素化靜電夾盤132之基板支撐表面)之諸多離散區域之射頻耦合的獨立及局部控制有利地賦能射頻輪廓之側向及/或方位角向調諧及減少諸如高或低射頻耦合之局部射頻不平處，該等不平處可影響蝕刻處理腔室100中之局部製程結果。
處理腔室100包括接地腔室主體102。腔室主體102包括側壁104、底部106，及蓋108，上述各者圍封內部體積124。基板支撐組件126安置於內部體積124中。像素化靜電夾盤132安置於基板支撐組件126上，且在處理期間將基板134支撐在自身上方。
處理腔室100之側壁104包括開口(未圖示)，基板134可由機器人經由該開口移送進出內部容積124。泵送口110在腔室主體102之側壁104或底部106中之一者中形成，及泵送口110以流體方式連接至泵送系統(未圖示)。泵送系統用以在處理腔室100之內部體積124內維持真空環境，同時移除處理副產物。
氣體分配盤112將處理氣體及/或其他氣體經由一或更多個入口端114提供至處理腔室100之內部容積124，該等入口端114穿過腔室主體102之蓋108或側壁104中之至少一者而形成。由氣體面板112提供之處理氣體在內部體積124內經通電以形成電漿122，該電漿122用以處理安置在像素化靜電夾盤132上之基板134。可由感應耦接至處理氣體之射頻功率對處理氣體通電，該射頻功率來自定位在腔室主體102 外部之電漿施用器120。在第1圖中繪示之實施例中，電漿施用器120是經由匹配電路118耦接至射頻功率來源116或電容耦合電漿(capacitively coupled plasma；CCP)腔室之一對共軸線圈。
控制器148耦接至處理腔室100以控制處理腔室100之操作及對基板134之處理。控制器148可為具有任一形式之通用資料處理系統之一個控制器，該處理系統可用於對於控制多種子處理器及子控制器而進行的工業設定。一般而言，控制器148包括中央處理單元(central processing unit；CPU)172及其他常見元件，該CPU與記憶體174及輸入/輸出(input/output；I/O)電路系統176通信。由控制器148之CPU執行之軟體指令使處理腔室例如將蝕刻劑氣體混合物(亦即處理氣體)引入內部體積124，藉由施加來自電漿施用器120之射頻功率由處理氣體形成電漿122，及蝕刻存在於基板134上之材料層。
基板支撐組件126一般包括至少一基板支撐件。在第1圖之實施例中，基板支撐件為靜電夾盤，及下文將該基板支撐件描述為像素化靜電夾盤132。基板支撐組件126可額外包括加熱器組件170。基板支撐組件126亦可包括冷卻基座130。或者，冷卻基座可與基板支撐組件126分離。基板支撐組件126可以可移除方式耦接至支撐台座125。支撐台座125安裝至腔室主體102，及支撐台座125可包括台座基座128。支撐台座125可視情況地包括設施板件180。可週期性地將基板支撐組件126從支撐台座125移除，以容許對基板支撐組 件126之一或更多個元件進行整修。
設施板件180經配置以容納複數個驅動機構，該等驅動機構經配置以升高及降低複數個升舉銷。此外，設施板件180亦經配置以容納來自像素化靜電夾盤132及冷卻基座130之複數個流體連接裝置。設施板件180亦經配置以容納來自像素化靜電夾盤132及加熱器組件170之複數個電連接裝置。各種連接裝置可在基板支撐組件126外部或內部運行，而設施板件180為該等連接裝置提供向各個終點之介面。
溫度控制冷卻基座130耦接至熱傳遞流體源144。熱傳遞流體源144提供諸如液體、氣體或該兩者之組合之熱傳遞流體，該熱傳遞流體在安置於冷卻基座130中之一或更多個導管160中循環。流經相鄰導管160之流體可經隔離以賦能在像素化靜電夾盤132與冷卻基座130之不同區域之間的熱傳遞之局部控制，此舉協助控制基板134之側向溫度輪廓。
在一或更多個實施例中，流體分配器可以流體方式耦接在熱傳遞流體源144的出口與溫度控制冷卻基座130之間。流體分配器操作以控制經提供至導管160之熱傳遞流體量。流體分配器可安置於處理腔室100外側、基板支撐組件126之內、台座基座128之內或其他適合之位置。
加熱器組件170可包括埋置入主體152中之一或更多個主要電阻加熱器154及視情況包括複數個輔助加熱器(未圖示)。主要電阻加熱器154可經提供以將基板支撐組件126之溫度升高至用於實施腔室製程之溫度。輔助加熱器(如存 在)可向由主要電阻加熱器154產生之像素化靜電夾盤132溫度輪廓提供耦接攝氏溫度之局部化調整。由此，主要電阻加熱器154以全域化大規模操作，而輔助加熱器則以局部化小規模操作。主要電阻加熱器154經由射頻濾波器184耦接至主要加熱器電源156。電源156可向主要電阻加熱器154提供500瓦特或更高功率。控制器148可控制主要加熱器電源156之操作，該電源一般經設定以加熱基板134。在一或更多個實施例中，主要電阻加熱器154包括複數個側向分隔的加熱區，其中控制器148賦能具有主要電阻加熱器154之一個加熱區相對於位於其他區中一或更多個區中之主要電阻加熱器154得以優先加熱。例如，主要電阻加熱器154可在複數個分隔的加熱區中經同心排列以賦能邊緣至中心之溫度控制。
或者，一或更多個主要電阻加熱器154及/或輔助加熱器可在像素化靜電夾盤132中形成。在主要電阻加熱器154及輔助加熱器皆形成於像素化靜電夾盤132中之彼等實施例中，基板支撐組件126可在沒有加熱器組件170之情況下形成，及像素化靜電夾盤132可直接安置於冷卻基座130上。
處理腔室100中之基板134之表面溫度可受由泵排出處理氣體、狹縫閥門、電漿122及其他因數之影響。冷卻基座130、一或更多個主要電阻加熱器154，及輔助加熱器全部有助於控制基板134之表面溫度。
像素化靜電夾盤132具有安裝表面131及與安裝表面131相對之工件表面133。像素化靜電夾盤132之工件表面 133可包括氣道(未圖示)，以用於向基板134與像素化靜電夾盤132之工件表面133之間界定之間隙空間提供背側熱傳遞氣體。像素化靜電夾盤132亦可包括升舉銷孔以用於容納升舉銷(兩者皆未圖示)，該等升舉銷用於將基板134升高至像素化靜電夾盤132之工件表面133上方以便於機器人移送進出處理腔室100。
像素化靜電夾盤132一般包括介電體150，該介電體150中埋置有一或更多個夾緊電極136。介電體150中亦可埋置有一或更多個像素電極140。像素電極140可與夾緊電極136共面。像素電極140可與夾緊電極136交替佈置，例如像素電極140可排列在柵格或極性陣列中，該柵格或極性陣列在形成於單個夾緊電極136中之孔口內交替佈置，或在複數個夾緊電極136之間交替佈置。
像素電極140及夾緊電極136可藉由直接使用MEMS技術整合至圓盤228中。每一像素電極140可藉由夾緊電極136而與相鄰像素電極140分隔。像素電極140及夾緊電極136可藉由電鍍、網印、物理氣相沉積、壓印、鋼絲網目或其他適合之方式形成。
往回參看介電體150，介電體150可具有經配置以與基板直徑相同或直徑略大於基板直徑之扁平圓盤形式。或者，介電體150可具有其他形式，如矩形、正方形，或其他平面形式。介電體150可由陶瓷材料製造而成，如AlN或Al2O3。當由陶瓷材料製造而成時，介電體150可被稱作圓盤(在第2圖中圖示為圓盤228)。或者，介電體150可由聚合 物製造而成，該聚合物如聚醯亞胺、聚醚醚酮、聚芳醚酮，等等。當由聚合物製造而成時，介電體150可被稱作撓曲堆疊。
像素化靜電夾盤132之主體150可由兩個或兩個以上之層形成，該等層在壓力下經加熱以形成一整塊主體150。例如，主體152可由聚醯亞胺層形成，該等層之上或之間具有像素電極140及夾緊電極136。在一些實施例中，主要電阻加熱器154亦可形成於聚醯亞胺層之上或之間。或者，像素化靜電夾盤132可由陶瓷材料形成。像素化靜電夾盤132可經燒結及可包含埋置於夾盤中之一或更多個夾緊電極136及像素電極140。
夾緊電極136可經配置為雙極性電極，或其他適合之配置。夾緊電極136經由射頻濾波器182耦接至夾緊電源138，該夾緊電源138提供射頻或直流電功率以靜電方式將基板134緊固至像素化靜電夾盤132之上表面。射頻濾波器182防止用以在處理腔室100內形成電漿122之射頻功率損害電氣設備或在腔室外部造成電氣危害。在一個實施例中，夾緊電源138向一或更多個夾緊電極136提供高壓。
複數個像素電極140可安置在像素化靜電夾盤132中及排列在緊鄰夾緊電極136之處。像素電極140經由像素電容器(第4圖及第5圖中圖示)經由電導線146耦接至地面142。像素電容器可經配置以具有固定或可變之電容，其中每一像素電容器之值經選定以單獨及局部地控制橫跨像素化靜電夾盤132之諸多離散區域之射頻耦合，以賦能對基板與 靜電夾盤132之間的功率耦合進行局部、側向及/或方位角向調諧，由此賦能局部、側向及/或方位角向製程結果在蝕刻處理腔室100中得以調諧。
在一或更多個實施例中，像素電容器可為可變電容器，該可變電容器之電容可以機械方式或電子方式變更。像素控制器210可用以控制像素電容器之電容。像素電容器之電容變更可用以影響在夾緊電極136之間經由一或更多個像素電極140的功率耦合之親合性，該功率經由基板134接至地面142，藉此以靜電方式將基板134夾緊至像素化靜電夾盤132。
像素電容器與電阻器、感應器及憶阻器皆屬於用於電子設備中之「被動元件」群組，該等元件用以傳輸夾持力，同時容許對處理結果進行可調諧控制。像素電容器可具有固定電容值，及/或具有可變電容器，該等可變電容器具有可變(修整器)或可調整(可調諧)電容值。像素電容器可為數位調諧電容器，如積體電路(integrated circuit；IC)可變電容器，該電容器之電容可由像素控制器210控制。像素電容器之電容值可經配置以調諧射頻信號以控制蝕刻處理腔室100中之蝕刻速率。
在一或更多個實施例中，像素電容器可製造為固態場效應電晶體(field-effect transistor；FET)開關。像素電容器可為微型機電系統(microelectromechanical system；MEMS)、基於鈦酸鍶鋇(barium strontium titanate；BST)之裝置、基於絕緣體上矽(silicon-on-insulator；SOI)之裝置/基於藍寶石上矽 (silicon-on-sapphire；SOS)之裝置、基於鐵電體之裝置，或其他適合之裝置技術。MEMS裝置具有高線性，因此適合於天線孔口調諧、動態阻抗匹配、功率放大器負載匹配，及可調濾波器。BST裝置藉由向該等裝置施加高壓來改變電容。調諧準確度僅因產生高壓之直流交流轉換器電路系統之準確度而受限。在需求嚴格之應用中，BST裝置具有在經過溫度變化時的優良穩定性及具有線性。SOI/SOS調諧裝置使用以二元加權值排列之金屬-絕緣體-金屬(metal-insulator-metal；MIM)蓋以獲取不同電容值。SOI/SOS開關具有高線性，且十分適合於不存在高電壓之低功率應用。高電壓耐受性需要多個串聯FET裝置，該等裝置增添串聯電阻，及降低品質因數。在一個實施例中，像素電極140是經數位調諧之可變MEMS裝置。
基於電漿之製程可能對靜電夾盤之較小局部射頻(radio frequency；RF)耦合變化靈敏度極高。像素化靜電夾盤132容許控制表面電容，以便對基板134之整個側剖面中分散位置處的蝕刻速率提供埃(Å)位準之臨界尺寸控制。
第2圖是局部橫剖面示意圖，該圖圖示基板支撐組件126之部分。第2圖中包括像素化靜電夾盤132、加熱器組件170、冷卻基座130、及設施板件180之部分。
加熱器組件170可為可選的，且具有絕緣區域264。絕緣區域264可防止加熱器組件170接觸電導線146，該等電導線146將像素電極140經由像素電容器及像素控制器210連接至地面142。在主要電阻加熱器154位於像素化靜電夾盤 132中之實施例中，基板支撐組件126中可不存在加熱器組件170。
加熱器組件170可藉由利用黏結劑244耦接至像素化靜電夾盤132之安裝表面131。黏結劑244可為黏合劑，如基於丙烯酸之黏合劑、環氧樹脂、矽基黏合劑、基於氯丁橡膠之黏合劑，或其他適合之黏合劑。在一個實施例中，黏結劑244是環氧樹脂。黏結劑244可具有選自從0.01至200W/mK之範圍中之熱傳導係數，且在一個示例性實施例中，選自從0.1至10W/mK之範圍中。包括黏結劑244之黏合劑材料可額外包括至少一個熱傳導陶瓷填充物，例如氧化鋁(Al2O3)、氮化鋁(AlN)，及二硼化鈦(TiB2)，等等。當整修像素化靜電夾盤132或加熱器組件170之時，可移除黏結劑244。在其他實施例中，像素化靜電夾盤132藉由利用緊固件或夾具(未圖示)以可移除方式耦接至加熱器組件170。
像素化靜電夾盤132之主體150在平面圖中一般可為圓柱形，但亦可以其他幾何形狀形成。主體150可為陶瓷及可燒結至第2圖中圖示之圓盤228內。圓盤228具有工件表面133以將基板134支撐在該圓盤上。此外，主體150亦可包括面對加熱器組件170之安裝表面131。
安置在電極136、140與基板134頂表面之間的圓盤228之部分形成介電質226，該介電質用於將功率電容式耦合至基板134。由於介電質226深度更深或圓盤228構形更扁平而導致的耦合至基板134之更大功率可能降低蝕刻速率，反之亦然。因為甚至低至0.25℃之溫度均勻性亦不足以維持良 好的側向蝕刻均勻性，所以功率至基板134之耦合在形成小於10奈米之半導體技術節點時具有十分重要的作用。由此，已發現，對於在基板134與像素化靜電夾盤132之間於整個像素化靜電夾盤132上側向離散的位置處之功率耦合的獨立控制，容許像素化靜電夾盤132中與像素電極140之一者及該像素電極140周圍的夾緊電極136相關連之每一位置處之蝕刻速率得以獨立控制。
視靜電夾盤之設計及所用材料而定，習用靜電夾盤在基板與夾緊電極之間的離散位置處可具有不同電容。例如，完全平坦的晶圓與完全平坦的習用靜電夾盤之間的電容可約為220pF。假定圓盤表面平面度及粗糙度及其他因數(如介電深度、夾緊電極與靜電夾盤表面之距離，及圓盤材料，及其他因數)發生變化，則靜電夾盤之一個區域與其他區域相比，該前一區域之電容可能遠高於其他區域中之電容。例如，一些習用靜電夾盤在整個基板支撐表面可具有約數千微微法拉第的電容變異。
本文所述之像素化靜電夾盤132之實施例容許藉由將像素化靜電夾盤132之整個基板支撐表面之局部電容變化控制在低於10%之程度，而將蝕刻速率均勻性控制在約5Å之內。例如，像素化靜電夾盤132之整個基板支撐表面之局部電容變化可經控制在約20pF至約數百微微法拉第之間。
在一或更多個實施例中，像素化靜電夾盤132之整個基板支撐表面之局部電容變化可藉由以下方式而經控制：充分地縮小介電質226之深度容限以便達成小於10%之電容 變化。例如，可將介電質226之深度容限縮小至小於約5%(在另一個5%與摻雜變化相關之情況下)，以達成小於10%之電容變化。
除縮小介電質226之深度容限之外，或替代性地，像素化靜電夾盤132之整個基板支撐表面之局部電容變化可藉由充分提高圓盤228表面之平面度及構形均勻性而經控制。例如，圓盤228之平面度容限可小於約10μm。除提高圓盤228之平面度以外，或替代性地，圓盤228之表面粗糙度變化可小於約10μm。
除改良介電質226及圓盤228之物理屬性(亦即深度容限、平面度、粗糙度，等等)中之一或更多者之外，或替代性地，像素化靜電夾盤132之整個基板支撐表面之局部電容變化可藉由為耦接至單個像素電極140之每一像素電容器選擇適當電容而經控制。藉由為耦接至單個像素電極140之每一像素電容器選擇適當電容，介電質226及圓盤228之物理屬性變化或處理環境中之變化可得以補償，以達到所需處理結果，如將蝕刻速率均勻性維持在約5Å內。
像素控制器210可用以為耦接至單個像素電極140之每一像素電容器選擇適當電容。例如，像素控制器210可藉由利用由像素控制器210產生之控制信號來控制每一像素電容器之電容。
使用獨立可控的像素電容器以平滑化或校正像素化靜電夾盤132之功率耦合輪廓賦能將整個基板134之局部射頻均勻性控制在極小容限。整個基板134之局部射頻均勻性 在處理基板134時賦能精確的製程及臨界尺寸控制。此外，像素電極140之小尺寸及高密度賦能對單個像素電極140與相鄰夾緊電極136之間經由基板134之功率耦合進行分散局部控制，同時大體上不影響像素化靜電夾盤132之相鄰區域之功率耦合，由此容許功率耦合之局部控制。具有多數個像素電極140之基板支撐組件126已經證實具有將在該組件上經處理之基板134之電容均勻性控制在小於約10%的能力，從而控制蝕刻均勻性之製程偏差降至約5Å。
第3圖是沿第2圖中之剖面線A-A截取之像素化靜電夾盤132的局部橫剖面頂視平面圖。在像素化靜電夾盤132中之像素電極140及夾緊電極136之佈局以實例方式而提供，及以替代性方式排列。像素電極140沿第2圖中穿過像素化靜電夾盤132之剖面線A-A所在平面而安置。圖示之像素電極140及夾緊電極136之數目僅以說明為目的，及任何數目之實施例可具有大體上更多(或更少)之像素電極140及夾緊電極136。此外，夾緊電極136可具有可獨立偏壓區段之形式，或複數個共同偏壓區段形式，或其他配置。像素化靜電夾盤132之整個工件支撐表面的局部電容可由像素電容器控制，以提供埃(Å)位準之蝕刻速率控制。
諸如第2圖中圖示之像素控制器210之像素控制器可控制每一像素電容器。在一個實施例中，像素電容器及用於將像素電容器耦接至選定像素電極140之開關安置於像素控制器210中。像素控制器210可將單個像素電極140耦接至電容器，該電容器具有與相鄰像素電極140相同或不同的 電容。在其他實施例中，像素控制器210可將相鄰像素電極140之群組耦接至具有相同電容之電容器，該電容可與相鄰像素電極140之群組之電容相同或不同，由此界定可獨立於其他區域而經控制的像素化靜電夾盤132中之一部分或一區域。像素控制器210可耦接複數個像素電極140，該等像素電極140經群組化以界定內側楔、周邊群組、餅狀區域，或其他所需幾何形狀配置，包括不連續配置。由此，藉由控制每一像素電極140之局部電容，可精確控制沿像素化靜電夾盤132的表面之單獨位置處之射頻耦合，此舉賦能對於基板處理結果的更精確控制。儘管圖示之像素電極140圖案排列為小單元之柵格，但該圖案可替代性地具有更大及/或用更小之單元，延伸至邊緣，或具有其他配置。
像素電極140之數目可大體上等於夾緊電極136之數目。或者，像素電極140之數目可大體上超過或小於夾緊電極136之數目。定位於整個基板支撐組件126中之像素電極140之數目可能易於超過數百。在一個實施例中，每一夾緊電極136有一對應像素電極140。在一替代實施例中，一或更多個夾緊電極有對應之像素電極140之群組。
像素電極140可以一圖案配置以在基板與地面之間有效地產生所需射頻耦合輪廓。圖案可為圍繞中點而對稱之柵格(如圖所示)或其他適合之圖案，該圖案在孔洞中及周圍提供空隙以用於升舉銷或其他機構、流體或電連接裝置及出入口(未圖示)。
第4圖是沿第3圖之B-B剖面線截取之像素化靜電 夾盤132之橫剖面視圖。第4圖圖示電容器之簡化示例性佈線示意圖，該等電容器耦接至像素化靜電夾盤132中之像素電極140。第4圖中之像素化靜電夾盤132圖示在該夾盤中形成之像素電極140及夾緊電極136。像素電極140耦接至一或更多個電容器440，該等電容器例如位於電容器組410中。電容器組410可置放於像素控制器210中或其他適合之位置。電容器440可具有固定或可變電容。在電容是可變電容之實施例中，可回應於來自像素控制器210之信號而選擇電容器440之電容。
像素控制器210可具有控制器412以用於斷開及/或閉合單個電路，該電路選擇性地將電容器440經由電導線141耦接至各個像素電極140。當像素控制器210之電路處於閉合位置時，像素電極140經由電容器440中之至少一者耦接至地面142。在一個實施例中，控制器412可將像素電極140F及電容器440F經由電導線141F連接至地面142，而其他電容器440中之一或更多者則相對於地面142為浮動(因為彼等電路處於斷開狀態)。在此配置中，像素化靜電夾盤132中局部至像素電極140F之區域可具有比例如像素化靜電夾盤132中局部至電極140G之區域更強之射頻耦合。控制器412可控制像素電極140F及電容器440F將接至地面142或相對於地面處於浮動狀態之持續時間或工作循環。控制器412可相對於像素電極140F或其他像素電極140額外控制其他像素電極140及電容器440將接至地面142或相對於地面處於浮動狀態之持續時間或工作循環。以此方式，像素化靜電夾盤 132之整個基板支撐表面每一位置處之相對電容可隨時間經過而經控制，由此容許控制局部射頻耦合，及因此賦能局部處理結果得以按需定製。
在另一實施例中，除了控制像素電極140與地面之間相對連接之工作循環及持續時間之外，或替代性地，控制器412亦可以可程式化方式改變每一電容器440之電容，以便可控制像素化靜電夾盤132之整個基板支撐表面上每一位置處之相對電容。像素電極140之數目及密度促進將整個基板134之射頻耦合均勻性控制至極小容限之能力。由此，對每一像素電極140與地面之間相對於另一像素電極140之電容的獨立控制賦能對基板134與像素化靜電夾盤132之間特定位置處之射頻耦合之局部及側向控制，此舉接著在處理基板134之時賦能精確的製程及臨界尺寸控制。
第5圖圖示可變電容器500之部分佈線示意圖之一個實施例，該可變電容器500用於將像素電極140耦接至地面142。可變電容器500可例如藉由更換第4圖中圖示之電容器440而用於上述像素控制器210中任何像素電極140與地面142之間。可變電容器500可包括可變電容器505及固定電容器570之混合，該等電容器經由去耦電阻器506耦接至薄膜電晶體(thin-film transistor；TFT)508。可變電容器500一般充當電壓控制可變電容器(變容器)，且可利用MEMS控制元件以作為可變電容器505。可變電容器500包括分支510、520、530、540、550、560，該等分支中每一分支包括至少一個可變電容器505及至少一個固定電容器570。
當可變電容器505經配置為MEMS控制元件時，可變電容器505為二元(開/關)控制，亦即可切換。可變電容器505可向可變電容器500提供約0pF至約3.4pF之間的電容。每一固定電容器570可向可變電容器500提供約0.5pF至約74pF之間的總電容。此外，安置在TFT 508與電容器505、570之間的去耦電阻器506可逐個提供約5歐姆電阻。
到達可變電容器500之電容可沿包括可變電容器500之一或更多個分支510、520、530、540、550、560配置有可選的二元加權電容。TFT 508可用以選擇分支510、520、530、540、550、560中之一或更多者為浮動，及分支510、520、530、540、550、560中之一或更多者將像素電極140耦接至地面142。
每一分支510、520、530、540、550、560之總電容是兩組電容器(亦即可變電容器505與固定電容器570)之組合。每一分支510、520、530、540、550、560可具有相同電容範圍或不同電容。例如，分支560可經配置具有最大總電容，分支550經配置具有第二大總電容，以此類推，分支510具有最小總電容。分支560可由六個可切換可變電容器505組成，每一可變電容器具有設定至約3.4pF之電容(對於約20.4pF之總電容)，且每一可變電容器與固定電容器576平行排列，該固定電容器576具有約74pF之電容。此配置為分支560產生16pF之總電容。分支550、540、530、520、510以類似方式建構，及可分別具有8pF、4pF、2pF、1pF，及0.5pF之總電容。具有小於3.4pF之總電容之分支530、520、 510可使用單個MEMS可變電容器505，該可變電容器505與單個固定電容器570並聯或串聯。固定電容器570可經配置以將分支530、520、510之總電容降低至所需值。例如，最小分支510可具有與固定電容器570並聯之單個可變電容器505，該固定電容器具有約0.6pF之電容。由此，當可變電容器505致動(亦即接通)時，最小分支510可具有0.5pF之有效電容。因此，藉由選擇性地在多個分支510、520、530、540、550、560中將可變電容器505接通/關閉，可獲得約0.5pF至約31.5pF之間的總電容。
或者，固定電容器576可與諸如MEMS可變電容器505之射頻MEMS電容器單元串聯。一或更多個並行電容器可串聯連接至像素電極140。在該種配置中，與在其中電容器576、505並聯置放之配置中相比，電容器576、505可經受更高的電壓。由此，諸如MEMS可變電容器505之射頻MEMS電容器單元的串聯配置可經配置以用於處理高電壓。在某些實施例中，此等電容器之至少一個具有約3.2mm x 3.2mm x 0.53mm或更小的尺寸。
第6圖是用於利用像素化靜電夾盤處理基板之方法600之一個實施例的流程圖，該像素化靜電夾盤如上述像素化靜電夾盤及其他組件。方法600始於方塊602，該步驟是向形成於像素化靜電夾盤中之主要電極應用功率。主要電極可為單個電極，或分段為多個區域。像素化靜電夾盤中之主要電極區域可為獨立可控。
在方塊604中，側向分佈在像素化靜電夾盤內之複 數個像素電極中之一或更多者選擇性地耦接至地面，從而將該基板有效地夾緊至靜電夾盤表面。每一像素電極與地面之耦合持續時間及/或工作循環可相對於安置在像素化靜電夾盤內之其他像素電極而經控制，以控制對安置在靜電夾盤上之基板的射頻耦合。在一些實施例中，可順序掃描整個像素化靜電夾盤上每一像素電極與地面之耦合。在其他實施例中，視情況地，除每一像素電極與地面耦合之持續時間及/或工作循環之外，單個像素電極與地面之間的電容亦可相對於安置在像素化靜電夾盤內之其他像素電極之接地路徑而以可控方式經選定。藉由定製像素電極與地面之間的局部電容，可實現對整個基板之處理結果之局部、側向，及/或方位角向調諧。
在方塊606中，基板可在像素化靜電夾盤上經處理。例如，基板可在真空腔室中例如使用電漿處理而經處理。可視情況在處理腔室內存在電漿之情況下執行之真空製程可為蝕刻、化學氣相沉積、物理氣相沉積、離子佈植、電漿處理、退火、氧化物去除、減排(abatement)或其他電漿製程中之一者。可以預期，工件可在其他環境(例如在大氣條件下)中之像素化靜電夾盤的射頻控制表面上進行處理以用於其他應用。在一實施例中，像素化靜電夾盤上之基板經蝕刻以形成10亞奈米之半導體技術節點。
視情況地，在方塊606中，在像素化靜電夾盤內側向分佈之複數個像素電極中的一或更多者與地面之間的耦合可回應於製程條件變更或製程配方變更而變更。例如，像素電極中的一或更多者與地面之間的電容可回應於製程條件變 更或製程配方變更利用來自像素控制器210之命令而變更。在另一實例中，像素電極中的一或更多者之耦合可回應於製程條件變更或製程配方變更利用來自像素控制器210之命令而在浮動與接地之間切換。
儘管前述內容係針對本發明之實施方式，但可在不背離本發明之基本範疇之情況下設計本發明之其他及更多實施方式，且本發明之範疇由下文之申請專利範圍決定。
132‧‧‧像素化靜電夾盤
136‧‧‧夾緊電極
136A‧‧‧夾緊電極
136B‧‧‧夾緊電極
138‧‧‧夾緊電源
140‧‧‧像素電極
140F‧‧‧像素電極
140G‧‧‧像素電極
141F‧‧‧電導線
141G‧‧‧電導線
142‧‧‧地面
210‧‧‧像素控制器
228‧‧‧圓盤
410‧‧‧電容器組
412‧‧‧控制器
440‧‧‧電容器
440F‧‧‧電容器

Claims (20)

  1. 一種像素化靜電夾盤(ESC)，包括：一介電主體，具有經配置以在其上接受一基板之一工件支撐表面；一或更多個夾緊電極，安置在該像素化靜電夾盤中；及複數個像素電極，可在一浮動狀態與一接地狀態之間切換，該等像素電極具有接地可變電容，或兩者兼有；該等像素電極及該等夾緊電極形成一電路，該電路可操作以將該基板以靜電方式夾緊至該工件支撐表面。
  2. 如請求項1所述之像素化靜電夾盤，進一步包括：一電容器組，耦接在該等像素電極與地面之間。
  3. 如請求項2所述之像素化靜電夾盤，其中該等電容器中之至少一者為一MEMS電容器。
  4. 如請求項3所述之像素化靜電夾盤，其中該等電容器為約3.2mm x 3.2mm x 0.53mm或更小。
  5. 如請求項1所述之像素化靜電夾盤，其中該等夾緊電極排列在一柵格中。
  6. 如請求項2所述之像素化靜電夾盤，其中該等電容器整合至該主體中。
  7. 如請求項2所述之像素化靜電夾盤，其中該等電容器為射頻可變電容器。
  8. 如請求項2所述之像素化靜電夾盤，其中該等電容器在整個該主體具有一電容均勻性，該電容均勻性小於約10%。
  9. 如請求項1所述之像素化靜電夾盤，其中該等電容器安置在該像素化靜電夾盤中。
  10. 如請求項1所述之像素化靜電夾盤，其中該等像素電極中之至少一者與地面之間的該電容為約20pF。
  11. 一種處理腔室，包括：腔室主體；一像素化靜電夾盤(ESC)，安置在該腔室主體中，該像素化靜電夾盤包括：一介電主體，具有經配置以在其上接受一基板之一工件支撐表面；一或更多個夾緊電極，安置於該像素化靜電夾盤中；及複數個像素電極，可在一浮動狀態與一接地狀態之間切換，該等像素電極具有接地可變電容，或兩者兼有；該 等像素電極及該等夾緊電極形成一電路，該電路可操作以將該基板以靜電方式夾緊至該工件支撐表面。
  12. 如請求項11所述之處理腔室，進一步包括：一電容器組，耦接在該等像素電極與地面之間。
  13. 如請求項12所述之處理腔室，其中該等電容器中之至少一者為一MEMS電容器。
  14. 如請求項11所述之處理腔室，其中該處理腔室為一蝕刻腔室、一沉積腔室，或一離子佈植腔室。
  15. 如請求項11所述之處理腔室，其中該等夾緊電極排列在一柵格中。
  16. 如請求項12所述之處理腔室，其中該等電容器為射頻可變電容器。
  17. 一種用於處理一基板之方法，包括以下步驟：向形成於一像素化靜電夾盤中之一主要夾緊電極施加功率；將側向分佈在該像素化靜電夾盤內之複數個像素電極中之一或更多者選擇性地耦合接地，以將一基板緊固至該像素化靜電夾盤；及 在該像素化靜電夾盤上處理該基板。
  18. 如請求項17所述之方法，進一步包括以下步驟：相對於安置在該像素化靜電夾盤內之其他該等像素電極控制每一像素電極與地面耦合之一持續時間及一工作循環中之至少一者。
  19. 如請求項17所述之方法，進一步包括以下步驟：相對於安置在該像素化靜電夾盤內之其他該等像素電極控制至少一個像素電極與地面之間的一電容。
  20. 如請求項17所述之方法，進一步包括以下步驟：回應於一製程條件變更或一製程配方變更，對在該像素化靜電夾盤內側向分佈之該複數個像素電極中之一或更多者與地面之間的一耦合進行變更。
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KR20170017003A (ko) 2017-02-14
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US9472410B2 (en) 2016-10-18
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JP6998136B2 (ja) 2022-01-18
CN106876313B (zh) 2019-09-27
CN108428663B (zh) 2022-08-30
US9536769B1 (en) 2017-01-03
CN105981156A (zh) 2016-09-28
TW201535588A (zh) 2015-09-16
JP2017509135A (ja) 2017-03-30
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US9805965B2 (en) 2017-10-31
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