CN108140568A - 局部半导体晶片削薄 - Google Patents

局部半导体晶片削薄 Download PDF

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Publication number
CN108140568A
CN108140568A CN201680059649.8A CN201680059649A CN108140568A CN 108140568 A CN108140568 A CN 108140568A CN 201680059649 A CN201680059649 A CN 201680059649A CN 108140568 A CN108140568 A CN 108140568A
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semiconductor base
back side
processing
electronic device
skiving
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CN108140568B (zh
Inventor
圣菲利波·卡尔梅洛
路易吉·梅林
伊莎贝拉·帕拉
乔瓦尼·里基耶里
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Weishi General Semiconductor LLC
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Weishi General Semiconductor LLC
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Abstract

局部削薄处理被用在半导体基底(诸如，晶片)的背面以便提高布置在晶片的前侧上或前侧内的电子装置的热性能。

Description

局部半导体晶片削薄
背景技术
半导体装置的运行对它的结温敏感。当结温超过它的功能限制时，半导体性能、寿命和可靠性可显著降低。
为了提高半导体装置的工作温度，它的部件能够被配置为提高热耗散。以这种方式，该装置能够更好地耗散热量，从而它能够在高温工作，或者从而在保持相同工作温度的同时，能够减少最终装置的面积。由于半导体装置的有源区域通常局限于它的表面和开始半导体基体材料的一部分(例如，通常比开始材料厚度薄的装置基体漂移区)，所以存在抑制热耗散的大量未使用的材料(例如，在该装置的背面)。利用需要专用技术的半导体削薄处理，能够去除这种过多的半导体基体材料。
在一个示例性制造过程中，半导体晶片的前侧经过半导体加工处理，以使得电子装置被形成在晶片的前侧。一个或多个金属化层通常被形成在晶片的前侧以用作前侧电极。在电子装置是功率场效应晶体管或绝缘栅双极晶体管(IGBT)的情况下，例如，控制电极位于晶片的前侧。在功率二极管的情况下，阳极位于晶片的前侧。
在已执行装置形成(包括装置的形成中所涉及的所有扩散处理步骤)之后，可执行晶片削薄。通常采用两种不同晶片削薄处理中的任一种晶片削薄处理。
在第一晶片削薄处理中，晶片被翻转，并且晶片的背面的中心部分在通常被称为Taiko研磨处理的处理中被削薄。然而，晶片的背面的外围边缘部分未被削薄。作为结果，留下晶片的较厚周围边缘支撑部分包围晶片的较薄中心部分。较厚周围边缘支撑部分提供机械强化，以使得较薄中心部分能够被处理，而不破坏晶片。较厚周围边缘支撑部分还在稍后的处理步骤中减少晶片翘曲。
在背面研磨之后，背面金属化层被形成在晶片的背面的较薄中心部分。金属化层在功率装置的背面形成电极。晶片的周围边缘支撑部分可随后被切掉，并且晶片的较薄中心部分可被切割以形成个体装置块。
在第二晶片削薄处理(有时被称为临时接合处理)中，半导体晶片(多个电子装置被形成在该晶片的前侧)通过粘合剂层而被接合到第二晶片(载体晶片)。
半导体晶片被从晶片背面削薄，直至达到预期目标厚度。基于半导体装置类型，背面被使用例如注入、热处理、金属化等处理以完成装置结构。在该装置被完成之后，将载体晶片与现在削薄的半导体晶片分离。
通过减小装置尺寸(装置尺寸重新调整)来实现半导体装置性能的持续提高，这需要半导体装置厚度的进一步减小以便优化装置热耗散。
发明内容
根据这里公开的主题的一个方面，局部削薄处理被用在半导体基底(诸如，晶片)的背面以便提高布置在晶片的前侧上或前侧中的电子装置的热性能。
在一个特定实现方式中，通过将掩模施加于半导体晶片的背面来完成局部晶片削薄。利用选择的几何图案对掩模进行图案化，并且半导体晶片的背面被蚀刻以将选择的几何图案从掩模转移到半导体晶片的背面。由合适的金属(例如，铜或任何导电材料)使用合适的相关沉积处理(例如，电镀、CVD、PVD等)填充图案化的背面结构以便保证良好的热导率。几何图案可被选择以优化装置的最终热性能和晶片的机械特性(在坚固性和翘曲方面)之间的折衷。
附图说明
图1A-1E示意性地显示用于局部性地削薄半导体晶片的背面的处理的一个示例。
图2A-2C示意性地显示在已执行半导体晶片局部削薄之后的处理的一个示例。
图3示意性地显示局部性地削薄的半导体装置的一个示例的最终结构，金属化堆栈被形成在晶片的削薄的背面。
图4A-4H显示可在晶片削薄处理期间施加于晶片的背面的示例性几何图案。
图5A和5B分别显示IGBT或在有源区域中以及在终止区域中具有不同半导体厚度的其它装置的俯视图和剖视图。
图6显示从理论计算获得的双极晶体管的作为未耗尽基极宽度和掺杂浓度的函数的硅击穿电压。
具体实施方式
在整个半导体表面上执行前述传统半导体晶片削薄处理。此外，这些处理采用专用装备管理晶片以避免任何机械破坏或变形，机械破坏或变形能够导致产生问题和/或装置的电性能的降低。
这里描述的主题解决这些和其它问题。例如，
在一个方面，公开的技术允许通过优化有源区域厚度(薄区域)和终止区域(厚区域)来提高外装置区域(终止区域)的装置阻断能力和雪崩粗糙度。另外，公开的技术允许通过利用高电导率材料(例如，铜)填充在局部削薄处理期间定义的沟槽结构来进一步改进最终装置的热性质和电性质。
如这里所使用，术语“晶片”和“基底”中的每一个表示独立自承结构，并且不应该被解释为形成在独立自承结构上的薄膜层。
图1A-1E显示表示局部晶片削薄处理的半导体装置的一系列剖视图。所述系列开始于图1A，图1A显示基材料，诸如半导体晶片1(例如，硅晶片)。半导体晶片1具有前侧2(也被称为上侧)和背面3(也被称为下侧)。在半导体晶片1的前侧2中或前侧2上组装一个或多个电子装置4。这种电子装置的说明性示例非限制性地包括IGBT、MOSFET、二极管或任何其它有源装置结构。
如图1B中所示，可选的保护层5(例如，带层)被沉积在半导体晶片1的前侧2以在随后的在背面3执行的处理期间保护电子装置4。同样地，如图1C中所示，另一可选的保护层6(或合适的材料层的堆栈)被沉积在半导体晶片1背面3以在随后的处理步骤期间保护表面。
接下来，在图1D中，第二层7(例如，聚合物层)被沉积在保护层6上。第二层7用作硬掩模，用于连续的处理步骤。使用合适的加工技术(诸如，例如光刻法)利用预期几何图案对第二层7进行图案化。所述几何图案定义局部削薄图案，所述局部削薄图案通过晶片1的选择的部分的去除而被转移到半导体晶片1的背面3。示例性几何图案被示出在图4A-4H中，其中较暗(或较亮)区域代表晶片1的背面3的被局部性地削薄的区域。通常，所述几何图案可包括多个凹入部分，诸如凹槽、沟槽、洞等或其任何组合。
现在参照图1E，执行蚀刻处理以将图案从第二层7转移到半导体晶片1。如图1E中所指示，在这个示例中转移的图案9在晶片1的背面3形成凹入部分13，并且对应于图4E中示出的凹槽的图案。随后的处理步骤包括从现在局部性地削薄的晶片1的背面3去除第一层6和第二层7，后面跟随有定义电子装置4的背面所需的任何其它处理步骤，包括例如沉积处理、光刻处理、热处理、机械处理和掺杂处理。
例如，图2A-2C显示在已执行局部削薄之后的半导体装置的一系列剖视图。在图1和6以及随后的附图中，相同的元件将会由相同的标号表示。如图2A中所指示，能够执行一个或多个掺杂沉积处理(从例如固体或液体源或通过离子注入)以定义绝缘栅双极晶体管(IGBT)的集电极区域(包括缓冲区域的形成)，或者定义装置的发射极区域。可随后执行热处理以在装置的背面3激活掺杂成分。然后，如图2B中所示，保护层5被去除，并且如图2C中所示，金属层12(或层的堆栈)被沉积在晶片1的背面3以定义电接触和热接触。应该注意的是，在这个示例中，金属层12填充已在局部削薄处理期间通过蚀刻而形成的晶片背面3的凹入部分13。
上述局部晶片削薄处理允许根据指定几何图案从晶片的背面选择性地去除半导体材料，因此减小最终半导体装置的热阻。此外，以这种方式构造装置背面使得能够更好地修改总体装置性能。另外，局部晶片削薄处理允许使翘曲最小化，提高半导体晶片强度，以及优化背表面的总体机械粗糙度以执行削薄处理之后的处理步骤。
接下来将提供前述处理步骤中的一些处理步骤的说明性详细示例。应该注意的是，仅为了说明而提供这些示例，并且这些示例不应该被解释为限制这里公开的主题。
在一个实施例中，保护层5(参见图1)(例如，合适的带材料)被沉积在晶片1的前侧2以在连续的处理步骤期间保护布置在晶片1中或布置在晶片1上的电子装置4。通过物理气相沉积或任何其它合适的沉积处理，薄的非导电层6(例如，氧化硅或任何合适的绝缘材料)(参见图1)被沉积在晶片1的背面3。非导电层6保护将在例如随后的金属(例如，铜)沉积处理期间不会涉及的半导体区域。
用作硬掩模的第二层7可以是光致抗蚀剂或适合光刻处理的任何聚合物材料，第二层7被沉积在非导电层6上以便在晶片背面转移预期几何图案。执行随后的光刻步骤以将几何图案8A和8B转移到晶片1的背面3。光致抗蚀剂层用作硬掩模，所述硬掩模保护不应被蚀刻的半导体区域。
执行深度反应离子蚀刻(DRIE)处理以将几何图案8A和8B转移到半导体晶片1的背面3。深度反应离子蚀刻是各向异性干法蚀刻处理，所述各向异性干法蚀刻处理使用等离子体以高纵横比对半导体材料(作为示例，硅)进行深度蚀刻。这种蚀刻的结果是晶片1中的沟槽。应该注意的是，仅作为说明而提供DRIE处理，并且更一般地讲，任何其它合适的半导体蚀刻处理可被用于这个目的。
在真空室中产生等离子体，并且在几乎垂直的方向上对离子进行加速。第一蚀刻步骤涉及包括四氟化碳(CF4)和氧混合物组成的等离子体以便去除不受光致抗蚀剂保护的氧化硅层区域(根据选择的几何图案8A和8B)。为了这个目的，可考虑任何其它合适的绝缘层蚀刻处理方法。
用于蚀刻的第二蚀刻步骤是Bosch处理，但为了这个目的，可考虑任何其它合适的半导体蚀刻处理方法。这种方法在两个阶段之间反复交替：标准硅去除阶段，使用六氟化硫(SF6)等离子体，所述六氟化硫(SF6)等离子体侵蚀直接露出的硅区域；和第二阶段，沉积八氟环丁烷(C4F8)的化学惰性钝化层，所述八氟环丁烷(C4F8)在材料侧壁上凝结并且保护它们免受侧向蚀刻。根据硅局部厚度的最后选择的值(例如，为了达到目标局部厚度而去除的材料的量)选择这些蚀刻和沉积序列的数量。C4F8钝化层沉积保护整个晶片免受进一步的化学侵蚀，并且防止进一步的蚀刻。然而，在蚀刻阶段期间，轰击基底的定向离子在沟槽的底部(但不沿着侧面)侵蚀C4F8钝化层。离子与材料基底碰撞，并且将它溅射掉，使基底暴露于化学蚀刻剂。这些蚀刻和沉积序列通常持续几秒并且重复多次，导致大量非常小的各向同性蚀刻步骤仅发生在蚀刻的凹坑的底部。
使用这两个阶段的组合，能够形成具有高度垂直的侧壁的深沟槽(例如，具有高纵横比)。基于蚀刻速度，可确立为了获得预期半导体厚度减小(例如，目标沟槽的最终深度)而需要的步骤的数量。在该处理期间，等离子体也对硬掩模7(参见图1)进行蚀刻，但光致抗蚀剂具有比硅小的蚀刻速度。在DRIE之后剩下的光致抗蚀剂对于下一个处理而言是很重要的，并且是待优化的过程参数。这种随后的沉积处理可包括例如在图2中提及的用于定义装置的集电极区域或发射极区域的所述单个或多个掺杂沉积处理，后面跟随有用于在晶片1的背面3激活掺杂成分的热处理的施加。
在一些实施例中，种子层可被沉积在晶片1的整个蚀刻的背面3。结合随后的合适的金属沉积处理(诸如，铜电镀)使用种子层，所述金属沉积处理定义晶片1的背面3的最终欧姆接触。种子层可包括通过任何合适的沉积处理(例如，电镀、CVD、PVD…)来沉积的由诸如钛、镍、金和铜的材料或任何其它合适材料序列形成的一系列不同薄膜，以便在晶片上具有良好的附着力并且防止扩散到基体材料中。种子层中的材料层的序列能够被选择以确保半导体(例如，硅)与最终金属背面接触的可靠附着和低电阻接触(欧姆接触)。此外，材料层的序列应该被选择以防止例如铜扩散到半导体材料中，所述扩散能够危害电子装置电性能。
通过光致抗蚀剂剥离处理，种子层能够被从侧壁顶部去除。最后，沟槽的底部可完全被种子层覆盖，并且侧壁顶部可被氧化硅层覆盖以避免铜生长。如图2C中所示，通过合适的相关沉积处理(例如，电镀、CVD、PVD…)，导电层12(例如，铜或任何合适的金属)被沉积在晶片1的背面3以定义存在于晶片1的前侧2的电子装置的阴极接触。
可使用电流执行电镀处理以减少任何溶解的金属阳离子以便形成一致的金属涂层。首先，半导体晶片被放置在电路的阴极中。阳极由将要被沉积在阴极半导体基底上的铜制成；两个部件都被浸没在包括允许电流动的硫酸铜的电解质溶液中。电力发电机将直流提供给阳极，通过失去两个电子来将铜原子氧化成Cu2+，Cu2+与存在于溶液中的阴离子联结。在阴极，通过获得两个电子，电解质溶液中的溶解的铜离子Cu2+在溶液和阴极之间的界面被还原成金属铜。阳极被溶解的速度等于阴极被镀覆的速度。以这种方式，电解槽中的离子连续地由阳极补充。结果是从阳极源到覆盖阴极的板的铜的有效转移。电镀处理允许凹入部分13(例如，沟槽)被铜填充，这定义晶片1的背面3的阴极12欧姆接触。在一些实施例中，替代于电镀处理，可使用任何其它合适的金属沉积处理方法，诸如例如化学气相沉积处理(CVD)或物理气相沉积(PVD)处理。
可在晶片1的背面3执行软背磨床处理或任何合适的处理以便去除超出洞和顶壁的金属以及绝缘层6。软背磨床处理使晶片表面变得平坦和规则。另外的金属堆栈可被沉积在金属层上以完成阴极结构12。图3中示出的所获得的最终结构表示背面金属化层12、在凹入部分13中位于金属化层12下方的种子层16和前金属化层14。
图5A和5B分别显示另一实施例的俯视图和剖视图，其中局部削薄处理被应用于IGBT装置(例如，具有位于晶片1的前侧2上或前侧2中的IGBT结构的任何装置)。在这种情况下，晶片仅在IGBT(诸如，例如平面或沟槽IGBT)所在的装置的有源区域18中被削薄，留下终止区域20中的晶片厚度等于它的开始值或为小于它的初始值但大于有源区域厚度的不同厚度。通过定义集电极和缓冲区域(通过使用例如合适的掺杂处理定义n和p型区域并且使用热处理激活沉积的掺杂成分)并且沉积背面接触金属12，完成装置结构。因为有源区域18和终止区域20中的不同晶片厚度，最终结构的特征在于终止区域中的长基极晶体管和有源区域中的短基极晶体管。
因此，在有源区域18中，IGBT的厚度和双极效率能够通过像在传统削薄技术中一样修改SOA、开关和导电损耗之间的权衡被优化。此外，由于长基极晶体管，局部削薄处理允许以低双极效率设计装置终止，抑制由于双极效应而导致的阻断能力的减小。因此，与晶片在有源区域和终止区域中具有相同的最终材料厚度的传统削薄处理相比，局部削薄处理允许终止雪崩粗糙度和阻断能力的显著增加。
众所周知，半导体双极结构的阻断能力强烈依赖于硅掺杂浓度、少数载流子寿命和未耗尽基极区域宽度。简单计算的结果被示出在图6中，图6表示半导体(作为示例，硅)阻断能力随着材料厚度(例如，随着未耗尽基极区域宽度)而增加。增加终止区域中的基极区域厚度允许显著提高终止阻断能力和雪崩粗糙度。因为铜提取当短路时在IGBT半导体体积中产生的热量的能力，局部削薄处理与厚铜集电极金属接触的采用的组合使用有益于IGBT的短路能力。
在另一实施例中，局部削薄方案被应用于二极管以及MOSFET(具有任何合适的MOS结构)。局部削薄方案允许相对于有源区域厚度调节终止厚度，导致终止阻断能力和雪崩粗糙度的优化，而对装置的有源区域的性能没有任何影响。
此外，这里描述的技术不限于这里示出的特定电子装置，而是更一般地讲，可被应用于各种不同电子装置以便提高它们的电性能和热性能。
虽然已按照特定于结构特征和/或方法动作的语言描述主题，但应该理解，在所附权利要求中定义的主题不必局限于上述特定特征或动作。相反地，描述的特定特征和动作被公开为实现权利要求的示例性形式。

Claims (23)

1.一种用于削薄半导体基底的方法，包括：
提供半导体基底，半导体基底具有前侧，至少一个电子装置被布置在前侧上或前侧中；
将掩模施加于半导体基底的背面；
利用选择的几何图案对掩模进行图案化；以及
对半导体基底的背面进行蚀刻以将选择的几何图案从掩模转移到半导体基底的背面。
2.如权利要求1所述的方法，其特征在于，所述转移到半导体基底的背面的选择的几何图案包括多个凹入部分。
3.如权利要求2所述的方法，其特征在于，所述多个凹入部分包括一个或多个凹槽、沟槽、洞或其组合。
4.如权利要求1所述的方法，其特征在于，还包括：在施加掩模之前将保护层施加于半导体基底的前侧。
5.如权利要求1所述的方法，其特征在于，还包括：将保护层施加于半导体基底的背面，其中施加掩模包括将掩模施加在保护层上。
6.如权利要求1所述的方法，其特征在于，所述掩模包括适合光刻处理的聚合物材料。
7.如权利要求1所述的方法，其特征在于，蚀刻半导体基底的背面和蚀刻任何最后绝缘保护层包括使用深度反应离子蚀刻处理来蚀刻半导体基底的背面。
8.如权利要求1所述的方法，其特征在于，蚀刻半导体基底的背面包括使用Bosch处理来蚀刻半导体基底的背面。
9.如权利要求1所述的方法，其特征在于，所述电子装置包括二极管。
10.如权利要求1所述的方法，其特征在于，所述电子装置包括双极晶体管。
11.如权利要求1所述的方法，其特征在于，所述电子装置包括功率场效应晶体管。
12.如权利要求1所述的方法，其特征在于，所述电子装置包括MOSFET。
13.如权利要求1所述的方法，其特征在于，还包括：在蚀刻半导体基底的背面之后，在半导体基底的背面执行一个或多个另外的处理。
14.如权利要求13所述的方法，其特征在于，从包括沉积处理、光刻处理、热处理、机械处理和掺杂处理的组中选择所述一个或多个另外的处理。
15.如权利要求13所述的方法，其特征在于，所述一个或多个另外的处理包括金属沉积处理。
16.如权利要求13所述的方法，其特征在于，所述一个或多个另外的处理包括用以填充沉积物于图案化的背面结构中的导电材料沉积处理。
17.如权利要求16所述的方法，其特征在于，还包括：在执行导电材料沉积另外处理之前，将种子层沉积在半导体基底的背面。
18.如权利要求1所述的方法，其特征在于，所述半导体基底包括有源区域和终止区域，电子装置被形成在有源区域上或形成在有源区域中，并且所述方法还包括在有源区域中而不在终止区域中蚀刻半导体基底的背面以使得背面仅在有源区域中被削薄。
19.如权利要求18所述的方法，其特征在于，从包括绝缘栅双极晶体管(IGBT)、场效应晶体管(FET)、MOSFET和二极管的组中选择所述电子装置。
20.一种根据在权利要求1中阐述的方法加工的半导体基底。
21.如权利要求20所述的半导体基底，其特征在于，还包括：电子装置，布置在基底的前侧。
22.如权利要求16所述的方法，其特征在于，所述导电材料是铜并且导电材料沉积处理是电镀处理。
23.如权利要求16所述的方法，其特征在于，所述一个或多个另外的处理包括用于填充图案化的背面结构中的凹入部分的化学气相沉积处理(CVD)或物理气相沉积(PVD)处理。
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