CN108054213A - 晶体管、存储器单元及半导体构造 - Google Patents

晶体管、存储器单元及半导体构造 Download PDF

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CN108054213A
CN108054213A CN201810003717.XA CN201810003717A CN108054213A CN 108054213 A CN108054213 A CN 108054213A CN 201810003717 A CN201810003717 A CN 201810003717A CN 108054213 A CN108054213 A CN 108054213A
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grid
ferroelectric
dielectric
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CN108054213B (zh
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尼马尔·拉马斯瓦米
柯尔克·D·普拉尔
韦恩·肯尼
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Micron Technology Inc
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Abstract

本申请涉及晶体管、存储器单元及半导体构造。一些实施例包含具有延伸到半导体基底中的栅极的半导体构造。导电掺杂源极及漏极区域在基底中与栅极邻近。栅极电介质具有：第一区段，其介于源极区域与栅极之间；第二区段，其介于漏极区域与栅极之间；及第三区段，其介于第一区段与第二区段之间。栅极电介质的至少一部分包括铁电材料。在一些实施例中，铁电材料在第一区段、第二区段及第三区段中的每一者内。在一些实施例中，铁电材料在第一区段或第三区段内。在一些实施例中，晶体管具有栅极、源极区域及漏极区域；且具有介于源极区域与漏极区域之间的沟道区域。晶体管具有栅极电介质，其包含介于源极区域与栅极之间的铁电材料。

Description

晶体管、存储器单元及半导体构造
分案申请的相关信息
本案是分案申请。该分案的母案是申请日为2013年10月15日、申请号为201380059900.7、发明名称为“晶体管、存储器单元及半导体构造”的发明专利申请案。
技术领域
本发明涉及晶体管、存储器单元及半导体构造。
背景技术
存储器为一种类型的集成电路且用于计算机系统中以存储数据。通常，以一或多个阵列的个别存储器单元制造集成存储器。所述存储器单元可为易失性、半易失性或非易失性。非易失性存储器单元可存储数据达延伸时间段且在一些情况中可在缺少电力的情况下存储数据。易失性存储器消散且因此被刷新/重新写入以维持数据存储。
所述存储器单元经配置以保持或存储至少两种不同可选状态中的信息。在二进制系统中，所述状态被视为“0”或“1”。在其它系统中，至少一些个别存储器单元可经配置以存储两种以上可选状态的信息。
动态随机存取存储器(DRAM)是一种类型的存储器且使用于许多电子系统中。DRAM单元可包括与电荷存储装置(例如，电容器)组合的晶体管。DRAM具有快速读/写的优点；但具有高易失性(通常每秒需要数百次的刷新)及在电力损耗时被擦除的缺点。
所以需要开发改进的存储器装置。
发明内容
根据本申请的一实施例，一种半导体构造包含：半导体基底，其具有通过上表面延伸进入所述基底的凹陷部，所述基底具有位于所述凹陷部的第一侧上的源极区域和位于所述凹陷部的第二侧上的漏极区域；栅极材料，其安置于所述源极区域和所述漏极区域之间的所述凹陷部内；栅极电介质材料，其安置于所述源极区域和所述栅极材料之间以及所述漏极区域和所述栅极材料之间，所述栅极电介质材料在所述凹陷部内沿着所述源极区域和所述漏极区域与所述半导体基底直接物理接触；以及铁电材料，其沿所述源极区域和所述漏极区域位于所述第一栅极电介质材料和所述栅极材料之间。
根据本申请的另一实施例，一种晶体管包含：凹入栅极；源极区域；漏极区域；以及栅极电介质，其位于所述栅极与所述源极区域和所述漏极区域之间，所述栅极电介质包含位于所述源极区域与所述凹入栅极之间的非铁电材料和铁电材料。
附图说明
图1为说明并入到实例性实施例存储器单元中的实例性实施例晶体管的半导体构造的一部分的示意横截面视图。
图2示意地说明在两种不同实例性存储器状态中的图1的存储器单元。
图3到7示意地说明并入到实例性实施例存储器单元中的实例性实施例晶体管。
图8说明包括图1的实例性实施例晶体管的另一实施例存储器单元。
具体实施方式
一些实施例包含晶体管，其包括并入到栅极电介质中的铁电材料。在一些实施例中，此类晶体管可并入到存储器单元中。参考图1到8描述实例性实施例。
参考图1，实例性实施例存储器单元40经说明为半导体构造10的部分。
构造10包含基底12。基底12可包括半导体材料及在一些实施例中可包括单晶硅，本质上由单晶硅组成，或由单晶硅组成。在一些实施例中，基底12可被视为包括半导体衬底。术语“半导体衬底”意指包括半导体材料的任何构造，包含(但不限于)块体半导体材料，例如半导体晶片(单独地或以包括其它材料的组合件形式)及半导体材料层(单独或以包括其它材料的组合件形式)。术语“衬底”是指任何支撑结构，包含(但不限于)上文所描述的半导体衬底。在一些实施例中，基底12可对应于含有与集成电路制造相关联的一或多种材料的半导体衬底。所述材料中的一些可在基底12的所展示区域的下方及/或可与基底12的所展示区域侧向邻近；且可对应于(例如)耐火金属材料、势垒材料、扩散材料、绝缘体材料等等中的一或多者。
晶体管栅极14延伸到基底12中。所述晶体管栅极包括栅极材料16。此栅极材料可为任何适当的组合物或所述组合物的组合；及在一些实施例中可包括以下各项中的一或多者，本质上由以下各项中的一或多者组成，或由以下各项中的一或多者组成：各种金属(例如，钨、钛等等)、含有金属的组合物(例如，金属氮化物、金属碳化物、金属硅化物等等)及导电掺杂半导体材料(例如，导电掺杂硅、导电掺杂锗等等)。在一些实例性实施例中，栅极材料16可包括以下各项中的一或多者，本质上由以下各项中的一或多者组成，或由以下各项中的一或多者组成：氮化钛、氮化铝钛、氮化钨、氮化铜及氮化钽。
栅极电介质18介于栅极材料16与基底12之间。所述栅极电介质经配置为沿图1的横截面的开口向上的容器24且栅极14在此容器内。在图1的实施例中，所述栅极电介质包括两种单独材料20及22，其可分别称为第一材料及第二材料。第一材料20形成容器24的外边界且直接抵靠半导体基底12。第二材料22介于第一材料20与栅极14之间。在一些实施例中，第一材料20为非铁电材料且第二材料为铁电材料。在此类实施例中，第一材料20可包括二氧化硅及氮化硅中的一或两者，本质上由二氧化硅及氮化硅中的一或两者组成，或由二氧化硅及氮化硅中的一或两者组成；且第二材料22可包括以下各项中的一或多者，本质上由以下各项中的一或多者组成，或由以下各项中的一或多者组成：钇掺杂氧化锆、钇掺杂氧化铪、镁掺杂氧化锆、镁掺杂氧化铪、硅掺杂氧化铪、硅掺杂氧化锆及钡掺杂氧化钛。因此，在一些实施例中，第一材料20可包括硅、氮及氧中的一或多者；且第二材料22可包括Hf、Zr、Si、O、Y、Ba、Mg及Ti中的一或多者。
在一些实施例中，铁电材料22可具有在从大约10埃到大约200埃的范围内的厚度，且非铁电材料20可具有在从大约10埃到大约20埃的范围内的厚度。
构造10包括延伸到基底12中的导电掺杂源极区域26及延伸到所述基底中的导电掺杂漏极区域28。以虚线示意地说明所述源极区域与所述漏极区域的下边界。所述源极区域及所述漏极区域两者均与栅极14邻近且通过栅极电介质18与所述栅极隔开。所述源极区域及所述漏极区域通过延伸到栅极14下方的沟道区域30彼此隔开。
在一些实施例中，源极区域26可称为基底的与栅极14邻近的第一区域，且漏极区域28可称为基底的与所述栅极邻近的第二区域。基底的此第一区域及此第二区域通过包括沟道区域30的所述基底的中介区域彼此隔开。
栅极电介质18可被视为包括介于源极区域26与栅极14之间的第一区段23、介于漏极区域28与栅极14之间的第二区段25及介于所述第一区段与所述第二区段之间的第三区段27。在一些实施例中，区段23可被视为对应于容器24的第一实质上垂直脚，区段25可被视为对应于所述容器的第二实质上垂直脚，且区段27可被视为包括所述容器的底部。
在所展示的实施例中，栅极电介质18的第一区段23、第二区段25及第三区段27的全部包括铁电材料22。在其它实施例中(下文参考图4到6论述其中一些)，此类区段中的一或多者可省略铁电材料22。
在一些实施例中，非铁电材料20提供介于铁电材料22与基底12之间的势垒，以避免所述铁电材料与所述基底之间的非所要成分扩散及/或避免介于所述铁电材料与所述基底之间的非所要反应或其它相互作用。在此类实施例中，可沿栅极电介质的外边缘(如图中所展示)整体提供非铁电材料20以抵靠半导体基底12(其中源极区域26及漏极区域28被视为所述基底的部分)形成容器24的边界。在一些实施例中，甚至在缺少至少一些非铁电材料的情况下，相对于铁电材料22的扩散及/或其它相互作用不会有问题，且因此区段23、25及27中的一或多者可省略一些或全部非铁电材料20。
在所展示的实施例中，非铁电材料20沿容器24的整体具有实质上一致的厚度。在其它实施例中(下文参考图7论述其中的一者)，沿容器24的一个区域的非铁电材料20相比于另一区域可具有不同厚度。
在所展示的实施例中，源极区域26电耦合到电路32，漏极区域28电耦合到电路34且栅极14电耦合到电路36。晶体管38包括栅极14以及源极/漏极区域26及28，且此晶体管通过电路32、34及36并入到集成电路中。
尽管图1的实施例使用晶体管38作为存储器单元40的部分，但在其它实施例中，晶体管38可用于其它应用。例如，晶体管38可代替常规晶体管用于逻辑或其它电路中。
栅极电介质18的铁电材料22可极化到两个稳定定向中的任一者中，此可实现存储器单元40的两个可选状态。图2中展示实例性存储器状态，其中所述存储器状态被标记为“存储器状态1”及“存储器状态2”。图2的所说明的存储器单元具有n型掺杂源极区域26及n型掺杂漏极区域28及p型掺杂沟道区域。在其它实施例中，源极区域及漏极区域可经p型掺杂且沟道区域可经n型掺杂。
相对于铁电材料22内电荷的定向，存储器状态1及存储器状态2彼此不同。图2的示意说明中，以“+”及“-”示意地说明此电荷定向。具体来说，图2的存储器状态经展示为相对于铁电材料22内的电荷极化彼此不同。图2中提供双头箭头41以示意地说明存储器单元40可在所展示的存储器状态之间可逆地转变。
在所展示的实施例中，铁电材料22内的极化变化尤其发生于介于栅极14与源极区域26之间的区域23内(所述极化变化也可发生于其它区域中，例如在一些实施例中与沟道邻近区域；或可仅发生于图2中所展示的区域23中)。存储器状态1包括沿n型掺杂源极区域26的极化铁电材料的“+”组分，且存储器状态2包括沿n型掺杂源极区域26的极化铁电材料的“-”组分。铁电材料的所述“-”组分经展示以在n型掺杂源极区域26内引发耗尽区域42(以虚线43示意地说明所述耗尽区域的边界)。在所说明的实施例中，耗尽区域42在源极区域26内部深处，且具体来说是沿着与沟道区域30介接的源极区域的一部分。相对于缺乏耗尽区域的模拟晶体管，晶体管38可具有增加的有效沟道长度，其可减少短沟道效应且借此提高存储器单元的可缩放性以实现更高的集成度。
在所展示的实施例中，非铁电材料20介于铁电材料22与源极区域26之间，且因此通过非铁电材料20的区段使耗尽区域42与铁电材料22隔开。在其它实施例中，可省略非铁电材料20且耗尽区域42可直接接触铁电材料22。
图2的存储器单元40可具有实质上非易失性且在缺少电力的情况下保持所存储的信息的优点。
可使用任何合适的操作来对存储器单元40进行编程，且在一些实例性实施例中，可使用栅极14与源极26之间的小于或等于大约10伏特的电压差来对存储器单元40进行编程；在一些实例性实施例中，使用小于或等于大约5伏特的电压差来对存储器单元40进行编程；且在一些实例性实施例中，使用从大约0.5伏特到大约5伏特的电压差来对存储器单元40进行编程。
在源极区域26及漏极区域28内所使用的掺杂剂浓度可为任何合适的掺杂剂浓度。在一些实施例中，漏极区域可比源极区域的至少一些更重掺杂；且在一些实施例中，漏极区域的整体可比源极区域的任何部分更重掺杂。在一些实施例中，相对重掺杂的漏极区域缓和铁电极化对晶体管38的漏极侧的操作的影响，同时源极区域的至少一些的相对轻掺杂使得铁电极化对所述晶体管的源极侧的影响相对于源极区域的较重掺杂将产生的影响有所增强。术语“相对重掺杂”及“相对轻掺杂”参考彼此而使用，且因此术语“相对重掺杂”意指比由术语“相对轻掺杂”所指示的掺杂较重的掺杂。
在一些实施例中，漏极区域28可经n型掺杂，且所述漏极区域的一些或全部可包括至少大约1×1020原子/cm3的掺杂剂浓度；例如(例如)在从大约1×1018原子/cm3到大约1×1020原子/cm3的范围内的掺杂剂浓度。在一些实施例中，源极区域26可经n型掺杂，且所述源极区域中的至少一些可包括小于大约1×1020原子/cm3的掺杂剂浓度；例如(例如)，在从大约1×1016原子/cm3到大约1×1019.5原子/cm3的范围内的掺杂剂浓度。
在一些实施例中，源极区域26可包括掺杂剂浓度的梯度，其中相比于源极区域的较浅位置，源极区域的较深位置处的掺杂剂浓度较低。图3展示构造10a，其说明在源极区域中掺杂剂浓度(掺杂剂浓度说明为[掺杂剂])随深度增加而降低的实例性实施例存储器单元40a。有利地，图3的构造可包括在源极区域内的一位置处较低的掺杂剂浓度，在对类似于图2的存储器状态2的存储器状态进行编程期间，耗尽区域42形成于所述位置处。
图1中所展示的实例性实施例存储器单元40包括在电介质材料18的全部区段23、25及27内的铁电材料22及非铁电材料20两者。图4展示仅在区段23内具有铁电材料22的替代实例性实施例存储器单元40b。
存储器单元40b为构造10b的部分，且包括含有栅极电介质18b的晶体管38b。栅极电介质18b包括介于铁电材料22与源极区域26之间的非铁电材料20，且包括贯穿区段25及27(即，沿漏极区域28及沟道区域30的区段)的额外非铁电材料50。非铁电材料50可包括任何合适的组合物或所述组合物的组合。在一些实施例中，非铁电材料50可包括与非铁电材料20相同的组合物，且在其它实施例中可包括与非铁电材料20不同的组合物。在一些实施例中，非铁电材料50可包括第二二氧化物及第二氮化物中的一或两者，本质上由第二二氧化物及第二氮化物中的一或两者组成或由第二二氧化物及第二氮化物中的一或两者组成。
如同上文所论述的图1的实施例，图4的存储器单元40b包括整体地沿源极区域26与栅极电介质的界面及整体地沿漏极区域28与栅极电介质的界面的非铁电材料。图5展示类似于图4的存储器单元的存储器单元，但其中栅极电介质与源极区域的界面包括铁电材料。具体来说，图5展示构造10c，其包括具有含有栅极电介质18c的晶体管38c的存储器单元40c。栅极电介质18c包括铁电材料22及非铁电材料50。铁电材料22直接接触源极区域26与栅极14两者。
在所展示的实施例中，介于源极区域与晶体管栅极之间的栅极电介质的区段的一部分(即，栅极电介质的区段23的一部分)由铁电材料组成，且所述栅极电介质的剩余部分(即，区段23的剩余部分以及区段25及27)由非铁电材料组成。在所展示的实施例中，介于栅极电介质18c与源极区域26之间的界面的仅一部分由铁电材料22组成。在其它实施例中，介于所述栅极电介质与所述源极区域之间的所述界面的整体可由铁电材料组成。
图6展示说明另一实例性实施例存储器单元40d的构造10d。所述存储器单元包括具有栅极电介质18d的晶体管38d。所述栅极电介质包括贯穿介于源极区域26与栅极14之间的区段的整体(即，区段23)及贯穿介于漏极区域28与栅极14之间的区段的整体(即，区段25)的非铁电材料50。所述栅极电介质进一步包括在沿沟道区域30的区段的至少一些(即，区段27)内的铁电材料22。此可实现铁电材料与沟道区域的选择性耦合，而不包括所述铁电材料与源极区域及/或漏极区域之间的耦合，其可实现针对特定应用调整存储器单元的操作特性。此外，如果除了作为存储器单元的一部分还在集成电路应用中使用晶体管38d取代常规晶体管，那么选择性耦合到沟道区域可实现针对特定应用调整此晶体管的操作方面。
图6的实施例展示提供于铁电材料22与基底12之间的非铁电材料20。在其它实施例中，可省略非铁电材料20使得铁电材料22直接接触基底12。
图7中展示另一实例性实施例存储器单元40e，其作为包括含有栅极电介质18e的晶体管38e的构造10e的部分。图7的存储器单元40e与图1的存储器单元40类似之处在于：存储器单元40e在栅极电介质的全部区段23、25及27内包括非铁电材料20及铁电材料22两者。然而，不同于图1的实施例，图7的实施例的非铁电材料20在区段27(即，沿由栅极电介质所界定的容器24的底部)内比区段23及25(即，沿由栅极电介质所界定的容器24的实质上垂直脚)内厚。此可缓和或消除铁电材料22与沟道30之间的耦合，其在一些实施例中可为期望的。在一些实施例中，非铁电材料20在区段23及25内可具有在从大约10埃到大约20埃的范围内的厚度，且沿容器24的底部可具有在从大约25埃到大约50埃的范围内的厚度。
在一些实施例中，上文所描述的存储器单元可包括DRAM型单元。例如，电路34可对应于电荷存储装置(例如(例如)，电容器)，电路32可包含存取/感测线(例如(例如)，位线)，且电路36可包含相对于图1到7的横截面延伸进出页面的字线。图8展示构造10f，其包括并入到DRAM型存储器单元80中的图1的晶体管38。
图8的DRAM型单元在某种意义上可被视为包含易失性存储器存储组件(电容器70，其中此组件通过使用电容器的不同电荷状态作为不同存储器状态而存储数据)及非易失性存储器存储组件(晶体管38，如上文参考图2所论述，此组件通过使用铁电材料22的不同极化定向作为不同存储器状态而存储数据)。
易失性存储器存储组件可具有类似于常规DRAM的快速读/写特性的快速读/写特性，且非易失性存储器存储组件可使单元具有超出常规DRAM的能力。例如，在一些实施例中，单元可经配置以使得非易失性存储器存储组件备份来自易失性存储器存储组件的信息，使得信息在电源中断的情况下稳定。如另一实例，在一些实施例中，单元可经配置以使得非易失性存储器存储组件用于与由易失性存储器存储组件所实行的操作分离的操作，及/或用于修改或重叠易失性存储器存储组件的操作的操作。此可使包括图8中所展示的类型的存储器单元80的DRAM阵列执行原本将包括常规集成电路的逻辑及存储器方面两者的操作，其可使包括图8中所展示的类型的存储器单元40的DRAM阵列按比例调整到比常规DRAM电路可实现的集成还更高阶的集成。
上文所论述的装置可并入到电子系统中。此类电子系统可用于(例如)存储器模块、装置驱动器、电源模块、通信调制解调器、处理器模块及专用模块，且可包含多层、多芯片模块。所述电子系统可为广泛范围的系统的任何者，例如(例如)时钟、电视、手机、个人计算机、汽车、工业控制系统、飞机等等。
图示中各种实施例的特定定向仅用于说明的目的，且在一些应用中所述实施例可相对于所展示的定向旋转。本文中所提供的描述及所附权利要求书属于具有介于各种特征之间的所描述关系的任何结构，而无论所述结构是否处于图示的特定定向或相对于此定向旋转。
附图说明的横截面视图仅展示在所述横截面的平面内的特征，且为了简化图示并不展示在所述横截面的平面的后方的材料。
上文中，当结构被称为“在另一结构上”或“抵靠”另一结构时，其可直接在另一结构上或也可存在中介结构。相比而言，当结构被称为“直接在另一结构上”或“直接抵靠”另一结构时，不存在中介结构。当结构被称为“连接”或“耦合”到另一结构时，其可直接连接或耦合到另一结构或可存在中介结构。相比而言，当结构被称为“直接连接”或“直接耦合”到另一结构时，不存在中介结构。
在一些实施例中，一种半导体构造包含半导体基底及延伸到所述基底中的栅极。与所述栅极邻近的所述基底的第一区域为导电掺杂源极区域，且与所述栅极邻近且与所述第一区域隔开的所述基底的第二区域为导电掺杂漏极区域。栅极电介质包括介于所述源极区域与所述栅极之间的第一区段、介于所述漏极区域与所述栅极之间的第二区段及介于所述第一区段与所述第二区段之间的第三区段。所述栅极电介质的至少一部分包括铁电材料。
在一些实施例中，一种晶体管包括栅极、源极区域、漏极区域及介于所述源极区域与所述漏极区域之间的沟道区域。所述晶体管还包括介于所述栅极与所述源极之间、漏极区域与沟道区域之间的栅极电介质。所述栅极电介质包括介于所述源极区域与所述栅极之间的铁电材料。
在一些实施例中，一种半导体构造包括半导体基底及延伸到所述基底中的栅极。在所述栅极的一侧上的所述基底的区域为导电掺杂源极区域，且在相对于所述一侧的所述栅极的相对侧上的所述基底的区域为导电掺杂漏极区域。所述漏极区域比所述源极区域更重掺杂。所述构造包含栅极电介质，其包括介于所述源极区域与所述栅极之间的第一区段、介于所述漏极区域与所述栅极之间的第二区段及介于所述第一区段与所述第二区段之间的第三区段。沿横截面的栅极电介质经配置为其中具有所述栅极的开口向上的容器。所述栅极电介质的所述第一区段包括所述容器的第一实质上垂直脚。所述栅极电介质的所述第二区段包括所述容器的第二实质上垂直脚。所述栅极电介质的所述第三区段包括所述容器的底部。所述栅极电介质包括直接抵靠铁电材料的非铁电材料，其中所述非铁电材料为直接抵靠半导体基底的所述容器的边界。沿所述容器的底部的非铁电材料比沿所述容器的第一实质上垂直脚及第二实质上垂直脚的非铁电材料厚。

Claims (17)

1.一种半导体构造，其包含：
半导体基底，其具有通过上表面延伸进入所述基底的凹陷部，所述基底具有位于所述凹陷部的第一侧上的源极区域和位于所述凹陷部的第二侧上的漏极区域；
栅极材料，其安置于所述源极区域和所述漏极区域之间的所述凹陷部内；
栅极电介质材料，其安置于所述源极区域和所述栅极材料之间以及所述漏极区域和所述栅极材料之间，所述栅极电介质材料在所述凹陷部内沿着所述源极区域和所述漏极区域与所述半导体基底直接物理接触；以及
铁电材料，其沿着所述源极区域和所述漏极区域位于所述第一栅极电介质材料和所述栅极材料之间。
2.根据权利要求1所述的半导体构造，其中所述铁电材料与所述栅极电介质材料直接物理接触。
3.根据权利要求1所述的半导体构造，其中所述铁电材料与所述栅极材料直接物理接触。
4.根据权利要求1所述的半导体构造，其中所述栅极电介质包含SiON。
5.根据权利要求1所述的半导体构造，其中所述铁电材料包含Hf、Zr、Si、O、Y、Ba、Mg和Ti中的一个或多个。
6.根据权利要求1所述的半导体构造，其中所述铁电材料包含氧化铪。
7.根据权利要求1所述的半导体构造，其中所述栅极材料包含金属。
8.根据权利要求1所述的半导体构造，其中所述栅极电介质材料在所述凹陷部内沿横截面排布在整个所述半导体基底上。
9.根据权利要求8所述的半导体构造，其中所述栅极电介质材料具有外表面及相对的内表面，所述外表面与所述半导体基底接触，且其中所述铁电材料沿所述横截面沿着整个所述内表面存在。
10.根据权利要求1所述的半导体构造，其中整个所述栅极材料位于所述凹陷部内且不在所述上表面上方延伸。
11.一种晶体管，其包含：
凹入栅极；
源极区域；
漏极区域；以及
栅极电介质，其位于所述栅极与所述源极区域和所述漏极区域之间，所述栅极电介质包含位于所述源极区域与所述凹入栅极之间的非铁电材料和铁电材料。
12.根据权利要求11所述的晶体管，其中所述栅极电介质进一步包含位于所述漏极区域与所述凹入栅极之间的非铁电材料和铁电材料。
13.根据权利要求11所述的晶体管，其中所述铁电材料包含Hf、Zr、Si、O、Y、Ba、Mg和Ti中的一个或多个。
14.根据权利要求11所述的晶体管，其中所述铁电材料包含氧化铪。
15.根据权利要求11所述的晶体管，其中所述非铁电材料包含SiON。
16.根据权利要求11所述的晶体管，其中所述凹入栅极安置于半导体材料中的凹陷部内，且其中所述栅极电介质沿横截面排布在整个所述凹陷部上。
17.根据权利要求11所述的晶体管，其中所述栅极电介质与所述半导体材料直接物理接触。
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