CN107665858A - 集成电路器件及其形成方法 - Google Patents

集成电路器件及其形成方法 Download PDF

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Publication number
CN107665858A
CN107665858A CN201710464190.6A CN201710464190A CN107665858A CN 107665858 A CN107665858 A CN 107665858A CN 201710464190 A CN201710464190 A CN 201710464190A CN 107665858 A CN107665858 A CN 107665858A
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stack
grid
gate
distance piece
side wall
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CN107665858B (zh
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廖志腾
邱意为
陈玺中
蔡嘉庆
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法包括在半导体区域上方形成伪栅极堆叠件，在伪栅极堆叠件的侧壁上形成栅极间隔件，去除伪栅极堆叠件以形成开口，在开口中形成置换栅极堆叠件，使置换栅极堆叠件凹进以形成凹槽，用导电材料填充凹槽，并且实施平坦化以去除栅极间隔件上方的导电材料的过量部分。导电材料的剩余部分形成了栅极接触插塞。栅极接触插塞的顶部与第一栅极间隔件的顶部处于相同的层级。本发明的实施例还涉及集成电路器件及其形成方法。

Description

集成电路器件及其形成方法
技术领域
本发明的实施例涉及集成电路器件及其形成方法。
背景技术
随着集成电路的尺寸变得越来越小，相应的形成工艺也变得越来越困难，并且可能将在传统不会出现问题的地方出现问题。例如，在鳍式场效应晶体管(FinFET)的形成中，金属栅极和邻近的源极和漏极区域可能彼此电短路。金属栅极的接触插塞也可能与邻近的源极和漏极区域的接触插塞短路。
此外，FinFET的形成可能涉及伪多晶硅栅极的形成，在随后的工艺中去除伪多晶硅栅极，并且用置换金属栅极填充由伪多晶硅栅极留下的凹槽。然而，由于伪多晶硅栅极变得非常窄，因此可能由于伪多晶硅栅极的不完全去除而留下多晶硅残留物，导致器件的性能退化。
发明内容
本发明的实施例提供了一种形成集成电路器件的方法，包括：在半导体区域上方形成伪栅极堆叠件；在所述伪栅极堆叠件的侧壁上形成第一栅极间隔件；去除所述伪栅极堆叠件以形成开口；在所述开口中形成置换栅极堆叠件；使所述置换栅极堆叠件凹进以形成凹槽；用导电材料填充所述凹槽；以及实施平坦化以去除所述第一栅极间隔件上方的所述导电材料的过量部分，其中，所述导电材料的剩余部分形成了栅极接触插塞，其中，所述栅极接触插塞的顶部与所述第一栅极间隔件的顶部处于相同的层级。
本发明的另一实施例提供了一种形成集成电路器件的方法，包括：在半导体鳍的顶面和侧壁上形成伪栅极堆叠件；形成具有接触所述伪栅极堆叠件的侧壁的侧壁的第一栅极间隔件；在所述伪栅极堆叠件的侧上形成源极/漏极区域；形成层间电介质以覆盖所述源极/漏极区域；去除所述伪栅极堆叠件以在所述第一栅极间隔件之间形成开口；用置换栅极堆叠件填充所述开口的底部；以及形成填充所述开口的顶部的栅极接触插塞，其中，所述栅极接触插塞位于所述第一栅极间隔件的顶部之间。
本发明的又一实施例提供了一种集成电路器件，包括：半导体区域；栅极堆叠件，位于所述半导体区域上方；源极/漏极区域，位于所述栅极堆叠件的侧上；第一栅极间隔件和第二栅极间隔件，位于所述栅极堆叠件的侧壁上；以及栅极接触插塞，位于所述栅极堆叠件上方，其中，所述栅极接触插塞位于所述第一栅极间隔件和所述第二栅极间隔件之间，其中，所述第一栅极间隔件和所述第二栅极间隔件的顶部与所述栅极接触插塞处于相同的层级。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图23示出了根据一些实施例的在晶体管的形成中的中间阶段的截面图。
图24示出了根据一些实施例的用于形成晶体管的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据各个示例性实施例提供了具有金属栅极和接触插塞的晶体管及其形成方法。根据一些实施例示出了形成具有金属栅极和接触插塞的晶体管的中间阶段。讨论了一些实施例的一些改变。贯穿各个视图和示例性实施例，相同的参考标号用于指定相同的元件。
图1至图23示出了根据本发明的一些实施例的在晶体管的形成中的中间阶段的截面图。图1至23所示的步骤也在图24所示的工艺流程500中示意性地示出。示出的实施例使用鳍式场效应晶体管(FinFET)的形成作为实例。本发明的概念容易应用于平面晶体管。
参照图1，提供了半导体衬底20，半导体衬底20是半导体晶圆2的一部分。根据本发明的一些实施例，半导体衬底20包括晶体硅。诸如碳、锗、镓、硼、砷、氮、铟、磷等其它常用的材料也可以包括在半导体衬底20中。衬底20也可以是包括III-V族化合物半导体的化合物衬底或硅锗。
半导体衬底20包括其中将要形成不同类型的晶体管的多个区域中的部分。根据一些实施例，多个区域包括标准器件区域100、高压(HV)器件区域200、长沟道器件区域300和输入-输出(IO)器件区域400。标准器件区域100可以用于形成核心/逻辑晶体管。HV器件区域200可以用于形成HV晶体管。长沟道器件区域300可以用于形成具有长沟道的晶体管，并且IO器件区域400可以用于形成IO晶体管。核心晶体管可以供应有低的正电源电压，例如，低于约1.0伏。HV晶体管可以供应有，并且配置为承受高于器件区域100中的器件的正电源电压的高的正电源电压。例如，HV器件区域200的电源电压可以在约1.5V和约3.3V之间。
根据本发明的一些实施例，衬底20包括半导体鳍20A，该半导体鳍20A是位于邻近的隔离区域上方的部分。图5B中示出了示例性鳍20A，图5B示出了高于邻近的隔离区域38(可以是浅沟槽隔离(STI)区域)的半导体鳍20A。应该注意，虽然为了简化，位于区域100、200、300和400中的鳍示出为彼此连接，但是实际上，位于不同器件区域中的鳍彼此分隔开。
回参照图1，在衬底20上方形成伪栅极电介质22。伪栅极电介质22可以由氧化硅形成。根据一些实施例，伪栅电极24形成在伪栅极电介质22上方，并且可以由多晶硅形成。
根据一些示例性实施例，掩模堆叠件112、212、312和412分别形成在器件区域100、200、300、和400中，并且分别具有宽度W112、W212、W312和W412，其关系为W412>W312>W212>W112。掩模堆叠件112可以包括层114、116和118，其可以由氧化硅、氮化硅、碳氮化硅、硅-碳氮氧化物等形成。掩模堆叠件212、312和412具有与掩模堆叠件112相同的层。
底部抗反射涂层(BARC)26形成在伪栅电极24上方，并且填充了掩模堆叠件112、212、312和412之间的间隔。根据一些实施例，BARC由诸如SiON的介电材料形成。BARC 26可以填充至覆盖掩模堆叠件112、212、312和412，或可以具有与层118的顶面齐平或高于层118的顶面的顶面。图案化的光刻胶28形成在BARC 26上方，并且覆盖掩模堆叠件212、312和412，留下掩模堆叠件112未被覆盖。
参照图2，使用光刻胶28作为蚀刻掩模图案化BARC 26。因此，暴露了掩模堆叠件112的侧壁。下一步，实施修整步骤，其中，该修整是各向同性的，并且可以是湿蚀刻工艺或干蚀刻工艺。相应的步骤示出为图24中所示的工艺流程中的步骤502。根据一些实施例，通过使用包括HF、去离子水、NH4OH、H2O2、异丙醇(IPA)的蚀刻溶液的湿蚀刻工艺实施修整。可选地，通过使用包括HBr、SO2或CF4的蚀刻气体的干蚀刻工艺实施修整。作为修整的结果，掩模堆叠件112具有宽度W112’，根据一些实施例，该宽度W112’小于约0.9x W112。
下一步，如图3所示，去除BARC 26和光刻胶28。可以实施另一修整工艺以使用各向同性蚀刻进一步修整掩模堆叠件112、212、312和412的宽度。相应的步骤也示出为图24中所示的工艺流程中的步骤502。蚀刻剂可以与用于图2中所示的修整的蚀刻剂相同(或不同)。因此，如图3所示，宽度W112”、W212’、W312’和W412’分别小于宽度W112’、W212、W312和W412的约90％。
参照图4，使用掩模堆叠件112、212、312和412作为蚀刻掩模蚀刻伪栅电极层24和伪栅极电介质22(图3)。蚀刻的伪栅电极层24的剩余部分是伪栅电极124、224、324和424。蚀刻的伪栅极电介质22的剩余部分分别是伪栅极电介质122、222、322和422。相应的步骤示出为图24中所示的工艺流程中的步骤504。在这个步骤期间，蚀刻穿过伪栅极电介质22(图3)，并且暴露了半导体鳍20A。也暴露了伪栅极电介质122、222、322和422的侧壁。可以消耗图3中所示的掩模层118。
通过图1至图4所示的工艺，可以将伪栅电极124、224、324和424的宽度调整和收缩至期望的值，这可以引起产生的晶体管(特别是标准晶体管和HV晶体管)的临界尺寸(CD，栅极宽度)的有利减小。根据本发明的一些实施例，栅电极124、224、324和424的宽度可以具有比率在1.0:1.0～1.3:1.3～1.6:4.0～4.5范围内的W112”:W212’:W312’:W412’。
随后在图5A/5B至图23中示出的工艺步骤示出了用于形成晶体管的中间步骤。示出了用于形成一种晶体管的工艺流程，其中，该工艺流程可以表示器件区域100中的标准晶体管、器件区域200中的HV晶体管、器件区域300中的长沟道晶体管和器件区域400中的IO晶体管的工艺流程。因此，根据将要形成的晶体管的类型，图5A中所示的组件表示图4中所示的掩模堆叠件以及相应的下面的伪栅电极和伪栅极电介质。例如，当将要形成标准晶体管时，图5A中的部件22’、24’、14和16分别表示图4中的部件122、124、114和116。类似地，当将要形成IO晶体管时，图5A中的部件22’、24’、14和16分别表示图4中的部件422、424、414和416。如图5A所示，伪栅极电介质22’和伪栅电极24’具有在半导体鳍20A的顶面和侧壁上延伸的侧壁部分(使用虚线示出)。在随后的讨论中，部件22’、24’、14和16统称为伪栅极堆叠件30。
图5B示出了图5A中所示的结构的截面图，其中，该截面图是从图5A中的平面交叉线5B-5B截取的。图5B示出了突出高于STI区域38的顶面38A的半导体鳍20A，以及在半导体鳍20A的顶面和侧壁上延伸的伪栅极堆叠件30。
图6示出了栅极间隔件32的形成，该栅极间隔件32形成在伪栅极堆叠件的侧壁上。相应的步骤示出为图24中所示的工艺流程中的步骤506。根据本发明的一些实施例，栅极间隔件32包括多个层，例如，层32A和位于层32A上方的层32B。虽然未示出，但是栅极间隔件32中可以包括多层。栅极间隔件32的材料包括氧化硅、氮化硅、氮氧化硅、碳氮氧化硅等。例如，层32A和层32B可以由不同的材料形成。可选地，层32A和层32B包括具有不同组分(具有不同百分比)的相同的元素(诸如硅和氮)。根据一些实施例，栅极间隔件32可以与半导体鳍20A的顶面和侧壁接触。
参照图7，形成源极/漏极区域36。相应的步骤示出为图24中所示的工艺流程中的步骤508。根据本发明的一些实施例，源极/漏极区域36的形成包括蚀刻未由伪栅极堆叠件30和栅极间隔件32覆盖的半导体鳍20A的部分，并且实施外延以在产生的凹槽中生长外延区域。根据一些示例性实施例，当将要形成n-型FinFET时，源极/漏极区域36包括硅磷(SiP)或磷掺杂的硅碳(SiCP)。当将要形成p-型FinFET时，源极/漏极区域36可以包括SiGe和诸如硼或铟的p-型杂质(可以在外延期间原位掺杂)。可以实施或不实施注入以将n-型杂质(用于n-型FinFET)或p-型杂质(用于p-型FinFET)掺杂至外延区域。根据可选实施例，通过注入半导体鳍20A实施源极/漏极区域36的形成。
图8示出了接触蚀刻停止层(CESL)40和位于CESL 40上方的层间电介质(ILD)42的形成。相应的步骤示出为图24中所示的工艺流程中的步骤510。根据一些实施例，在CESL 40的形成之前，在源极和漏极区域36上形成缓冲氧化物层(未示出)。缓冲氧化物层可以由氧化硅形成，并且CESL 40可以由氮化硅、碳氮化硅等形成。例如，可以使用原子层沉积(ALD)形成缓冲氧化物层和CESL 40。ILD 42可以使用例如可流动化学汽相沉积(FCVD)由可流动氧化物形成。ILD 42也可以包括磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、正硅酸乙酯(TEOS)氧化物等。可以实施诸如化学机械抛光(CMP)的平坦化以使伪栅极堆叠件30、栅极间隔件32、CESL 40和ILD 42的顶面齐平。
之后，如图9和图10所示，去除伪栅极堆叠件30。相应的步骤示出为图24中所示的工艺流程中的步骤512。首先去除掩模层14和16，并且产生的结构如图9所示。例如，可以使用诸如CF4/O2/N2、NF3/O2、SF6或SF6/O2的含氟工艺气体或使用H3PO4溶液去除掩模层14和16。下一步，形成阶梯以蚀刻氧化物层，该氧化物层是在伪栅电极24’上形成的自然氧化物层。可以使用NF3和NH3实施氧化物的去除，当暴露在RF下时，NF3和NH3彼此反应以形成NH4F，NH4F用于蚀刻氧化硅(当加热时，例如至约40℃)以产生(NH4)2SiF6和水。(NH4)2SiF6是固体，并且当退火(例如，在高于约100℃的温度下)时，产生气体SiF4、NH3和HF，该气体通过泵(未示出)从室44排出。
图9进一步示出了根据本发明的一些实施例的伪栅电极24’的蚀刻。将晶圆2放置在室44中，并且引入工艺气体NF3和H2，并且由NF3产生等离子体，NF3与H2(和产生的等离子体)反应以形成H(氢)自由基和F(氟)自由基。离子也由工艺气体产生。图9示出了由字符“R”表示的自由基，并且分别由“+”和“-”符号表示正离子和负离子。过滤器46(其可以是选择性调制器件)用于过滤掉离子，同时允许自由基穿过过滤器46以到达晶圆2。氟自由基与硅(伪栅电极24’)反应以产生气态的SiH4和H2，其通过泵(未示出)从室44排出。在伪栅电极24’的蚀刻期间，氟自由基是不定向的并且不具有轰击效果。因此，伪栅电极24’的底部拐角部分被完全蚀刻而没有留下残留物。
如图10所示，在伪栅电极24’的去除之后，例如，使用NF3/NH3或HF去除伪栅极电介质22’，使得半导体鳍20A的顶面和侧壁暴露，并且形成凹槽48。有利地，由于伪栅极介电层22(图2和图3)的蚀刻穿过，因此没有留下直接位于栅极间隔件32下面的伪栅极电介质。因此，没有直接在栅极间隔件32下方形成底切，其中，该底切(如果形成)可以填充有用于形成置换栅极的随后沉积的金属，并且可能产生泄漏/短路路径。因此，伪栅极介电层22的蚀刻穿过有利地去除了泄漏/短路路径。
图11和图12示出了根据一些实施例的栅极间隔件50的形成。相应的步骤示出为图24中所示的工艺流程中的步骤514。根据可选实施例，跳过图11和图12所示的步骤。参照图11，例如，使用诸如ALD或CVD的共形沉积方法形成栅极间隔件层49。因此，栅极间隔件层49的水平部分和垂直部分的厚度彼此接近，例如，其差值小于水平部分的厚度的约20％或10％。根据本发明的一些实施例，栅极间隔件层由氮化硅、碳氮化硅、氮氧化硅或其它介电材料(可以与栅极间隔件32的材料以及CESL 40和ILD42的材料不同)形成。栅极间隔件50的形成有利地将随后形成的金属栅极和源极/漏极区域36分隔开并且彼此远离，并且减小了它们之间泄漏和电短路的可能性。
参照图12，实施各向异性蚀刻以去除栅极间隔件49的水平部分，留下栅极间隔件32的侧壁上的栅极间隔件50。
之后，如图13A所示，置换栅极堆叠件52形成在凹槽48中，并且在半导体鳍20A的顶面和侧壁上延伸。相应的步骤示出为图24中所示的工艺流程中的步骤516。栅极堆叠件52可以包括界面介电层54、高k栅极电介质56和置换栅电极58。根据本发明的一些实施例，界面介电层54是通过热氧化或化学氧化形成的氧化硅层，在热氧化或化学氧化期间氧化半导体鳍20A的表面层。高k介电层56可以具有大于7或大于20的k值。示例性高k介电材料包括氧化铪、氧化锆、氧化镧等。置换栅电极58可以是由同质导电材料形成的单层，或可以是包括由TiN、氮化钛硅(TSN)、TaSiN、WN、TiAl、TiAlN、TaC、TaN、铝、钨或它们的组合形成的多个层的复合层。高k介电层56和栅电极58的形成可以包括ALD、物理汽相沉积(PVD)、金属有机化学汽相沉积(MOCVD)和/或其它适用的方法。实施诸如CMP的平坦化以去除过量的栅极堆叠件52。
在栅极堆叠件52上方形成硬掩模60。根据本发明的一些实施例，回蚀刻平坦化的栅极堆叠件52，并且在产生的凹槽(由栅极堆叠件52的蚀刻的部分留下的)中形成硬掩模60。硬掩模60的形成包括沉积步骤和平坦化步骤以去除栅极间隔件32和ILD 42上方的过量沉积的材料。例如，硬掩模60可以由氮化硅形成。
图13B示意性示出了晶圆上物理形成的金属栅极的轮廓。可以看出，置换栅电极58可以具有在边缘部分之上突出的中间部分的轮廓。因此，在图13B所示的截面图中，该顶面形成了角α。如前面的段落讨论的，示出的晶体管可以表示标准晶体管、HV晶体管、长沟道晶体管和IO晶体管。由于栅电极的宽度不同，因此，这些晶体管的轮廓可以彼此不同。例如，假设当示出的晶体管是标准晶体管、HV晶体管、长沟道晶体管或IO晶体管时，角α分别等于α1、α2、α3或α4，则比率α1:α2:α3:α4可以在1.0:1.7～1.8:1.9～2.0:2.0～2.1的范围内。
栅极堆叠件52的高度HMG从硬掩模60的顶面至STI区域38(图5B)的顶面38A测量，假设当示出的晶体管是标准晶体管、HV晶体管、长沟道晶体管或IO晶体管时，高度HMG分别等于高度HMG1、高度HMG2、高度HMG3或高度HMG4，则比率HMG1:HMG2:HMG3:HMG4可以在1.0:1.0～1.1:0.9～1.0:1.0～1.1的范围内。
当示出的晶体管分别是标准晶体管、HV晶体管、长沟道晶体管或IO晶体管时，栅极堆叠件52的体积V可以表示为V1、V2、V3或V4。根据本发明的一些实施例，比率V1:V2:V3:V4可以在1.0:0.9～0.98:30～38:42～48的范围内。
栅极间隔件50的侧壁的倾斜角β1可以小于约89度，并且栅极间隔件32的侧壁的倾斜角β2可以小于约89度。根据本发明的一些实施例，栅极堆叠件52的边缘基本是直的，并且因此倾斜角β1和β2接近90度。
图14至图16示出了下源极/漏极接触插塞的形成。相应的步骤示出为图24中所示的工艺流程中的步骤518。参照图14，形成牺牲介电层62，随后是图案化的光刻胶64的施加。牺牲介电层62由与ILD 42的材料不同的介电材料形成。例如，牺牲介电层62可以由选自用于形成ILD 42的相同备选介电材料的介电材料形成，但它们仍由不同的材料形成。下一步，如图15所示，蚀刻牺牲介电层62、ILD 42和CESL 40以形成接触开口66。之后，例如通过自对准硅化工艺形成源极/漏极硅化区域68。应该理解，源极/漏极接触开口66可以在单个光刻工艺中形成，或可以在使用两个光刻工艺的双图案化工艺中形成，其中，位于置换栅极堆叠件52的左侧上的源极/漏极接触开口66的图案在第一光刻掩模中，并且位于置换栅极堆叠件52的右侧上的源极/漏极接触开口66的图案在第二光刻掩模中。之后，去除光刻胶64。
参照图16，用导电材料填充接触开口66，随后是平坦化工艺，因此形成源极/漏极接触插塞70。根据一些实施例，源极/漏极接触插塞70包括由钛、氮化钛、钽或氮化钽形成的扩散阻挡层，以及位于扩散阻挡层上方的诸如钨、铝、铜等的金属。根据可选实施例，接触插塞70由诸如钨或合金的同质材料形成的单层形成。
图17至图19示出了栅极接触插塞的形成。相应的步骤示出为图24中所示的工艺流程中的步骤520。参照图17，使用光刻掩模(未示出)实施光刻工艺以蚀刻穿过牺牲介电层62。之后，去除硬掩模60，形成开口72。根据本发明的一些实施例，开口72的形成包括蚀刻穿过牺牲介电层62的各向异性蚀刻，以及去除硬掩模60的各向同性蚀刻(干或湿)。因此，暴露了栅极间隔件50的侧壁。在未形成栅极间隔件50的实施例中，栅极间隔件32的侧壁暴露于开口72。选择用于蚀刻牺牲介电层62和硬掩模60的蚀刻剂，从而使得栅极间隔件50和32基本未蚀刻。根据本发明的可选实施例，开口72比硬掩模60窄，并且因此留下硬掩摸60的一些边缘部分，其中，使用虚线72’示出相应的开口72和硬掩模60。
参照图18，沉积导电材料74，其中，形成了单层或复合层(包括多个导电层)。栅极接触插塞74的材料和结构可以选自接触插塞70的相同的备选材料和结构。下一步，实施诸如CMP的平坦化步骤以去除牺牲介电层62和位于牺牲介电层62内部和上方的部分导电材料70。因此，如图19所示，形成栅极接触插塞74。也降低了源极/漏极接触插塞70。
栅极接触插塞74’和源极/漏极接触插塞70具有与栅极间隔件32和ILD 42的顶面基本共面的顶面。此外，栅极间隔件50(或如果未形成栅极间隔件50，则为栅极间隔件32)延伸至接触栅极接触插塞74’的侧壁。或者说，根据一些实施例，栅极接触插塞74’的侧壁和栅极堆叠件52的侧壁与相应的栅极间隔件50(或32)的相同侧壁接触。因此，栅极间隔件50和32将栅极接触插塞74’与源极/漏极接触插塞70分隔开。栅极间隔件50的添加有利地减小了栅极接触插塞74’和源极/漏极接触插塞70之间的泄漏或电短路的可能性。
根据可选实施例，其中，没有完全去除硬掩模60，栅极接触插塞74’通过硬掩摸60的剩余部分与一个或两个栅极间隔件分隔开，其中，硬掩模60的顶面也与栅极间隔件32和ILD 42的顶面共面。根据这些实施例，虚线示出了栅极接触插塞74’的侧壁。
图20示出了蚀刻停止层76、ILD 78以及蚀刻停止层76和ILD 78中的源极/漏极接触插塞82的形成。蚀刻停止层76可以包括碳化硅、氮氧化硅、碳氮化硅等。ILD 78可以包括选自PSG、BSG、BPSG、氟掺杂的硅玻璃(FSG)、TEOS或其它无孔低k介电材料的材料。可以使用诸如CVD的沉积方法形成蚀刻停止层76。ILD 78可以使用旋涂、可流动化学汽相沉积(FCVD)等形成，或使用诸如等离子体增强化学汽相沉积(PECVD)、低压化学汽相沉积(LPCVD)等的沉积方法形成。
蚀刻ILD 78和蚀刻停止层76以形成开口(由82和80占据)。可以使用例如反应离子蚀刻(RIE)实施蚀刻。在随后的步骤中，形成接触间隔件80。接触间隔件80可以由选自SiN、SiON、SiCN、SiOCN、AlON、AlN、它们的组合和/或它们的多层的介电材料形成。形成方法可以与栅极间隔件50的形成基本相同，该形成方法包括毯式沉积和各向异性蚀刻。之后，例如，通过沉积和平坦化形成接触插塞82。相应的步骤示出为图24中所示的工艺流程中的步骤522。
图21示出了蚀刻停止层84、介电层86、导电通孔88以及通孔开口90的形成。可以使用分别与蚀刻停止层76和ILD 78类似(或不同)的材料和类似的方法形成蚀刻停止层84和介电层86。通孔88可以包括由钛、氮化钛、钽或氮化钽形成的阻挡层以及位于阻挡层上方的诸如铜、钨等的导电材料。通过蚀刻层76、78、84和86形成开口90。
下一步，如图22所示，填充开口90以形成通孔92，该通孔92可以由与通孔88类似的材料形成。相应的步骤示出为图24中所示的工艺流程中的步骤524。可以在通孔88和/或90的侧壁上形成通孔间隔件94以用于减少泄漏或电短路。图23示出了包括金属线96的底部金属层的形成。
本发明的实施例具有一些有利特征。通过掩模堆叠件的修整，减小了一些晶体管的宽度，并且减小了相应的晶体管的尺寸。伪栅极电介质的蚀刻穿过减小了由栅极间隔件下方形成的底切引起的电短路和泄漏的可能性。在由伪栅极堆叠件留下的凹槽中的额外的栅极间隔件的形成也有利地减少了电短路和泄漏。使用自由基蚀刻伪栅电极产生了更好的去除而没有留下残留物。此外，接触间隔件的形成也减少了泄漏并且也减小了栅极接触插塞和源极/漏极接触插塞之间短路的可能性。
根据本发明的一些实施例，方法包括在半导体区域上方形成伪栅极堆叠件，在伪栅极堆叠件的侧壁上形成栅极间隔件，去除伪栅极堆叠件以形成开口，在开口中形成置换栅极堆叠件，使置换栅极堆叠件凹进以形成凹槽，用导电材料填充凹槽，并且实施平坦化以去除栅极间隔件上方的导电材料的过量部分。导电材料的剩余部分形成了栅极接触插塞。栅极接触插塞的顶部与第一栅极间隔件的顶部处于相同的层级。
在上述方法中，其中，实施所述平坦化直至暴露所述第一栅极间隔件。
在上述方法中，其中，去除所述伪栅极堆叠件包括：由含氟工艺气体产生等离子体；从所述等离子体过滤掉离子并且留下氟自由基；以及使用所述氟自由基蚀刻所述伪栅极堆叠件的多晶硅层。
在上述方法中，进一步包括：形成具有不同宽度的第一掩模堆叠件和第二掩模堆叠件；形成光刻胶以覆盖所述第二掩模堆叠件；修整所述第一掩模堆叠件的第一宽度；去除所述光刻胶；同时进一步修整所述第一掩模堆叠件的所述第一宽度和所述第二掩模堆叠件的第二宽度；以及使用所述第一掩模堆叠件和所述第二掩模堆叠件作为蚀刻掩模以蚀刻伪栅电极层和伪栅极介电层。
在上述方法中，其中，在所述半导体区域上方形成所述伪栅极堆叠件包括：蚀刻伪栅电极层以揭露伪栅极介电层；以及蚀刻穿过所述伪栅极介电层以暴露所述半导体区域。
在上述方法中，进一步包括：在去除所述伪栅极堆叠件以形成所述开口之后，在所述开口中形成第二栅极间隔件，其中，所述第二栅极间隔件具有接触所述第一栅极间隔件的第一侧壁，以及接触所述栅极接触插塞的侧壁的第二侧壁。
在上述方法中，其中，所述栅极接触插塞包括接触所述第一栅极间隔件的侧壁的侧壁。
根据本发明的一些实施例，方法包括在半导体鳍的顶面和侧壁上形成伪栅极堆叠件，形成具有接触伪栅极堆叠件的侧壁的侧壁的栅极间隔件，在伪栅极堆叠件的侧上形成源极/漏极区域，形成层间电介质以覆盖源极/漏极区域，去除伪栅极堆叠件以在栅极间隔件之间形成开口，用置换栅极堆叠件填充开口的底部，并且形成填充开口的顶部的栅极接触插塞。栅极接触插塞位于栅极间隔件的顶部之间。
在上述方法中，其中，所述栅极接触插塞通过以下步骤形成：蚀刻所述置换栅极堆叠件的顶部以在所述第一栅极间隔件的所述顶部之间形成凹槽；用硬掩模层填充所述凹槽；去除所述硬掩模层以再生所述凹槽；用导电材料填充所述凹槽；以及实施平坦化以去除所述导电材料的过量部分，其中，所述导电材料的剩余部分形成所述栅极接触插塞。
在上述方法中，其中，形成所述置换栅极堆叠件包括：填充延伸至所述开口内的栅极介电层，所述开口是由去除的伪栅极堆叠件留下的；在所述栅极介电层上方沉积栅电极层；以及对所述栅极介电层和所述栅电极层实施平坦化以形成所述置换栅极堆叠件。
在上述方法中，进一步包括：蚀刻所述层间电介质以形成源极/漏极接触开口，其中，所述源极/漏极区域暴露于所述源极/漏极接触开口；形成源极/漏极接触插塞以填充所述源极/漏极接触开口，其中，当形成所述栅极接触插塞时，所述栅极接触插塞的相同的材料沉积在所述源极/漏极接触插塞上方并且接触所述源极/漏极接触插塞；以及去除沉积在所述源极/漏极接触插塞上方并且接触所述源极/漏极接触插塞的所述栅极接触插塞的相同的材料的部分。
在上述方法中，其中，形成所述栅极接触插塞包括：在所述层间电介质上方形成牺牲介电层；蚀刻所述牺牲介电层以在所述层间电介质中形成额外的开口；将金属材料填充至所述额外的开口内以及所述开口的顶部；以及去除所述牺牲介电层和填充在所述额外的开口中的所述金属材料的部分。
在上述方法中，进一步包括：在去除所述伪栅极堆叠件以形成所述开口之后，在所述开口中形成第二栅极间隔件，其中，所述第二栅极间隔件具有接触所述第一栅极间隔件的所述侧壁的第一侧壁，以及接触所述栅极接触插塞的侧壁的第二侧壁。
在上述方法中，其中，所述栅极接触插塞包括接触所述第一栅极间隔件的侧壁的侧壁。
根据本发明的一些实施例，器件包括半导体区域、位于半导体区域上方的栅极堆叠件、位于栅极堆叠件的侧上的源极/漏极区域，以及位于栅极堆叠件的侧壁上的第一栅极间隔件和第二栅极间隔件。栅极接触插塞位于栅极堆叠件上方，并且栅极接触插塞位于第一栅极间隔件和第二栅极间隔件之间，其中，第一栅极间隔件和第二栅极间隔件的顶部与栅极接触插塞处于相同的层级。
在上述器件中，其中，所述栅极接触插塞与所述第一栅极间隔件和所述第二栅极间隔件的侧壁接触，并且所述栅极堆叠件的相对侧壁与所述第一栅极间隔件和所述第二栅极间隔件的所述侧壁接触。
在上述器件中，其中，所述第一栅极间隔件和所述第二栅极间隔件与所述半导体区域的顶面物理接触。
在上述器件中，进一步包括：第一源极/漏极接触插塞，位于所述源极/漏极区域上方并且电连接至所述源极/漏极区域，其中，所述第一源极/漏极接触插塞包括与所述第一栅极间隔件和所述第二栅极间隔件的顶面共面的顶面；蚀刻停止层，位于所述第一源极/漏极接触插塞和所述栅极接触插塞上方；介电层，位于所述蚀刻停止层上方；第二源极/漏极接触插塞，位于所述第一源极/漏极接触插塞上方并且接触所述第一源极/漏极接触插塞，其中，所述第二源极/漏极接触插塞位于所述蚀刻停止层和所述介电层中；以及介电接触间隔件，环绕并且接触所述第二源极/漏极接触插塞。
在上述器件中，进一步包括第三栅极间隔件和第四栅极间隔件，其中，所述第一栅极间隔件和所述第二栅极间隔件位于所述第三栅极间隔件和所述第四栅极间隔件之间，其中，所述第三栅极间隔件包括：第一层，具有L形状；以及第二层，直接位于所述第一层的水平支脚上方。
在上述器件中，其中，在所述集成电路器件的截面图中，所述栅极接触插塞的侧壁与所述栅极堆叠件的所述侧壁垂直对准。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成集成电路器件的方法，包括：
在半导体区域上方形成伪栅极堆叠件；
在所述伪栅极堆叠件的侧壁上形成第一栅极间隔件；
去除所述伪栅极堆叠件以形成开口；
在所述开口中形成置换栅极堆叠件；
使所述置换栅极堆叠件凹进以形成凹槽；
用导电材料填充所述凹槽；以及
实施平坦化以去除所述第一栅极间隔件上方的所述导电材料的过量部分，其中，所述导电材料的剩余部分形成了栅极接触插塞，其中，所述栅极接触插塞的顶部与所述第一栅极间隔件的顶部处于相同的层级。
2.根据权利要求1所述的方法，其中，实施所述平坦化直至暴露所述第一栅极间隔件。
3.根据权利要求1所述的方法，其中，去除所述伪栅极堆叠件包括：
由含氟工艺气体产生等离子体；
从所述等离子体过滤掉离子并且留下氟自由基；以及
使用所述氟自由基蚀刻所述伪栅极堆叠件的多晶硅层。
4.根据权利要求1所述的方法，进一步包括：
形成具有不同宽度的第一掩模堆叠件和第二掩模堆叠件；
形成光刻胶以覆盖所述第二掩模堆叠件；
修整所述第一掩模堆叠件的第一宽度；
去除所述光刻胶；
同时进一步修整所述第一掩模堆叠件的所述第一宽度和所述第二掩模堆叠件的第二宽度；以及
使用所述第一掩模堆叠件和所述第二掩模堆叠件作为蚀刻掩模以蚀刻伪栅电极层和伪栅极介电层。
5.根据权利要求1所述的方法，其中，在所述半导体区域上方形成所述伪栅极堆叠件包括：
蚀刻伪栅电极层以揭露伪栅极介电层；以及
蚀刻穿过所述伪栅极介电层以暴露所述半导体区域。
6.根据权利要求1所述的方法，进一步包括：
在去除所述伪栅极堆叠件以形成所述开口之后，在所述开口中形成第二栅极间隔件，其中，所述第二栅极间隔件具有接触所述第一栅极间隔件的第一侧壁，以及接触所述栅极接触插塞的侧壁的第二侧壁。
7.根据权利要求1所述的方法，其中，所述栅极接触插塞包括接触所述第一栅极间隔件的侧壁的侧壁。
8.一种形成集成电路器件的方法，包括：
在半导体鳍的顶面和侧壁上形成伪栅极堆叠件；
形成具有接触所述伪栅极堆叠件的侧壁的侧壁的第一栅极间隔件；
在所述伪栅极堆叠件的侧上形成源极/漏极区域；
形成层间电介质以覆盖所述源极/漏极区域；
去除所述伪栅极堆叠件以在所述第一栅极间隔件之间形成开口；
用置换栅极堆叠件填充所述开口的底部；以及
形成填充所述开口的顶部的栅极接触插塞，其中，所述栅极接触插塞位于所述第一栅极间隔件的顶部之间。
9.根据权利要求8所述的方法，其中，所述栅极接触插塞通过以下步骤形成：
蚀刻所述置换栅极堆叠件的顶部以在所述第一栅极间隔件的所述顶部之间形成凹槽；
用硬掩模层填充所述凹槽；
去除所述硬掩模层以再生所述凹槽；
用导电材料填充所述凹槽；以及
实施平坦化以去除所述导电材料的过量部分，其中，所述导电材料的剩余部分形成所述栅极接触插塞。
10.一种集成电路器件，包括：
半导体区域；
栅极堆叠件，位于所述半导体区域上方；
源极/漏极区域，位于所述栅极堆叠件的侧上；
第一栅极间隔件和第二栅极间隔件，位于所述栅极堆叠件的侧壁上；以及
栅极接触插塞，位于所述栅极堆叠件上方，其中，所述栅极接触插塞位于所述第一栅极间隔件和所述第二栅极间隔件之间，其中，所述第一栅极间隔件和所述第二栅极间隔件的顶部与所述栅极接触插塞处于相同的层级。
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