CN112018036A - 半导体装置结构的制造方法 - Google Patents

半导体装置结构的制造方法 Download PDF

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Publication number
CN112018036A
CN112018036A CN202010406637.6A CN202010406637A CN112018036A CN 112018036 A CN112018036 A CN 112018036A CN 202010406637 A CN202010406637 A CN 202010406637A CN 112018036 A CN112018036 A CN 112018036A
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China
Prior art keywords
layer
gate stack
dielectric layer
metal gate
work function
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CN202010406637.6A
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张容浩
林立德
林斌彦
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US16/676,057 external-priority patent/US11183580B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN112018036A publication Critical patent/CN112018036A/zh
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

提供半导体装置的结构及半导体装置结构的制造方法。前述方法包括在半导体基底上方形成虚设栅极堆叠，以及在前述虚设栅极堆叠的侧壁上方形成多个间隔元件。前述方法亦包括移除前述虚设栅极堆叠以在前述间隔元件之间形成凹槽，以及在前述凹槽中形成金属栅极堆叠。前述方法还包括在前述金属栅极堆叠保持在温度介于约20℃至约55℃的范围内时，回蚀刻前述金属栅极堆叠。此外，前述方法包括在回蚀刻前述金属栅极堆叠之后，在前述金属栅极堆叠上方形成保护元件。

Description

半导体装置结构的制造方法
技术领域
本公开实施例涉及一种半导体装置结构的制造方法，特别涉及一种在特定温度范围内回蚀刻金属栅极堆叠的半导体装置结构的制造方法。
背景技术
半导体集成电路(IC)产业已经历快速的成长。集成电路材料与设计的科技进步已产生多个世代的集成电路。每一个世代都相较于前一个世代具有更小且更复杂的电路。
在集成电路演进的过程中，功能密度(即每芯片面积中互连装置的数量)已普遍增加，而几何尺寸(即利用一工艺所能产生的最小元件(或线))则会缩小。这种缩小尺寸的工艺提供增加生产效率以及降低相关成本的技术效果。
然而，这些进步已增加加工及制造集成电路的复杂度。由于特征尺寸持续缩小，工艺会变得更难以执行。因此，要形成尺寸愈来愈小的可靠半导体装置便成为一挑战。
发明内容
本公开实施例提供一种半导体装置结构的制造方法，包括：在半导体基底上方形成虚设栅极堆叠，且在前述虚设栅极堆叠的侧壁上方形成多个间隔元件。移除前述虚设栅极堆叠以在前述间隔元件之间形成凹槽，以及在前述凹槽中形成金属栅极堆叠。在前述金属栅极堆叠保持在温度介于约20℃至约55℃的范围内时，回蚀刻前述金属栅极堆叠。在回蚀刻前述金属栅极堆叠之后，在前述金属栅极堆叠上方形成保护元件。
本公开实施例提供一种半导体装置结构的制造方法，包括：在鳍结构上方形成金属栅极堆叠。在前述金属栅极堆叠保持在温度介于约20℃至约55℃的范围内时，利用蚀刻工艺移除前述金属栅极堆叠的上部。在前述蚀刻工艺中使用的反应气体混合物包括第一含卤素气体以及第二含卤素气体，第一含卤素气体具有第一分子量，第二含卤素气体具有第二分子量，且第二分子量大于第一分子量。以第一流率提供前述第一含卤素气体，以第二流率提供前述第二含卤素气体，且第一流率大于第二流率。在移除前述金属栅极堆叠的上部之后，在前述金属栅极堆叠上方形成保护元件。
本公开实施例提供一种半导体装置结构，包括：半导体基底、金属栅极堆叠以及间隔元件。金属栅极堆叠位于半导体基底上方，其中前述金属栅极堆叠包括栅极介电层以及位于前述栅极介电层上方的功函数层。间隔元件位于前述金属栅极堆叠的侧壁上方，其中前述间隔元件的顶部相较于前述栅极介电层的顶部高出一第一高度差，前述栅极介电层的顶部相较于前述功函数层的顶部高出一第二高度差，且前述第一高度差和第二高度差的比值小于约1/14。
附图说明
根据以下的详细说明并配合说明书附图以更好地了解本公开实施例的概念。应注意的是，根据本产业的标准惯例，附图中的各种部件未必按照比例绘制。事实上，可能任意地放大或缩小各种部件的尺寸，以做清楚的说明。在通篇说明书及附图中以相似的标号标示相似的特征。
图1A至图1N示出根据一些实施例的形成半导体装置结构的工艺的不同阶段的剖视图。
图2示出根据一些实施例的在形成半导体装置结构的工艺的一些阶段中使用的工艺腔室。
图3A至图3B示出根据一些实施例的形成半导体装置结构的工艺的不同阶段的剖视图。
附图标记说明：
10,20：区域
100：半导体基底
102A,102B：鳍结构
104A,104B：虚设栅极堆叠
106：虚设栅极介电层
108：虚设栅极电极
110：间隔元件
112A,112B：外延结构
114：蚀刻停止层
116：介电层
118：凹槽
120：栅极介电层
122：功函数层
124：导电填充层
126A,126B：金属栅极堆叠
128：清洁处理
130：保护层
132：凹槽
134A,134B：保护元件
136A,136B：导电接点
138：蚀刻停止层
140：介电层
142：接触开口
144A,144B：导电接点
201：工艺腔室
202：等离子体供应器
204：基底支架
H1,H2：高度差
T1,T2：厚度
W1,W2：宽度
具体实施方式
以下的公开内容提供许多不同的实施例或范例以实施本公开实施例的不同特征。以下叙述构件及配置的特定范例，以简化本公开实施例的说明。当然，这些特定的范例仅为示范并非用以限定本公开实施例。举例而言，在以下的叙述中提及第一特征形成于第二特征上或上方，即表示其可包括第一特征与第二特征是直接接触的实施例，亦可包括有附加特征形成于第一特征与第二特征之间，而使第一特征与第二特征可能未直接接触的实施例。另外，在以下的公开内容的不同范例中可能重复使用相同的参考符号及/或标记。这些重复是为了简化与清晰的目的，并非用以指定所讨论的不同实施例及/或结构之间的关系。
此外，在此可使用与空间相关用词。例如“底下”、“下方”、“较低的”、“上方”、“较高的”及类似的用词，以便于描述附图中示出的一个元件或部件与另一个(些)元件或特征之间的关系。除了在附图中示出的方位外，这些空间相关用词意欲包括使用中或操作中的装置的不同方位。装置可能被转向不同方位(旋转90度或其他方位)，且在此使用的空间相关词也可依此做同样的解释。
本公开所属技术领域中技术人员将可理解以下说明中的用语“大致上”(例如在“大致上平坦”中或“大致上共平面”中)。在一些实施例中，此形容词可大致上被去除。当适用时，用语“大致上”亦可包括符合“整个”、“完全地”、“全部”等的实施例。当适用时，用语“大致上”可与90％或以上有关，例如95％或以上，尤其99％或以上，且包括100％。另外，用语例如“大致上平行”或“大致上垂直”是被解读为不排除从特定排列的微幅偏差，且可包括例如高达10°的偏差。用语“大致上”不排除“完全”，例如“大致上不含”Y的组成可以完全不含Y。
与特定距离或尺寸连接的用语例如“约”是解读为不排除从特定距离或尺寸的微幅偏差，且可包括例如高达10％的偏差。用语“约”与数值x相连可表示x正负5％或10％。
本公开实施例可与具有鳍片的鳍式场效晶体管(Fin Field Effect Transistor；FinFET)有关。可通过任何适合的方式将鳍片图案化。举例而言，可利用一或多个微影工艺将鳍片图案化，包括双重图案化工艺或多重图案化工艺。普遍地，双重图案化工艺或多重图案化工艺结合微影工艺和自对准工艺，其允许产生出间距小于利用单一且直接的微影工艺所能得到之间距的图案。利用自对准工艺沿图案化牺牲层的侧边形成间隔件。接着，移除牺牲层，且可利用剩余的间隔件来将鳍片图案化。然而，可利用一或多个其他适用的工艺来形成鳍片。
以下说明本公开的一些实施例。可在这些实施例中所述的阶段之前、期间及/或之后提供额外的操作。可对于不同实施例将所述的其中一些阶段进行替换或删减。可将额外的特征加入半导体装置结构中。可对于不同实施例将以下所述的其中一些特征进行替换或删减。虽然以下所述的一些实施例是以特定的顺序来进行操作，但这些操作也可用另一合乎逻辑的顺序来进行。
图1A至图1N示出根据一些实施例的形成半导体装置结构的工艺的不同阶段的剖视图。如图1A所示，接收或提供半导体基底100。半导体基底100包括区域10和20。在一些实施例中，设计较窄的栅极堆叠和较宽的栅极堆叠，分别形成在区域10和20上方。在一些实施例中，在区域10上方的栅极堆叠的分布密度大于在区域20上方的栅极堆叠的分布密度。
在一些实施例中，半导体基底100是体半导体(bulk semiconductor)，例如半导体晶圆。举例而言，半导体基底100包括硅或其他元素半导体材料，例如锗。半导体基底100可以是非掺杂的或掺杂的(例如p型、n型或前述的组合)。在一些实施例中，半导体基底100包括介电层上的外延成长半导体层。外延成长半导体层可由硅锗、硅、锗、一或多个其他适合的材料或前述的组合。
在其他一些实施例中，半导体基底100包括化合物半导体。举例而言，化合物半导体包括一或多个三五族化合物(III-V compound)半导体，其具有由化学式AlX1GaX2InX3AsY1PY2NY3SbY4所定义的组成，其中X1、X2、X3、Y1、Y2、Y3和Y4表示相对的比例，前述代数的每一者都大于或等于零，并且将所有代数相加会等于1。化合物半导体可以包括碳化硅、砷化镓、砷化铟、磷化铟、一或多个其他适合的化合物半导体或前述的组合，但也可以使用包括二六族化合物(II-VI compound)半导体的其他适合的基底。
在一些实施例中，半导体基底100为绝缘体上半导体(semiconductor-on-insulator；SOI)基底的主动层。可利用氧离子布植分离式(separation by implantationof oxygen；SIMOX)工艺、晶圆结合工艺、其他适用的方法或前述的组合来制造绝缘体上半导体(SOI)基底。在其他一些实施例中，半导体基底100包括多层结构。举例而言，半导体基底100包括形成在体硅(bulk silicon)层上的硅锗层。
如图1A所示，根据一些实施例，形成多个鳍结构102A和102B。在一些实施例中，在半导体基底100中形成多个凹槽(或沟槽)。如此一来，在凹槽之间形成或定义有凸出半导体基底100表面的多个鳍结构。在一些实施例中，利用一或多个微影工艺或蚀刻工艺来形成凹槽。在一些实施例中，鳍结构102A和102B与半导体基底100直接接触。
然而，本公开实施例具有许多变化及/或修改。在其他一些实施例中，鳍结构102A和102B不与半导体基底100直接接触。可在半导体基底100和鳍结构102A、102B之间形成一或多层其他材料层。举例而言，可在半导体基底100和鳍结构102A、102B之间形成介电层。
接着，根据一些实施例，在凹槽中形成隔离部件(未图示)以围绕鳍结构102A和102B的下部。隔离部件是用以定义且电性隔离形成在半导体基底100中及/或上方的各个装置元件。在一些实施例中，隔离部件包括浅沟槽隔离(shallow trench isolation；STI)部件、硅局部氧化(local oxidation of silicon；LOCOS)部件、其他适合的隔离部件或前述的组合。
在一些实施例中，隔离部件具有多层结构。在一些实施例中，隔离部件是由介电材料制成。介电材料可包括氧化硅、氮化硅、氮氧化硅、氟掺杂硅酸盐玻璃(fluoride-dopedsilicate glass；FSG)、低介电常数(low-K)的介电材料、其他适合的介电材料或前述的组合。在一些实施例中，形成浅沟槽隔离(STI)衬垫(未图示)以降低半导体基底100和隔离部件之间界面处的晶体缺陷。相似地，浅沟槽隔离衬垫亦可用以降低鳍结构和隔离部件之间界面处的晶体缺陷。
在一些实施例中，在半导体基底100上方沉积介电材料层。介电材料覆盖鳍结构102A和102B，且填充鳍结构之间的凹槽。在一些实施例中，利用流动式化学气相沉积(flowable chemical vapor deposition；FCVD)工艺、化学气相沉积(chemical vapordeposition；CVD)工艺、原子层沉积(atomic layer deposition；ALD)工艺、旋转涂布工艺、一或多种其他适用的工艺或前述的组合来沉积介电材料。
在一些实施例中，执行平坦化工艺以使介电材料层变薄并且暴露鳍结构102A和102B。平坦化工艺可包括化学机械抛光(chemical mechanical polishing；CMP)工艺、研磨工艺、蚀刻工艺、干式抛光工艺、一或多种其他适用的工艺或前述的组合。接着，回蚀刻介电材料层至鳍结构102A和102B的顶部下方。如此一来，介电材料层的其余部分形成隔离部件。鳍结构102A和102B凸出于隔离部件的顶面。
如图1A所示，根据一些实施例，虚设栅极堆叠104A和104B形成在半导体基底100上方。虚设栅极堆叠104A和104B分别部分地覆盖且围绕鳍结构102A和102B。如图1A所示，虚设栅极堆叠104A具有宽度W1，且虚设栅极堆叠104B具有宽度W2。宽度W2大于宽度W1。
在一些实施例中，虚设栅极堆叠104A和104B的每一者具有虚设栅极介电层106和虚设栅极电极108。虚设栅极介电层106可包括氧化硅、氧氮化硅、氮化硅、一或多种其他适合的材料或前述的组合或由前述材料制成。虚设栅极电极108可包括例如多晶硅的半导体材料或由前述材料制成。
在一些实施例中，在半导体基底100以及鳍结构102A和102B上方依序地沉积介电材料层和栅极电极层。可使用化学气相沉积(CVD)工艺、原子层沉积(ALD)工艺、热氧化工艺，物理气相沉积(physical vapor deposition；PVD)工艺、一或多种其他适用的工艺或前述的组合来沉积介电材料层。
接着，可使用一或多种微影工艺和蚀刻工艺来部分地去除介电材料层和栅极电极层。如此一来，介电材料层和栅极电极层的剩余部分形成虚设栅极堆叠104A和104B。
接着，根据一些实施例，如图1A所示，在虚设栅极堆叠104A和104B的侧壁上方形成间隔元件110。间隔元件110可用于保护虚设栅极堆叠104A和104B，且辅助用于形成源极/漏极部件及/或金属栅极的后续工艺。在一些实施例中，间隔元件110包括介电材料或由介电材料制成。介电材料可包括氮化硅、氮氧化硅、氧化硅、碳化硅、一或多种其他适合的材料或前述的组合。
在一些实施例中，在半导体基底100、鳍结构102A和102B以及虚设栅极堆叠104A和104B上方沉积介电材料层。可使用化学气相沉积工艺、原子层沉积工艺、旋转涂布工艺、一或多种其他适用的工艺或前述的组合来沉积介电材料层。之后，使用蚀刻工艺(例如非等向性蚀刻工艺)来部分地去除介电材料层。如此一来，位于虚设栅极堆叠104A和104B的侧壁上方的介电材料层的剩余部分形成间隔元件110。
如图1B所示，根据一些实施例，在鳍结构102A和102B上方分别形成外延结构112A和112B。外延结构112A和112B可用作源极/漏极部件。在一些实施例中，在形成外延结构112A和112B之前，使鳍结构102A和102B的未被虚设栅极堆叠104A和104B覆盖的部分形成有凹槽。在一些实施例中，前述凹槽会在虚设栅极堆叠104A和104B下方朝向通道区横向地延伸。举例而言，凹槽的一部分位在间隔元件110的正下方。接着，在凹槽的侧壁和底部上生长一或多种半导体材料以形成外延结构112A和112B。
在一些实施例中，外延结构112A和112B都是p型半导体结构。在其他一些实施例中，外延结构112A和112B都是n型半导体结构。在其他一些实施例中，外延结构112A和112B的其中一者是p型半导体结构，而另一者是n型半导体结构。
p型半导体结构可以包括外延生长的硅锗或掺杂硼的硅锗。n型半导体结构可以包括外延生长的硅、外延生长的碳化硅(SiC)、外延生长的磷化硅(SiP)或其他适合的外延生长半导体材料。
在一些实施例中，同时形成外延结构112A和112B。在其他一些实施例中，外延结构112A和112B分别是使用例如分开的外延生长工艺的分开的工艺所形成。在一些实施例中，当外延结构112A生长在鳍结构102A上时，使用第一遮罩元件以覆盖鳍结构102B。之后，去除第一遮罩元件，且形成第二遮罩元件以覆盖外延结构112A。暴露出鳍结构102B而不被第二遮罩元件覆盖。然后，在鳍结构102B上生长外延结构112B。之后，去除第二遮罩元件，且获得图1B所示的结构。
在一些实施例中，外延结构112A和112B通过使用选择性外延生长(selectiveepitaxial growth；SEG)工艺、化学气相沉积工艺(例如气相外延(vapor-phase epitaxy；VPE)工艺、低压化学气相沉积(low pressure chemical vapor deposition LPCVD)及/或超高真空化学气相沉积(ultra-high vacuum CVD；UHV-CVD)工艺)、分子束外延工艺、一或多种其他适用的工艺或前述的组合。
在一些实施例中，外延结构112A和112B的其中一者或两者掺杂有一或多种适合的掺杂剂。举例而言，外延结构112A和112B是掺杂有硼(B)、铟(In)或其他适合的掺杂剂的硅锗源极/漏极部件。可替代地，在其他一些实施例中，外延结构112A和112B中的一者或两者是掺杂有磷(P)、锑(Sb)或其他适合的掺杂剂的硅源极/漏极部件。
在一些实施例中，外延结构112A和112B在其外延生长期间被原位掺杂。在其他一些实施例中，在外延结构112A和112B的生长期间不掺杂外延结构112A和112B，而是在形成外延结构112A和112B之后，在后续的工艺中掺杂外延结构112A和112B。在一些实施例中，通过使用离子布植工艺、等离子体浸没离子布植工艺、气体及/或固体源扩散工艺、一或多种其他适用的工艺或前述的组合来实现掺杂。在一些实施例中，外延结构112A和112B更暴露于一或多种退火工艺以活化掺杂剂。举例而言，可使用快速热退火工艺。
如图1C所示，根据一些实施例，在半导体基底100以及外延结构112A、112B上方依序沉积蚀刻停止层114和介电层116。蚀刻停止层114可沿着间隔元件110以及外延结构112A、112B的表面顺应性地延伸。介电层116覆盖蚀刻停止层114，且围绕间隔元件110以及虚设栅极堆叠104A、104B。
蚀刻停止层114可包括氮化硅、氮氧化硅、碳化硅、一或多种其他适合的材料或前述的组合或由前述材料制成。在一些实施例中，使用化学气相沉积工艺、原子层沉积工艺、物理气相沉积工艺、一或多种其他适用的工艺或前述的组合，将蚀刻停止层114沉积在半导体基底100以及虚设栅极堆叠104A、104B上方。
介电层116可包括氧化硅、氮氧化硅、硼硅玻璃(borosilicate glass；BSG)、磷硅玻璃(phosphoric silicate glass；PSG)、硼磷硅玻璃(borophosphosilicate glass；BPSG)、氟硅玻璃(fluorinated silicate glass；FSG)、低介电常数(low-k)材料、多孔介电材料、一或多种其他适合的材料或前述的组合或由前述材料制成。在一些实施例中，使用化学气相沉积工艺、原子层沉积工艺、流动式化学气相沉积工艺、物理气相沉积工艺，一或多种其他适用的工艺或前述的组合，将介电层116沉积在蚀刻停止层114以及虚设栅极堆叠104A和104B上方。
随后，使用平坦化工艺来去除介电层116、蚀刻停止层114、间隔元件110以及虚设栅极叠层104A和104B的上部。如此一来，介电层116、蚀刻停止层114、间隔元件110以及虚设栅极堆叠104A和104B的顶面大致上相互齐平，这有利于后续的工艺。平坦化工艺可包括化学机械抛光工艺、研磨工艺、蚀刻工艺、干式抛光工艺、一或多种其他适用的工艺或前述的组合。
如图1D所示，根据一些实施例，去除虚设栅极堆叠104A和104B以形成多个凹槽118。凹槽118的每一者位在彼此相对的两个间隔元件110之间。如图1D所示，凹槽118暴露鳍结构102A和102B的一部分。可使用一或多种蚀刻工艺来去除虚设栅极堆叠104A和104B。
如图1E所示，根据一些实施例，在介电层116上方沉积栅极介电层120。栅极介电层120沿着凹槽118的侧壁和底部延伸至凹槽118中。在一些实施例中，栅极介电层120沿着凹槽118的侧壁顺应性地延伸。
在一些实施例中，栅极介电层120包括具有高介电常数(high-K)的介电材料或由前述材料制成。栅极介电层120可包括氧化铪、氧化锆、氧化铝、二氧化铪-氧化铝合金、氧化铪硅、氮氧化铪硅、氧化铪钽、氧化铪钛、氧化铪锆、一或多种其他适合的高介电常数材料或前述的组合或由前述材料制成。
可使用原子层沉积工艺、化学气相沉积工艺、一或多种其他适用的工艺或前述的组合来沉积栅极介电层120。在一些实施例中，栅极介电层120的形成涵盖热操作。
在一些实施例中，在形成栅极介电层120之前，在鳍结构102A和102B的暴露表面上形成界面层。界面层可用于改善栅极介电层120和鳍结构102A、102B之间的粘着力。界面层可包括例如氧化硅或氧化锗的半导体氧化材料或由前述材料制成。可使用热氧化工艺、含氧等离子体操作、一或多种其他适用的工艺或前述的组合来形成界面层。
随后，根据一些实施例，如图1E所示，在栅极介电层120上沉积功函数层122。在一些实施例中，功函数层122填充在区域10上方的凹槽118的剩余空间。在一些实施例中，功函数层122部分填充在区域20上方的凹槽118。功函数层122沿着在区域20上方的凹槽118的侧壁延伸至凹槽118中。在一些实施例中，功函数层122沿着在区域20上方的凹槽118的侧壁顺应性地延伸。
功函数层122可用于为晶体管提供需要的功函数，以增强装置性能，包括改善阈值电压。在一些实施例中，功函数层122用于形成n型金属氧化物半导体(n-type metal oxidesemiconductor；NMOS)装置。功函数层122是n型功函数层。n型功函数层能够提供适合于装置的功函数值，例如等于或小于约4.5eV。
n型功函数层可包括金属、金属碳化物、金属氮化物或前述的组合。举例而言，n型功函数层包括氮化钛、钽、氮化钽、一或多种其他适合的材料或前述的组合。在一些实施例中，n型功函数是含铝层，此含铝层可包括TiAlC、TiAlO、TiAlN、一或多种其他适合的材料或前述的组合或由前述材料制成。
在一些实施例中，功函数层122用于形成p型金属氧化物半导体(p-type metaloxide semiconductor；PMOS)装置。功函数层122是p型功函数层。p型功函数层能够提供适合于装置的功函数值，例如等于或大于约4.8eV。
p型功函数层可包括金属、金属碳化物、金属氮化物、其他适合的材料或前述的组合。举例而言，p型金属包括氮化钽、氮化钨、钛、氮化钛、其他适合的材料或前述的组合。
功函数层122亦可包括铪、锆、钛、钽、铝、金属碳化物(例如碳化铪、碳化锆、碳化钛、碳化铝)、铝化物、钌、钯、铂、钴、镍、导电金属氧化物或前述的组合或由前述材料制成。可微调功函数层122的厚度及/或组成以调节功函数能阶。举例而言，取决于氮化钛层的厚度及/或组成，可将氮化钛层用作p型功函数层或n型功函数层。
可使用原子层沉积工艺、化学气相沉积工艺、物理气相沉积工艺、电镀工艺、化学镀工艺、一或多种其他适用的工艺或前述的组合将功函数层122沉积在栅极介电层120上方。
在一些实施例中，在形成功函数层122之前形成阻障层以使其与栅极介电层120和随后形成的功函数层122交界。前述阻障层亦可用于防止栅极介电层120和功函数层122之间的扩散。阻障层可包括含金属的材料或由前述材料制成。此含金属的材料可包括氮化钛、氮化钽、一或多种其他适合的材料或前述的组合。可使用原子层沉积工艺、化学气相沉积工艺、物理气相沉积工艺、电镀工艺、化学镀工艺、一或多种其他适用的工艺或前述的组合来沉积阻障层。
之后，根据一些实施例，如图1E所示，在功函数层122上方沉积导电填充层124，以填充在区域20上方的凹槽118的剩余空间。导电填充层124包括金属材料或由金属材料制成。金属材料可包括钨、铝、铜、钴、一或多种其他适合的材料或前述的组合。可使用化学气相沉积工艺、原子层沉积工艺、物理气相沉积工艺、电镀工艺、化学镀工艺、一或多种其他适用的工艺或前述的组合来沉积导电填充层124。
在一些实施例中，在形成导电填充层124之前，在功函数层122上方形成阻挡层。此阻挡层可用于防止随后形成的导电填充层124扩散或渗透至功函数层122中。阻挡层可包括氮化钽、氮化钛、一或多种其他适合的材料或前述的组合或由前述材料制成。可使用原子层沉积工艺、物理气相沉积工艺、电镀工艺、化学镀工艺、一或多种其他适用的工艺或前述的组合来沉积阻挡层。
可对本公开的实施例做出许多变化及/或修改。在其他一些实施例中，在沉积栅极介电层120、功函数层122和导电填充层124之前，部分地去除间隔元件110的上部以扩大凹槽118。可使用非等向性蚀刻工艺以部分地去除间隔元件110。由于凹槽118的上部被加宽，因此栅极介电层120、功函数层122和导电填充层124的后续沉积工艺可变得更容易。
如图1F所示，根据一些实施例，执行平坦化工艺以去除栅极介电层120、功函数层122和导电填充层124的在凹槽118之外的部分。如此一来，栅极介电层120和功函数层122的剩余部分形成金属栅极堆叠126A。栅极介电层120、功函数层122和导电填充层124的剩余部分形成金属栅极堆叠126B。平坦化工艺可包括化学机械抛光工艺、研磨工艺、蚀刻工艺、干式抛光工艺、一或多种其他适用的工艺或前述的组合。
如图1G所示，根据一些实施例，在金属栅极堆叠126A和126B的表面上执行清洁处理128。清洁处理128可用于去除在功函数层122和导电填充层124的表面上生长的原生氧化物材料。在去除原生氧化物材料之后，可更平滑地执行后续工艺。
在一些实施例中，清洁处理128涵盖对金属栅极堆叠126A和126B的等离子体处理。图2示出根据一些实施例的在用于形成半导体装置结构的工艺的某些阶段中使用的工艺腔室201。在一些实施例中，清洁处理128在工艺腔室201中执行。
在一些实施例中，工艺腔室201包括等离子体供应器202和基底支架204。等离子体供应器202可将所提供的反应气体混合物激发成等离子体。然后，可将所产生的等离子体引导到半导体基底100的表面上以执行清洁处理128。基底支架204可用于固持半导体基底100。基底支架204亦可用于向半导体基底100施加偏压及/或改变半导体基底100的温度。
在一些实施例中，在清洁处理128中使用的反应气体混合物包括Cl2、O2和N2。工艺腔室201的工艺压力可保持在约1mtorr至约5mtorr的范围内。用于将反应气体混合物激发成等离子体的功率可介于约300W至约800W的范围内。施加至半导体基底100的偏压可介于约50V至约150V的范围内。工作周期可介于约10至约30的范围内。清洁处理128的操作时间可介于约5秒至约15秒的范围内。
如图1H所示，根据一些实施例，在通过清洁处理128处理的表面上形成保护层130。在一些实施例中，在清洁处理128之后立即在工艺腔室201中原位形成保护层130，而不将半导体基底100从工艺腔室201中取出。因此，防止新的原生氧化物材料在金属栅极堆叠126A和126B的表面上生长。在一些实施例中，保护层130由聚合物材料制成或包括聚合物材料。
在一些实施例中，保护层130的形成涵盖使用等离子体。在一些实施例中，用于形成保护层130的反应气体混合物包括Cl2、BCl3、CH4和Ar。工艺腔室201的工艺压力可保持在介于约1mTorr至约6mTorr的范围内。用于将反应气体混合物激发成等离子体的功率可介于约300W至约800W的范围内。施加至半导体基底100的偏压可介于约20V至约50V的范围内。工作周期可介于约20至约50的范围内。形成保护层130的操作时间可介于约10秒至约60秒的范围内。
在一些实施例中，由于区域10和20上方的金属栅极堆叠的分布密度不同，因此保护层130在区域20上方的沉积速率大于其在区域10上方的沉积速率。保护层130在区域10上方的部分形成为具有厚度T1。保护层130在区域20上方的部分形成为具有厚度T2。在一些实施例中，厚度T2大于厚度T1。保护层130可用以控制或平衡在具有不同宽度的金属栅极堆叠126A和126B上的蚀刻负载。
如图1I所示，根据一些实施例，回蚀刻工艺是用以去除保护层130以及金属栅极堆叠126A和126B的上部。如此一来，如图1I所示，形成凹槽132。由于保护层130控制或平衡不同区域10和20的蚀刻负载，因此区域10和20上的凹槽132具有大致上相同的深度。
在一些实施例中，回蚀刻工艺是使用等离子体的干式蚀刻工艺。在一些实施例中，回蚀刻工艺在低温下执行，这允许在功函数层122(或导电填充层124)和栅极介电层120之间具有高蚀刻选择性。在一些实施例中，干式蚀刻工艺部分地去除功函数层122和导电填充层124，而大致上在不蚀刻或仅微幅蚀刻栅极介电层120。栅极介电层120可保护间隔元件110的内侧壁。因此，间隔元件110可在随后用于形成暴露金属栅极堆叠126A和126B的接触孔的蚀刻工艺期间维持且不受损。
在一些实施例中，在形成保护层130之后立即在工艺腔室201中原位执行回蚀工艺，而不将半导体基底从工艺腔室201中取出。在一些实施例中，在回蚀刻工艺中使用的反应气体混合物包括第一含卤素气体和第二含卤素气体。第二含卤素气体的分子量大于第一含卤素气体的分子量。第一含卤素气体可包括Cl2、F2或其他适合的气体。第二含卤素气体可包括BCl3、SiCl4或其他适合的气体。在一些实施例中，反应气体混合物还包括惰性气体。惰性气体可包括Ar、He、Ne、Kr、Xe或Rn。
在一些实施例中，以第一流率提供第一含卤素气体，且以第二流率提供第二含卤素气体。在一些实施例中，第一流率比第二流率更快。第一含卤素气体的第一流率可介于约50每分钟标准立方公分(sccm)至约500sccm的范围内。第二含卤素气体的第二流率可介于约5sccm至约100sccm的范围内。惰性气体的流率可介于约1sccm至约1000sccm的范围内。然而，在其他一些实施例中，不使用惰性气体。
用于执行回蚀刻处理的工艺腔室201的工艺压力可保持在介于约2mTorr至约20mTorr的范围内。用于将反应气体混合物激发成等离子体的功率可介于约200W至约900W的范围内。施加至半导体基底100的偏压可介于约50V至约150V的范围内。工作周期可介于约3至约20的范围内。回蚀刻工艺的操作时间可介于约50秒至约450秒的范围内。
如上所述，在低温下执行回蚀刻工艺，以便在功函数层122(或导电填充层124)和栅极介电层120之间提供高蚀刻选择性。图2中所示的基底支架可用于将半导体基底100以及金属栅极堆叠126A和126B保持在希望的操作温度。操作温度可介于约20℃至约55℃的范围内。在其他一些实施例中，操作温度介于约45℃至约50℃的范围内。
通过使用低操作温度，栅极介电层120的蚀刻速率和功函数层122(或导电填充层124)的蚀刻速率皆降低。在上述操作温度范围内，在一些实施例中，栅极介电层120的蚀刻速率的降低远大于功函数层122(或导电填充层124)的蚀刻速率的降低。功函数层122(或导电填充层124)的蚀刻变得稍慢一些，而栅极介电层120的蚀刻变得更慢许多。因此，功函数层122(或导电填充层124)与栅极介电层120之间的蚀刻选择性显著地提高。在一些实施例中，功函数层122对栅极介电层120的蚀刻选择性增加到超过15或甚至超过17。
在其他情况下，操作温度不在上述范围内。在一些情况下，如果操作温度高(例如高于约55℃或高于约80℃)，则功函数层122(或导电填充层124)和栅极介电层120之间的蚀刻选择性可能不足，而可能会去除更大量的栅极介电层120。因此，隔离元件110的内侧壁的上部被暴露而不会被栅极介电层120保护。如此一来，如果随后形成接触孔而暴露出金属栅极堆叠126A和126B，则隔离元件110可能会受损。接触孔可能会穿透间隔元件110以暴露电性连接至外延结构112A及/或112B的导电接点。可能会在金属栅极堆叠和外延结构之间形成短路。
在其他一些情况下，如果操作温度低于约20℃，则回蚀刻工艺可能由于低温而进行得太慢。晶圆产量可能降低太多，这也是不希望的结果。
可对本公开的实施例做出许多变化及/或修改。在其他一些实施例中，回蚀刻工艺中使用的反应气体混合物还包括含氧气体。含氧气体可以包括O2、O3、NO、NO2或其他适合的气体。通过添加含氧气体，可进一步降低栅极介电层120的蚀刻速率。由含氧气体所产生的等离子体可能会与第二含卤素气体反应或与由第二含卤素气体所产生的等离子体反应。如此一来，所产生的等离子体可具有大致上不与栅极介电层120反应的自由基。因此，功函数层122(或导电填充层124)对栅极介电层120的蚀刻选择性显著地提高。
含氧气体的流率可介于约1sccm至约20sccm的范围内。在一些实施例中，含氧气体的流率与第二含卤素气体的流率的比值介于约0.05至约0.6的范围内。
在某些情况下，如果流率比大于约0.6，则含氧气体的流速可能太高。金属栅极堆叠126A和126B可能具有被氧化的风险，这可能会降低金属栅极堆叠126A和126B的性能。
如图1J所示，根据一些实施例，在凹槽132中形成保护元件134A和134B。在一些实施例中，保护元件134A和134B的顶面与介电层116的顶表面大致上齐平。在一些实施例中，保护元件134A和134B包括介电材料或由介电材料制成。介电材料可包括氮化硅、碳化硅、氮化硅碳、氮氧化硅、一或多种其他适合的材料或前述的组合。在一些实施例中，保护元件134A和134B大致上不含氧。
在一些实施例中，在图1I所示的结构上沉积保护材料层以过度填充凹槽132。可使用化学气相沉积工艺、原子层沉积工艺、流动式化学气相沉积工艺、旋转沉积工艺、其他适用的工艺或前述的组合来沉积保护材料层。
之后，根据一些实施例，去除保护材料层位在凹槽132之外的部分。如此一来，如图1J所示，凹槽132中的保护材料层的剩余部分形成保护元件134A和134B。在一些实施例中，使用平坦化工艺来部分地去除凹槽132之外的保护材料层。平坦化工艺可以包括化学机械抛光工艺、研磨工艺、蚀刻工艺、干式抛光工艺、一或多个其他适用的工艺或前述的组合。
如图1K所示，根据一些实施例，在介电层116中形成导电接点136A和136B。导电接点136A和136B进一步穿透蚀刻停止层114以分别电连接到外延结构112A和112B。导电接点136A和136B可包括钴、钨、钌、铝、铜、金、一或多种其他适合的材料或前述的组合或前述材料制成。
在一些实施例中，使用一或多种微影工艺和一或多种蚀刻工艺以形成暴露外延结构112A和112B的接触孔。之后，可在外延结构112A和112B的暴露表面上形成金属半导体化合物区(例如金属硅化物区)。可沿着接触孔的侧壁形成阻障层或阻障区。接着，沉积导电材料以过度填充接触孔。执行平坦化工艺以去除导电材料位在接触孔之外的部分。如此一来，接触孔内部的导电材料的剩余部分形成导电接点136A和136B。
如图1L所示，根据一些实施例，在图1K所示的结构上依序沉积蚀刻停止层138和介电层140。蚀刻停止层138的材料和形成方法可与蚀刻停止层114的材料和形成方法相同或相似。介电层140的材料和形成方法可以与介电层116的材料和形成方法相同或相似。接着使用平坦化工艺以提供介电层140大致上平坦的顶面。平坦化工艺可包括化学机械抛光工艺、研磨工艺、蚀刻工艺、干式抛光工艺、一或多种其他适用的工艺或前述的组合。
如图1M所示，根据一些实施例，形成接触开口142以暴露金属栅极堆叠126A和126B。接触开口142穿透介电层140、蚀刻停止层138以及保护元件134A和134B。可使用一或多种微影工艺和一或多种蚀刻工艺来形成接触开口142。在一些实施例中，可能发生覆盖偏移，使得栅极介电层120被导电开口142暴露。
在用于形成接触开口142的蚀刻工艺期间，间隔元件110被栅极介电层120保护，防止蚀刻剂穿透间隔元件110而到达导电接点136A及/或136B。导电接点136A和136B被栅极介电层120、间隔元件110和蚀刻停止层114保护，而未被接触开口142所暴露。防止在接触开口142中于导电接点136A(或136B)与其他导电结构之间形成短路。
如图1N所示，根据一些实施例，在接触开口142中形成导电接点144A和144B。导电接点144A和144B分别形成到金属栅极堆叠126A和126B的电性连接。导电接点144A和144B可包括钨、钌、钴、铜、铝、金、一或多种其他适合的材料或前述的组合或由前述材料制成。由于栅极介电层120的保护，防止导电接点144A、144B以及导电接点136A、136B一起产生短路。
在一些实施例中，在由图1M所示的接触开口142暴露的金属栅极堆叠126A和126B的表面上形成金属半导体化合物区(例如金属硅化物区)。可沿着接触开口142的侧壁形成阻障层或阻障区。然后，沉积导电材料以过度填充接触开口142。执行平坦化工艺以去除位于接触开口142之外的导电材料的部分。如此一来，接触孔142内部的导电材料的剩余部分形成导电接点144A和144B。
图3A至图3B示出根据一些实施例的形成半导体装置结构的工艺的不同阶段的剖视图。如图3A所示，接收或形成与图1I所示的结构相似的结构。在一些实施例中，即使由于低的操作温度及/或增加含氧气体而显著提高功函数层122对栅极介电层的蚀刻选择性，在回蚀刻工艺期间也会微幅蚀刻栅极介电层120。
如图3A所示，间隔元件110的顶部相较于栅极介电层120的顶部高出一高度差H1。栅极介电层120的顶部相较于功函数层122的顶部高出一高度差H2。由于栅极介电层120具有慢的蚀刻速率，因此高度差H1小于高度差H2。在一些实施例中，高度差H1与高度差H2的比值(H1/H2)小于约1/14。在某些情况下，如果比值(H1/H2)大于1/14，则高度差H1可能会太大。如此一来，栅极介电层120可能无法为间隔元件110提供足够的保护。
之后，根据一些实施例，执行与图1J-图1L所示的工艺相同或相似的工艺。如此一来，形成图3B所示的结构。
在一些实施例中，导电接点144A与栅极介电层120直接接触。在一些实施例中，导电接点144A与间隔元件110直接接触。由于仅微幅蚀刻栅极介电层120，故间隔元件110的暴露面积是小的。栅极介电层120仍为隔离元件110提供足够的保护，防止隔离元件110受损，且确保导电接点144A和112A之间的电性隔离。保持半导体装置结构的性能和可靠性。
本公开的实施例涉及用于形成金属栅极堆叠的栅极替换工艺。金属栅极堆叠包括栅极介电层和功函数层。接着，回蚀刻金属栅极堆叠以形成用于容纳保护元件的空间。在低温下执行回蚀刻工艺以确保功函数层对栅极介电层的高蚀刻选择性。栅极介电层大致上未被蚀刻或被微幅地蚀刻。栅极介电层能够保护位于金属栅极堆叠旁的间隔元件，以持续进行用于形成接触开口至金属栅极堆叠的后续蚀刻工艺，大幅地提高半导体装置结构的性能和可靠性。
根据一些实施例，提供一种半导体装置结构的制造方法。前述方法包括：在半导体基底上方形成虚设栅极堆叠，以及在前述虚设栅极堆叠的侧壁上方形成多个间隔元件。前述方法亦包括移除前述虚设栅极堆叠以在前述间隔元件之间形成凹槽，以及在前述凹槽中形成金属栅极堆叠。前述方法还包括在前述金属栅极堆叠保持在温度介于约20℃至约55℃的范围内时，回蚀刻前述金属栅极堆叠。此外，前述方法包括在回蚀刻前述金属栅极堆叠之后，在前述金属栅极堆叠上方形成保护元件。
在一些实施例中，前述温度介于约45℃至约50℃的范围内。
在一些实施例中，利用干式蚀刻工艺回蚀刻前述金属栅极堆叠。
在一些实施例中，在前述干式蚀刻工艺中使用的反应气体混合物包括第一含卤素气体、第二含卤素气体以及惰性气体，第一含卤素气体具有第一分子量，第二含卤素气体具有第二分子量，且第二分子量大于第一分子量。
在一些实施例中，前述第一含卤素气体包括氯气、氟气或前述的组合。
在一些实施例中，前述第二含卤素气体包括三氯化硼、四氯化硅或前述的组合。
在一些实施例中，在前述干式蚀刻工艺中使用的反应气体混合物还包括含氧气体。
在一些实施例中，前述含氧气体包括氧气、臭氧、一氧化氮、二氧化氮或前述的组合。
在一些实施例中，以第一流率提供前述含氧气体，以第二流率提供前述第二含卤素气体，且前述第一流率和第二流率的比值介于约0.05至约0.6的范围内。
在一些实施例中，前述方法还包括激发前述反应气体混合物以产生等离子体。
本公开实施例提供一种半导体装置结构的制造方法，包括：在鳍结构上方形成金属栅极堆叠。在前述金属栅极堆叠保持在温度介于约20℃至约55℃的范围内时，利用蚀刻工艺移除前述金属栅极堆叠的上部。在前述蚀刻工艺中使用的反应气体混合物包括第一含卤素气体以及第二含卤素气体，第一含卤素气体具有第一分子量，第二含卤素气体具有第二分子量，且第二分子量大于第一分子量。以第一流率提供前述第一含卤素气体，以第二流率提供前述第二含卤素气体，且第一流率大于第二流率。在移除前述金属栅极堆叠的上部之后，在前述金属栅极堆叠上方形成保护元件。
在一些实施例中，前述反应气体混合物还包括含氧气体。
在一些实施例中，前述第二含卤素气体包括三氯化硼。
在一些实施例中，前述含氧气体包括氧气。
在一些实施例中，以第三流率提供前述含氧气体，且前述第三流率和第二流率的比值介于约0.05至约0.6的范围内。
本公开实施例提供一种半导体装置结构，包括：半导体基底、金属栅极堆叠以及间隔元件。金属栅极堆叠位于半导体基底上方，其中前述金属栅极堆叠包括栅极介电层以及位于前述栅极介电层上方的功函数层。间隔元件位于前述金属栅极堆叠的侧壁上方，其中前述间隔元件的顶部相较于前述栅极介电层的顶部高出一第一高度差，前述栅极介电层的顶部相较于前述功函数层的顶部高出一第二高度差，且前述第一高度差和第二高度差的比值小于约1/14。
在一些实施例中，前述半导体装置结构还包括保护元件，位于前述金属栅极堆叠上方。
在一些实施例中，前述间隔元件沿前述保护元件的侧壁延伸。
在一些实施例中，前述半导体装置结构还包括导电接点，穿透前述保护元件且与前述金属栅极堆叠电性接触。
在一些实施例中，前述导电接点与前述栅极介电层直接接触。
以上概述了许多实施例的特征，使本公开所属技术领域中技术人员可以更加理解本公开的各实施例。本公开所属技术领域中技术人员应可理解，可以本公开实施例为基础轻易地设计或改变其他工艺及结构，以实现与在此介绍的实施例相同的目的及/或达到与在此介绍的实施例相同的优点。本公开所属技术领域中技术人员也应了解，这些相等的结构并未背离本公开的构思与范围。在不背离后附权利要求的构思与范围的前提下，可对本公开实施例进行各种改变、置换及变动。

Claims (1)

1.一种半导体装置结构的制造方法，包括：
在一半导体基底上方形成一虚设栅极堆叠；
在该虚设栅极堆叠的多个侧壁上方形成多个间隔元件；
移除该虚设栅极堆叠以在该等间隔元件之间形成一凹槽；
在该凹槽中形成一金属栅极堆叠；
在该金属栅极堆叠保持在温度介于约20℃至约55℃的范围内时，回蚀刻该金属栅极堆叠；以及
在回蚀刻该金属栅极堆叠之后，在该金属栅极堆叠上方形成一保护元件。
CN202010406637.6A 2019-05-30 2020-05-14 半导体装置结构的制造方法 Pending CN112018036A (zh)

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Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130181265A1 (en) * 2012-01-18 2013-07-18 Globalfoundries Inc. Methods of Forming a Gate Cap Layer Above a Replacement Gate Structure and a Semiconductor Device That Includes Such a Gate Structure and Cap Layer
US8896030B2 (en) * 2012-09-07 2014-11-25 Intel Corporation Integrated circuits with selective gate electrode recess
US9202691B2 (en) * 2013-01-18 2015-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having modified profile metal gate
US9306032B2 (en) * 2013-10-25 2016-04-05 United Microelectronics Corp. Method of forming self-aligned metal gate structure in a replacement gate process using tapered interlayer dielectric
KR102271239B1 (ko) * 2015-03-23 2021-06-29 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US10411113B2 (en) * 2015-05-22 2019-09-10 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure
US9450099B1 (en) * 2015-06-18 2016-09-20 Taiwan Semiconductor Manufacturing Co., Ltd Structure and formation method of semiconductor device structure
US9614089B2 (en) * 2015-06-15 2017-04-04 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure
US10008574B2 (en) * 2015-11-30 2018-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. Gate structure and method of fabricating the same
US10134872B2 (en) * 2015-12-28 2018-11-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
US9779997B2 (en) * 2015-12-31 2017-10-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
US9847398B1 (en) * 2016-07-13 2017-12-19 United Microelectronics Corp. Semiconductor device with gate structure having dielectric layer on one side and contact plug on the other side
US10121873B2 (en) * 2016-07-29 2018-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate and contact plug design and method forming same
US9859165B1 (en) * 2016-07-29 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Planarization process for forming semiconductor device structure
US9929271B2 (en) * 2016-08-03 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
CN107808849B (zh) * 2016-09-08 2021-07-13 联华电子股份有限公司 半导体元件及其制作方法
US10229983B1 (en) * 2017-11-16 2019-03-12 International Business Machines Corporation Methods and structures for forming field-effect transistors (FETs) with low-k spacers
US10505045B2 (en) * 2017-11-24 2019-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device structure with conductive layer between gate and gate contact
KR102593708B1 (ko) * 2018-08-14 2023-10-26 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법

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