CN106104770A - 层叠半导体集成电路装置 - Google Patents

层叠半导体集成电路装置 Download PDF

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Publication number
CN106104770A
CN106104770A CN201480077088.5A CN201480077088A CN106104770A CN 106104770 A CN106104770 A CN 106104770A CN 201480077088 A CN201480077088 A CN 201480077088A CN 106104770 A CN106104770 A CN 106104770A
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semiconductor
semiconductor regions
semiconductor substrate
integrated circuit
circuit device
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CN201480077088.5A
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CN106104770B (zh
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黑田忠广
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Crystal Electronics Japan Japan
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Crystal Electronics Japan Japan
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Abstract

涉及层叠半导体集成电路装置，通过廉价的结构缩小用于层叠的三维空间，并且提供足够的电源质量。在第1半导体集成电路装置上设置在厚度方向上贯通第1半导体基体并且与第1电源电位连接的第1贯通半导体区域，以及与第2电源电位连接的第2贯通半导体区域，层叠第2半导体集成电路装置，该第2半导体集成电路装置具有分别与第1贯通半导体区域和第2贯通半导体区域连接的第1电极和第2电极。

Description

层叠半导体集成电路装置
技术领域
本发明涉及层叠半导体集成电路装置，涉及用于提供层叠的半导体芯片间的电源电位的构造。
背景技术
近年来，要求三维地层叠芯片而提高了集成度的集成电路。例如，如果层叠存储器芯片，则能够增加存储器容量，能够降低数据转送所需要的消耗电力。作为这样的在层叠的芯片之间对信号和电源进行连接的技术，已知利用引线接合进行的连接、利用带式自动接合(Tape Automated Bonding；TAB)进行的连接、或者利用硅贯通电极(Through SiliconVia；TSV)进行的连接等。
这其中，在引线接合中，为了不堵塞接合用的电源用焊盘开口部而必须使芯片偏移并进行层叠，因此，存在安装容积较大的问题。此外，每1根接合线的电流容量较小，接合线根数也存在上限，因此，存在无法得到足够的电源质量的问题。
此外，在TAB中，与引线接合相比，电流容量较大，在芯片的周边以外也能够配置电源用焊盘，但是，TAB需要用于在层叠芯片间通过的较大的间隙，存在层叠方向的芯片间节距变大的问题。
与此相对，TSV具有能够解决全部这样的课题的优点。并且，不仅能够在单片芯片的情况下使用，还能够在层叠晶片而进行连接的情况下使用，还具有能够提高制造效率(吞吐量)的优点。然而，需要进行用于在硅基板上开孔，在孔的内壁面上形成绝缘膜，填充电极，对电极进行凸块连接的追加工序，因此，存在制造成本提高的课题。
另一方面，本发明人提出了使用通过半导体集成电路芯片的布线而形成的线圈的电感耦合，在所层叠的芯片中进行无线数据通信的电子电路，与数据连接相关地解决了上述的问题(例如，参照专利文献1或专利文献2)。
例如，如果使用专利文献1所示的发明，则能够在所层叠的芯片间使用线圈对的电感耦合来进行无线数据通信。此外，如果使用专利文献2所示的发明，则能够对同一芯片进行层叠安装，在芯片间进行无线数据通信，并且能够使用引线接合来提供电源。
现有技术文献
专利文献
专利文献1：日本特开2005-228981号公报
专利文献2：国际公开公报WO2009/069532
非专利文献
非专利文献1：http：//www.disco.co.jp/jp/solution/apexp/polisher/gettering.html
非专利文献2：Y.S.Kim et.al.、IEDM Tech.Dig.、vol.365(2009)
非专利文献3：N.Maeda et al.、Symp.VLSI Tech.Dig.、vol.105(2010)
非专利文献4：N.Maeda et al.、Symp.VLSI Tech.Dig.、vol.105(2010)
发明内容
发明要解决的问题
然而，TSV虽然能够解决上述的技术课题，但是，制造成本提高，因此，现在未在实际的生产线中采用。
因此，本发明的目的在于，通过廉价的结构缩小层叠用的三维空间，并且提供足够的电源质量。
用于解决问题的手段
(1)为了解决上述的课题，本发明的特征在于，在层叠半导体集成电路装置中，至少具有第1半导体集成电路装置和第2半导体集成电路装置，该第1半导体集成电路装置具有：第1半导体基体；第1n型半导体区域，其设于所述第1半导体基体，设置有包括晶体管在内的元件；第1p型半导体区域，其设于所述第1半导体基体，设置有包括晶体管在内的元件；第1贯通半导体区域，其在厚度方向上贯通所述第1半导体基体，并且与第1电源电位连接；第2贯通半导体区域，其在厚度方向上贯通所述第1半导体基体，并且与第2电源电位连接，该第2半导体集成电路装置与所述第1半导体集成电路装置形成层叠构造，具有：与第1贯通半导体区域电连接的第1电极；以及与所述第2贯通半导体区域连接的第2电极。
这样，代替制造成本较高的TSV，通过使用高杂质浓度的贯通半导体区域，能够不使芯片偏移而进行层叠，能够提高足够的电源质量，并且，能够减小层叠方向上的芯片间节距。
(2)此外，本发明的特征在于，在上述(1)中，所述第2半导体集成电路装置具有：第2半导体基体；第2n型半导体区域，其设于所述第2半导体基体，设置有包括晶体管在内的元件；第2p型半导体区域，其设于所述第2半导体基体，设置有包括晶体管在内的元件；第3贯通半导体区域，其在厚度方向上贯通所述第2半导体基体，并且与所述第1电源电位连接；以及第4贯通半导体区域，其在厚度方向上贯通所述第2半导体基体，并且与所述第2电源电位连接，在所述第3贯通半导体区域上设有所述第1电极，在所述第4贯通半导体区域上设有所述第2电极。
这样，在第2半导体集成电路装置上还设有贯通半导体区域，从而能够实现3个以上的芯片的层叠。
(3)此外，本发明的特征在于，在上述(2)中，所述第1半导体集成电路装置的元件配置与所述第2半导体集成电路装置的元件配置相同。这样，通过使各半导体集成电路装置的元件配置相同，例如能够廉价地实现大容量的存储器装置。
(4)此外，本发明的特征在于，在上述(2)中，使所述第1半导体集成电路装置的元件配置与所述第2半导体集成电路装置的元件配置不同。这样，通过使各半导体集成电路装置的元件配置不同，例如能够廉价地实现存储器和逻辑电路等混合而成的多功能半导体装置。
(5)此外，本发明的特征在于，在上述(1)至(4)中的任意一项中，层叠有多片所述第1半导体集成电路装置。通过这样的层叠构造，例如能够实现将第1半导体集成电路装置作为非易失性存储器、第2半导体集成电路装置作为控制器芯片的层叠半导体集成电路装置。
(6)此外，本发明的特征在于，在上述(1)至(5)中的任意一项中，所述第1贯通半导体区域和所述第2贯通半导体区域的电阻值为3mΩ以下。这样，通过使贯通半导体区域的电阻值为3mΩ以下，与使用Au线的情况相比，能够使电源布线的电阻值降低1个位数的电阻值。为了实现这样的电阻值，将贯通半导体区域的杂质浓度设为高浓度并且增大贯通半导体区域的平面面积即可。
(7)此外，本发明的特征在于，在上述(1)至(5)中的任意一项中，所述第1半导体基体的厚度为10μm以下。这样，通过将第1半导体基体的厚度设为10μm以下，能够使用当前的离子注入装置来保证足够的电源质量。
(8)此外，本发明的特征在于，在上述(7)中，所述第1半导体基体的厚度为5μm以下。这样，通过使半导体基板的厚度薄层化为5μm以下，即使使用当前普及类型的离子注入装置，也能够形成可保证足够的电源质量的贯通半导体区域。
(9)此外，本发明的特征在于，在上述(1)至(8)中的任意一项中，所述第1贯通半导体区域与所述第1半导体基体是相同导电型，所述第2贯通半导体区域与所述第1半导体基体是相反导电型。通过设为这样的导电型的组合，能够防止第1贯通半导体区域和第2贯通半导体区域的短路。
(10)此外，本发明的特征在于，上述(1)至(8)中的任意一项中，所述第1贯通半导体区域及所述第2贯通半导体区域与所述第1半导体基体是相同导电型，所述第2贯通半导体区域通过相反导电型层而与所述第1半导体基体电分离。这样，通过设置相反导电型层，能够使用相同的导电型的贯通半导体区域，将一方与第1电源电位(VSS)连接，将另一方与第2电源电位(VDD)连接。
(11)此外，本发明的特征在于，上述(1)至(10)中的任意一项中，所述第1p型半导体区域或所述第1n型半导体区域内的与所述第1半导体基体为相同导电型的半导体区域通过相反导电型分离层而与所述第1半导体基体电分离，并且，所述相反导电型分离层从所述第1半导体基体的背面露出。这样，在使一方的半导体区域在相反导电型区域、即深阱区域中从半导体基板电分离的情况下，深阱区域也可以从第1半导体基体的背面露出。
(12)此外，本发明的特征在于，在上述(1)至(11)中，所述第1半导体集成电路装置和所述第2半导体集積装置具有进行信号的收发的线圈。这样，期望在信号的收发中使用利用了线圈的电感耦合。即，在使用贯通半导体区域作为信号线的情况下，由于通过该电阻值而引起的信号延迟，不可能进行高速数据通信，因此，使用不需要电信号线的线圈实现的电感耦合数据通信是最合适的。
(13)此外，本发明的特征在于，在上述(12)中，所述第1半导体集成电路装置具有与所述第1半导体基体为相反导电型的信号用贯通半导体区域、和与所述第1半导体基体为相同导电型的信号用贯通半导体区域中的至少一方，其中，与所述第1半导体基体为相同导电型的信号用贯通半导体区域通过与所述第1半导体基体为相反导电型的分离层而被分离。在芯片选择信号等低速信号的情况下，能够将贯通半导体区域用作信号用区域。另外，该情况下，为了在信号成为高电平的情况下，在与第1半导体基体之间不流过漏电流，需要将信号用贯通半导体区域设为与第1半导体基体为相反导电型的贯通半导体区域、或者通过与第1半导体基体为相反导电型的分离层而分离的与第1半导体基体为相同导电型的贯通半导体区域。
(14)此外，本发明的特征在于，在上述(13)中，在所述信号用贯通半导体层中传播的信号的频率为100MHz以下。这样，在100MHz以下的低速的信号，特别是芯片选择信号等10MHz以下的低速信号的情况下，能够充分传播信号。
(15)此外，本发明的特征在于，在上述(13)或(14)中，所述第2半导体集成电路装置具有与所述第2半导体基体为相反导电型的信号用贯通半导体区域或与所述第2半导体基体为相同导电型的信号用贯通半导体区域中的至少一方，其中，与所述第2半导体基体为相同导电型的信号用贯通半导体区域通过与所述第2半导体基体为相反导电型的分离层而被分离，从层叠方向观察时，所述第1半导体基体上设置的信号用贯通半导体区域和所述第2半导体基体上设置的信号用半导体区域重叠。这样，通过设置成从层叠方向观察时，第1半导体基体上设置的信号用贯通半导体区域和第2半导体基体上设置的信号用半导体区域重叠，从而在连接两者时不需要连接布线。
发明的效果
如果使用公开的层叠半导体集成电路装置，则能够通过廉价的结构缩小层叠用的三维空间，并且提供足够的电源质量。
附图说明
图1是本发明的实施方式的层叠半导体集成电路装置的概略的剖视图。
图2是本发明的实施方式的层叠半导体集成电路装置中的贯通半导体区域的配置例的说明图。
图3是退火后的杂质浓度分布图。
图4是电阻值的基板厚度依存性的说明图。
图5是本发明的实施例1的层叠半导体集成电路装置的到中途为止的制造工序的说明图。
图6是本发明的实施例1的层叠半导体集成电路装置的图5以后的到中途为止的制造工序的说明图。
图7是本发明的实施例1的层叠半导体集成电路装置的图6以后的到中途为止的制造工序的说明图。
图8是本发明的实施例1的层叠半导体集成电路装置的图7以后的到中途为止的制造工序的说明图。
图9是本发明的实施例1的层叠半导体集成电路装置的图8以后的到中途为止的制造工序的说明图。
图10是本发明的实施例1的层叠半导体集成电路装置的图9以后的制造工序的说明图。
图11是本发明的实施例2的层叠半导体集成电路装置的概略的剖视图。
图12是本发明的实施例3的层叠半导体集成电路装置的概略的剖视图。
图13是本发明的实施例4的层叠半导体集成电路装置的到中途为止的制造工序的说明图。
图14是本发明的实施例4的层叠半导体集成电路装置的图13以后的到中途为止的制造工序的说明图。
图15是本发明的实施例4的层叠半导体集成电路装置的图14以后的制造工序的说明图。
图16是本发明的实施例5的层叠半导体集成电路装置的到中途为止的制造工序的说明图。
图17是本发明的实施例5的层叠半导体集成电路装置的图16以后的到中途为止的制造工序的说明图。
图18是本发明的实施例5的层叠半导体集成电路装置的图17以后的制造工序的说明图。
图19是本发明的实施例6的层叠半导体集成电路装置的概略的剖视图。
图20是本发明的实施例7的层叠半导体集成电路装置的到中途为止的制造工序的说明图。
图21是本发明的实施例7的层叠半导体集成电路装置的图20以后的到中途为止的制造工序的说明图。
图22是本发明的实施例7的层叠半导体集成电路装置的图21以后的制造工序的说明图。
图23是本发明的实施例8的层叠半导体集成电路装置的到中途为止的制造工序的说明图。
图24是本发明的实施例8的层叠半导体集成电路装置的图23以后的到中途为止的制造工序的说明图。
图25是本发明的实施例8的层叠半导体集成电路装置的图24以后的制造工序的说明图。
图26是本发明的实施例9的层叠半导体集成电路装置的概略的剖视图。
图27是本发明的实施例10的层叠半导体集成电路装置的概略的剖视图。
图28是本发明的实施例11的层叠半导体集成电路装置的到中途为止的制造工序的说明图。
图29是本发明的实施例11的层叠半导体集成电路装置的图28以后的到中途为止的制造工序的说明图。
图30是本发明的实施例11的层叠半导体集成电路装置的图29以后的制造工序的说明图。
图31是本发明的实施例12的层叠半导体集成电路装置的概略的剖视图。
图32是本发明的实施例13的层叠半导体集成电路装置的概略的剖视图。
具体实施方式
这里，参照图1至图4对本发明的实施方式的层叠半导体集成电路装置进行说明。图1是本发明的实施方式的层叠半导体集成电路装置的概略的剖视图，这里，示出了元件结构与第1半导体集成电路装置11相同的第2半导体集成电路装置12的2层层叠构造。
第1半导体集成电路装置11在第1半导体基体21上设有第1n型半导体区域31和第1p型半导体区域41，作为通常的半导体元件区域。这里，在第1半导体基体21上设有贯通第1半导体基体21的第1贯通半导体区域51和第2贯通半导体区域61作为电源布线。这样，通过将第1贯通半导体区域51和第2贯通半导体区域61作为电源布线，能够大幅降低制造成本。另外，“半导体基体(semiconductor body)”是指，半导体基板(semiconductor substrate)自身、半导体基板和在其上设置的外延生长层的层叠构造体，或者去除半导体基板后的外延生长层。
这里，第2半导体集成电路装置12也在第2半导体基体22上设有第2n型半导体区域32和第2p型半导体区域42，作为通常的半导体元件区域。此外，在第2半导体基体22上设有贯通第2半导体基体22的第3贯通半导体区域52和第4贯通半导体区域62作为电源布线。但是，第2半导体集成电路装置12不需要是与第1半导体集成电路装置11相同的构造，在用于层叠构造的最终级的情况下，第3贯通半导体区域52和第4贯通半导体区域62不一定是必需的。
图2是本发明的实施方式的层叠半导体集成电路装置中的贯通半导体区域的配置例的说明图。图2的(a)是在第1半导体基体21、即半导体芯片的一边设有第1贯通半导体区域51和第2贯通半导体区域61的例子。此外，图2的(b)是在第1半导体基体21的对置的2个边上分割设置第1贯通半导体区域51和第2贯通半导体区域61的例子。此外，图2的(c)是将第1贯通半导体区域51和第2贯通半导体区域61分割成微小区域而进行设置的例。无论哪种情况，通过确保规定的面积作为整体的平面积，能够设为足够低的布线电阻值。
将该情况下的布线电阻值，即贯通半导体区域的电阻值、和贯通半导体区域与接触电极的接触电阻的合计的电阻设为足够小，典型地设为3mΩ以下，由此，能够设为足够高的电源质量。另外，当设作为接合线的Au线的直径为25μmφ、长度为0.5mm、电阻率为2.21×10-8Ωm时，Au线的电阻值为20mΩ。因此，如果是3mΩ，则相比于以往的接合线的电阻足够低，能够得到足够高的电源质量。
但是，在贯通半导体区域中，即使将杂质浓度设为高浓度，与接合线、TAB或TSV中使用的金或铜的电阻率为2.21×10-8Ωm或1.68×10-8Ωm的情况相比，其电阻率高达4位数，例如是4.2×10-4Ωm。因此，为了实现相同的电阻值，需要使截面面积除以芯片厚度而得到的值为10000倍左右，因此，至今为止没有进行使用包含信号线的贯通电极这样的尝试。但是，仔细研究的结果为，发现例如在芯片的厚度为5μm、贯通半导体区域的图案尺寸为0.1mm×7mm的情况下，贯通半导体区域的垂直方向的电阻值为4.2×10-4[Ωm]＊5×10-6[m]/{0.1×10-3[m]＊7×10-3[m]}≒3mΩ，能够用于供电。
如上所述，用于实现3mΩ的电阻的贯通半导体区域的图案尺寸例如是0.1mm×7mm，截面面积是700000μm2。与TSV的截面面积为例如40μm×40μm(＝1600μm2)的情况相比，高出400倍以上。但是，仔细研究的结果为，发现存储器芯片通常一边是7mm以上，在NAND闪存的情况下长边是14mm以上，因此，能够比较廉价地配置2个左右的0.1mm×7mm的高浓度阱用于电源线。另外，通常，用作信号线的100根以上的布线在面积上来讲是不可能进行配置的，如果设为能够进行配置的小面积，则电阻值会变得非常高，信号大幅降低，因此，无法用作信号用布线。另外，这意味着，在芯片选择信号等100MHz以下的低速信号、例如芯片选择信号等10MHz以下的低速信号的情况下，能够将贯通半导体区域用作信号布线。
这里，问题是贯通半导体区域的杂质浓度和基板方向的厚度，因此，参照图3和图4来讨论基于贯通半导体区域的电源布线的可能性。图3是退火后的杂质浓度分布图，图3的(a)示出P的杂质浓度分布，图3的(b)示出B的杂质浓度分布。这里，示出了通过TCAD对贯通半导体区域的杂质分布(profile)进行模拟得到的结果。
该情况下的模拟的前提条件如下。半导体基板是p型高电阻基板(7Ωm)，表面氧化膜厚为10nm。关于杂质，n+为磷(P)，p+为硼(B)。关于剂量，调查了1×1016cm-2和1×1017cm-2这2种情况。离子注入能量为200keV。激活用的热处理条件是1050℃、50小时。
该情况下的条件与通常的集成器件的制造条件相比，除了以下2点以外是相同的。
1)扩散时间通常为10分钟以下。但是，如果在制造现有器件的处理之前进行高浓度阱的扩散，不会对现有器件的性能产生影响。
2)剂量通常为1×1015cm-2。但是，即使使用在通常的量产中使用的离子注入装置，也能够实现1×1016cm-2的剂量。此外，还存在能够实现1×1017cm-2的离子注入的制造装置。根据以上，模拟的条件基本与量产时的条件相同。此外，如上所述，贯通半导体区域的图案尺寸设为0.1mm×7mm。
根据图3可知，无论在磷的情况下还是在硼的情况下，如果提高剂量则高浓度区域变深。此外，可知相比于磷，硼会扩散，直到高浓度区域变深。另外，图中的虚线是离子刚刚注入后(as impla.)的分布。
图4是电阻值的基板厚度依存性的说明图，这里，是根据图3的结果计算改变基板的厚度时的贯通半导体区域的从正面电极到背面电极的电阻值的结果。这里，正面电极和背面电极为200nm厚的铝。关于各电极和高浓度贯通半导体区域的接合电阻，是作为考虑了硅的费米能级和铝的费米能级之差的欧姆接触而计算的，因此，在计算中反映了背面的杂质浓度和n型/p型导致的电阻值的差异。
根据图4可知，如果使半导体基体的厚度薄层化至5μm，则能够在n型杂质中使用磷，使用硼作为p型杂质，实现具有3mΩ的值的贯通半导体区域。此外可知，在将剂量增大1位数而设为1×1017cm-2的情况下，即使将半导体基体的厚度设为10μm，也能够实现3mΩ的电阻值的贯通半导体区域。
接着，对基板厚度对元件特性的影响进行讨论。半导体基体(不包括布线层)的厚度比作为现有器件的元件形成区域的N-well、P-well厚，但是，如上所述，与以往典型的厚度即40μm相比，需要设为非常薄的5μm或10μm。在这样的非常薄的半导体基体的情况下，担心如下的元件性能劣化：由于金属污染而使pn结泄漏增加等。
但是，近年来开发了如下技术：在研磨半导体基板的背面时产生微裂纹(细微的裂缝)，将该微裂纹作为吸除位点(gettering site)来捕获重金属杂质(吸除(gettering))(例如，参照非专利文献1)。其结果为，例如进行了如下的报告：即使使芯片的厚度薄至7μm，也不存在CMOS逻辑集成电路的性能劣化(例如，参照非专利文献2)。此外，存在如下报告：即使使芯片的厚度薄至9μm，也不存在FRAM(注册商标)存储器集成电路的性能劣化(例如，参照非专利文献3)。因此，即使将半导体基体的厚度设为10μm以下，也能够充分发挥元件性能。
以上，讨论了各种条件，但是，首次确认到：通过利用200keV左右的加速电压，以1×1016cm-2～1×1017cm-2的剂量将P和B的杂质注入到0.7mm2以上的面积，并将半导体基体的厚度设为10μm以下，从而能够将贯通半导体区域用作电源布线。另外，如上所述，由于不能采用贯通半导体区域作为信号线，因此，期望在信号的收发中使用利用了线圈的电感耦合数据通信。
另外，在进行半导体集成电路装置的层叠时，在支承基板上固定了第1半导体集成电路装置后，进行研磨而薄层化至2μm～10μm左右的厚度，在贯通半导体区域的露出面形成背面电极，接着，将相同元件构造或不同元件构造的第2半导体集成电路装置层叠成使得正面电极与第1半导体集成电路装置的背面电极接触即可。进而，在进行层叠的情况下，该第2半导体集成电路装置也通过研磨使得高杂质浓度区域成为贯通半导体区域即可。另外，由于贯通半导体区域是高杂质浓度区域，因此，接触电极和背面电极也可以是Al或Cu。例如，在层叠中途的芯片不需要焊盘，因此，也可以在由Cu形成的多层布线的最上层形成有正面电极。另外，为了取得良好的欧姆接合，也可以采用由接触层(TiN、TaN)/阻挡层(TiW、TaN)/金属构成的层叠结构。或者，既可以以使得正面电极彼此相面对的方式进行层叠，也可以使背面电极彼此相面对而进行层叠。进而，当形成背面电极时成本提高，因此，也可以不形成背面电极，而是以在使高杂质浓度的贯通半导体区域露出的状态下与另一方的半导体集成电路装置的正面电极抵接的方式进行层叠。另外，杂质扩散的深度与热处理时间的大致平方根成比例。因此，例如，在从5μm薄层化至一半即2.5μm的情况下，热处理时间为(2.5μm/5μm)2＝1/4，能够缩短至50小时×1/4＝12.5小时。
另外，在使半导体基体薄层化后，还考虑从半导体基体的背面进行离子注入而进一步降低贯通半导体区域的电阻。但是，是形成元件区域后的工序，为了激活而退火很可能对元件的特性产生不好的影响，因此是不期望的。
这样的层叠工序也可以在晶片的阶段进行，或者，也可以在芯片化后进行。进而，作为晶片，也可以使用通过KGD(Known Good Die：已知合格之晶片)重建的晶片。即，在晶片上进行测试而找到合格芯片，进行芯片分选而切出芯片单片，舍弃不合格芯片而仅将合格芯片重新在晶片形状的支承基板上排列，并用粘接剂进行固定，重建为晶片即可。
实施例1
接着，参照图5至图10对本发明的实施例1的层叠半导体集成电路装置进行说明，这里，说明层叠3片相同的存储器芯片的例子。首先，如图5的(a)所示，在p-型Si基板21上以200keV的加速能量并以1×1016cm-2的剂量对B进行离子注入，形成0.1mm×7mm的尺寸的p++型阱区域22，接着，以200keV的加速能量并以1×1016cm-2的剂量对P进行离子注入，形成0.1mm×7mm的尺寸的n++型阱区域23。接着，在1050℃下进行50小时热处理，从而将所注入的离子激活，并且，在基板厚度方向上较深地扩散。另外，如果需要，将由于热处理而在基板表面附着的氧化膜消除。
接着，如图5的(b)所示，与以往的制造工序同样，在p-型Si基板21上形成作为元件形成区域的p型阱区域24和n型阱区域25。接着，在p型阱区域24上形成p+型基板接触区域26，并且形成作为源极区域、漏极区域等的n型区域27，通过设置栅极电极(省略图示)形成了n通道MOSFET。另一方面，在n型阱区域25上形成n+型基板接触区域28，并且形成作为源极区域、漏极区域等的p型区域29，通过设置栅极电极(省略图示)形成了p通道MOSFET。
接着，如图5的(c)所示，在p++型阱区域22和n++型阱区域23的表面形成由Cu构成的接触电极30、31，并且，使用多层布线技术形成布线层33、34。接着，形成与接触电极30连接的由Al或Cu构成的正面电极36以及与接触电极31连接的由Al或Cu构成的正面电极37。此时，利用多层布线形成用于电感耦合数据通信的线圈(省略图示)。此外，对表面进行研磨以使其平坦化。另外，图中的标号32、35是由SiO2构成的层间绝缘膜。
接着，如图6的(d)所示，形成有正面电极36、37的面以抵接的方式与在Si基板构成的支承基板50上暂时接合。接着，如图6的(e)所示，在磨削至规定的厚度后，使用化学机械研磨(CMP)法进行研磨，以使得p-型Si基板21的厚度成为5μm。
接着，如图7的(f)所示，在研磨面形成SiO2保护膜38后，形成露出p++型阱区域22和n++型阱区域23的开口，通过Al或Cu形成背面电极39、40。另外，此时也进行研磨，以使表面平坦化。
接着，如图7的(g)所示，对利用到图5的(c)为止的工序制作的其他半导体晶片进行层叠。此时，以使得第一级的半导体集成电路装置的背面电极39、40与第二级的半导体集成电路装置的正面电极36、37抵接的方式进行层叠。此时的接合是通过金属间的金属表面激活后的常温加压接合，即基于金属间扩散的固相接合而进行的。
接着，如图8的(h)所示，在将第二级的p-型Si基板21磨削至规定的厚度后，使用化学机械研磨法进行研磨，使得p-型Si基板21的厚度成为5μm。
接着，如图8的(i)所示，再次在研磨面上形成SiO2保护膜38后，形成露出p++型阱区域22和n++型阱区域23的开口，通过Al或Cu形成背面电极39、40。另外，此时也进行研磨，以使表面平坦化。
接着，如图9的(j)所示，再次对利用到图5的(c)为止的工序制作的其他半导体晶片进行层叠。此时，也以使得第二级的半导体集成电路装置的背面电极39、40与第三级的半导体集成电路装置的正面电极36、37抵接的方式进行层叠。此时的接合也是通过金属间的金属表面激活后的常温加压接合，即基于金属间扩散的固相接合而进行的。
接着，如图10的(k)所示，将层叠的晶片从支承基板50取下，分割成规定的尺寸的芯片后，使用粘接剂63将其固定在封装基板60上。接着，利用接合线64将施加VSS的电源用焊盘61和与p++型阱区域22连接的正面电极36连接。另一方面，通过利用接合线65将施加VDD的电源用焊盘62和与n++型阱区域23连接的正面电极37连接，从而完成本发明的实施例1的层叠半导体集成电路装置的基本构造。另外，根据处理的容易性和确保机械强度的观点，不期望使第三级的p-型Si基板薄层化。
这样，在本发明的实施例1中，使用了以往不会想到作为贯通布线的高杂质浓度阱区域，来作为层叠半导体集成电路装置的电源布线，因此，能够廉价地实现足够的电源质量的电源布线。此外，与TSV同样，在进行层叠时，不需要使芯片偏移，此外，不需要在芯片间插入TAB等，因此，能够进一步缩小三维的尺寸。
实施例2
接着，参照图11对本发明的实施例2的层叠半导体集成电路装置进行说明，基本的制造工序和构造与上述的实施例1同样，因此仅示出最终构造。图11是本发明的实施例2的层叠半导体集成电路装置的概略的剖视图，在最终级(图中为最下层的第三级)的半导体集成电路装置上没有形成高杂质阱区域，因此，其以外的结构与上述的实施例1同样。
这样，最终级的芯片由于不需要向次级传递电源，因此，不需要高杂质阱区域。因此，在层叠特性不同的芯片的情况下，在最终级配置特性不同的芯片，由此，构成最终级的芯片不需要高杂质阱区域的形成工序，因此，能够降低制造成本。
实施例3
接着，参照图12对本发明的实施例3的层叠半导体集成电路装置进行说明，基本的制造工序和构造与上述的实施例1同样，因此仅示出最终构造。图12是本发明的实施例3的层叠半导体集成电路装置的概略的剖视图，在芯片间的接合中，代替常温加压接合而使用微凸块66，因此，其以外的结构与上述的实施例1同样。
这样，通过在芯片间的接合中使用微凸块66，能够进一步强固芯片间的电气结合和机械结合。
实施例4
接着，参照图13至图15对本发明的实施例4的层叠半导体集成电路装置进行说明，该实施例4中，使用相同的导电型的p++型阱区域作为VSS用和VDD用的电源布线。首先，如图13的(a)所示，在p-型Si基板21中以200keV的加速能量并以1×1016cm-2的剂量对B进行离子注入，形成0.1mm×7mm的尺寸的p++型阱区域22、41。
接着，如图13的(b)所示，以200keV的加速能量并以1×1016cm-2的剂量对P进行离子注入，以包围p++型阱区域41的外侧的方式形成n++型分离区域42。接着，在1050℃下进行50小时热处理，从而将所注入的离子激活，并且，在基板厚度方向上较深地扩散。另外，如果需要，将由于热处理而在基板表面附着的氧化膜消除。
接着，如图13的(c)所示，与以往的制造工序同样，在p-型Si基板21上形成作为元件形成区域的p型阱区域24和n型阱区域25。接着，在p型阱区域24上形成p+型基板接触区域26，并且形成作为n通道MOSFET的源极区域、漏极区域等的n型区域27，通过设置栅极电极(省略图示)形成了n通道MOSFET。另一方面，在n型阱区域25上形成n+型基板接触区域28，并且形成作为源极区域、漏极区域等的p型区域29，通过设置栅极电极(省略图示)形成了p通道MOSFET。
接着，如图14的(d)所示，与上述的实施例1同样，在p++型阱区域22和p++型阱区域41的表面形成由Cu构成的接触电极30、31，并且，使用多层布线技术形成布线层33、34。接着，形成与接触电极30连接的由Al或Cu构成的正面电极36以及与接触电极31连接的由Al或Cu构成的正面电极37。此时，也利用多层布线形成用于电感耦合数据通信的线圈(省略图示)。此外，对表面进行研磨以使其平坦化。另外，图中的标号32、35是由SiO2构成的层间绝缘膜。
接着，如图14的(e)所示，形成有正面电极36、37的面以抵接的方式在由Si基板构成的支承基板50上暂时接合。接着，在磨削至规定的厚度后，使用化学机械研磨法进行研磨，以使得p-型Si基板21的厚度成为5μm。
接着，如图14的(f)所示，在研磨面形成SiO2保护膜38后，形成露出p++型阱区域22和p++型阱区域41的开口，通过Al或Cu形成背面电极39、40。另外，此时也进行研磨，以使表面平坦化。以后，依次进行上述的实施例1的图7的(g)至图10的(k)的工序，从而得到图15的最终构造。
在该实施例4中，通过n++型分离区域42将p++型阱区域41从p-型Si基板电分离，因此，在VSS用和VDD用的电源布线中使用了p++型阱区域22、41，其中，该p++型阱区域22、41在到达比磷深的位置使用了作为低电阻的硼，所以，能够进一步降低电源布线的电阻。或者，在芯片厚度加厚成6μm左右的情况下，也能够实现3mΩ的相同的电源布线的电阻。
实施例5
接着，参照图16至图18对本发明的实施例5的层叠半导体集成电路装置进行说明，该实施例5除了利用n型深阱区域覆盖作为元件形成区域的p型阱区域以外，与上述的实施例1基本相同。首先，如图16的(a)所示，与上述的实施例1同样，在p-型Si基板21上以200keV的加速能量并以1×1016cm-2的剂量对B进行离子注入，形成0.1mm×7mm的尺寸的p++型阱区域22，接着，以200keV的加速能量并以1×1016cm-2的剂量对P进行离子注入，形成0.1mm×7mm的尺寸的n++型阱区域23。接着，在1050℃下进行50小时热处理，从而将所注入的离子激活，并且在基板厚度方向上较深地扩散。另外，如果需要，将由于热处理而在基板表面附着的氧化膜消除。
接着，如图16的(c)所示，与以往的制造工序同样，在p-型Si基板21上形成作为元件形成区域的p型阱区域24和n型阱区域25。但是，这里，预先形成包围p型阱区域24的n型深阱区域43，以使得将p型阱区域24从p-型Si基板21电分离。接着，在p型阱区域24上形成p+型基板接触区域26，通过设置栅极电极(省略图示)形成了n通道MOSFET。另一方面，在n型阱区域25上形成n+型基板接触区域28，并且，形成作为源极区域、漏极区域等的p型区域29，通过设置栅极电极(省略图示)形成了p通道MOSFET。
接着，如图16的(c)所示，与上述的实施例1同样，在p++型阱区域22和p++型阱区域41的表面形成由Cu构成的接触电极30、31，并且，使用多层布线技术形成布线层33、34，接着，形成与接触电极30连接的由Al或Cu构成的正面电极36以及与接触电极31连接的由Al或Cu构成的正面电极37。此时，利用多层布线形成用于电感耦合数据通信的线圈(省略图示)。此外，对表面进行研磨，以使其平坦化。另外，图中的标号32、35是由SiO2构成的层间绝缘膜。
接着，如图17的(d)所示，形成有正面电极36、37的面以抵接的方式在由Si基板构成的支承基板50上暂时接合。接着，如图17的(e)所示，在磨削至规定的厚度后，使用化学机械研磨法进行研磨，以使得p-型Si基板21的厚度成为3μm。此时，n型深阱区域43的底面从研磨面露出。以后，依次进行上述的实施例1的图7的(f)至图10的(k)的工序，从而得到图18的最终构造。
在该实施例5中，虽然研磨到更薄，直到n型深阱区域43的底面从研磨面露出，但是，由于作为元件形成区域的p型阱区域24不直接露出，因此，对元件特性的影响微小。
实施例6
接着，参照图19对本发明的实施例6的层叠半导体集成电路装置进行说明，该实施例6除了要层叠的半导体集成电路装置的种类不同的以外，与上述的实施例1同样，因此，仅说明最终的构造。图19是本发明的实施例6的层叠半导体集成电路装置的概略的剖视图，在上述的图9的工序中，在第3级层叠与第1级和第2级的存储器芯片不同的控制器芯片。
在该情况下的控制器芯片中，在p-型Si基板71上，在与存储器芯片设置的的p++型阱区域22相同的位置处设置p++型阱区域72，在与n++型阱区域23相同的位置处设置n++型阱区域73。接着，在p-型Si基板71上形成作为元件形成区域的p型阱区域74和n型阱区域75。接着，在p型阱区域74上形成p+型基板接触区域76，并且，形成作为源极区域、漏极区域等的n型区域77、78，通过设置栅极电极(省略图示)形成了n通道MOSFET。另一方面，在n型阱区域75上形成n+型基板接触区域79，并且形成作为源极区域、漏极区域等的p型区域80，通过设置栅极电极(省略图示)形成了p通道MOSFET。
接着，在p++型阱区域72和n++型阱区域73的表面形成由Cu构成的接触电极81、82，并且使用多层布线技术形成布线层84、85。接着，形成与接触电极81连接的由Al或Cu构成的正面电极87以及与接触电极82连接的由Al或Cu构成的正面电极88。
此时，利用多层布线形成用于电感耦合数据通信的通信用线圈92，但是，在进行了层叠的情况下，形成为使得成为与存储器芯片上设置的通信用线圈44相同的位置。此外，对表面进行研磨，以使其平坦化。另外，图中的标号83、86是由SiO2构成的层间绝缘膜。
接着，在封装基板60上使用粘接剂63固定用于形成控制器芯片的p-型Si基板71的背面。接着，利用接合线64将施加VSS的电源用焊盘61和与p++型阱区域22连接的正面电极36连接。另一方面，通过利用接合线65将施加VDD的电源用焊盘62和与n++型阱区域23连接的正面电极37连接，从而完成本发明的实施例6的层叠半导体集成电路装置的基本构造。
这样，本发明的实施例6中，通过一并使用薄层化技术和层叠化技术，能够紧凑并且廉价地实现层叠存储器芯片和对存储器芯片进行驱动控制的控制器芯片而得到的半导体存储装置。
实施例7
接着，参照图20至图22对本发明的实施例7的层叠半导体集成电路装置进行说明，在该实施例7中，通过对背面电极彼此进行金属接合，由此，实现了紧凑的固体摄像装置。首先，如图20的(a)所示，在控制器芯片上层叠存储器芯片，形成进行了薄层化后的层叠体。另外，虽然是控制器芯片和存储器芯片的组合，但是，薄层化工序和层叠工序本身与图5的(a)至图8的(i)的工序同样。
另一方面，如图20的(b)所示，在图像传感器芯片中，在p-型Si基板101上，在与存储器芯片上设置的p++型阱区域22相同的位置处设置p++型区域102，在与n++型阱区域23相同的位置处设置n++型阱区域103。接着，在p-型Si基板101上形成作为元件形成区域的p型阱区域104和n型阱区域105。接着，在p型阱区域104上形成p+型基板接触区域106，并且，将作为像素要素的n型区域107形成为矩阵阵列状。另一方面，在n型阱区域105上形成n+型基板接触区域108，并且形成作为源极区域、漏极区域等的p型区域109，通过设置栅极电极(省略图示)形成了p通道MOSFET。
接着，在p++型阱区域102和n++型阱区域103的表面形成由Cu构成的接触电极110、111，并且，使用多层布线技术形成布线层113、114。接着，形成与接触电极110连接的由Al或Cu构成的正面电极116以及与接触电极111连接的由Al或Cu构成的正面电极117。此时，利用多层布线形成用于电感耦合数据通信的通信用线圈。此外，对表面进行研磨，以使其平坦化。另外，图中的标号112、115是由SiO2构成的层间绝缘膜。
接着，在支承基板51上固定图像传感器芯片并使其薄层化，在研磨面上形成SiO2保护膜118后，形成露出p++型阱区域102和p++型阱区域103的开口，通过Al或Cu形成背面电极119、120。另外，此时也对表面进行研磨，以使其平坦化。
接着，如图21的(c)所示，以使得存储器芯片的背面电极39、40与图像传感器的背面电极119、120彼此抵接的方式进行层叠。此时的接合是通过金属间的金属表面激活后的常温加压接合、即基于金属间扩散的固相接合而进行的。
接着，如图22的(d)所示，将层叠的晶片从支承基板50、51取下，分割成规定的尺寸的芯片后，在封装基板60上，通过凸块68将控制器芯片的正面电极87、88熔接在电源用焊盘61、62上，由此，完成本发明的实施例7的层叠半导体集成电路装置的基本构造。此时，在封装基板60和控制器芯片之间填充底部填充树脂。另外，图中的标号67是信号用焊盘，通过凸块68与在控制器芯片的表面设置的焊盘(省略图示)连接。
在本发明的实施例7中，在对通过另外的工序形成的图像传感器进行薄层化后，使其他芯片与背面电极彼此金属接合而一体化，由此，能够以使得形成作为摄像面的像素的面成为表面的方式进行层叠，并且，由于进行了薄层化，由此，能够通过电感耦合数据通信进行各芯片间的信号的收发。此外，存储器芯片也进行一体化，并且具有高度的功能的控制器芯片也层叠而一体化，因此，能够紧凑并且廉价地实现高功能摄像装置。
实施例8
接着，参照图23至图25对本发明的实施例8的层叠半导体集成电路装置进行说明，在该实施例8中，在不使用引线接合的情况下实现具有与实施例6所示的半导体存储装置同等的功能的半导体存储装置。首先，如图23的(a)所示，与上述的图5的(a)至图7的(g)的工序同样，形成层叠了2片存储器芯片的层叠体。
另一方面，如图23的(b)所示，将控制器芯片固定在支承基板51上并进行了薄层化后，形成背面电极90、91。另外，控制器芯片的元件构造与图19所示的控制器芯片同样。
接着，如图24的(c)所示，取下支承基板50，以使得控制器芯片的背面电极90、91和存储器芯片的正面电极36、37彼此抵接的方式进行层叠。该情况下，由于p-型Si基板21足够厚，因此，能够实现取下支承基板50的状态下的层叠。此时的接合是通过金属间的金属表面激活后的常温加压接合、即基于金属间扩散的固相接合而进行的。
接着，如图25的(d)所示，将层叠的晶片从支承基板51取下，分割成规定的尺寸的芯片后，在封装基板60上，通过凸块68将控制器芯片的正面电极87、88熔接在电源用焊盘61、62上，由此，完成本发明的实施例8的层叠半导体集成电路装置的基本构造。此时，在封装基板60和控制器芯片之间填充底部填充树脂。另外，图中的标号67是信号用焊盘，通过凸块68与在控制器芯片的表面上设置的焊盘(省略图示)连接。
在本发明的实施例8中，不使用接合线，而是使用焊盘将控制器芯片与封装基板电连接，因此，不需要配置接合线的空间，能够更节省空间。
实施例9
接着，参照图26对本发明的实施例9的层叠半导体集成电路装置进行说明，在该实施例9中，在不使用引线接合的情况下形成具有与实施例1所示的存储器装置同等的功能的存储器装置。如图26所示，与上述的图5的(a)至图9的(j)的工序同样，形成层叠了3片存储器芯片的层叠体。
接着，将层叠的晶片从支承基板取下，分割成规定的尺寸的芯片后，在封装基板60上，通过凸块68将存储器芯片的正面电极36、37熔接在电源用焊盘61、62上，由此，完成本发明的实施例9的层叠半导体集成电路装置的基本构造。此时，在封装基板60和控制器芯片之间填充底部填充树脂。另外，图中的标号67是信号用焊盘，通过凸块68与在存储器芯片的表面上设置的焊盘(省略图示)连接。
在本发明的实施例9中，不使用接合线，而是使用焊盘将存储器芯片与封装基板电连接，因此，不需要配置接合线的空间，能够更节省空间。
实施例10
接着，参照图27对本发明的实施例10的层叠半导体集成电路装置进行说明。在该实施例10中，不设置背面电极，将p++型阱区域22与正面电极36，以及n++型阱区域23与正面电极37直接接合，除此以外与上述的实施例1同样。图27是本发明的实施例10的层叠半导体集成电路装置的概略的剖视图，是在使第1级的芯片薄层化后，层叠并接合第2级的芯片，接着，在进行薄层化后，层叠并接合第三级的芯片而得到的。
该情况下，在层叠的状态下以常温进行加压，由此，首先，硅氧化膜之间进行基于扩散的固相接合，或者硅和硅氧化膜进行基于扩散的固相接合，其结果是，一方的芯片的正面电极与另一方的芯片的高杂质浓度阱区域压接而电连接。
接着，将层叠的晶片从支承基板取下，分割成规定的尺寸的芯片后，使用粘接剂63固定在封装基板60上。接着，利用接合线64将施加VSS的电源用焊盘61和与p++型阱区域22连接的正面电极36连接。另一方面，通过利用接合线65将施加VDD的电源用焊盘62和与n++型阱区域23连接的正面电极37连接，从而完成本发明的实施例10的层叠半导体集成电路装置的基本构造。
在本发明的实施例10中，省略了背面电极，由此，能够降低制造成本，并且能够降低层叠高度。
实施例11
接着，参照图28至图30对本发明的实施例11的层叠半导体集成电路装置进行说明，在该实施例11中，利用正面电极彼此的接合，形成具有与实施例8所示的半导体存储装置同等的功能的半导体存储装置。首先，如图28的(a)所示，进行了薄层化后，将形成有背面电极的2片存储器芯片以使背面电极彼此接合的方式接合。即，使与上述的图5的(a)至图7的(f)的工序同样地形成的2片存储器芯片以背面对置的方式层叠。
另一方面，如图28的(b)所示，将控制器芯片固定在支承基板51上，进行薄层化后，形成背面电极90、91。另外，控制器芯片的元件构造与图19所示的控制器芯片同样。
接着，如图29的(c)所示，将控制器芯片的背面电极90、91固定在新的硅基板构成的支承基板52上。接着，控制器芯片的正面电极87、88和存储器芯片的正面电极36、37彼此以抵接的方式层叠。此时的接合是通过金属间的金属表面激活后的常温加压接合、即基于金属间扩散的固相接合而进行的。
接着，如图30的(d)所示，将层叠的晶片从支承基板50、52取下，分割成规定的尺寸的芯片后，在封装基板60上，通过凸块68将控制器芯片的正面电极87、88熔接在电源用焊盘61、62上，由此，完成本发明的实施例11的层叠半导体集成电路装置的基本构造。此时，在封装基板60和控制器芯片之间填充底部填充树脂。另外，图中的标号67是信号用焊盘，通过凸块68与在控制器芯片的表面上设置的焊盘(省略图示)连接。
在本发明的实施例11中，不使用接合线，而是使用焊盘将控制器芯片与封装基板电连接，不需要配置接合线的空间，能够更节省空间。此外，控制器芯片上设置的通信用线圈与存储器芯片之间的距离缩短了与控制器芯片的厚度相当的量，因此，能够省略用于电感耦合数据通信的电力。
实施例12
接着，参照图31对本发明的实施例12的层叠半导体集成电路装置进行说明，在该实施例12中，仅通过设置贯通半导体区域作为芯片选择信号的信号用布线，其他的结构与上述的实施例6同样，因此，仅对最终构造进行说明。图31是本发明的实施例12的层叠半导体集成电路装置的概略的剖视图，在上述的图19中，在第1级和第2级的存储器芯片上，在p-型Si基板21、71上设置n++型阱区域45，芯片选择信号用的信号作为布线。以与该n++型阱区域45连接的方式设置接触电极93和由Al或Cu构成的正面电极95。此外，在背面侧以与n++型阱区域45连接的方式设置由Al或Cu构成的背面电极96。
在第3级的控制器芯片上，设置与芯片选择信号布线(省略图示)连接的接触电极94和由Al或Cu构成的正面电极97。此外，该情况下，也利用多层布线形成用于电感耦合数据通信的通信用线圈92，但是，在进行了层叠的情况下，形成为：成为与存储器芯片上设置的通信用线圈44相同的位置。此外，对表面进行研磨，以使其平坦化。另外，图中的标号83、86是由SiO2构成的层间绝缘膜。
接着，使用粘接剂63将形成控制器芯片的p-型Si基板71的背面固定在封装基板60上。接着，利用接合线64将施加VSS的电源用焊盘61和与p++型阱区域22连接的正面电极36连接。另一方面，通过利用接合线65将施加VDD的电源用焊盘62和与n++型阱区域23连接的正面电极37连接，由此，完成本发明的实施例12的层叠半导体集成电路装置的基本构造。
这样，在本发明的实施例12中，使用n++型阱区域45作为10MHz以下的低速信号的芯片选择信号用布线，由于根数较少，由此，在面积上能够进行配置。此外，能够通过的信号的频率是根据由电阻和电容积确定的CR时间常数的倒数而大致确定的，由此，如果是能够通过电源用TSV的通常的信号的1/400左右的信号，则能够利用TSV程度的截面面积的贯通半导体区域进行布线。这里，通常的信号在存储器的情况下为几百MHz，由此，如果使用TSV的几倍程度以下的截面面积，则能够通过大致10MHz以下的信号。
实施例13
接着，参照图32对本发明的实施例13的层叠半导体集成电路装置进行说明，在该实施例13中，除了使用上述的实施例4中所示的通过n++分离区域而被分离的p++型阱区域来作为芯片选择信号的信号用布线以外，与上述的实施例12同样，由此，仅对最终构造进行说明。图31是本发明的实施例12的层叠半导体集成电路装置的概略的剖视图，在上述的图19中，在第1级和第2级的存储器芯片上，在p-型Si基板21、71上设置通过n++型分离区域47而被分离的p++型阱区域46，芯片选择信号用的信号作为布线。以与该p++型阱区域46连接的方式设置接触电极93和由Al或Cu构成的正面电极95。此外，在背面侧以与n++型阱区域45连接的方式设置由Al或Cu构成的背面电极96。
在第3级的控制器芯片上，设置与芯片选择信号布线(省略图示)连接的接触电极94和由Al或Cu构成的正面电极97。此外，该情况下，也利用多层布线形成用于电感耦合数据通信的通信用线圈92，但是，在进行了层叠的情况下，形成为：成为与存储器芯片上设置的通信用线圈44相同的位置。此外，对表面进行研磨，以使其平坦化。另外，图中的标号83、86是由SiO2构成的层间绝缘膜。
接着，使用粘接剂63将形成控制器芯片的p-型Si基板71的背面固定在封装基板60上。接着，利用接合线64对施加VSS的电源用焊盘61和与p++型阱区域22连接的正面电极36进行连接。另一方面，通过利用接合线65将施加VDD的电源用焊盘62和与n++型阱区域23连接的正面电极37连接，由此，完成本发明的实施例12的层叠半导体集成电路装置的基本构造。
这样，在本发明的实施例13中，作为10MHz以下的低速信号的芯片选择信号用布线，使用了与p-型Si基板21、71相同导电型的p++型阱区域45，但是，通过n++型分离区域47从p-型Si基板21、71分离，因此，在信号成为高电平的情况下，与p-型Si基板21、71之间不会流过漏电流。
另外，在上述的各实施例中，在彼此不同的芯片中，在相同的位置处设置p++型阱区域和n++型阱区域，但是，也可以在彼此不同的位置处设置，该情况下，将层叠的芯片的正面电极与背面电极、背面电极彼此或者正面电极彼此设置在相同的位置即可。此外，在各实施例中，将层叠构造安装在封装基板上，但是，也可以安装在电路基板等其他安装基板上。
标号说明
11：第1半导体集成电路装置
12：第2半导体集成电路装置
21：第1半导体基体
22：第2半导体基体
31：第1n型半导体区域
32：第2n型半导体区域
41：第1p型半导体区域
42：第2p型半导体区域
51：第1贯通半导体区域
52：第3贯通半导体区域
61：第2贯通半导体区域
62：第4贯通半导体区域
71、72：第1电极
81、82：第2电极
91～102：布线
21、71、101：p-型Si基板
22、72、102：p++型阱区域
23、73、103：n++型阱区域
24、74、104：p型阱区域
25、75、105：n型阱区域
26、76、106：p+型基板接触区域
27、77、78、107：n型区域
28、79、108：n+型基板接触区域
29、80、109：p型区域
30、31、81、82、93、94、110、111：接触电极
32、35、83、86、112、115：层间绝缘膜
33、34、84、85、113、114：布线层
36、37、87、88、95、97、116、117：正面电极
38、89、118：SiO2保护膜
39、40、90、91、96、119、120：背面电极
41：p++型阱区域
42：n++型分离区域
43：n型深阱区域
44、92：通信用线圈
45：n++型阱区域
46：p++型阱区域
47：n++型分离区域
50、51、52：支承基板
60：封装基板
61、62：电源用焊盘
63：粘接剂
64、65：接合线
66：微凸块
67：信号用焊盘
68：凸块
权利要求书(按照条约第19条的修改)
1.(修改后)一种层叠型半导体集成电路装置，其特征在于，该层叠型半导体集成电路装置至少具有第1半导体集成电路装置和第2半导体集成电路装置，
该第1半导体集成电路装置具有：
厚度为10μm以下的第1半导体基体；
第1n型半导体区域，其设于所述第1半导体基体，设置有包括晶体管在内的元件；
第1p型半导体区域，其设于所述第1半导体基体，设置有包括晶体管在内的元件；
第1贯通半导体区域，其在厚度方向上贯通所述第1半导体基体，并且与第1电源电位连接；以及
第2贯通半导体区域，其在厚度方向上贯通所述第1半导体基体，并且与第2电源电位连接，
该第2半导体集成电路装置与所述第1半导体集成电路装置形成层叠构造，具有：与第1贯通半导体区域电连接的第1电极；以及与所述第2贯通半导体区域连接的第2电极，
所述第1贯通半导体区域和所述第2贯通半导体区域的电阻值为3mΩ以下。
2.(修改后)根据权利要求1所述的层叠型半导体集成电路装置，其特征在于，
所述第2半导体集成电路装置具有：
第2半导体基体；
第2n型半导体区域，其设于所述第2半导体基体，设置有包括晶体管在内的元件；
第2p型半导体区域，其设于所述第2半导体基体，设置有包括晶体管在内的元件；
第3贯通半导体区域，其在厚度方向上贯通所述第2半导体基体，并且与所述第1电源电位连接；以及
第4贯通半导体区域，其在厚度方向上贯通所述第2半导体基体，并且与所述第2电源电位连接，
所述第2半导体集成电路装置设置有与所述第3贯通半导体区域电连接的所述第1电极以及与所述第4贯通半导体区域电连接的所述第2电极。
3.根据权利要求2所述的层叠型半导体集成电路装置，其特征在于，
所述第1半导体集成电路装置的元件配置与所述第2半导体集成电路装置的元件配置相同。
4.根据权利要求2所述的层叠型半导体集成电路装置，其特征在于，
所述第1半导体集成电路装置的元件配置与所述第2半导体集成电路装置的元件配置不同。
5.根据权利要求1所述的层叠型半导体集成电路装置，其特征在于，
层叠有多片所述第1半导体集成电路装置。
6.(删除)
7.(删除)
8.根据权利要求1所述的层叠型半导体集成电路装置，其特征在于，
所述第1半导体基体的厚度为5μm以下。
9.根据权利要求1所述的层叠型半导体集成电路装置，其特征在于，
所述第1贯通半导体区域与所述第1半导体基体是相同导电型，所述第2贯通半导体区域与所述第1半导体基体是相反导电型。
10.根据权利要求1所述的层叠型半导体集成电路装置，其特征在于，
所述第1贯通半导体区域及所述第2贯通半导体区域与所述第1半导体基体是相同导电型，所述第2贯通半导体区域通过相反导电型层而与所述第1半导体基体电分离。
11.根据权利要求1所述的层叠型半导体集成电路装置，其特征在于，
所述第1p型半导体区域或所述第1n型半导体区域中的与所述第1半导体基体为相同导电型的半导体区域通过相反导电型分离层而与所述第1半导体基体电分离，并且，所述相反导电型分离层从所述第1半导体基体的背面露出。
12.根据权利要求1所述的层叠型半导体集成电路装置，其特征在于，
所述第1半导体集成电路装置和所述第2半导体集成电路装置具有进行信号的收发的线圈。
13.根据权利要求12所述的层叠型半导体集成电路装置，其特征在于，
所述第1半导体集成电路装置具有与所述第1半导体基体为相反导电型的信号用贯通半导体区域或与所述第1半导体基体为相同导电型的信号用贯通半导体区域中的至少一方，其中，与所述第1半导体基体为相同导电型的信号用贯通半导体区域通过与所述第1半导体基体为相反导电型的分离层而被分离。
14.根据权利要求13所述的层叠型半导体集成电路装置，其特征在于，
在所述信号用贯通半导体层中传播的信号的频率为100MHz以下。
15.根据权利要求13所述的层叠型半导体集成电路装置，其特征在于，
所述第2半导体集成电路装置具有与所述第2半导体基体为相反导电型的信号用贯通半导体区域或与所述第2半导体基体为相同导电型的信号用贯通半导体区域中的至少一方，其中，与所述第2半导体基体为相同导电型的信号用贯通半导体区域通过与所述第2半导体基体为相反导电型的分离层而被分离，
从层叠方向观察时，在所述第1半导体基体上设置的信号用贯通半导体区域和在所述第2半导体基体上设置的信号用半导体区域重叠。
说明或声明(按照条约第19条的修改)
权利要求1通过补入权利要求6和权利要求7的内容，明确了用于由贯通半导体区域实现电源布线的条件。
权利要求2只是单纯地改正了笔误。
对比文件1(JP2007-250561A)中所记载的贯通半导体区域是小区选择信号布线而并不是电源布线。另外，记载于对比文件1的【0032】中的电阻值(几十Ω)与本申请权利要求1中所限定的3mΩ以下相比，相差了3位数以上，在对比文件1所记载的条件中，由于电阻值过高，因此很难将贯通半导体区域实际用作布线(虽然形式上有可能，但是在实际装置中，由于信号大幅延迟，因此不会采用)。
另外，关于对比文件1中的半导体基板的厚度，记载为5μm～150μm，但是具体的示例为50μm(【0033】)。
然而，根据本申请的图3的结果可知，如果不将半导体基体(半导体基板)的厚度设为10μm以下，则由于电阻值过高而无法将贯通半导体区域实际用作布线。
关于该事项，在对比文件1的【0007】的关于现有技术例的记载中，相当于讲明了：现有技术例并没有公开到可根据发行时的技术常识来制作该半导体元件的程度，结果上依然没有解决技术问题。该对比文件1中的与贯通半导体区域相关的公开内容并没有揭示出能根据发行时的技术常识来将该贯通半导体区域用作布线的程度的结构，结果上依然没有解决技术问题。“半导体基体的厚度为10μm以下且贯通半导体区域的电阻值为3mΩ以下”这一点是相比于现有技术例而具有创造性的证明。
另外，在对比文件2至对比文件6中，没有涉及将贯通半导体区域用作布线的记载。

Claims (15)

1.一种层叠型半导体集成电路装置，其特征在于，该层叠型半导体集成电路装置至少具有第1半导体集成电路装置和第2半导体集成电路装置，
该第1半导体集成电路装置具有：
第1半导体基体；
第1n型半导体区域，其设于所述第1半导体基体，设置有包括晶体管在内的元件；
第1p型半导体区域，其设于所述第1半导体基体，设置有包括晶体管在内的元件；
第1贯通半导体区域，其在厚度方向上贯通所述第1半导体基体，并且与第1电源电位连接；以及
第2贯通半导体区域，其在厚度方向上贯通所述第1半导体基体，并且与第2电源电位连接，
该第2半导体集成电路装置与所述第1半导体集成电路装置形成层叠构造，具有：与第1贯通半导体区域电连接的第1电极；以及与所述第2贯通半导体区域连接的第2电极。
2.根据权利要求1所述的层叠型半导体装置，其特征在于，
所述第2半导体集成电路装置具有：
第2半导体基体；
第2n型半导体区域，其设于所述第2半导体基体，设置有包括晶体管在内的元件；
第2p型半导体区域，其设于所述第2半导体基体，设置有包括晶体管在内的元件；
第3贯通半导体区域，其在厚度方向上贯通所述第2半导体基体，并且与所述第1电源电位连接；以及
第4贯通半导体区域，其在厚度方向上贯通所述第2半导体基体，并且与所述第2电源电位连接，
所述第2半导体集成电路装置设置有与所述第3贯通半导体区域电连接的所述第1电极以及与所述第4贯通半导体区域电连接的所述第2电极。
3.根据权利要求2所述的层叠型半导体集成电路装置，其特征在于，
所述第1半导体集成电路装置的元件配置与所述第2半导体集成电路装置的元件配置相同。
4.根据权利要求2所述的层叠型半导体集成电路装置，其特征在于，
所述第1半导体集成电路装置的元件配置与所述第2半导体集成电路装置的元件配置不同。
5.根据权利要求1所述的层叠型半导体集成电路装置，其特征在于，
层叠有多片所述第1半导体集成电路装置。
6.根据权利要求1所述的层叠型半导体集成电路装置，其特征在于，
所述第1贯通半导体区域和所述第2贯通半导体区域的电阻值为3mΩ以下。
7.根据权利要求1所述的层叠型半导体集成电路装置，其特征在于，
所述第1半导体基体的厚度为10μm以下。
8.根据权利要求1所述的层叠型半导体集成电路装置，其特征在于，
所述第1半导体基体的厚度为5μm以下。
9.根据权利要求1所述的层叠型半导体集成电路装置，其特征在于，
所述第1贯通半导体区域与所述第1半导体基体是相同导电型，所述第2贯通半导体区域与所述第1半导体基体是相反导电型。
10.根据权利要求1所述的层叠型半导体集成电路装置，其特征在于，
所述第1贯通半导体区域及所述第2贯通半导体区域与所述第1半导体基体是相同导电型，所述第2贯通半导体区域通过相反导电型层而与所述第1半导体基体电分离。
11.根据权利要求1所述的层叠型半导体集成电路装置，其特征在于，
所述第1p型半导体区域或所述第1n型半导体区域中的与所述第1半导体基体为相同导电型的半导体区域通过相反导电型分离层而与所述第1半导体基体电分离，并且，所述相反导电型分离层从所述第1半导体基体的背面露出。
12.根据权利要求1所述的层叠型半导体集成电路装置，其特征在于，
所述第1半导体集成电路装置和所述第2半导体集成电路装置具有进行信号的收发的线圈。
13.根据权利要求12所述的层叠型半导体集成电路装置，其特征在于，
所述第1半导体集成电路装置具有与所述第1半导体基体为相反导电型的信号用贯通半导体区域或与所述第1半导体基体为相同导电型的信号用贯通半导体区域中的至少一方，其中，与所述第1半导体基体为相同导电型的信号用贯通半导体区域通过与所述第1半导体基体为相反导电型的分离层而被分离。
14.根据权利要求13所述的层叠型半导体集成电路装置，其特征在于，
在所述信号用贯通半导体层中传播的信号的频率为100MHz以下。
15.根据权利要求13所述的层叠型半导体集成电路装置，其特征在于，
所述第2半导体集成电路装置具有与所述第2半导体基体为相反导电型的信号用贯通半导体区域或与所述第2半导体基体为相同导电型的信号用贯通半导体区域中的至少一方，其中，与所述第2半导体基体为相同导电型的信号用贯通半导体区域通过与所述第2半导体基体为相反导电型的分离层而被分离，
从层叠方向观察时，在所述第1半导体基体上设置的信号用贯通半导体区域和在所述第2半导体基体上设置的信号用半导体区域重叠。
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