WO2020081006A1

WO2020081006A1 - Stacked arrangement and method of forming the same

Info

Publication number: WO2020081006A1
Application number: PCT/SG2019/050488
Authority: WO
Inventors: Masaya Kawano
Original assignee: Agency For Science, Technology And Research
Priority date: 2018-10-16
Filing date: 2019-09-25
Publication date: 2020-04-23

Abstract

Various embodiments may provide a method of forming a stacked arrangement. The method may include forming a first doped region in a first substrate, a first dielectric layer in contact with the first substrate, one or more first interconnects so that the one or more first interconnects are in electrical connection with the first doped region, a second doped region in a second substrate, a second dielectric layer in contact with the second substrate, and one or more second interconnects so that the one or more second interconnects are in electrical connection with the second doped region. The method may further include bonding the first dielectric layer with the second dielectric layer, and removing a portion of the first substrate so that the first doped region extends from a first surface of the thinned first substrate to a second surface of the thinned first substrate.

Description

l

STACKED ARRANGEMENT AND METHOD OF FORMING THE SAME

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of priority of Singapore application No. 10201809081V filed October 16, 2018, the contents of it being hereby incorporated by reference in its entirety for all purposes.

TECHNICAL FIELD

[0002] Various aspects of this disclosure relate to a stacked arrangement. Various aspects of this disclosure relate to a method of forming a stacked arrangement.

BACKGROUND

[0003] For mobile computing and graphic processing systems, it is strongly desirable to improve performance without increasing operating frequency or power consumption, because of issues such as frequency limitations in large-scale integrated circuit (LSI) operations, battery- related power limitations, and cooling problems. In order to improve memory access band width as well as power consumption efficiency without having a high frequency interface, wide input/output (IO) memory bus may be required.

[0004] In addition, as the system performance improves, the memory capacity provided in such systems may also become larger. In order to cater to demand, high capacity memories are introduced to the market, while IO density and per IO pin data-rates in new memory technologies are increased using circuit techniques. Further, three-dimensional (3D) system architectural solutions have also been introduced to stack multi-chip memories so that the data-rate and memory capacity may be further improved via small form factor. However, this kind of memory products are presently implemented only in limited areas, such as high-end computing, due to expensive process cost necessary to fabricate through-silicon vias (TSVs) and multi-chip stacking.

[0005] High-Bandwidth Memory (HBM) has been introduced recently in the market to achieve next generation portable computing systems. It increases the bandwidth and reduces the power consumption. HBM (Generation 1) contains 3982 micro-bumps with a staggered pitch of 27.5mhi and 48 27.5mih, with a bump size of 25um. Each die has TSVs to enable vertical interconnections, and each die is 3D stacked at chip-level. The die-to-die IOs are around 1200.

[0006] From a process cost point of view, wafer to wafer stacking approach is more attractive than chip to chip stacking, since multiple chips can be 3D stacked simultaneously at a wafer level. In addition, fabrication cost of micro-bumps and TSVs occupy a large portion of assembly cost. A cost model shows micro-bump and TSV cost around 100 US$ and 500 US$ respectively per 300 mm wafer. In order to reduce the assembly cost without sacrificing device performance, bumpless wafer stacking process has been proposed. These bump-less wafer bonding technologies, however, still require TSVs for each layer. In addition, multiple TSVs may also be required to connect different layers with one another, thus requiring more areas for TSVs and resulting in higher cost. Furthermore, each layer may be required to have different metal patterns for landing pads of TSVs. Each device wafer may be fabricated with metal structure dedicated to a specific layer.

[0007] Another approach to make three-dimensional integrated circuits (3D-IC) is by using doped wells and metal connections instead of using TSV. FIGS. 1 A - D show a method of forming a three-dimensional stack by using doped wells and metal connections. FIG. 1A shows ion implantation into a substrate and forming of interlayer insulating film. Boron is ion implanted into a p- type silicon (Si) substrate, and p++ type well region is formed. A n++ well region is also formed. As shown in step (b), n-wells, p-wells, and contact regions are also formed. Then, by performing a 50-hour heat treatment at 1050 °C, the implanted ions are activated. The activated ions diffuse deeper in the substrate thickness direction. Interlayer insulating films are formed on the substrate. Surface electrodes made of copper (Cu) are formed, and polishing is performed in order to flatten the surface.

[0008] FIG. 1B shows attaching of the substrate to a temporary substrate and using chemical mechanical polishing (CMP) to grind the substrate to a thickness of approximately 5 mih.

[0009] FIG. 1C shows the formation of a silicon dioxide (Si0₂) protective film on the polished surface with back electrodes, and the lamination of with another semiconductor wafer (i.e. top semiconductor wafer) that is formed by steps (a) - (c). As shown in step (f), openings are then formed to expose the p++ region and the n++region in the bottom semiconductor wafer. A protective film with openings is formed, and the openings are deposited with aluminum (Al) or copper (copper) to form back electrodes in the bottom semiconductor wafer. Polishing is performed to planarize the surface. As shown in step (g), the back electrodes of the bottom semiconductor wafer may then be laminated with the front surface electrodes of the top semiconductor wafer so that a back electrode of the bottom semiconductor wafer is in contact with a front surface electrode of the top semiconductor wafer. The metal surfaces may be activated by room temperature pressure bonding which causes intermetallic diffusion, leading to solid-phase joining.

[0010] FIG. 1D shows the grinding of the top semiconductor wafer to a predetermined thickness using chemical mechanical polishing (CMP), and forming a further silicon dioxide (Si0₂) protective film on the top semiconductor wafer. The substrate may be reduced to a thickness of approximately 5 mih. After forming of the further silicon dioxide (Si0₂) protective film, openings are formed to expose the p++ and n++ wells in the top semiconductor wafer. The openings are filled with aluminum (Al) or copper (copper) to form back electrodes. Polishing is performed to planarize the surface.

[0011] Although the above mentioned describes 3D integration process without using TSV, vertical contact is achieved by metal (i.e. Al or Cu) and doped-Si connections. There are two problems for this type of electrical connections. First, a metal-Si interface creates a Schottky barrier which leads to abnormal current-voltage (IV) characteristics. In order to mitigate this problem, high temperature annealing, e.g. >500 °C, is necessary to make metal diffuse into silicon. In most cases of 3D integration, allowable maximum temperature is not so high. It is around 300 ~ 400 °C or below. If Schottky barrier still exists at the interface, it degrades device performance due to non-linear IV characteristics. Secondly, supposing that metal diffuses into Si, there is a risk that transistor characteristics would be affected. Above all, Cu is well known minority carrier lifetime killer that degrades device performance.

[0012] Besides, there is no indication on how to control the total thickness variation (TTV) of Si precisely. At the thickness range of around 5 um, a little variation of Si thickness would affect the device performance, since depth of diffusion layer such as deep N-well is around 2 um. Taking the width of depletion layer into consideration, the TTV should be controlled to within 0.5 um or less. However, this requirement is difficult to achieve by back grinding. One possible approach would be to use a silicon-on-insulator (SOI) wafer. In this case, final thinning process is done by wet etching, thus Si thickness is determined by the original top Si thickness of SOI substrate. However, using SOI wafers increase substrate cost by three times.

SUMMARY

[0013] Various embodiments may provide a method of forming a stacked arrangement. The method may include forming a first doped region in a first substrate. The method may also include forming a first dielectric layer in contact with the first substrate. The method may further include forming one or more first interconnects so that the one or more first interconnects are in electrical connection with the first doped region and extends from a first surface of the first dielectric layer to a second surface of the first dielectric layer opposite the first surface of the first dielectric layer. The method may additionally include forming a second doped region in a second substrate. The method may further include forming a second dielectric layer in contact with the second substrate. The method may also include forming one or more second interconnects so that the one or more second interconnects are in electrical connection with the second doped region and extends from a first surface of the second dielectric layer to a second surface of the second dielectric layer opposite the first surface of the second dielectric layer. The method may further include bonding the first dielectric layer with the second dielectric layer so that the one or more first interconnects are in electrical connection with the one or more second interconnects. The method may additionally include removing a portion of the first substrate so that the first doped region extends from a first surface of the thinned first substrate to a second surface of the thinned first substrate opposite the first surface of the thinned first substrate.

[0014] Various embodiments may relate to a stacked arrangement. The stacked arrangement may include a thinned first substrate including a first doped region, the first doped region extending from a first surface of the thinned first substrate to a second surface of the thinned first substrate opposite the first surface of the thinned first substrate. The stacked arrangement may also include a first dielectric layer in contact with the thinned first substrate. The stacked arrangement may further include one or more first interconnects extending from a first surface of the first dielectric layer to a second surface of the first dielectric layer opposite the first surface of the first dielectric layer, the one or more first interconnects in electrical connection with the first doped region. The stacked arrangement may additionally include a second substrate including a second doped region. The stacked arrangement may also include a second dielectric layer in contact with the second substrate. The stacked arrangement may further include one or more second interconnects extending from a first surface of the second dielectric layer to a second surface of the second dielectric layer opposite the first surface of the second dielectric layer, the one or more second interconnects in electrical connection with the second doped region. The one or more first interconnects extending from a first surface of the first dielectric layer to a second surface of the first dielectric layer opposite the first surface of the first dielectric layer, the one or more first interconnects in electrical connection with the first doped region. The first dielectric layer may be bonded with the second dielectric layer so that the one or more first interconnects are in electrical connection with the one or more second interconnects.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The invention will be better understood with reference to the detailed description when considered in conjunction with the non-limiting examples and the accompanying drawings, in which:

FIG. 1 A shows ion implantation into a substrate and forming of interlayer insulating film.

FIG. 1B shows attaching of the substrate to a temporary substrate and using chemical mechanical polishing (CMP) to grind the substrate to a thickness of approximately 5 mhi.

FIG. 1C shows the formation of a silicon dioxide (Si0₂) protective film on the polished surface with back electrodes, and the lamination of with another semiconductor wafer (i.e. top semiconductor wafer) that is formed by steps (a) - (c).

FIG. 1D shows the grinding of the top semiconductor wafer to a predetermined thickness using chemical mechanical polishing (CMP), and forming a further silicon dioxide (Si0₂) protective film on the top semiconductor wafer.

FIG. 2 shows a general illustration of a method of forming a stacked arrangement according to various embodiments.

FIG. 3 shows a schematic of a stacked arrangement according to various embodiments.

FIG. 4A shows forming of deep trench isolation (DTI) on a first substrate, implantation, and forming of a first dielectric layer on the first substrate according to various embodiments. FIG. 4B shows bonding of two device substrates or wafers via hybrid bonding according to various embodiments.

FIG. 4C shows the back grinding of the top device substrate or wafer, followed by the first chemical mechanical polishing (CMP) according to various embodiments.

FIG. 4D shows the back grinding of the second chemical mechanical polishing (CMP) according to various embodiments.

FIG. 4E shows back-to-back (B2B) bonding of two of the two-layer stacked structure formed in FIG. 4D according to various embodiments.

FIG. 5A shows implantation of ions onto a first substrate, and forming of a first dielectric layer on the first substrate according to various embodiments.

FIG. 5B shows bonding of two device substrates or wafers via hybrid bonding according to various embodiments.

FIG. 5C shows back grinding and polishing of the top device substrate or wafer as well as forming deep trenches surrounding the first doped regions according to various embodiments.

FIG. 5D shows the forming of deep trench isolation (DTI) according to various embodiments. FIG. 5E shows back-to-back (B2B) bonding of two of the two-layer stacked structure formed in FIG. 5D according to various embodiments.

FIG. 6A shows implantation of ions onto a first substrate, and forming of a first dielectric layer on the first substrate according to various embodiments.

FIG. 6B shows bonding of two device substrates or wafers via hybrid bonding according to various embodiments.

FIG. 6C shows back grinding and polishing of the top device substrate or wafer as well as forming deep trenches surrounding the first doped regions according to various embodiments.

FIG. 6D shows the forming of deep trench isolation (DTI) according to various embodiments. FIG. 6E shows back-to-back (B2B) bonding of two of the two-layer stacked structure formed in FIG. 6D according to various embodiments.

FIG. 7A shows implantation of ions onto a first substrate, and forming of a first dielectric layer on the first substrate according to various embodiments.

FIG. 7B shows bonding of two device substrates or wafers via hybrid bonding according to various embodiments. FIG. 7C shows back grinding and polishing of the top device substrate or wafer as well as forming deep trenches surrounding the first doped regions according to various embodiments.

FIG. 7D shows the forming of deep trench isolation (DTI) according to various embodiments. FIG. 7E shows back-to-back (B2B) bonding of two of the two-layer stacked structure formed in FIG. 7D according to various embodiments.

FIG. 8A shows implantation of ions onto a first substrate, and forming of a first dielectric layer on the first substrate according to various embodiments.

FIG. 8B shows bonding of two device substrates or wafers via hybrid bonding according to various embodiments.

FIG. 8C shows back grinding and polishing of the top device substrate or wafer according to various embodiments.

FIG. 8D shows the depositing a dielectric material on the first surface of the thinned first substrate 802 according to various embodiments.

FIG. 8E shows back-to-back (B2B) bonding of two of the two-layer stacked structure formed in FIG. 8D according to various embodiments.

FIG. 9A shows implantation of ions onto a first substrate, and forming of a first dielectric layer on the first substrate according to various embodiments.

FIG. 9B shows bonding of two device substrates or wafers via hybrid bonding according to various embodiments.

FIG. 9C shows back grinding and polishing of the top device substrate or wafer according to various embodiments.

FIG. 9D shows deposition of a dielectric material and subsequent removal of a portion of the dielectric material to form passivation structures around the doped regions according to various embodiments.

FIG. 9E shows back-to-back (B2B) bonding of two of the two-layer stacked structure formed in FIG. 9D according to various embodiments.

FIG. 10 shows a portion of a stacked arrangement according to various embodiments.

FIG. 11 shows a portion of a stacked arrangement according to various embodiments to illustrate accommodation of misalignment between the substrates or wafers in back-to-back (B2B) bonding. FIG. 12 shows a portion of a stacked arrangement according to various other embodiments to illustrate accommodation of misalignment between the substrates or wafers in back-to-back (B2B) bonding.

DETAILED DESCRIPTION

[0016] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, and logical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.

[0017] Embodiments described in the context of one of the methods or stacked arrangements are analogously valid for the other methods or stacked arrangements. Similarly, embodiments described in the context of a method are analogously valid for a stacked arrangement, and vice versa.

[0018] Features that are described in the context of an embodiment may correspondingly be applicable to the same or similar features in the other embodiments. Features that are described in the context of an embodiment may correspondingly be applicable to the other embodiments, even if not explicitly described in these other embodiments. Furthermore, additions and/or combinations and/or alternatives as described for a feature in the context of an embodiment may correspondingly be applicable to the same or similar feature in the other embodiments.

[0019] In the context of various embodiments, the articles“a”,“an” and“the” as used with regard to a feature or element include a reference to one or more of the features or elements.

[0020] In the context of various embodiments, the term“about” or“approximately” as applied to a numeric value encompasses the exact value and a reasonable variance.

[0021] As used herein, the term“and/or” includes any and all combinations of one or more of the associated listed items.

[0022] Various embodiments may seek to address or mitigate the issues described above. [0023] FIG. 2 shows a general illustration of a method of forming a stacked arrangement according to various embodiments. The method may include, in 202, forming a first doped region in a first substrate. The method may also include, in 204, forming a first dielectric layer in contact with the first substrate. The method may further include, in 206, forming one or more first interconnects so that the one or more first interconnects are in electrical connection with the first doped region and extends from a first surface of the first dielectric layer to a second surface of the first dielectric layer opposite the first surface of the first dielectric layer. The method may additionally include, in 208, forming a second doped region in a second substrate. The method may further include, in 210, forming a second dielectric layer in contact with the second substrate. The method may also include, in 212, forming one or more second interconnects so that the one or more second interconnects are in electrical connection with the second doped region and extends from a first surface of the second dielectric layer to a second surface of the second dielectric layer opposite the first surface of the second dielectric layer. The method may further include, in 214, bonding the first dielectric layer with the second dielectric layer so that the one or more first interconnects are in electrical connection with the one or more second interconnects. The method may additionally include, in 216, removing a portion of the first substrate so that the first doped region extends from a first surface of the thinned first substrate to a second surface of the thinned first substrate opposite the first surface of the thinned first substrate.

[0024] In other words, the method may include forming dielectric layers over two substrates with doped regions, and subsequently forming electrical interconnects in each dielectric layer so that the electrical interconnects extend from one surface of the dielectric layer to another surface of the dielectric layer to contact the doped region in a respective substrate. The method may further include bonding the dielectric layers together to connect the electrical interconnects. The method may also include thinning one of the two substrates.

[0025] For avoidance of doubt, FIG. 2 does not limit the sequence of the various steps. For instance, steps 202 may occur before step 208, at the same time as step 208, or after step 208.

[0026] In various embodiments, electrical connections of different device substrate or wafer (each device substrate or wafer including a substrate and a dielectric layer) may be established without using TSVs. This may reduce process cost because TSV fabrication may play a significant role of unnecessary cost increase for 3D integration. In addition, various embodiments may allow for ultra-thin layers less than 10 um, this allowing fabrication of devices with low profile 3D devices as well as short electrical path length, which results in better electrical performance. For these reasons, a semiconductor device suitable for high-speed operation with small device area may be obtained in a cost-effective way.

[0027] In various embodiments, the substrate may include a suitable semiconductor such as silicon (Si), or any other suitable semiconductors such as germanium, silicon carbide (SiC), gallium nitride (GaN), indium phosphide (InP), or gallium arsenide (GaAs). In various embodiments, the substrate may be a semiconductor wafer such as a Si wafer.

[0028] In various embodiments, the method may include forming a third doped region in a third substrate. The method may also include forming a third dielectric layer in contact with the third substrate. The method may further include forming one or more third interconnects so that the one or more third interconnects are in electrical connection with the third doped region and extends from a first surface of the third dielectric layer to a second surface of the third dielectric layer opposite the first surface of the third dielectric layer. In various embodiments, the method may include forming a fourth doped region in a fourth substrate. The method may also include forming a fourth dielectric layer in contact with the fourth substrate. The method may further include forming one or more fourth interconnects so that the one or more fourth interconnects are in electrical connection with the fourth doped region and extends from a first surface of the fourth dielectric layer to a second surface of the fourth dielectric layer opposite the first surface of the fourth dielectric layer. The method may additionally include bonding the third dielectric layer with the fourth dielectric layer so that the one or more third interconnects are in electrical connection with the one or more fourth interconnects. The method may also include removing a portion of the third substrate so that the third doped region extends from a first surface of the thinned third substrate to a second surface of the thinned third substrate opposite the first surface of the thinned third substrate. The method may further include bonding the thinned first substrate and the thinned third substrate so that the first doped region is in contact with the third doped region.

[0029] In various embodiments, the method may include forming a deep trench isolation ring in the first substrate before forming the first doped region. The method may further include forming a deep trench isolation ring in the second substrate before forming the second doped region. The first doped region may be formed within a perimeter defined by the deep trench isolation ring formed in the first substrate. The second doped region may be formed within a perimeter defined by the deep trench isolation ring formed in the second substrate.

[0030] The method may further include forming a first outer deep trench isolation ring such that that the first outer deep trench isolation ring surrounds the first deep trench isolation ring. The method may also include forming a second outer deep trench isolation ring such that the second outer deep trench isolation ring surrounds the second deep trench isolation ring.

[0031] In various other embodiments, the method may further include removing a portion of the thinned first substrate surrounding the first doped region to form a trench. The method may also include depositing a dielectric material into the trench to form a deep trench isolation ring, and on the first surface of the thinned first substrate. The method may further include removing a portion of the deposited material on the first surface of the thinned first substrate.

[0032] In yet various other embodiments, the portion of the first substrate may be removed in such a manner that the first doped region protrudes out from the thinned first substrate. The method further may include removing a portion of the thinned first substrate surrounding the first doped region to form a trench. The method may also include depositing a dielectric material into the trench to form a deep trench isolation ring, and on the first surface of the thinned first substrate. The method may additionally include removing a portion of the deposited dielectric material on the first surface of the thinned first substrate so that a further portion of the deposited material remaining on the first surface of the thinned first substrate is planarized, thereby exposing the first doped region to the second surface of the thinned first substrate opposite the first surface of the thinned first substrate.

[0033] In yet various other embodiments, the method may include removing a portion of the thinned first substrate surrounding the first doped region to form a trench extending from the first surface of the thinned first substrate to the second surface of the thinned first substrate, the trench wider at the first surface relative to at the second surface. The method may also include depositing a dielectric material into the trench and on the first surface of the thinned first substrate. The method may additionally include removing a portion of the deposited dielectric material on the first surface of the thinned first substrate to form a deep trench isolation ring.

[0034] In yet various embodiments, the portion of the first substrate may be removed in such a manner that the first doped region protrudes out from the thinned first substrate. The method may include depositing a dielectric material on the first surface of the thinned first substrate. The method may also include removing a portion of the deposited dielectric material so that a further portion of the deposited dielectric material remaining on the first surface of the thinned first substrate is planarized.

[0035] In yet various other embodiments, the portion of the first substrate may be removed in such a manner that the first doped region protrudes out from the thinned first substrate. The method may further include removing a further region of the thinned first substrate adjacent to a top region of the first doped region to form a passivation groove. The method may also include depositing a dielectric material in the passivation groove to form a passivation structure around the top region of the first doped region, and on the first surface of the thinned first substrate. The method may also include removing the deposited material on the first surface of the thinned first substrate.

[0036] In various embodiments, the first substrate may include one or more further doped regions, each of the one or more further doped regions having a depth less than a depth of the first doped region. The second substrate may include one or more further doped regions, each of the one or more further doped regions having a depth less than a depth of the second doped region. The method may include forming the one or more further doped regions on the first substrate, e.g. via ion implantation. The method may also include forming the one or more further doped regions on the second substrate, e.g. via ion implantation. The one or more further doped regions on the first substrate may be n- wells and/or p-wells. The one or more further doped regions on the second substrate may be n- wells and/or p-wells.

[0037] In various embodiments, the third substrate may include one or more further doped regions, each of the one or more further doped regions having a depth less than a depth of the third doped region. The fourth substrate may include one or more further doped regions, each of the one or more further doped regions having a depth less than a depth of the fourth doped region. The method may include forming the one or more further doped regions on the third substrate, e.g. via ion implantation. The method may also include forming the one or more further doped regions on the fourth substrate, e.g. via ion implantation. The one or more further doped regions on the third substrate may be n-wells and/or p-wells. The one or more further doped regions on the fourth substrate may be n-wells and/or p-wells. [0038] In various embodiments, bonding the first dielectric layer with the second dielectric layer may include hybrid bonding. Hybrid bonding may be a direct bonding technology which obtains metal-metal bonding and dielectric-dielectric bonding simultaneously.

[0039] The one or more first interconnects and the one or more second interconnects may include copper. The one or more third interconnects and the one or more fourth interconnects may include copper.

[0040] FIG. 3 shows a schematic of a stacked arrangement 300 according to various embodiments. The stacked arrangement 300 may include a thinned first substrate 302 including a first doped region 304, the first doped region 304 extending from a first surface of the thinned first substrate 302 to a second surface of the thinned first substrate 302 opposite the first surface of the thinned first substrate 302. The stacked arrangement 300 may also include a first dielectric layer 306 in contact with the thinned first substrate 302. The stacked arrangement 300 may further include one or more first interconnects 308 extending from a first surface of the first dielectric layer 306 to a second surface of the first dielectric layer 306 opposite the first surface of the first dielectric layer 306, the one or more first interconnects 308 in electrical connection with the first doped region 304. The stacked arrangement 300 may additionally include a second substrate 310 including a second doped region 312. The stacked arrangement 300 may also include a second dielectric layer 314 in contact with the second substrate 310. The stacked arrangement 300 may further include one or more second interconnects 316 extending from a first surface of the second dielectric layer 314 to a second surface of the second dielectric layer 314 opposite the first surface of the second dielectric layer 314, the one or more second interconnects 316 in electrical connection with the second doped region 312. The one or more first interconnects 308 extending from a first surface of the first dielectric layer 306 to a second surface of the first dielectric layer 306 opposite the first surface of the first dielectric layer 306, the one or more first interconnects 308 in electrical connection with the first doped region 304. The first dielectric layer 306 may be bonded with the second dielectric layer 314 so that the one or more first interconnects 308 are in electrical connection with the one or more second interconnects 316.

[0041] In other words, various embodiments may include a stacked arrangement include two device substrates or wafers, each device substrate or wafer including a substrate 302, 310 and a respective dielectric layer 306, 314. The two dielectric layers 306, 314 may be bonded together so that interconnects 308, 316 are in electrical connection. The interconnects 308 may be electrically connected to doped region 304 in substrate 302, while the interconnects 316 may be electrically connected to doped region 312 in substrate 310.

[0042] In various embodiments, the stacked arrangement 300 may also include a thinned third substrate including a third doped region, the third doped region extending from a first surface of the thinned third substrate to a second surface of the thinned third substrate opposite the first surface of the thinned third substrate. The stacked arrangement 300 may also include a third dielectric layer in contact with the thinned third substrate. The stacked arrangement 300 may additionally include one or more third interconnects extending from a first surface of the third dielectric layer to a second surface of the third dielectric layer opposite the first surface of the third dielectric layer, the one or more third interconnects in electrical connection with the third doped region.

[0043] The stacked arrangement 300 may also include a fourth substrate including a fourth doped region. The stacked arrangement 300 may further include a fourth dielectric layer in contact with the fourth substrate. The stacked arrangement 300 may also include one or more fourth interconnects extending from a first surface of the fourth dielectric layer to a second surface of the fourth dielectric layer opposite the first surface of the fourth dielectric layer, the one or more fourth interconnects in electrical connection with the fourth doped region. The third dielectric layer may be bonded with the fourth dielectric layer so that the one or more third interconnects are in electrical connection with the one or more fourth interconnects.

[0044] The thinned first substrate 302 and the thinned third substrate may be bonded so that the first doped region is in contact with the third doped region.

[0045] In various embodiments, the thinned first substrate 302 further may include a deep trench isolation ring or a passivation groove surrounding the first doped region 304. In various embodiments, the thinned first substrate 302 may also include an outer deep trench isolation ring surrounding the deep trench isolation ring.

[0046] In various embodiments, the second substrate 310 may further include a deep trench isolation ring or a passivation groove surrounding the second doped region 312.

[0047] In various embodiments, the thinned third substrate further may include a deep trench isolation ring or a passivation groove surrounding the third doped region. In various embodiments, the thinned third substrate may also include an outer deep trench isolation ring surrounding the deep trench isolation ring.

[0048] In various embodiments, the fourth substrate may further include a deep trench isolation ring or a passivation groove surrounding the fourth doped region.

[0049] FIGS. 4A - E show a method of forming a stacked arrangement according to various embodiments. FIG. 4A shows forming of deep trench isolation (DTI) 418 on a first substrate 402, implantation, and forming of a first dielectric layer 406 on the first substrate 402 according to various embodiments. In step (1), deep trench isolation (DTI) 418 (e.g. deep trench isolation rings) may be formed on the first substrate 402, such as a silicon substrate. The DTI 418 may include a dielectric material such as silicon dioxide (Si0₂).

[0050] The purposes of the DTI 418 may include i) for acting as a stop layer during Si thinning and ii) for isolation of doped wells which are used for vertical interconnections. By combining face-to-face (F2F) hybrid bonding and back-to-back (B2B) doped well bonding, 3D interconnection may be achieved. The top metal layers for even/odd layers may be substantially mirror image pattern each other.

[0051] The depth of the DTI 418 may be substantially the same as the final targeted thickness of the substrate 402.

[0052] In step (2), high energy implantation followed by annealing may form the first doped regions 404 in the first substrate 402. A first doped region may be formed within a perimeter defined by a deep trench isolation ring formed in the first substrate 402. The first doped regions may be the deepest well region for vertical 3D interconnection.

[0053] In step (3), the first dielectric layer 406 may be formed on or over the first substrate. The first dielectric layer 406 may include a plurality of sub-layers. One or more first interconnects 408 may also be formed so that the one or more first interconnects 408 are in electrical connection with the first doped region 404 and extends from a first surface of the first dielectric layer 406 to a second surface of the first dielectric layer 406 opposite the first surface of the first dielectric layer 406. The first dielectric layer 406 and the one or more first interconnects 408 may be formed by complementary metal oxide semiconductor (CMOS) process and multi-layer interconnect process. The one or more first interconnects 408 may include metal pads which are exposed on the planarized top surface of the first dielectric layer 406. [0054] FIG. 4B shows bonding of two device substrates or wafers via hybrid bonding according to various embodiments. The top device substrate or wafer may include the first substrate 402 with the first doped regions 404 and the DTI 418, as well as the first dielectric layer 406 with first interconnects 408 on or over the first substrate 402, and may be formed using the processes illustrated in FIG. 4 A. The bottom device substrate or wafer may include the second substrate 410 with the second doped regions 412 and the DTI 420, as well as the second dielectric layer 414 with second interconnects 416 on or over the second substrate 410, and may also be formed using processes similar to the processes for the top device substrate or wafer, i.e. those illustrated in FIG. 4A. The two device substrates or wafers may be bonded via metal/oxide hybrid bonding, and may be annealed for mutual diffusion at the metal interface. The one or more first interconnects 408 and the one or more second interconnects 416 may include copper (Cu), which may be suitable for hybrid bonding. The DTI 420 may also include a dielectric material such as silicon dioxide (Si0₂).

[0055] FIG. 4C shows the back grinding of the top device substrate or wafer, followed by the first chemical mechanical polishing (CMP) according to various embodiments. The DTI 418 may be used as a etch stop to control the TTV. The doped regions 418, i.e. the deepest well for 3D interconnection, may be exposed by this step. However, the CMOS device structure, such as other doped wells (e.g. n- wells) may not be exposed.

[0056] FIG. 4D shows the back grinding of the second chemical mechanical polishing (CMP) according to various embodiments. The second CMP may be used to form recess by removing part of the DTI 418.

[0057] FIG. 4E shows back-to-back (B2B) bonding of two of the two-layer stacked structure formed in FIG. 4D according to various embodiments. The B2B bonding may form a 4-layer stacked structure.

[0058] In other words, the method may include forming a third doped region 404’ in a third substrate 402’; forming DTI 418’ before forming the third doped region 404’; forming a third dielectric layer 406’ in contact with the third substrate 402’; forming one or more third interconnects 408’ so that the one or more third interconnects 408’ are in electrical connection with the third doped region 404’ and extends from a first surface of the third dielectric layer 406’ to a second surface of the third dielectric layer 406’ opposite the first surface of the third dielectric layer 406’. [0059] The method may also include forming a fourth doped region 4l2’in a fourth substrate 410’; forming DTI 420’ before forming the fourth doped region 412’; forming a fourth dielectric layer 414’ in contact with the fourth substrate 410’; forming one or more fourth interconnects 416’ so that the one or more fourth interconnects 416’ are in electrical connection with the fourth doped region 412’ and extends from a first surface of the fourth dielectric layer 414’ to a second surface of the fourth dielectric layer 414’ opposite the first surface of the fourth dielectric layer 414’. The method may further include bonding the third dielectric layer 406’ with the fourth dielectric layer 414’ so that the one or more third interconnects 408’ are in electrical connection with the one or more fourth interconnects 416’. The method may additionally include removing a portion of the third substrate 402’ so that the third doped region 404’ extends from a first surface of the thinned third substrate 402’ to a second surface of the thinned third substrate 402’ opposite the first surface of the thinned third substrate 402’.

[0060] The method may further include bonding the thinned first substrate 402 and the thinned third substrate 402’ so that the first doped region 404 is in contact with the third doped region 404’.

[0061] Steps 4 - 7 may be repeated to form a stacked arrangement including 8 or more device substrates or wafers.

[0062] FIGS. 5 A - E show a method of forming a stacked arrangement according to various other embodiments. The DTI 518 may be formed or fabricated after substrate or wafer stacking and thinning. The DTI process is not used for most semiconductor devices. As such, if the DTI process is moved to downstream steps after device wafer fabrication, it may allow the supply chain to be more flexible, and may reduce the reliance on the capability of the foundry to provide the DTI process.

[0063] FIG. 5A shows implantation of ions onto a first substrate 502, and forming of a first dielectric layer 506 on the first substrate 502 according to various embodiments. In step (1), high energy implantation followed by annealing may form the first doped regions 504 in the first substrate 502 for vertical 3D interconnection.

[0064] In step (2), the first dielectric layer 506 may be formed on or over the first substrate 502. The first dielectric layer 506 may include a plurality of sub-layers. One or more first interconnects 508 may also be formed so that the one or more first interconnects 508 are in electrical connection with the first doped region 504 and extends from a first surface of the first dielectric layer 506 to a second surface of the first dielectric layer 506 opposite the first surface of the first dielectric layer 506. The first dielectric layer 506 and the one or more first interconnects 508 may be formed by complementary metal oxide semiconductor (CMOS) process and multi-layer interconnect process. The one or more first interconnects 508 may include metal pads which are exposed on the planarized top surface of the first dielectric layer 506.

[0065] FIG. 5B shows bonding of two device substrates or wafers via hybrid bonding according to various embodiments. The top device substrate or wafer may include the first substrate 502 with the first doped regions 504, as well as the first dielectric layer 506 with first interconnects 508 on or over the first substrate 502, and may be formed using the processes illustrated in FIG. 5A. The bottom device substrate or wafer may include the second substrate 510 with the second doped regions 512, as well as the second dielectric layer 514 with second interconnects 516 on or over the second substrate 510, and may also be formed using the processes as illustrated for the top device substrate or wafer, i.e. similar to that illustrated in FIG. 5A. The two device substrates or wafers may be bonded via metal/oxide hybrid bonding, and may be annealed for mutual diffusion at the metal interface. The one or more first interconnects 508 and the one or more second interconnects 516 may include copper (Cu), which may be suitable for hybrid bonding.

[0066] FIG. 5C shows back grinding and polishing of the top device substrate or wafer as well as forming deep trenches surrounding the first doped regions 504 according to various embodiments. As shown in FIG. 5C, a portion of the first substrate 502 is removed until the first doped regions 504, i.e. the deepest wells, is exposed. The deep trenches may then be formed surrounding the first doped regions 504, i.e. the deepest wells.

[0067] FIG. 5D shows the forming of deep trench isolation (DTI) according to various embodiments. A dielectric material such as silicon dioxide (Si0₂) may be deposited via chemical vapour deposition (CVD) to fill the deep trenches, thereby forming the DTI 518. Chemical mechanical polishing (CMP) to reduce the silicon dioxide (Si0₂) overburden and to form remove at least a portion of the DTI 518 to form recesses.

[0068] FIG. 5E shows back-to-back (B2B) bonding of two of the two-layer stacked structure formed in FIG. 5D according to various embodiments. The B2B bonding may form a 4-layer stacked structure. [0069] In other words, the method may include forming a third doped region 504’ in a third substrate 502’; forming a third dielectric layer 506’ in contact with the third substrate 502’; forming one or more third interconnects 508’ so that the one or more third interconnects 508’ are in electrical connection with the third doped region 504’ and extends from a first surface of the third dielectric layer 506’ to a second surface of the third dielectric layer 506’ opposite the first surface of the third dielectric layer 506’.

[0070] The method may also include forming a fourth doped region 5l2’in a fourth substrate 510’; forming a fourth dielectric layer 514’ in contact with the fourth substrate 510’; forming one or more fourth interconnects 516’ so that the one or more fourth interconnects 516’ are in electrical connection with the fourth doped region 512’ and extends from a first surface of the fourth dielectric layer 514’ to a second surface of the fourth dielectric layer 514’ opposite the first surface of the fourth dielectric layer 514’. The method may further include bonding the third dielectric layer 506’ with the fourth dielectric layer 514’ so that the one or more third interconnects 508’ are in electrical connection with the one or more fourth interconnects 516’. The method may additionally include removing a portion of the third substrate 502’ so that the third doped region 504’ extends from a first surface of the thinned third substrate 502’ to a second surface of the thinned third substrate 502’ opposite the first surface of the thinned third substrate 502’. The method may also include forming a trench around the third doped region 504’, and depositing silicon dioxide (Si0₂) via chemical vapour deposition (CVD) in the trench to form DTI 518’.

[0071 ] The method may further include bonding the thinned first substrate 502 and the thinned third substrate 502’ so that the first doped region 504 is in contact with the third doped region 504’.

[0072] Steps 3 - 6 may be repeated to form a stacked arrangement including 8 or more device substrates or wafers.

[0073] FIGS. 6A - E show a method of forming a stacked arrangement according to yet various other embodiments. The DTI 618 may be fabricated or formed after substrate or wafer stacking and thinning. The backside silicon dioxide (Si0₂) may not be completely removed by Si0₂ CMP except portions directly on the doped regions 604, i.e. the deepest wells. This may increase the misalignment tolerance. The height of the doped regions 604 may be slightly higher compared to the rest of the substrate 602 after back grinding and DTI etching. [0074] FIG. 6A shows implantation of ions onto a first substrate 602, and forming of a first dielectric layer 606 on the first substrate 602 according to various embodiments. In step (1), high energy implantation followed by annealing may form the first doped regions 604 in the first substrate 602 for vertical 3D interconnection.

[0075] In step (2), the first dielectric layer 606 may be formed on or over the first substrate 602. The first dielectric layer 606 may include a plurality of sub-layers. One or more first interconnects 608 may also be formed so that the one or more first interconnects 608 are in electrical connection with the first doped region 604 and extends from a first surface of the first dielectric layer 606 to a second surface of the first dielectric layer 606 opposite the first surface of the first dielectric layer 606. The first dielectric layer 606 and the one or more first interconnects 608 may be formed by complementary metal oxide semiconductor (CMOS) process and multi-layer interconnect process. The one or more first interconnects 608 may include metal pads which are exposed on the planarized top surface of the first dielectric layer 606.

[0076] FIG. 6B shows bonding of two device substrates or wafers via hybrid bonding according to various embodiments. The top device substrate or wafer may include the first substrate 602 with the first doped regions 604, as well as the first dielectric layer 606 with first interconnects 608 on or over the first substrate 602, and may be formed using the processes illustrated in FIG. 6A. The bottom device substrate or wafer may include the second substrate 610 with the second doped regions 612, as well as the second dielectric layer 614 with second interconnects 616 on or over the second substrate 610, and may also be formed using the processes similar to the processes for the top device substrate or wafer, i.e. those illustrated in FIG. 6A. The two device substrates or wafers may be bonded via metal/oxide hybrid bonding, and may be annealed for mutual diffusion at the metal interface. The one or more first interconnects 608 and the one or more second interconnects 616 may include copper (Cu), which may be suitable for hybrid bonding.

[0077] FIG. 6C shows back grinding and polishing of the top device substrate or wafer as well as forming deep trenches surrounding the first doped regions 604 according to various embodiments. As shown in FIG. 6C, the portion of the first substrate 602 may be removed in such a manner that the first doped regions 604 protrude out from the thinned first substrate 602. The deep trenches may then be formed surrounding the first doped regions 604, i.e. the deepest wells. [0078] FIG. 6D shows the forming of deep trench isolation (DTI) according to various embodiments. A dielectric material such as silicon dioxide (Si0₂) may be deposited via chemical vapour deposition (CVD) to fill the deep trenches, thereby forming the DTI 618. In addition, the dielectric material may also be deposited on the first surface of the thinned first substrate. A CMP may be carried out to planarize the backside surface to form dielectric layer 622 (alternatively referred to as passivation layer). The surface of the dielectric layer 622 may be flushed with the surface of the doped regions 604.

[0079] FIG. 6E shows back-to-back (B2B) bonding of two of the two-layer stacked structure formed in FIG. 6D according to various embodiments. The B2B bonding may form a 4-layer stacked structure.

[0080] In other words, the method may include forming a third doped region 604’ in a third substrate 602’; forming a third dielectric layer 606’ in contact with the third substrate 602’; forming one or more third interconnects 608’ so that the one or more third interconnects 608’ are in electrical connection with the third doped region 604’ and extends from a first surface of the third dielectric layer 606’ to a second surface of the third dielectric layer 606’ opposite the first surface of the third dielectric layer 606’.

[0081] The method may also include forming a fourth doped region 6l2’in a fourth substrate 610’; forming a fourth dielectric layer 614’ in contact with the fourth substrate 610’; forming one or more fourth interconnects 616’ so that the one or more fourth interconnects 616’ are in electrical connection with the fourth doped region 612’ and extends from a first surface of the fourth dielectric layer 614’ to a second surface of the fourth dielectric layer 614’ opposite the first surface of the fourth dielectric layer 614’. The method may further include bonding the third dielectric layer 606’ with the fourth dielectric layer 614’ so that the one or more third interconnects 608’ are in electrical connection with the one or more fourth interconnects 616’. The method may additionally include removing a portion of the third substrate 602’ in such a manner that the third doped regions 604’ protrude out from the thinned third substrate 602’, forming of trenches around the third doped regions 604’, as well as forming of DTI 618’ and dielectric layer 622’.

[0082] The method may further include bonding the thinned first substrate 602 and the thinned third substrate 602’ so that the first doped region 604 is in contact with the third doped region 604’. The dielectric layers 622, 622 may also be bonded together. [0083] Steps 4 - 6 may be repeated to form a stacked arrangement including 8 or more device substrates or wafers.

[0084] FIGS. 7 A - E show a method of forming a stacked arrangement according to yet various other embodiments. The DTI 718 may be fabricated after wafer or substrate stacking and thinning. When the substrate 702 is etched for trench fabrication, the top opening may be made wider to increase bonding misalignment tolerance.

[0085] FIG. 7A shows implantation of ions onto a first substrate 702, and forming of a first dielectric layer 706 on the first substrate 702 according to various embodiments. In step (1), high energy implantation followed by annealing may form the first doped regions 704 in the first substrate 702 for vertical 3D interconnection.

[0086] In step (2), the first dielectric layer 706 may be formed on or over the first substrate 702. The first dielectric layer 706 may include a plurality of sub-layers. One or more first interconnects 708 may also be formed so that the one or more first interconnects 708 are in electrical connection with the first doped region 704 and extends from a first surface of the first dielectric layer 706 to a second surface of the first dielectric layer 706 opposite the first surface of the first dielectric layer 706. The first dielectric layer 706 and the one or more first interconnects 708 may be formed by complementary metal oxide semiconductor (CMOS) process and multi-layer interconnect process. The one or more first interconnects 708 may include metal pads which are exposed on the planarized top surface of the first dielectric layer 706.

[0087] FIG. 7B shows bonding of two device substrates or wafers via hybrid bonding according to various embodiments. The top device substrate or wafer may include the first substrate 702 with the first doped regions 704, as well as the first dielectric layer 706 with first interconnects 708 on or over the first substrate 702, and may be formed using the processes illustrated in FIG. 7A. The bottom device substrate or wafer may include the second substrate 710 with the second doped regions 712, as well as the second dielectric layer 714 with second interconnects 716 on or over the second substrate 710, and may also be formed using the processes similar to the processes for the top device substrate or wafer, i.e. those illustrated in FIG. 7A. The two device substrates or wafers may be bonded via metal/oxide hybrid bonding, and may be annealed for mutual diffusion at the metal interface. The one or more first interconnects 708 and the one or more second interconnects 716 may include copper (Cu), which may be suitable for hybrid bonding. [0088] FIG. 7C shows back grinding and polishing of the top device substrate or wafer as well as forming deep trenches surrounding the first doped regions 704 according to various embodiments. As shown in FIG. 7C, trenches may be formed such that they are wider at the first surface (of the thinned first substrate 702) relative to at the second surface (of the thinned first substrate 702). The trenches may be formed by etching the thinned substrate 702, which may be a Si substrate.

[0089] FIG. 7D shows the forming of deep trench isolation (DTI) according to various embodiments. A dielectric material such as silicon dioxide (Si0₂) may be deposited via chemical vapour deposition (CVD) to fill the deep trenches. Chemical mechanical polishing (CMP) may be used to remove Si0₂ overburden and form the DTI 718.

[0090] FIG. 7E shows back-to-back (B2B) bonding of two of the two-layer stacked structure formed in FIG. 7D according to various embodiments. The B2B bonding may form a 4-layer stacked structure.

[0091] In other words, the method may include forming a third doped region 704’ in a third substrate 702’; forming a third dielectric layer 706’ in contact with the third substrate 702’; forming one or more third interconnects 708’ so that the one or more third interconnects 708’ are in electrical connection with the third doped region 704’ and extends from a first surface of the third dielectric layer 706’ to a second surface of the third dielectric layer 706’ opposite the first surface of the third dielectric layer 706’.

[0092] The method may also include forming a fourth doped region 7l2’in a fourth substrate 710’; forming a fourth dielectric layer 714’ in contact with the fourth substrate 710’; forming one or more fourth interconnects 716’ so that the one or more fourth interconnects 716’ are in electrical connection with the fourth doped region 712’ and extends from a first surface of the fourth dielectric layer 714’ to a second surface of the fourth dielectric layer 714’ opposite the first surface of the fourth dielectric layer 714’. The method may further include bonding the third dielectric layer 706’ with the fourth dielectric layer 714’ so that the one or more third interconnects 708’ are in electrical connection with the one or more fourth interconnects 716’. The method may additionally include removing a portion of the third substrate 702’ in such a manner that the third doped regions 704’ protrude out from the thinned third substrate 702’, forming of trenches around the third doped regions 704’, as well as forming of DTI 718’. [0093] The method may further include bonding the thinned first substrate 702 and the thinned third substrate 702’ so that the first doped region 704 is in contact with the third doped region 704’.

[0094] Steps 4 - 6 may be repeated to form a stacked arrangement including 8 or more device substrates or wafers.

[0095] FIGS. 8A - E show a method of forming a stacked arrangement according to yet various other embodiments. Various embodiments may not include deep trench isolation (DTI). Isolation may be achieved instead by reverse biasing at a p-n junction formed between the doped regions 804 (i.e. deepest wells) and the substrate 802. The doped regions 804 may protrude from the substrate 802. Chemical and mechanical polishing (CMP) and back grinding may result in the formation of the protrusions. The difference in hardness between heavily doped silicon and a normal silicon substrate may cause the protrusions to form. The protrusion may also be made by lithography patterning and slight silicon dry etching.

[0096] FIG. 8A shows implantation of ions onto a first substrate 802, and forming of a first dielectric layer 806 on the first substrate 802 according to various embodiments. In step (1), high energy implantation followed by annealing may form the first doped regions 804 in the first substrate 802 for vertical 3D interconnection.

[0097] In step (2), the first dielectric layer 806 may be formed on or over the first substrate 802. The first dielectric layer 806 may include a plurality of sub-layers. One or more first interconnects 808 may also be formed so that the one or more first interconnects 808 are in electrical connection with the first doped region 804 and extends from a first surface of the first dielectric layer 806 to a second surface of the first dielectric layer 806 opposite the first surface of the first dielectric layer 806. The first dielectric layer 806 and the one or more first interconnects 808 may be formed by complementary metal oxide semiconductor (CMOS) process and multi-layer interconnect process. The one or more first interconnects 808 may include metal pads which are exposed on the planarized top surface of the first dielectric layer 806.

[0098] FIG. 8B shows bonding of two device substrates or wafers via hybrid bonding according to various embodiments. The top device substrate or wafer may include the first substrate 802 with the first doped regions 804, as well as the first dielectric layer 806 with first interconnects 808 on or over the first substrate 802, and may be formed using the processes similar to the processes for the top device substrate or wafer, i.e. those illustrated in FIG. 8A. The bottom device substrate or wafer may include the second substrate 810 with the second doped regions 812, as well as the second dielectric layer 814 with second interconnects 816 on or over the second substrate 810, and may also be formed using the processes similar to the processes for the top device substrate or wafer, i.e. those illustrated in FIG. 8A. The two device substrates or wafers may be bonded via metal/oxide hybrid bonding, and may be annealed for mutual diffusion at the metal interface. The one or more first interconnects 808 and the one or more second interconnects 816 may include copper (Cu), which may be suitable for hybrid bonding.

[0099] FIG. 8C shows back grinding and polishing of the top device substrate or wafer according to various embodiments. The portion of the first substrate 802 may be removed in such a manner that the first doped regions 804 protrude out from the thinned first substrate 802.

[00100] FIG. 8D shows the depositing a dielectric material on the first surface of the thinned first substrate 802 according to various embodiments. A portion of the deposited dielectric material may be removed (e.g. via CMP) so that a further portion of the deposited dielectric material remaining on the first surface of the thinned first substrate is planarized, thereby exposing doped regions 804 and forming dielectric layer 822 (alternatively referred to as passivation layer).

[00101] FIG. 8E shows back-to-back (B2B) bonding of two of the two-layer stacked structure formed in FIG. 8D according to various embodiments. The B2B bonding may form a 4-layer stacked structure.

[00102] In other words, the method may include forming a third doped region 804’ in a third substrate 802’; forming a third dielectric layer 806’ in contact with the third substrate 802’; forming one or more third interconnects 808’ so that the one or more third interconnects 808’ are in electrical connection with the third doped region 804’ and extends from a first surface of the third dielectric layer 806’ to a second surface of the third dielectric layer 806’ opposite the first surface of the third dielectric layer 806’.

[00103] The method may also include forming a fourth doped region 8l2’in a fourth substrate 810’; forming a fourth dielectric layer 814’ in contact with the fourth substrate 810’; forming one or more fourth interconnects 816’ so that the one or more fourth interconnects 816’ are in electrical connection with the fourth doped region 812’ and extends from a first surface of the fourth dielectric layer 814’ to a second surface of the fourth dielectric layer 814’ opposite the first surface of the fourth dielectric layer 814’. The method may further include bonding the third dielectric layer 806’ with the fourth dielectric layer 814’ so that the one or more third interconnects 808’ are in electrical connection with the one or more fourth interconnects 816’. The method may additionally include removing a portion of the third substrate 802’ in such a manner that the third doped regions 804’ protrude out from the thinned third substrate 802’ as well as forming of dielectric layer 822’.

[00104] The method may further include bonding the thinned first substrate 802 and the thinned third substrate 802’ so that the first doped region 804 is in contact with the third doped region 804’.

[00105] Steps 4 - 6 may be repeated to form a stacked arrangement including 8 or more device substrates or wafers.

[00106] FIGS. 9A - E show a method of forming a stacked arrangement according to yet various other embodiments. Various embodiments may not include deep trench isolation (DTI). Isolation may be achieved instead by reverse biasing at a p-n junction formed between the doped regions 904 (i.e. deepest wells) and the substrate 902. In addition, a dielectric layer or passivation layer may not be used at the backside of the substrate 902. In such as case, leak current may be generated at bonding interface where discontinuity of (e.g. Si) single crystal exists. In order to prevent or mitigate the leak current, dielectric (e.g. Si0₂) passivation may be fabricated only surrounding the doped regions 904 (e.g. deepest well).

[00107] FIG. 9A shows implantation of ions onto a first substrate 902, and forming of a first dielectric layer 906 on the first substrate 902 according to various embodiments. In step (1), high energy implantation followed by annealing may form the first doped regions 904 in the first substrate 902 for vertical 3D interconnection.

[00108] In step (2), the first dielectric layer 906 may be formed on or over the first substrate 902. The first dielectric layer 906 may include a plurality of sub-layers. One or more first interconnects 908 may also be formed so that the one or more first interconnects 908 are in electrical connection with the first doped region 904 and extends from a first surface of the first dielectric layer 906 to a second surface of the first dielectric layer 906 opposite the first surface of the first dielectric layer 906. The first dielectric layer 906 and the one or more first interconnects 908 may be formed by complementaiy metal oxide semiconductor (CMOS) process and multi-layer interconnect process. The one or more first interconnects 908 may include metal pads which are exposed on the planarized top surface of the first dielectric layer 906. [00109] FIG. 9B shows bonding of two device substrates or wafers via hybrid bonding according to various embodiments. The top device substrate or wafer may include the first substrate 902 with the first doped regions 904, as well as the first dielectric layer 906 with first interconnects 908 on or over the first substrate 902, and may be formed using the processes illustrated in FIG. 9A. The bottom device substrate or wafer may include the second substrate 910 with the second doped regions 912, as well as the second dielectric layer 914 with second interconnects 916 on or over the second substrate 910, and may also be formed using the processes similar to the processes for the top device substrate or wafer, i.e. those illustrated in FIG. 9A. The two device substrates or wafers may be bonded via metal/oxide hybrid bonding, and may be annealed for mutual diffusion at the metal interface. The one or more first interconnects 908 and the one or more second interconnects 916 may include copper (Cu), which may be suitable for hybrid bonding.

[00110] FIG. 9C shows back grinding and polishing of the top device substrate or wafer according to various embodiments. The portion of the first substrate 902 may be removed in such a manner that the first doped regions 904 protrude out from the thinned first substrate 902.

[00111] FIG. 9D shows deposition of a dielectric material and subsequent removal of a portion of the dielectric material to form passivation structures 918 around the doped regions 904 according to various embodiments. The method may include removing a region of the thinned first substrate 902 adjacent to a top region of the first doped region 904 to form a passivation groove, depositing the dielectric material (e.g. Si0₂) in the passivation groove to form the passivation structure around the top region of a first doped region 904, and on the first surface of the thinned first substrate 902. The method may further include removing the deposited material on the first surface of the thinned first substrate, thereby forming the passivation structures 918 within the passivation grooves.

[00112] FIG. 9E shows back-to-back (B2B) bonding of two of the two-layer stacked structure formed in FIG. 9D according to various embodiments. The B2B bonding may form a 4-layer stacked structure.

[00113] In other words, the method may include forming a third doped region 904’ in a third substrate 902’; forming a third dielectric layer 906’ in contact with the third substrate 902’; forming one or more third interconnects 908’ so that the one or more third interconnects 908’ are in electrical connection with the third doped region 904’ and extends from a first surface of the third dielectric layer 906’ to a second surface of the third dielectric layer 906’ opposite the first surface of the third dielectric layer 906’.

[00114] The method may also include forming a fourth doped region 9l2’in a fourth substrate 910’; forming a fourth dielectric layer 914’ in contact with the fourth substrate 910’; forming one or more fourth interconnects 916’ so that the one or more fourth interconnects 916’ are in electrical connection with the fourth doped region 912’ and extends from a first surface of the fourth dielectric layer 914’ to a second surface of the fourth dielectric layer 914’ opposite the first surface of the fourth dielectric layer 914’. The method may further include bonding the third dielectric layer 906’ with the fourth dielectric layer 914’ so that the one or more third interconnects 908’ are in electrical connection with the one or more fourth interconnects 916’. The method may additionally include removing a portion of the third substrate 902’ and forming of passivation structures 918’.

[00115] The method may further include bonding the thinned first substrate 902 and the thinned third substrate 902’ so that the first doped region 904 is in contact with the third doped region 904’.

[00116] Steps 4 - 6 may be repeated to form a stacked arrangement including 8 or more device substrates or wafers.

[00117] FIG. 10 shows a portion of a stacked arrangement according to various embodiments. FIG. 10 shows the interface between a thinned first substrate 1002 and a thinned third substrate 1002’. The first dielectric layer 1006 with the one or more one or more first interconnects 1008 may be in contact with the thinned first substrate 1002, while the third dielectric layer 1006’ with the one or more one or more third interconnects 1008’ may be in contact with the thinned third substrate 1002’.

[00118] As also shown in FIG. 10, the first doped region 1004 and the third doped region 1004’ may be in contact with each other. The first doped region 1004 may be the deepest well in the thinned first substrate 1002, and the third doped region 1004’ may be the deepest well in the thinned third substrate 1002’. In addition to the first doped region 1004, the thinned first substrate 1002 may also include other wells, such as n-well l024a, p-well l024b, and deep n-well l024c. Similarly, in addition to the third doped region 1004’, the thinned third substrate 1004’ may also include other wells, such as n-well l024a’, p-well l024b’, and deep n-well l024c’. During the thinning process (such as steps 5 and 6 shown in FIG. 4C and Fig. 4D respectively), these other wells (such as wells l024a-c, l024a’-c’) may not be exposed. Additionally, if the substrate 1002, 1002’ is a p-type substrate, the substrate 1002, 1002’ may further include a depletion region at the bottom or interface of the n- wells of the substrate 1002, 1002’. The thinning process may not also reach this depletion region. If the thinning reaches this depletion region, it may result in leakage current and affect the device characteristics. Accordingly, there may be a need for precise control of the TTV of the substrate. In addition, wafer bonding misalignment may be required to be taken into consideration. If ground voltage is applied to the deepest well 1004, 1004’, the misalignment may not cause significant problem from leakage current point of views. Trench isolation may also not be necessary. However, if supply voltage or negative voltage is applied to the deepest wells 1004, 1004’, the DTI may need to take into account the misalignment to avoid contact between the deepest well 1004, 1004’ and the respective substrate 1002, 1002’.

[00119] FIG. 11 shows a portion of a stacked arrangement according to various embodiments to illustrate accommodation of misalignment between the substrates or wafers 1102, 1102’ in back- to-back (B2B) bonding. The first wafer or substrate 1102 may include first doped regions 1 l04a, 1 l04b connected to first interconnects 1108 in first dielectric layer 1106, while the second wafer or substrate 1102’ may include third doped regions 1104a’, 1104b’ connected to third interconnects 1108’ in third dielectric layer 1106’. The first doped region 1104a in the first substrate 1102, and the third doped region 1 l04a’ in the third substrate 1102’ may be at ground- level voltage. As the substrates 1 102, 1102’ are at the same electric potential as the doped regions 1104a, 1104a’, there may be not much of an issue involving the doped regions 1104a, 1104a’ contacting the substrates 1102, 1102’. On the other hand, supply voltage and/or signal input/output (I/O) pins may be required to be electrically isolated from substrates 1102, 1102’. The first doped region 1 l04b in the first substrate 1102, and the third doped region 1 l04b’ in the third substrate 1102’ may be at a positive voltage or a negative voltage. In this case, width of DTI 1118, 1118’ may be required to greater than the amount of wafer-to-wafer misalignment to avoid short circuit.

[00120] Wafer-to-wafer misalignment may generally be about ±0.5 um ~ several microns depending on wafer bonder capability. This means DTI width of 1 um or more may be necessary to accommodate the misalignment. Dielectric (e.g.Si0₂) filling and subsequent planarization of device surface may be challenging to make such wide DTI. [00121] FIG. 12 shows a portion of a stacked arrangement according to various other embodiments to illustrate accommodation of misalignment between the substrates or wafers 1202, 1202’ in back-to-back (B2B) bonding. The first wafer or substrate 1202 may include first doped regions l204a, l204b connected to first interconnects 1208 in first dielectric layer 1206, while the second wafer or substrate 1202’ may include third doped regions l204a’, l204b’ connected to third interconnects 1208’ in third dielectric layer 1206’. The first doped region l204a in the first substrate 1202, and the third doped region l204a’ in the third substrate 1202’ may be at ground- level voltage. As highlighted above, since the substrates 1202, 1202’ are at the same electric potential as the doped regions 1204, 1204’, there may be not much of an issue involving the doped regions l204a, l204a’ contacting the substrates 1202, 1202’. On the other hand, as also highlighted above, the supply voltage and/or signal input/output (I/O) pins may be required to be electrically isolated from substrates 1202, 1202’. The first doped region l204b in the first substrate 1202, and the third doped region l204b’ in the third substrate 1202’ may be at a positive voltage or a negative voltage. The first substrate 1202 may include an inner DTI ring 1218a and an outer DTI ring l2l8b. Similarly, the third substrate 1202’ may include an inner DTI ring 1218a’ and an outer DTI ring 1218b’ . The inner DTI rings l2l8a, l2l8a’ may each have a width smaller than about lum. The outer DTI rings 1218b, 1218b’ may be fabricated to prevent short failure by misalignment. The outer DTI rings 1218b, 1218b’ may each also have a width smaller than about lum. Accordingly, narrow DTI of less than about lum width may also be used for electrical isolation of vertical interconnections.

[00122] Increasing bandwidth requirement of high-speed electronic systems may require electronic packaging technologies to be developed to meet fine-pitch IO requirements. In this work, various embodiments may involve using wafer-level stacking process without using TSV. Various embodiments may allow for a greater flexibility for signal and power/IO routing in a small form factor. Various embodiments may relate, but may not be limited to stacked dynamic random- access memory (DRAM), stacked NAND flash, memory/logic three-dimensional silicon-in package (3D-SiP), three-dimensional field-programmable gate array (3D FPGA), and image sensor devices etc.

[00123] Various embodiments may relate to 3D integrated circuits (IC) using doped diffusion layer for vertical connection by B2B bonding. Various embodiments may relate to metal hybrid face-to-face (F2F) combined with doped semiconductor, e.g. doped silicon, B2B bonding for vertical connections in a multi-layer structure.

[00124] DTI may be fabricated to isolate the doped semiconductor connections. DTI may work as CMP stopping layer to improve TTV to reduce or prevent device performance variation.

[00125] Various embodiments may not require TSVs to enable vertical connections. Temporary bonding and debonding (TBDB) processes may not be necessary to make 3D stacked devices. Various embodiments may not face the Schottky barrier issue at the bonding interface. Various embodiments may not have metal contamination issue in the complementary metal oxide semiconductor (CMOS) layer.

[00126] The TTV may be precisely controlled to prevent or reduce resistance variation of vertical connections as well as device performance degradation. The device structure may be symmetrical, resulting in low warpage by cancelling or reducing internal stress.

[00127] DTIs may be fabricated on a semiconductor substrate, e.g. a silicon substrate. Part of the DTIs may surround the deepest wells fabricated in subsequent steps.

[00128] Highly doped wells may be fabricated by implantation and annealing to form the deepest well for vertical connections. After CMOS and multi-layer metal layer fabrication, hybrid bonding may be conducted by F2F bonding to make 2-layer stack. In Step A, one of the substrates, e.g. Si substrates, may be thinned by back grinding and a I^st CMP until DTIs are exposed. In Step B, a second CMP may be carried out to remove the Si damaged layer and to form recessed DTIs. In Step C, Si/Si B2B bonding may be carried out to form a 4-layers stacks. Steps A-C may be repeated for further stacking if necessary.

[00129] Various embodiments may be of low cost. Various embodiments may be high throughput wafer stacking methods. Various embodiments may relate to 3DIC with ultra-thin layers of less than about 10 mih per layer. Various embodiments may relate to a multiple layer stacking device of more than 8 layers for memory applications such as dynamic random access memory (DRAM) and NAND FLASH.

[00130] As mentioned above, various embodiments may not require TSV or TBDB processes, resulting in cost-effective process, and shorter lead-times of fabrication.

[00131] In addition, various embodiments may have high manufacturability due to parallel processes of F2F and B2B bonding. [00132] Various embodiments may include DTI for isolation and precise TTV control.

[00133] Various embodiments may face higher resistance compared to metal TSVs. The I/O pads may be required to be fabricated on back surface of top layer.

[00134] There may be process integration (PI) improvement by shortest interconnections. There may be system integration (SI) improvement through low parasitic capacitance due to F2F and B2B stacking.

[00135] Various embodiments may enable high-density inter-chip interconnections which are required for high bandwidth memory.

[00136] Various embodiments may be integrated with logic devices such as central processing units (CPUs) and graphic processing units (GPUs) with high bandwidth connections to stacked DRAMs.

[00137] Various embodiments may relate to 3DIC integration by using wafer stacking processes.

[00138] Various embodiments may be used for stacked memory and CPU/memory application. Costs may be reduced compared to current chip stacking products.

[00139] Various embodiments may be cost effective and/or be easily detectable.

[00140] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

Claims

1. A method of forming a stacked arrangement, the method comprising:

forming a first doped region in a first substrate;

forming a first dielectric layer in contact with the first substrate; forming one or more first interconnects so that the one or more first interconnects are in electrical connection with the first doped region and extends from a first surface of the first dielectric layer to a second surface of the first dielectric layer opposite the first surface of the first dielectric layer;

forming a second doped region in a second substrate;

forming a second dielectric layer in contact with the second substrate;

forming one or more second interconnects so that the one or more second interconnects are in electrical connection with the second doped region and extends from a first surface of the second dielectric layer to a second surface of the second dielectric layer opposite the first surface of the second dielectric layer; bonding the first dielectric layer with the second dielectric layer so that the one or more first interconnects are in electrical connection with the one or more second interconnects; and

removing a portion of the first substrate so that the first doped region extends from a first surface of the thinned first substrate to a second surface of the thinned first substrate opposite the first surface of the thinned first substrate.

2. The method of claim 1, further comprising:

forming a third doped region in a third substrate;

forming a third dielectric layer in contact with the third substrate; forming one or more third interconnects so that the one or more third interconnects are in electrical connection with the third doped region and extends from a first surface of the third dielectric layer to a second surface of the third dielectric layer opposite the first surface of the third dielectric layer; forming a fourth doped region in a fourth substrate;

forming a fourth dielectric layer in contact with the fourth substrate; forming one or more fourth interconnects so that the one or more fourth interconnects are in electrical connection with the fourth doped region and extends from a first surface of the fourth dielectric layer to a second surface of the fourth dielectric layer opposite the first surface of the fourth dielectric layer; bonding the third dielectric layer with the fourth dielectric layer so that the one or more third interconnects are in electrical connection with the one or more fourth interconnects;

removing a portion of the third substrate so that the third doped region extends from a first surface of the thinned third substrate to a second surface of the thinned third substrate opposite the first surface of the thinned third substrate; and bonding the thinned first substrate and the thinned third substrate so that the first doped region is in contact with the third doped region.

3. The method of claim 1, further comprising:

forming a deep trench isolation ring in the first substrate before forming the first doped region; and

forming a deep trench isolation ring in the second substrate before forming the second doped region;

wherein the first doped region is formed within a perimeter defined by the deep trench isolation ring formed in the first substrate; and

wherein the second doped region is formed within a perimeter defined by the deep trench isolation ring formed in the second substrate.

4. The method of claim 1, further comprising:

removing a portion of the thinned first substrate surrounding the first doped region to form a trench; and depositing a dielectric material into the trench to form a deep trench isolation ring, and on the first surface of the thinned first substrate; and

removing a portion of the deposited material on the first surface of the thinned first substrate.

5. The method of claim 1,

wherein the portion of the first substrate is removed in such a manner that the first doped region protrudes out from the thinned first substrate;

wherein the method further comprises removing a portion of the thinned first substrate surrounding the first doped region to form a trench;

wherein the method also comprises depositing a dielectric material into the trench to form a deep trench isolation ring, and on the first surface of the thinned first substrate; and

wherein the method also comprises removing a portion of the deposited dielectric material on the first surface of the thinned first substrate so that a further portion of the deposited material remaining on the first surface of the thinned first substrate is planarized, thereby exposing the first doped region to the second surface of the thinned first substrate opposite the first surface of the thinned first substrate.

6. The method of claim 1, further comprising:

removing a portion of the thinned first substrate surrounding the first doped region to form a trench extending from the first surface of the thinned first substrate to the second surface of the thinned first substrate, the trench wider at the first surface relative to at the second surface; and

depositing a dielectric material into the trench and on the first surface of the thinned first substrate; and

removing a portion of the deposited dielectric material on the first surface of the thinned first substrate to form a deep trench isolation ring.

7. The method of claim 3, further comprising: forming a first outer deep trench isolation ring such that that the first outer deep trench isolation ring surrounds the first deep trench isolation ring; and

forming a second outer deep trench isolation ring such that the second outer deep trench isolation ring surrounds the second deep trench isolation ring.

8. The method of claim 1,

wherein the method further comprises depositing a dielectric material on the first surface of the thinned first substrate; and

wherein the method also comprises removing a portion of the deposited dielectric material so that a further portion of the deposited dielectric material remaining on the first surface of the thinned first substrate is planarized.

9. The method of claim 1,

wherein the method further comprises removing a further region of the thinned first substrate adjacent to a top region of the first doped region to form a passivation groove; and

wherein the method also comprises depositing a dielectric material in the passivation groove to form a passivation structure around the top region of the first doped region, and on the first surface of the thinned first substrate; and

wherein the method also comprises removing the deposited material on the first surface of the thinned first substrate.

10. The method of claim 1,

wherein the first substrate comprises one or more further doped regions, each of the one or more further doped regions having a depth less than a depth of the first doped region; and wherein the second substrate comprises one or more further doped regions, each of the one or more further doped regions having a depth less than a depth of the second doped region.

11. The method of claim 2,

wherein the third substrate comprises one or more further doped regions, each of the one or more further doped regions having a depth less than a depth of the third doped region; and

wherein the fourth substrate comprises one or more further doped regions, each of the one or more further doped regions having a depth less than a depth of the fourth doped region.

12. The method of claim 1,

wherein bonding the first dielectric layer with the second dielectric layer comprises hybrid bonding.

13. The method of claim 1,

wherein the one or more first interconnects and the one or more second interconnects comprise copper.

14. The method of claim 2,

wherein the one or more third interconnects and the one or more fourth interconnects comprise copper.

15. A stacked arrangement comprising:

a thinned first substrate comprising a first doped region, the first doped region extending from a first surface of the thinned first substrate to a second surface of the thinned first substrate opposite the first surface of the thinned first substrate;

a first dielectric layer in contact with the thinned first substrate; one or more first interconnects extending from a first surface of the first dielectric layer to a second surface of the first dielectric layer opposite the first surface of the first dielectric layer, the one or more first interconnects in electrical connection with the first doped region;

a second substrate comprising a second doped region;

a second dielectric layer in contact with the second substrate;

one or more second interconnects extending from a first surface of the second dielectric layer to a second surface of the second dielectric layer opposite the first surface of the second dielectric layer, the one or more second interconnects in electrical connection with the second doped region;

wherein the first dielectric layer is bonded with the second dielectric layer so that the one or more first interconnects are in electrical connection with the one or more second interconnects.

16. The stacked arrangement of claim 15, further comprising:

a thinned third substrate comprising a third doped region, the third doped region extending from a first surface of the thinned third substrate to a second surface of the thinned third substrate opposite the first surface of the thinned third substrate; a third dielectric layer in contact with the thinned third substrate;

one or more third interconnects extending from a first surface of the third dielectric layer to a second surface of the third dielectric layer opposite the first surface of the third dielectric layer, the one or more third interconnects in electrical connection with the third doped region;

a fourth substrate comprising a fourth doped region;

a fourth dielectric layer in contact with the fourth substrate;

one or more fourth interconnects extending from a first surface of the fourth dielectric layer to a second surface of the fourth dielectric layer opposite the first surface of the fourth dielectric layer, the one or more fourth interconnects in electrical connection with the fourth doped region; wherein the third dielectric layer is bonded with the fourth dielectric layer so that the one or more third interconnects are in electrical connection with the one or more fourth interconnects; and

wherein the thinned first substrate and the thinned third substrate are bonded so that the first doped region is in contact with the third doped region.

17. The stacked arrangement of claim 15,

wherein the thinned first substrate further comprises a deep trench isolation ring surrounding the first doped region.

18. The stacked arrangement of claim 17,

wherein the second substrate further comprises a deep trench isolation ring surrounding the second doped region.

19. The stacked arrangement of claim 16,

wherein the thinned third substrate further comprises a deep trench isolation ring surrounding the third doped region.

20. The stacked arrangement of claim 19,

wherein the fourth substrate further comprises a deep trench isolation ring surrounding the fourth doped region.