WO2020173058A1 - Cmos图像传感器封装模块及其形成方法、摄像装置 - Google Patents

Cmos图像传感器封装模块及其形成方法、摄像装置 Download PDF

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Publication number
WO2020173058A1
WO2020173058A1 PCT/CN2019/102254 CN2019102254W WO2020173058A1 WO 2020173058 A1 WO2020173058 A1 WO 2020173058A1 CN 2019102254 W CN2019102254 W CN 2019102254W WO 2020173058 A1 WO2020173058 A1 WO 2020173058A1
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connection
image sensor
cmos image
interconnection
package module
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PCT/CN2019/102254
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English (en)
French (fr)
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向阳辉
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中芯集成电路（宁波）有限公司
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Priority to KR1020217015009A priority Critical patent/KR20210079333A/ko
Priority to US17/434,638 priority patent/US20220173151A1/en
Publication of WO2020173058A1 publication Critical patent/WO2020173058A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14632—Wafer-level processed structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present invention relates to the field of image sensors, in particular to a CMOS image sensor package module and its forming method, and a camera device.
  • digital cameras are also currently installed on devices such as laptops, tablets, smart phones, and smart toys.
  • Commonly used digital cameras project the generated optical image onto the surface of the photosensitive element through the camera lens.
  • the light is decomposed into different colors by the filter on the surface of the photosensitive element, and each color light is sensed by the pixel unit corresponding to each filter and produces a difference.
  • the intensity of the analog signal is collected by the circuit of the photosensitive element.
  • the analog signal is converted into a digital signal by a digital-to-analog converter, and then the image signal processor (ISP, image signal processor) processes these digital signals. It is sent to the mobile phone processor for processing, and then transferred to the memory card for storage and becomes a viewable image on the screen.
  • ISP image signal processor
  • CMOS Complementary Metal Oxide Semiconductor, complementary metal-oxide-semiconductor
  • CCD Complementary Metal Oxide Semiconductor
  • CMOS image sensors can achieve more flexible image capture, higher sensitivity, wider dynamic range, higher resolution, lower power consumption, and better system integration.
  • the light is incident from the back of the CMOS image sensor and is directed to the photosensitive element without passing through the interconnection layer on the photosensitive element, which reduces the light loss.
  • a single pixel unit can obtain more light energy, which is more effective for painting. The quality has improved significantly.
  • the present invention provides a CMOS image sensor package module and a forming method thereof to optimize the structure of the CMOS image sensor package module and facilitate the improvement of imaging quality when the CMOS image sensor package module is used for shooting.
  • CMOS image sensor package module including:
  • the pixel circuit substrate includes a photosensitive area and a readout circuit area, the pixel array of the CMOS image sensor is arranged in the photosensitive area, the readout circuit is arranged in the readout circuit area, and the readout circuit has a circuit interconnection terminal,
  • the pixel circuit substrate includes a first surface and a second surface opposed to each other; a bonding layer is laid on the first surface; a signal processing chip and a DRAM chip are located on the bonding layer in parallel, and the signal processing chip has an orientation The first connection end and the second connection end of the first surface, the DRAM chip has a third connection end and a fourth connection end facing the first surface; a first interconnection structure, electrically connected to the first connection End and the third connection end, the first interconnection structure includes a first connection block embedded in the bonding layer and a second connection block embedded in the bonding layer, the first connection block and the The first connection end is in contact and electrical connection, the second connection block is in contact and electrical connection with the third connection end, and the first connection block is
  • the first interconnection structure further includes an interconnection member on the first surface, and the first connection block and the second connection block are electrically connected through the interconnection member.
  • the interconnection member includes an interconnection line and a first bonding pad and a second bonding pad located at both ends of the interconnection line, and the first bonding pad is connected to the first bonding pad through the first connection block.
  • the connection end is connected, and the second solder pad is connected to the third connection end through the second connection block.
  • the interconnection member includes an interconnection line, and two ends of the interconnection line are respectively connected to the first connection end through the first connection block, and to the first connection end through the second connection block. Three-terminal connection.
  • first connection block and the second connection block are the same connection block, and the same connection block extends from the first connection end to the third connection end.
  • the second interconnection structure includes a first conductive plug disposed in the pixel circuit substrate, and the first conductive plug electrically connects the circuit interconnection end and the rewiring layer.
  • the circuit interconnection terminal includes a first circuit interconnection terminal and a second circuit interconnection terminal
  • the second interconnection structure includes two of the first conductive plugs to electrically connect the first conductive plugs respectively.
  • the second interconnection structure includes a second conductive plug passing through the pixel circuit substrate and the bonding layer, and the second conductive plug is electrically connected to the second connection terminal and the second connecting terminal. Wiring layer.
  • the second interconnection structure includes a third conductive plug passing through the pixel circuit substrate and the bonding layer, and the third conductive plug is electrically connected to the fourth connection terminal and the second terminal. Wiring layer.
  • the signal processing chip and the DRAM chip are disposed on the first surface corresponding to the readout circuit area.
  • the rewiring layer includes rewiring and bonding pads electrically connected to the rewiring.
  • the CMOS image sensor packaging module further includes an packaging layer disposed on the first surface, and the packaging layer covers the signal processing chip and the DRAM chip and fills gaps.
  • the CMOS image sensor packaging module further includes a dummy chip, the dummy chip is located on the bonding layer, and the packaging layer also covers the dummy chip.
  • the incident light is set to enter the pixel array from a side of the second surface, and the dummy chip is disposed on the first surface corresponding to the photosensitive area.
  • the CMOS image sensor is a back-illuminated CMOS image sensor.
  • the bonding layer includes an adhesive material.
  • an imaging device including the above-mentioned CMOS image sensor package module.
  • CMOS image sensor package module including the following steps:
  • a pixel circuit substrate, a signal processing chip and a DRAM chip are provided.
  • the pixel circuit substrate includes a photosensitive area and a readout circuit area.
  • the pixel array of the CMOS image sensor is arranged in the photosensitive area, and the readout circuit is arranged in the readout circuit area.
  • the readout circuit has a circuit interconnection terminal, the pixel circuit substrate includes a first surface and a second surface opposed to each other, the signal processing chip has a first connection terminal and a second connection terminal, and the DRAM chip has a first connection terminal and a second connection terminal.
  • connection terminals and a fourth connection terminal Three connection terminals and a fourth connection terminal; a bonding layer is formed on the first surface, and the signal processing chip and the DRAM chip are bonded on the bonding layer, the first connection terminal and the second connection End, the third connection end, and the fourth connection end all face the first surface; a first interconnection structure is formed to electrically connect the first connection end and the third connection end, the first An interconnection structure includes a first connection block embedded in the bonding layer and a second connection block embedded in the bonding layer.
  • the first connection block is electrically connected to the first connection terminal, and the second The connection block is electrically connected to the third connection terminal in contact, and the first connection block is electrically connected to the second connection block; forming a second interconnection structure, which is disposed in the pixel circuit substrate and the bonding layer, Are electrically connected to the circuit interconnection terminal, the second connection terminal, and the fourth connection terminal; and a rewiring layer is formed on the second surface, and the rewiring layer is connected to the second interconnection structure Electric connection.
  • the method for forming the CMOS image sensor package module further includes: forming an interconnection on the first surface, wherein the first connection block and the second The connection block is electrically connected through the interconnection.
  • the bonding layer has an opening, and the opening exposes an area of the interconnection opposite to the first connection end and an area opposite to the third connection end.
  • the method of forming the first connection block and the second connection block includes:
  • first connection block and the second connection block are formed in the opening, wherein the first connection block covers an area of the interconnection opposite to the first connection end and is connected to the first connection end In contact and electrical connection, the second connection block covers an area of the interconnection opposite to the third connection end and is in contact and electrical connection with the third connection end.
  • the opening exposes the interconnection
  • the first connection block and the second connection block are the same connection block
  • the same connection block extends from the first connection end to the first connection block. Three connection ends.
  • the materials of the first connection block and the second connection block include one or more of copper, nickel, zinc, tin, silver, gold, tungsten, and magnesium.
  • the method of forming the second interconnect structure includes performing a hole etching process and a hole filling process from one side of the second surface to form a plurality of conductive plugs.
  • the plurality of conductive plugs include a first conductive plug, and the first conductive plug is disposed in the pixel circuit substrate and electrically connects the circuit interconnection terminal and the rewiring layer.
  • the plurality of conductive plugs includes a second conductive plug, the second conductive plug passes through the pixel circuit substrate and the bonding layer, and electrically connects the second connection terminal and the Rewiring layer.
  • the plurality of conductive plugs includes a third conductive plug, the third conductive plug passes through the pixel circuit substrate and the bonding layer, and electrically connects the fourth connection terminal and the Rewiring layer.
  • the method for forming the CMOS image sensor package module further includes: forming an encapsulation layer on the first surface, and The packaging layer covers the signal processing chip and the DRAM chip and fills the gap.
  • the method for forming the CMOS image sensor packaging module further includes: bonding a dummy chip on the bonding layer; wherein the packaging layer also covers the dummy chip.
  • the signal processing chip and the DRAM chip are joined to correspond to the readout circuit area, the incident light is set to enter the pixel array from the side of the second surface, and the dummy chip corresponds to The photosensitive areas are joined.
  • CMOS image sensor package module In the CMOS image sensor package module provided by the present invention, a signal processing chip and a DRAM chip are joined on a pixel circuit substrate, the signal processing chip and the DRAM chip are electrically connected through a first interconnection structure, and the second interconnection structure is connected to the signal processing chip and DRAM
  • the chip and the readout circuit in the pixel circuit substrate are electrically connected, and a rewiring layer is provided for electrical connection with the second interconnection structure, which realizes the electrical interconnection between the pixel circuit substrate, the DRAM chip and the signal processing chip.
  • the structure of the package module is optimized, and it is convenient to cache the digital image signal output by the readout circuit in the DRAM chip, and then transmit the DRAM chip to the signal processing chip for processing.
  • the CMOS image sensor package module is used for image shooting, It is beneficial to improve the processing speed and image quality of the transmitted data and digital image signals.
  • the camera device provided by the present invention includes the above-mentioned CMOS image sensor package module, and thus has the same or similar advantages as the above-mentioned CMOS image sensor package module.
  • the method for forming a CMOS image sensor package module can form the above-mentioned CMOS image sensor package module.
  • the signal processing chip and the DRAM chip are joined on the pixel circuit substrate, and there is no need to provide the same functional signal processing circuit on the substrate.
  • the lateral size of the substrate does not need to be increased.
  • the overall size of the module is small, and the chip and the pixel circuit substrate are directly joined. This method eliminates defective chips such as signal processing wafers and DRAM wafers before bonding, which is less difficult than wafer-level bonding.
  • a first interconnection structure is formed to electrically connect the first connection terminal of the signal processing chip and the third connection terminal of the DRAM chip
  • a second interconnection structure is formed to electrically connect the circuit interconnection terminal of the readout circuit.
  • the second connection end of the signal processing chip and the fourth connection end of the DRAM chip also form an electrical connection between the rewiring layer and the second interconnection structure.
  • the DRAM chip can be used as a buffer element of the CMOS image sensor package module. When used for image shooting, it is beneficial to increase the processing speed of the transmitted data and digital image signals, thereby improving the image quality.
  • FIG. 1 is a schematic cross-sectional view of a pixel circuit substrate, a signal processing chip, and a DRAM chip in a method for forming a CMOS image sensor package module according to an embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of a signal processing chip and a DRAM chip after bonding a signal processing chip and a DRAM chip by a bonding layer in a method for forming a CMOS image sensor package module according to an embodiment of the present invention.
  • FIG 3 is a schematic cross-sectional view after forming a first interconnection structure in the method for forming a CMOS image sensor package module according to an embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view after forming a second interconnection structure in the method for forming a CMOS image sensor package module according to an embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view after forming a rewiring layer in the method for forming a CMOS image sensor package module according to an embodiment of the present invention.
  • FIG. 6 is a schematic cross-sectional view of a CMOS image sensor package module according to an embodiment of the invention.
  • the current CMOS image signal processor is often integrated on the pixel circuit substrate with the photosensitive element through SOC (system on chip) technology, or through the wafer-level bonding method (usually using metal and oxide hybrid bonding) and the photosensitive element
  • SOC system on chip
  • wafer-level bonding method usually using metal and oxide hybrid bonding
  • the pixel circuit substrates are bonded together, the process is difficult, the cost is high, and the wafer-level bonding method makes the two wafers bonded together, which is very difficult to deal with the defective chips on the signal processing wafer. Will increase costs.
  • the packaged module of CMOS image sensor is applied to digital camera, the digital signal obtained through the pixel circuit (or readout circuit) on the pixel circuit substrate is directly output to the image signal processor for processing and then stored in the storage through the mobile phone processor, for example.
  • the data processing speed (such as frame rate) of the card, photosensitive element, and pixel circuit is limited by the processing speed of the image signal processor and the processing speed of the mobile phone processor, which easily affects the shooting quality.
  • the packaging structure and packaging method of the CMOS image sensor still need to be improved.
  • the present invention provides a CMOS image sensor package module, in which a signal processing chip and a DRAM chip are joined on a pixel circuit substrate, and the signal processing chip and the DRAM chip are interconnected by a first interconnection structure, and a second mutual The connection structure is electrically connected to the readout circuit, the signal processing chip, and the DRAM chip, and the rewiring layer is arranged to be electrically connected to the second interconnection structure, thereby providing a way to realize the electrical interconnection of the pixel circuit substrate, the signal processing chip and the DRAM chip
  • the independent signal processing chip is beneficial to provide better computing power and imaging quality, and the defective chips on the wafer are eliminated during bonding, which is less difficult than the wafer-level bonding method.
  • the signal processing chip and the DRAM chip are joined on the pixel circuit substrate, which can increase the design margin of the pixel circuit substrate and help reduce the overall size of the package module.
  • the DRAM chip can be used as a buffer element to store the transmitted image signal data first, and then output according to the processing speed of the signal processing chip, which is beneficial to improve the processing speed of the transmitted data and digital image signal and the image quality.
  • CMOS image sensor package module its forming method, and the camera device of the present invention will be described in further detail below in conjunction with the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be understood that the following embodiments are only exemplary specific implementations for applying the present invention, and do not constitute a limitation on the protection scope of the present invention.
  • the CMOS image sensor package module of this embodiment includes a pixel circuit substrate 100, and the pixel circuit substrate 100 is arranged with a photosensitive area I and a readout circuit area II (FIG.
  • the pixel array of the CMOS image sensor is arranged in the photosensitive area I, where the pixel array of the CMOS image sensor refers to
  • the CMOS image sensor consists of an array of pixel units including photodiodes, the readout circuit is arranged in the readout circuit area II, and the photodiodes and readout circuits are formed in the pixel circuit substrate 100 in the corresponding area by semiconductor technology.
  • the readout circuit has a circuit interconnection terminal for interconnection.
  • the pixel circuit substrate 100 of this embodiment includes a first surface 100a and a second surface 100b opposite to each other.
  • the pixel circuit substrate 100 may specifically be a substrate for manufacturing a CMOS image sensor on a substrate, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, etc.
  • the material of the substrate may also include germanium and silicon germanium. , Silicon carbide, gallium arsenide, indium gallium or other III and V group compounds.
  • the CMOS image sensor in this embodiment is preferably a back-illuminated CMOS image sensor.
  • the back-illuminated CMOS image sensor is on the back side of the substrate (that is, the opposite side when the photodiode is made on the substrate), usually thinned and provided with a dielectric layer for planarization, and used to obtain different colors of light.
  • the circuit substrate includes a photosensitive layer provided with numerous photodiodes, and millions of pixel cells or pixel units distributed in an array can be provided in the photosensitive layer.
  • Each pixel unit includes, for example, one photodiode and multiple driving circuits.
  • the MOS transistor When the MOS transistor is working, light enters from the lens layer and enters the pixel unit in the photosensitive layer through the color filter layer and the medium layer to form a photocurrent.
  • a number of different areas can be set according to different functions.
  • the interconnection layer formed on the photosensitive layer may include a multilayer interconnection metal layer stacked together and a plug layer connecting two adjacent interconnection metal layers.
  • the interconnection layer is used to electrically connect the photodiode, the driving circuit, and Peripheral circuit to process the photocurrent signal of the photodiode.
  • Peripheral circuits may specifically include analog signal processing circuits, analog-to-digital conversion circuits, digital logic circuits, and readout circuits, etc.
  • the readout circuits are arranged in readout circuit area II, and processed on the pixel circuit substrate 100 in readout circuit area II.
  • the completed digital image signal is output or used to transmit other signals, and the output digital image signal enters an image signal processing circuit (Image Signal Processor, ISP) or an image signal processing chip for further processing.
  • ISP Image Signal Processor
  • the specific structure of the pixel array substrate can also be implemented with reference to the disclosed technology.
  • the CMOS image sensor may also be a front-illuminated CMOS image sensor, or a stacked CMOS image sensor.
  • the side surface of the pixel circuit substrate 100 where the interconnection layer is formed is used as the first surface 100a, and the side surface where light is incident is used as the second surface 100b, which corresponds to the readout circuit area II.
  • the pixel circuit substrate 100 may include a dielectric layer, a circuit layer, and an interconnection layer (also may include a lens layer and a color filter layer, not shown in the figure) along the direction from the second surface 100b to the first surface 100a.
  • the dielectric layer may be used On the surface of the flattened substrate and used as an electrical isolation layer, the circuit layer includes the above-mentioned readout circuit.
  • the circuit layer can be made together with the photosensitive layer in the photosensitive area I.
  • the interconnection layer is superimposed on the circuit layer and the readout circuit is arranged in it.
  • a circuit interconnection terminal, the circuit interconnection terminal may specifically include a plurality of connection terminals for different connection purposes, for example, including a first circuit interconnection terminal 101 and a second circuit interconnection terminal 102, the first circuit interconnection terminal 101 and the second circuit interconnection terminal 102 are connected to an external chip or circuit for transmitting image digital signals or other signals.
  • the bonding layer 300 is laid on the first surface 100 a of the pixel circuit substrate 100.
  • the material of the bonding layer 300 may include oxide or other suitable materials.
  • it may be a bonding material, that is, a signal processing chip and a DRAM chip are bonded to the first surface 100a of the pixel circuit substrate 100 by means of fusion bonding or vacuum bonding.
  • the bonding layer 300 may also include an adhesive material, such as die attach film (DAF) or dry film (dry film), that is, the signal processing chip and the DRAM chip are bonded to the first pixel circuit substrate 100 by bonding.
  • the bonding layer 300 preferably adopts a dry film.
  • the dry film is a viscous photoresist film. After being irradiated by ultraviolet rays, it can polymerize to form a stable substance attached to the adhesive surface, and the chip can adhere to the dry film.
  • the signal processing chip 200 and the DRAM chip 600 are arranged in parallel on the bonding layer 300.
  • the signal processing chip 200 has a first connection terminal 201 and a second connection terminal 202.
  • the DRAM chip 600 has a third connection terminal 601 and a second connection terminal 202.
  • the four connecting terminals 602, in order to interconnect with the pixel circuit substrate 100, the above-mentioned connecting terminals (which may be contact pads) of the signal processing chip 200 and the DRAM chip 600 are preferably arranged toward the first surface 100a of the pixel circuit substrate 100.
  • the signal processing chip 200 and the DRAM chip 600 are arranged in the readout circuit area II of the pixel circuit substrate 100 to avoid the influence on the photosensitive area I. But it is not limited to this. Under the premise of not affecting the light incident on the pixel array of the photosensitive area, the two can also be joined to other areas on the first surface 100a.
  • the signal processing chip 200 may be an image signal processor (ISP) or a digital signal processor (DSP) or the like.
  • ISP image signal processor
  • DSP digital signal processor
  • the image signal processor can process the output data of the pixel circuit substrate 100, such as automatic exposure control (AEC), automatic gain control (AGC), automatic white balance (AWB), color correction, lens correction (Lens Shading) ), Gamma correction, bad pixel removal, and Auto Black Level processing.
  • AEC automatic exposure control
  • AEC automatic gain control
  • AVB automatic white balance
  • color correction lens correction
  • Gamma correction bad pixel removal
  • Auto Black Level processing Auto Black Level processing.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • a DRAM chip 600 is provided in a CMOS image sensor package module.
  • One of the purposes is to interconnect with the signal processing chip 200 and the pixel circuit substrate 100.
  • the CMOS image sensor package module of this embodiment is used in image capture equipment. (Such as a mobile phone camera), the DRAM chip 600 can be used to store the captured high-speed image information, and output at the optimal rate of the input interface according to the system design.
  • the signal processing chip 200 and the DRAM chip 600 may be independently designed and manufactured chips (as opposed to the signal processing circuit integrated on the pixel circuit substrate), and specifically may be bare chips to be packaged (different from uncut chips on the wafer) Compared with the signal processing circuit integrated on the pixel circuit substrate, the bonded signal processing chip has better computing power and imaging quality. For example, when it is used in camera equipment such as mobile phones, the independent signal processing chip can be supplied by mobile phone manufacturers. Provider customization helps to achieve a better fit with other components of the camera, and also facilitates the reduction of the horizontal size of the pixel circuit substrate, thereby reducing the overall size of the package module.
  • this embodiment focuses on a CMOS image sensor package module including a pixel circuit substrate 100 and a signal processing chip 200 and a DRAM chip 600 disposed on its first surface 100a, but it does not mean the CMOS image sensor package of this embodiment.
  • the module only includes the above-mentioned components, and other chips (such as analog signal processing chips, analog-to-digital conversion chips, logic chips, etc.) or other devices (such as power devices, bipolar devices, etc.) may also be arranged/joined on the pixel circuit substrate 100. Devices, resistors, capacitors, etc.), devices and connection relationships known in the art may also be included.
  • the CMOS image sensor package module of this embodiment further includes a first interconnection structure 210 for electrically connecting the first connection terminal 201 of the signal processing chip 200 and the third connection terminal 601 of the DRAM chip 600.
  • the first interconnect structure 210 includes a connection block 211 embedded in the bonding layer 300, and the connection block 211 is connected to the first connection end 201 of the signal processing chip 200 and the third connection end 601 of the DRAM chip 600 All contact and electrical connection.
  • the connection block 211 is an integral metal block.
  • FIG. 6 is a schematic cross-sectional view of a CMOS image sensor package module according to an embodiment of the present invention. Referring to FIG.
  • the first interconnect structure 210 includes embedded in the bonding layer 300
  • the connecting end 601 is electrically connected to each other, and the first connecting block 2111 is electrically connected to the second connecting block 2112.
  • the first connection block 2111 and the second connection block 2112 are, for example, metal blocks formed by electroplating or electroless plating.
  • the first connection block 2111 and the second connection block 2112 can be respectively disposed in the bonding layer 300 relative to the first connection end 201 and the third connection end 601, or can be connected to form a connection block, such as the connection block 211 in FIG. 5, That is, the first connecting block 2111 and the second connecting block 2112 serve as the same connecting block, and the same connecting block extends from the first connecting end 201 to the third connecting end 601.
  • the material of the first connection block 2111 and the second connection block 2112 may include one or more of copper, nickel, zinc, tin, silver, gold, tungsten, and magnesium.
  • the first interconnect structure 210 further includes an interconnect 103, the interconnect 103 is disposed on the first surface 100a of the pixel circuit substrate 100, and the interconnect 103 It may be formed on the first surface 100a before the bonding layer 300, and both the first connection block 2111 and the second connection block 2112 in the bonding layer 300 are in contact with the interconnection 103, and thus can be electrically connected through the interconnection 103.
  • the interconnect 103 may be a conductive element disposed on the first surface 100a of the pixel circuit substrate 100 in a passive or active manner.
  • the interconnect 103 may also be connected to the pixel circuit substrate 100. The circuit interconnection ends of the readout circuit are electrically connected.
  • the interconnection 103 may include an interconnection line formed on the first surface 100a, one end of the interconnection line is connected to the first connection end 201 through the first connection block 2111, and the interconnection The other end of the wire is connected to the third connecting end 601 through the second connecting block 2112.
  • the interconnection member may include an interconnection line formed on the first surface 100a and a first bonding pad and a second bonding pad located at both ends of the interconnection line. The first bonding pad is connected to the first connection terminal 201 of the signal processing chip 200 through the first connection block 2111, and the second bonding pad is connected to the third connection terminal 601 of the DRAM chip 600 through the second connection block 2112 .
  • the CMOS image sensor package module of the embodiment of the present invention further includes a second interconnect structure 220, the second interconnect structure 220 is disposed in the pixel circuit substrate 100 and the bonding layer 300, In order to interconnect the readout circuit of the pixel circuit substrate 100 with the signal processing chip 200 and the DRAM chip 600.
  • the second interconnection structure 220 and the circuit interconnection end of the readout circuit (this embodiment includes the first circuit interconnection end 101 and the second circuit interconnection end 102), and the second connection end 202 of the signal processing chip 200 And the fourth connection terminal 602 of the DRAM chip 600 is electrically connected.
  • the CMOS image sensor package module of this embodiment can realize the DRAM chip 600 through the first interconnect structure 210 and the second interconnect structure 220.
  • the interconnection with any two of the signal processing chip 200 and the pixel circuit substrate 100 optimizes the packaging structure.
  • the end (or electrical contact) of the second interconnect structure 220 may extend to the second surface 100b to rewire the connected signal end.
  • the CMOS image sensor package module of this embodiment may further include a rewiring layer 500 (or rewiring layer, RDL), which is laid on the second surface 100b, and the rewiring layer 500 is connected to the second interconnection.
  • the structure 220 is electrically connected.
  • the rewiring layer 500 may include rewiring and a bonding pad (I/O pad) electrically connected to the rewiring.
  • the rewiring layer 500 is preferably laid on the second surface 100b corresponding to the peripheral area of the pixel circuit substrate 100.
  • the above-mentioned second interconnect structure 220 may include one or more electrical contacts, electrical connections, and electrical connection lines formed between the pixel circuit substrate 100 and the bonding layer 300.
  • the second interconnection structure may include a first conductive plug 111 disposed in the pixel circuit substrate 100, and one end of the first conductive plug 111 is in contact with the readout circuit.
  • the circuit interconnection end (such as the first circuit interconnection end 101 or the second circuit interconnection end 102 in this embodiment), the other end faces the second surface 100b and is electrically connected to the rewiring layer 500.
  • the second interconnection structure includes a second conductive plug 112, one end of the second conductive plug 112 is in contact with the second connection end 202 of the electrical connection signal processing chip 200, and the other end faces the second surface 100b is also electrically connected to the rewiring layer 500.
  • the second interconnection structure includes a third conductive plug 113, one end of the third conductive plug 113 is in contact with the fourth connection terminal 602 electrically connected to the DRAM chip 600, and the other end faces the second surface 100b And it is electrically connected to the rewiring layer 500. Referring to FIG. 5 (or FIG.
  • the second interconnect structure 220 includes the first conductive plug 111, the second conductive plug 112, and the third conductive plug 113 described above.
  • the second interconnection structure 220 includes two first conductive plugs 111 to electrically connect the first circuit interconnection terminal 101 and the second circuit interconnection terminal 102 with the The rewiring layer 500 is described.
  • the rewiring layer 500 in the drawings is only an example.
  • the rewiring layer may also be connected to the conductive plugs (or electrical connections) of the second interconnect structure 220 respectively.
  • Each of the second interconnection structure 220 and the rewiring layer 500 and the electrical connection between the two can be designed according to specific circuits to achieve preset functions, and are not limited as shown in the figure.
  • the above-mentioned CMOS image sensor package module may further include an encapsulation layer 400 disposed above the first surface 100a of the pixel circuit substrate 100, and covering the signal processing chip 200, the DRAM chip 600, and the gaps (for example, covering the first surface 100a). On the surface of the first interconnect structure 210 or the exposed bonding layer 300). Therefore, the encapsulation layer 400 protects the signal processing chip 200, the DRAM chip 600, and the exposed first interconnect structure 210 and the bonding layer 300 from the side of the first surface 100a.
  • the encapsulation layer 400 is, for example, a plastic material, so that it can be softened or flowed to form a certain shape during the molding process, and the material of the encapsulation layer 400 can also undergo a chemical reaction to crosslink and solidify.
  • the material of the encapsulation layer 400 includes at least one of thermosetting resins such as phenolic resin, urea-formaldehyde resin, formaldehyde resin, epoxy resin, unsaturated resin, polyurethane, and polyimide, such as epoxy resin.
  • the encapsulation layer 400 may include filler materials and various additives (for example, curing agents, modifiers, release agents, thermocolor agents, flame retardants, etc.).
  • the area corresponding to the photosensitive area I is relatively large, and the area corresponding to the peripheral circuit is relatively small. Therefore, in order to optimize the packaging effect, a dummy chip can be bonded on the bonding layer 300 (dummy chip) 10, so that the encapsulation layer 400 also covers the dummy chip 10.
  • the dummy chip 10 is bonded to the first surface 100a of the pixel circuit substrate 100 corresponding to the photosensitive area I. It can be understood that the dummy chip 10 bonded corresponding to the photosensitive area I is arranged on the opposite side of the light incident. In this embodiment, the light is set to incident from the second surface 100a.
  • the dummy chip is, for example, a silicon chip. According to the specific conditions of the pixel circuit substrate 100 and the size of the dummy chip, one or more dummy chips can be joined to the photosensitive area I. In this embodiment, the dummy chip 10 helps control the warping of the package module. Curvature.
  • the signal processing chip 200 and the DRAM chip 600 are integrated on the pixel circuit substrate 100, and the two are interconnected, the structure of the package module is optimized, and the digital output of the readout circuit is facilitated.
  • the image signal is first buffered in the DRAM chip 600, and then through the interconnection between the DRAM chip 600 and the signal processing chip 200, the buffered data is output at the optimal rate of the signal processing chip 200.
  • Using the DRAM cache function can fully mobilize the work of the CMOS image sensor, which is helpful to solve the problems of slow continuous shooting of mobile phones, poor video quality, and low video frames. For users, after using DRAM cache, they can use mobile phones. Shooting slow-motion video of, for example, 960fps, and can correspondingly reduce the jelly effect produced when shooting high-speed moving objects, which helps to improve the imaging effect and improve the image quality.
  • This embodiment also includes a method for forming a CMOS image sensor package module. It can be used to make the above-mentioned CMOS image sensor package module.
  • the method for forming a CMOS image sensor package module of this embodiment includes a first step of providing a pixel circuit substrate 100, a signal processing chip 200 and a DRAM chip 600.
  • the pixel circuit substrate 100 is provided with a photosensitive area I and a reading Out of the circuit area II, the pixel array of the CMOS image sensor is arranged in the photosensitive area I, and the readout circuit is arranged in the readout circuit area II.
  • the pixel circuit substrate 100 includes a first surface 100a and a second surface 100b opposite to each other.
  • the signal processing chip 200 includes a first connection terminal 201 and a second connection terminal 202, and the DRAM chip 600 has a third connection terminal 601 and a fourth connection terminal 602.
  • the CMOS image sensor is, for example, a back-illuminated type, in which incident light can enter the photodiode of the pixel array from the first surface 100a or the second surface 100b of the pixel circuit substrate 100. In this embodiment, it can be set to The surface 100b enters the photodiode of the pixel array.
  • CMOS image sensor package module For the respective characteristics of the pixel circuit substrate 100, the signal processing chip 200, and the DRAM chip 600, reference may be made to the description in the above-mentioned CMOS image sensor package module.
  • one or more dummy chips 10 may be provided in the first step to be bonded on the pixel circuit substrate 100 corresponding to the bonding positions of the signal processing chip 200 and the DRAM chip 600, so as to control the warpage of the entire package module.
  • the interconnection 103 is formed on the first surface 100a, and the interconnection 103 can be used as an optional signal processing chip.
  • the interconnection components between the 200 and the DRAM chip 600 can be used as a seed layer for electroplating or electroless plating when an electrical connection is formed between the signal processing chip 200 and the DRAM chip 600 by electroplating or electroless plating.
  • the interconnect 103 may be a conductive element that is provided on the first surface 100a of the pixel circuit substrate 100 in a passive or active manner. In an alternative embodiment, the interconnect 103 may be connected to the readout circuit in the pixel circuit substrate 100. The circuit interconnection ends are electrically connected.
  • the interconnect 103 may have various forms.
  • the interconnection 103 is an interconnection line formed on the first surface 100.
  • the method for forming the interconnection line is, for example, depositing a metal layer on the first surface 100a and performing a patterning process.
  • the interconnection 103 includes an interconnection line, and further includes a first bonding pad and a second bonding pad located at both ends of the interconnection line, so that the first bonding pad and the second bonding pad are connected to each other through the first bonding pad and the second bonding pad.
  • the signal processing chip 200 and the DRAM chip 600 are interconnected.
  • the method of forming a CMOS image sensor package module of this embodiment includes a second step of forming a bonding layer 300 on the first surface 100a of the pixel circuit substrate 100, and bonding the signal processing chip on the bonding layer 300 200 and the DRAM chip 600, the first connection end 201 and the second connection end 202 of the signal processing chip 200, and the third connection end 601 and the fourth connection end 602 of the DRAM chip 600 all face the first surface 100a.
  • the signal processing chip 200 and the DRAM chip 600 may be bonded to the pixel circuit substrate 100 by bonding or bonding, that is, the bonding layer 300 may be a bonding material or an adhesive material.
  • the signal processing chip 200 and the DRAM chip 600 can be bonded corresponding to the peripheral area of the pixel circuit substrate 100 such as the readout circuit area II, and one or more dummy chips 10 can be bonded on the first surface 100a corresponding to the photosensitive area I.
  • the signal processing chip 200 and the DRAM chip 600 can be connected to each other at the interconnection 103.
  • the first connection terminal 201 of the signal processing chip 200 and the DRAM chip 600 The third connecting ends 601 are arranged oppositely and are all located above the interconnection 103.
  • an opening 300a is formed in the bonding layer 300, and the opening 300a at least exposes the area of the interconnect 103 opposite to the first connection terminal 201 (Part)
  • the area (part) opposite to the third connecting end 601, that is, the opening 300a may be two separate small openings to respectively expose the two areas of the interconnection 103 (for example, the corresponding interconnection The two solder pads of the component 103), the opening 300a can also be one, which exposes all the interconnecting components 103.
  • the opening 300 a is used to form a first interconnect structure to electrically connect the DRAM chip 600 and the signal processing chip 200.
  • the opening 300 a may be formed in the bonding layer 300 by forming the bonding material only in a part of the area, wherein the interconnect 103 is exposed in the bonding layer 300.
  • the bonding layer 300 covering the interconnect 103 may be formed first, and then part of the bonding layer 300 material may be removed by, for example, a dry etching process to form the opening 300a.
  • the method for forming a CMOS image sensor package module of this embodiment includes a third step of forming a first interconnection structure 210 to electrically connect the first connection terminal 201 and the third connection terminal 601.
  • the connection structure 210 includes a first connection block embedded in the bonding layer 300 and a second connection block embedded in the bonding layer 300.
  • the first connection block is electrically connected to the first connection end 201.
  • the second connection block is electrically connected to the third connection end 601 in contact, and the first connection block is electrically connected to the second connection block.
  • the opening 300a exposes all the interconnecting members 103, the first connecting block and the second connecting block are connected and formed as a whole connecting block 211, and the connecting block 211 is connected from the first
  • the end 201 extends to the third connecting end 601. It can be understood that the first connecting block and the second connecting block may also be arranged separately as shown in FIG. 6.
  • the connecting block 211 is disposed in the opening 300a, and can be formed by electroplating or electroless plating.
  • the interconnect 103 can be used as a seed layer for electroplating or electroless plating.
  • the electroless plating process may include the following steps: placing the pixel circuit substrate 100 with the signal processing chip 200 and the DRAM chip 600 and the opening 300a formed in the bonding layer 300 in a solution containing metal ions (such as electroless silver plating) , Nickel plating, copper plating, etc.), the metal ions are reduced to metal by a strong reducing agent and deposited in the opening 300a.
  • the metal material forms the first connection block and the second connection block (this embodiment In an example, after electroless plating, the first connection block and the second connection block are connected as a whole, which can be regarded as the same connection block, that is, the connection block 211 in FIG. 3), wherein the first connection block covers the interconnection
  • the part of the member 103 opposite to the first connecting terminal 201 is electrically connected to the first connecting terminal 201
  • the second connecting block covers the part of the interconnecting member 103 opposite to the third connecting terminal 601 and is in contact with the third connecting terminal 601 Electric connection.
  • the first interconnection structure 210 includes the above-mentioned first connection block and the second connection block, and may also include the interconnection 103.
  • the first connection terminal 201 of the signal processing chip 200 and the third connection terminal 601 of the DRAM chip 600 are electrically connected by forming the first connection block and the second connection block on the interconnect 103, without wire bonding or Re-connection in the pixel circuit substrate is beneficial to reduce the size of the package structure, and basically does not affect the photosensitive layer and peripheral circuits in the pixel circuit substrate 100, which can improve the reliability of the package module.
  • the method for forming a CMOS image sensor package module of this embodiment includes a fourth step, forming a second interconnect structure 220, the second interconnect structure 220 is disposed on the pixel circuit substrate 100 and the bonding layer In 300, the second interconnection structure 220 is electrically connected to the circuit interconnection end of the readout circuit, the second connection end 202 of the signal processing chip 200, and the fourth connection end 602 of the DRAM chip 600.
  • a step of forming an encapsulation layer 400 on the first surface 100a may be further included.
  • the encapsulation layer 400 covers the signal processing chip 200, the DRAM chip 600, and the gaps on the first surface 100a, that is, the encapsulation layer 400 may also cover the exposed bonding layer 300 and the first interconnect structure 210.
  • the encapsulation layer 400 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc., and may also include such as polycarbonate, polyethylene terephthalate, polyethersulfone, polyphenylene oxide,
  • Thermoplastic resins such as polyamides, polyetherimides, methacrylic resins or cyclic polyolefin resins can also include epoxy resins, phenolic resins, urea-formaldehyde resins, formaldehyde resins, polyurethanes, acrylic resins, vinyl ester resins, and acrylic resins.
  • Thermosetting resins such as imine resins, urea resins or melamine resins may also include organic insulating materials such as polystyrene and polyacrylonitrile.
  • the encapsulation layer 400 may be formed by, for example, a chemical vapor deposition process or an injection molding process. In the process of manufacturing the encapsulation layer 400, the top surface can also be flattened by a planarization process, so that the encapsulation layer can be used as a supporting surface in the subsequent process of forming the conductive plug and the rewiring layer.
  • one or more dummy chips 10 may be bonded to the bonding layer 300, so that the packaging layer 400 also covers all The pseudo chip 10.
  • the signal processing chip 200 and the DRAM chip 600 are joined to the readout circuit area of the pixel circuit substrate 100, incident light is set to enter the pixel array from the second surface 100 side, and the dummy chip 10 corresponds to The photosensitive regions of the pixel circuit substrate 100 are joined.
  • the second interconnect structure 220 may include one or more electrical contacts, electrical connections, and electrical connection lines formed between the pixel circuit substrate 100 and the bonding layer 300.
  • the method of forming the second interconnection structure 220 may include performing a hole etching process and a hole filling process from the side of the second surface 100b to form a plurality of conductive plugs (conducting with metal, etc.). Material filling holes).
  • the plurality of conductive plugs include a first conductive plug 111 electrically connected to a circuit interconnection end of the readout circuit, and the first conductive plug 111 is disposed in the pixel circuit substrate 100.
  • the plurality of conductive plugs may further include a second conductive plug 112 for electrically connecting to the second connection end 202 of the signal processing chip 200, and/or a fourth connection for electrically connecting to the DRAM chip 600
  • the third conductive plug 113 of the end 602, the second conductive plug 112 and the third conductive plug 113 both pass through the pixel circuit substrate 100 and the bonding layer 300.
  • the plurality of conductive plugs may include ends exposed on the second surface 100b to be electrically connected to the rewiring layer formed later. The plurality of conductive plugs may also be formed by the disclosed method.
  • the plurality of conductive plugs include a first conductive plug 111, a second conductive plug 112, and a third conductive plug 113, and the first conductive plug 111 is in contact and electrically connected to read
  • the circuit interconnection end of the output circuit (such as the first circuit interconnection end 101 and the second circuit interconnection end 102 in FIG. 4)
  • the second conductive plug 112 contacts and electrically connects the second connection end of the signal processing chip 200 202.
  • the third conductive plug 113 contacts and electrically connects to the fourth connection terminal 602 of the DRAM chip 600.
  • 5 is a schematic cross-sectional view after forming a rewiring layer in the method for forming a CMOS image sensor package module according to an embodiment of the present invention.
  • the method for forming a CMOS image sensor package module of this embodiment after forming the second interconnection structure 220 further includes a fifth step of forming a rewiring layer 500 on the second surface 100b of the pixel circuit substrate 100 so that The rewiring layer 500 is electrically connected to the second interconnect structure 220.
  • the rewiring layer 500 may be formed on the dielectric layer on the side of the second surface 100b of the pixel circuit substrate 100, and may be in contact with the plurality of conductive plugs of the second interconnection structure 220, thereby being connected to the second interconnection.
  • the structure 220 is electrically connected.
  • the formation process of the rewiring layer 500 is, for example, first depositing a metal layer on the second surface 100b of the pixel circuit substrate 100 by physical vapor deposition (PVD), atomic layer deposition (ALD) or chemical vapor deposition (CVD), and then patterning Chemical treatment to form the rewiring layer 500.
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • the rewiring layer 500 can also be produced by a public method.
  • the above-mentioned rewiring layer 500 may further include rewiring and a bonding pad (I/O pad) electrically connected to the rewiring.
  • the rewiring layer 500 may be used for the second interconnection structure 220 (and further for the signal processing chip 200 according to design requirements).
  • the electrical connections between the DRAM chip 600 and the pixel circuit substrate 100) are re-arranged.
  • the solder pads that are electrically connected to the rewiring can be used to connect the rewiring layer to external signals or devices of the packaged module to process or control the electrical signals transmitted by the rewiring.
  • the method for forming a CMOS image sensor package module of this embodiment joins the signal processing chip 200 and the DRAM chip 600 on the first surface 100a of the pixel circuit substrate 100, and provides the pixel circuit The process of interconnection between the substrate 100, the signal processing chip 200 and the DRAM chip 600.
  • the DRAM chip 600 can be used as a buffer to store the output data of the readout circuit and output the stored data to the signal processing chip 200 according to the working rate
  • the signal processing chip 200 is beneficial to increase the processing speed of the transmitted data and digital image signals when the formed CMOS image sensor package module is used for image shooting, thereby improving the image quality.
  • the signal processing chip 200 and the DRAM chip 600 are bonded on the pixel circuit substrate 100, and the design margin of the pixel array substrate 100 is large, which helps to reduce the overall size of the package module.
  • the signal processing chip set by bonding is beneficial to provide better computing power and imaging quality. Defective chips on the same wafer are discarded before bonding, which is less difficult than the wafer-level bonding method.
  • An embodiment of the present invention also provides an imaging device, which is provided with the CMOS image sensor packaging module described in the embodiment of the present invention.
  • the imaging device in the embodiment of the present invention may be a miniature camera, a digital camera, or various electronic devices such as a mobile phone, a tablet, a notebook computer, smart glasses, a digital helmet, a monitor, and the like with a miniature camera function.
  • the imaging device of the embodiment of the present invention adopts the CMOS image sensor package module of the embodiment of the present invention, which helps to achieve a smaller size and better image quality.

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Abstract

一种CMOS图像传感器封装模块及其形成方法、包括CMOS图像传感器封装模块的摄像装置。CMOS图像传感器封装模块在像素电路基板（100）上接合有信号处理芯片（200）和DRAM芯片（600），信号处理芯片（200）和DRAM芯片（600）通过第一互连结构（210）电连接，像素电路基板（100）中的读出电路、信号处理芯片（200）以及DRAM芯片（600）均与第二互连结构（220）电连接，再布线层（500）与第二互连结构（220）电连接，优化了封装模块的结构，便于将读出电路输出的数字图像信号先缓存于DRAM芯片（600），再由DRAM芯片（600）传输至信号处理芯片（200）进行处理，在CMOS图像传感器封装模块用于图像拍摄时，有利于提高对传输的数据以及数字图像信号的处理速度，进而提高图像质量。

Description

CMOS图像传感器封装模块及其形成方法、摄像装置 技术领域
本发明涉及图像传感器领域，特别涉及一种CMOS图像传感器封装模块及其形成方法、摄像装置。
背景技术
出于拍摄景物的需要，目前诸如笔记本电脑、平板电脑、智能手机、智能玩具等设备上也配置了数字摄像头。常用的数字摄像头通过摄像镜头，将生成的光学图像投射到感光元件表层，光线被感光元件表层上的滤镜分解成不同的色光，各色光被各滤镜相对应的像素单元感知，并产生不同强度的模拟信号，再由感光元件的电路将这些信号收集起来，模拟信号通过数模转换器转换成为数字信号，再由图像信号处理器(ISP，image signal processor)对这些数字信号进行处理，再被送到手机处理器进行处理，然后再被传输到存储卡保存起来，成为屏幕上能够观看的图像。
目前常用的感光元件为背照式CMOS(Complementary Metal Oxide Semiconductor，互补金属-氧化物-半导体)图像传感器。与CCD图像传感器相比，CMOS图像传感器能够实现更灵活的图像捕获、更高的灵敏度、更宽的动态范围、更高的分辨率、更低的功耗以及更加优良的系统集成等。并且，光从CMOS图像传感器的背面入射，无需穿过感光元件上的互连层即射向感光元件，减少了光线损失，在单位时间内，单个像素单元能获取的光能量更大，对画质有明显的提升。
但是，随着对CMOS图像传感器的尺寸以及成像质量等方面的要求提高，仍需要进一步优化CMOS图像传感器封装模块的结构。
发明内容
针对上述问题，本发明提供了一种CMOS图像传感器封装模块及其形成方法，以优化CMOS图像传感器封装模块的结构，便于提高利用该CMOS图像传感器封装模块进行拍摄时的成像质量。
根据本发明的一方面，提供了一种CMOS图像传感器封装模块，包括：
像素电路基板，其中包括感光区和读出电路区，CMOS图像传感器的像素阵列设置于所述感光区，读出电路设置于所述读出电路区，所述读出电路具有电路互连端，所述像素电路基板包括相对的第一表面和第二表面；接合层，铺设于所述第一表面；并列位于所述接合层上的信号处理芯片和DRAM芯片，所述信号处理芯片具有朝向所述第一表面的第一连接端和第二连接端，所述DRAM芯片具有朝向所述第一表面的第三连接端和第四连接端；第一互连结构，电连接所述第一连接端和所述第三连接端，所述第一互连结构包括嵌于所述接合层的第一连接块和嵌于所述接合层的第二连接块，所述第一连接块与所述第一连接端接触电连接，所述第二连接块与所述第三连接端接触电连接，所述第一连接块与所述第二连接块电连接；第二互连结构，设置于所述像素电路基板和所述接合层中，与所述电路互连端、所述第二连接端以及所述第四连接端均电连接；以及再布线层，铺设于所述第二表面，所述再布线层与所述第二互连结构电连接。
可选的，所述第一互连结构还包括位于所述第一表面上的互连件，所述第一连接块与所述第二连接块通过所述互连件电连接。
可选的，所述互连件包括互连线及位于所述互连线两端的第一焊垫、第二焊垫，所述第一焊垫通过所述第一连接块与所述第一连接端连接，所述第二焊垫通过所述第二连接块与所述第三连接端连接。
可选的，所述互连件包括互连线，所述互连线的两端分别通过所述第一连接块与所述第一连接端连接、通过所述第二连接块与所述第三连接端连接。
可选的，所述第一连接块和所述第二连接块为同一连接块，所述同一连接块从所述第一连接端延伸至所述第三连接端。
可选的，所述第二互连结构包括设置于所述像素电路基板中的第一导电插塞，所述第一导电插塞电连接所述电路互连端和所述再布线层。
可选的，所述电路互连端包括第一电路互连端和第二电路互连端，所述第二互连结构包括两个所述第一导电插塞，以分别电连接所述第一电路互连端与所述再布线层以及所述第二电路互连端与所述再布线层。
可选的，所述第二互连结构包括穿过所述像素电路基板和所述接合层的第二导电插塞，所述第二导电插塞电连接所述第二连接端和所述再布线层。
可选的，所述第二互连结构包括穿过所述像素电路基板和所述接合层的第 三导电插塞，所述第三导电插塞电连接所述第四连接端和所述再布线层。
可选的，所述信号处理芯片和所述DRAM芯片对应于所述读出电路区设置于所述第一表面上。
可选的，所述再布线层包括再布线以及与所述再布线电连接的焊垫。
可选的，所述CMOS图像传感器封装模块还包括封装层，所述封装层设置于所述第一表面上，所述封装层覆盖所述信号处理芯片、所述DRAM芯片并填充间隙。
可选的，所述CMOS图像传感器封装模块还包括伪芯片，所述伪芯片位于所述接合层上，所述封装层还覆盖所述伪芯片。
可选的，入射光被设定为从所述第二表面一侧进入所述像素阵列，所述伪芯片对应于所述感光区设置于所述第一表面上。
可选的，所述CMOS图像传感器为背照式CMOS图像传感器。
可选的，所述接合层包括胶黏材料。
根据本发明的另一方面，提供了一种摄像装置，包括上述CMOS图像传感器封装模块。
根据本发明的再一方面，提供了一种CMOS图像传感器封装模块的形成方法，包括以下步骤：
提供像素电路基板、信号处理芯片和DRAM芯片，所述像素电路基板包括感光区和读出电路区，CMOS图像传感器的像素阵列设置于所述感光区，读出电路设置于所述读出电路区，所述读出电路具有电路互连端，所述像素电路基板包括相对的第一表面和第二表面，所述信号处理芯片具有第一连接端和第二连接端，所述DRAM芯片具有第三连接端和第四连接端；在所述第一表面形成接合层，并在所述接合层上接合所述信号处理芯片和所述DRAM芯片，所述第一连接端、所述第二连接端、所述第三连接端和所述第四连接端均朝向所述第一表面；形成第一互连结构，以电连接所述第一连接端和所述第三连接端，所述第一互连结构包括嵌于所述接合层的第一连接块和嵌于所述接合层的第二连接块，所述第一连接块与所述第一连接端接触电连接，所述第二连接块与所述第三连接端接触电连接，所述第一连接块与所述第二连接块电连接；形成第二互连结构，设置于所述像素电路基板和所述接合层中，与所述电路互连端、所述第二连接端以及所述第四连接端均电连接；以及在所述第二表面形成再布线 层，所述再布线层与所述第二互连结构电连接。
可选的，在形成所述接合层之前，所述CMOS图像传感器封装模块的形成方法还包括：在所述第一表面上形成互连件，其中，所述第一连接块与所述第二连接块通过所述互连件电连接。
可选的，所述接合层中具有开口，所述开口暴露出所述互连件与所述第一连接端相对的区域和与所述第三连接端相对的区域。
可选的，形成所述第一连接块和所述第二连接块的方法包括：
将设置有所述接合层、所述信号处理芯片和所述DRAM芯片的像素电路基板放置到化学镀溶液中，所述化学镀溶液中包括金属离子和还原剂；以及经预定时间后，在所述开口中形成所述第一连接块和所述第二连接块，其中，所述第一连接块覆盖所述互连件与所述第一连接端相对的区域并与所述第一连接端接触电连接，所述第二连接块覆盖所述互连件与所述第三连接端相对的区域并与所述第三连接端接触电连接。
可选的，所述开口暴露出所述互连件，所述第一连接块和所述第二连接块为同一连接块，所述同一连接块从所述第一连接端延伸至所述第三连接端。
可选的，所述第一连接块和所述第二连接块的材料包括铜、镍、锌、锡、银、金、钨和镁中的一种或多种。
可选的，形成所述第二互连结构的方法包括从所述第二表面一侧执行孔刻蚀工艺和填孔工艺，以形成多个导电插塞。
可选的，所述多个导电插塞包括第一导电插塞，所述第一导电插塞设置于所述像素电路基板中，并电连接所述电路互连端和所述再布线层。
可选的，所述多个导电插塞包括第二导电插塞，所述第二导电插塞穿过所述像素电路基板和所述接合层，并电连接所述第二连接端和所述再布线层。
可选的，所述多个导电插塞包括第三导电插塞，所述第三导电插塞穿过所述像素电路基板和所述接合层，并电连接所述第四连接端和所述再布线层。
可选的，在形成所述第一互连结构之后、形成所述第二互连结构之前，所述CMOS图像传感器封装模块的形成方法还包括：在所述第一表面上形成封装层，所述封装层覆盖所述信号处理芯片、所述DRAM芯片并填充间隙。
可选的，在形成所述接合层之后，所述CMOS图像传感器封装模块的形成方法还包括：在所述接合层上接合伪芯片；其中所述封装层还覆盖所述伪芯片。
可选的，所述信号处理芯片和所述DRAM芯片对应于所述读出电路区接合，入射光被设定为从所述第二表面一侧进入所述像素阵列，所述伪芯片对应于所述感光区接合。
本发明提供的CMOS图像传感器封装模块，在像素电路基板上接合了信号处理芯片和DRAM芯片，信号处理芯片和DRAM芯片通过第一互连结构电连接，第二互连结构与信号处理芯片、DRAM芯片以及像素电路基板中的读出电路电连接，并设置了再布线层与第二互连结构电连接，即实现了像素电路基板、DRAM芯片和信号处理芯片三者之间的电气互连，优化了封装模块的结构，并且便于将读出电路输出的数字图像信号先缓存于DRAM芯片，再由DRAM芯片传输至信号处理芯片进行处理，在所述CMOS图像传感器封装模块用于图像拍摄时，有利于提高对传输的数据以及数字图像信号的处理速度以及图像质量。
本发明提供的摄像装置包括上述CMOS图像传感器封装模块，从而具有与上述CMOS图像传感器封装模块相同或类似的优点。
本发明提供的CMOS图像传感器封装模块的形成方法，可形成上述CMOS图像传感器封装模块。其中，信号处理芯片和DRAM芯片接合在像素电路基板上，不需要在基板上设置同样功能的信号处理电路，基板的横向尺寸不需要增加，模块整体尺寸较小，并且直接接合芯片与像素电路基板，这种方法在接合之前即摒弃了例如信号处理晶圆和DRAM晶圆上的缺陷芯片，相对于晶圆级键合方式工艺难度较低。此外，在接合之后，形成了第一互连结构电连接信号处理芯片的第一连接端和DRAM芯片的第三连接端，并形成了第二互连结构电连接读出电路的电路互连端、信号处理芯片的第二连接端以及DRAM芯片的第四连接端，还形成了再布线层与第二互连结构电连接。DRAM芯片可作为CMOS图像传感器封装模块的缓存元件，在用于图像拍摄时，有利于提高对传输的数据以及数字图像信号的处理速度，进而提高图像质量。
附图说明
图1是本发明一实施例的CMOS图像传感器封装模块的形成方法中像素电路基板、信号处理芯片和DRAM芯片的剖面示意图。
图2是本发明一实施例的CMOS图像传感器封装模块的形成方法中利用接合层接合信号处理芯片和DRAM芯片后的剖面示意图。
图3是本发明一实施例的CMOS图像传感器封装模块的形成方法中形成第一互连结构后的剖面示意图。
图4是本发明一实施例的CMOS图像传感器封装模块的形成方法中形成第二互连结构后的剖面示意图。
图5是本发明一实施例的CMOS图像传感器封装模块的形成方法中形成再布线层后的剖面示意图。
图6是本发明一实施例的CMOS图像传感器封装模块的剖面示意图。
附图标记说明：
100-像素电路基板；200-信号处理芯片；600-DRAM芯片；100a-第一表面；100b-第二表面；101-第一电路互连端；102-第二电路互连端；201-第一连接端；202-第二连接端；601-第三连接端；602-第四连接端；300-接合层；300a-开口；400-封装层；500-再布线层；210-第一互连结构；211-连接块；2111-第一连接块；2112-第二连接块；103-互连件；111-第一导电插塞；112-第二导电插塞；113-第三导电插塞；220-第二互连结构；10-伪芯片。
具体实施方式
目前的CMOS图像信号处理器常通过SOC(system on chip)技术集成在设置感光元件的像素电路基板上，或者通过晶圆级键合方式(通常采用金属和氧化物混合键合)与设置感光元件的像素电路基板键合在一起，工艺难度大，成本高，而且晶圆级键合方式使两个晶圆键合在一起，对例如信号处理晶圆上的缺陷芯片的处理难度很大，同样会增加成本。此外CMOS图像传感器的封装模块在应用于数字摄像时，通过像素电路基板上的像素电路(或读出电路)得到的数字信号直接输出至图像信号处理器进行处理进而通过诸如手机处理器储存到存储卡，感光元件以及像素电路处理数据的速度(例如帧频)受到了图像信号处理器的处理速度以及手机处理器的处理速度的限制，容易影响拍摄质量。随着对CMOS图像传感器的封装模块的尺寸以及成像质量等方面的要求提高，CMOS图像传感器的封装结构和封装方法仍需要改进。
基于上述研究，本发明提供一种CMOS图像传感器封装模块，在像素电路基板上接合了信号处理芯片和DRAM芯片，并利用第一互连结构使信号处理芯片和DRAM芯片互连，利用第二互连结构与读出电路、信号处理芯片和DRAM 芯片均电连接，并设置再布线层与第二互连结构电连接，从而提供了一种实现像素电路基板、信号处理芯片和DRAM芯片电气互连的封装结构。独立的信号处理芯片有利于提供更佳的运算能力以及成像质量，并且接合时即摒弃了晶圆上的缺陷芯片，相对于晶圆级键合方式工艺难度较低。信号处理芯片和DRAM芯片接合在像素电路基板上，可以增加像素电路基板的设计余量，有利于缩小封装模块的整体尺寸。在用于图像拍摄时，DRAM芯片可作为缓存元件先将传输的例如图像信号数据存储起来，再根据信号处理芯片的处理速度输出，有利于提高对传输的数据以及数字图像信号的处理速度以及图像质量。
以下结合附图和具体的实施例对本发明的CMOS图像传感器封装模块及其形成方法、摄像装置作进一步详细说明。根据下面的说明，本发明的优点和特征将更清楚。应当理解，下述实施例仅是应用本发明的示例性的具体实施方式，并不构成对本发明保护范围的限制。
需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。除非另有其它说明，否则不同附图中的相应的数字和标号通常涉及相应的部件。并且，下文中的术语“第一”、“第二”等用于在类似要素之间进行区分，且未必是用于描述特定次序或时间顺序。要理解，在适当情况下，如此使用的这些术语可替换，例如可使得本文所述的本发明实施例能够不同于本文所述的或所示的其它顺序来操作。类似的，如果本文所述的方法包括一系列步骤，且本文所呈现的这些步骤的顺序并非必须是可执行这些步骤的唯一顺序，且一些所述的步骤可被省略和/或一些本文未描述的其他步骤可被添加到该方法。
本实施例首先介绍一种CMOS图像传感器封装模块。参照图5，本实施例的CMOS图像传感器封装模块包括一像素电路基板100，像素电路基板100内布置有感光区Ⅰ和读出电路区Ⅱ(图5示意出了感光区Ⅰ和读出电路区Ⅱ的位置，感光区Ⅰ和读出电路区Ⅱ的范围可以不限于图中所示区域)，CMOS图像传感器的像素阵列设置于所述感光区Ⅰ，此处CMOS图像传感器的像素阵列指的是CMOS图像传感器的包括光电二极管的像素单元组成的阵列，读出电路设置于所述读出电路区Ⅱ，光电二极管和读出电路利用半导体工艺形成于对应区域的像素电路基板100内。所述读出电路具有用于互连的电路互连端。为了方便说明，本实施例的所述像素电路基板100包括相对的第一表面100a和第二表面 100b。
像素电路基板100具体可以是在衬底上制造CMOS图像传感器的基板，所述衬底例如是硅衬底或绝缘体上硅(SOI)衬底等，衬底的材料还可以包括锗、锗化硅、碳化硅、砷化镓、镓化铟或其它Ⅲ、Ⅴ族化合物。由于已知的优点，本实施例中的CMOS图像传感器优选为背照式CMOS图像传感器。背照式CMOS图像传感器在衬底的背面一侧(即衬底上制作光电二极管时的相反一侧)，通常会进行减薄并设置用于平坦化的介质层、用于得到不同颜色光线的滤色层(图中未示出)以及用于增加光入射量的透镜层(图中未示出)，在衬底的正面一侧(即制作光电二极管和互连层的一侧)，像素电路基板包括设置有众多光电二极管的感光层，感光层中可设置数百万个阵列分布的像素单元(pixel cell or pixel unit)，每个像素单元例如包括一个光电二极管和多个用作驱动电路的MOS晶体管，在工作时，光从透镜层入射，经过滤色层和介质层进入感光层内的像素单元，形成光电流。在像素电路基板中，根据功能不同可设置多个不同的区域，通常将像素单元设置于感光区Ⅰ，而在感光区Ⅰ的周围设置外围电路，从而感光区Ⅰ和读出电路区Ⅱ也对应于像素电路基板100表面的不同区域。形成于感光层上的互连层可包括叠置在一起的多层互连金属层和连接相邻两层互连金属层的插塞层，互连层用于电连接光电二极管、驱动电路和外围电路，以对光电二极管的光电流信号进行处理。外围电路具体又可以包括模拟信号处理电路、模数转换电路、数字逻辑电路以及读出电路等，其中读出电路设置于读出电路区Ⅱ，在读出电路区Ⅱ，像素电路基板100上处理完毕的数字图像信号被输出，或者用于传输其它信号，输出的数字图像信号进入图像信号处理电路(Image Signal Processor，ISP)或者图像信号处理芯片被进一步处理。关于像素阵列基板的具体结构也可以参考公开技术实施。在另一实施例中，CMOS图像传感器也可采用前照式CMOS图像传感器，或者采用堆栈式CMOS图像传感器。
本实施例中，例如以像素电路基板100形成互连层的一侧表面作为第一表面100a，而将光入射的一侧表面作为第二表面100b，对应于所述读出电路区Ⅱ所述像素电路基板100沿第二表面100b向第一表面100a的方向依次可包括介质层、电路层以及互连层(也可包括透镜层和滤色层，图中未示出)，介质层可以用于平坦化基板的表面并作为电隔离层，电路层包括上述读出电路，电路层可以与感光区Ⅰ的感光层一起制作，互连层叠加于电路层上并在其中设置了读 出电路的电路互连端，所述电路互连端具体可包括多个不同连接用途的连接端，示例的，其中包括第一电路互连端101和第二电路互连端102，第一电路互连端101和第二电路互连端102与外部芯片或电路连接，用于传输图像数字信号或者其它信号。
参照图5，本实施例的CMOS图像传感器封装模块中，接合层300铺设于像素电路基板100的第一表面100a上。接合层300的材料可包括氧化物或其它合适的材料。例如，可以是键合材料，即通过熔融键合或真空键合等方式将信号处理芯片和DRAM芯片键合于像素电路基板100的第一表面100a而成。接合层300还可以包括胶黏材料，例如是粘片膜(Die Attach Film，DAF)或干膜(dry film)，即通过黏结方式将信号处理芯片和DRAM芯片接合在像素电路基板100的第一表面100a。本实施例中接合层300优选采用干膜，干膜属于粘性的光致抗蚀膜，通过紫外线的照射后能够发生聚合反应形成一种稳定的物质附着于粘着面，芯片可以黏附在干膜的上表面。
信号处理芯片200和DRAM芯片600并列设置于所述接合层300上，所述信号处理芯片200具有第一连接端201和第二连接端202，所述DRAM芯片600具有第三连接端601和第四连接端602，为了与像素电路基板100互连，信号处理芯片200和DRAM芯片600的上述连接端(可以是接触垫)优选朝向像素电路基板100的第一表面100a设置。优选方案中，信号处理芯片200和DRAM芯片600设置在像素电路基板100的读出电路区Ⅱ，以避免对感光区Ⅰ的影响。但不限于此，在不影响光线入射到感光区的像素阵列的前提下，二者也可以接合在第一表面100a上的其它区域。
具体的，信号处理芯片200可以是图像信号处理器(ISP)或者数字信号处理器(DSP)等。以图像信号处理器为例，它可以处理像素电路基板100的输出数据，例如进行自动曝光控制(AEC)、自动增益控制(AGC)、自动白平衡(AWB)、色彩校正、镜头校正(Lens Shading)、伽马(Gamma)校正、祛除坏点、自动黑平衡(Auto Black Level)等处理。DRAM(Dynamic Random Access Memory，动态随机存取存储器)为常见的系统内存装置，DRAM使用电容存储数据，隔一段时间刷新一次，如果存储单元没有被刷新，存储的信息就会丢失，从而可作为系统的缓存。本实施例在CMOS图像传感器封装模块中设置DRAM芯片600，其中一个目的是通过其与信号处理芯片200和像素电路基板100互连，在 将本实施例的CMOS图像传感器封装模块用于图像拍摄设备(例如手机相机)时，DRAM芯片600可用于存储拍摄到的高速图像信息，并根据系统设计以输入接口的最佳速率输出。
信号处理芯片200和DRAM芯片600可以是独立设计和制作(相对于集成在像素电路基板上的信号处理电路)的芯片，具体可以是待封装的裸芯片(不同于晶圆上未切割的芯片)，接合设置的信号处理芯片相对于集成在像素电路基板上的信号处理电路具有更佳的运算能力以及成像质量，在例如用于手机等相机设备时，独立的信号处理芯片可以由手机商向芯片提供商定制，有助于实现与相机其它组件更佳的契合度，并且还有利于像素电路基板横向尺寸的缩小，从而缩小封装模块整体尺寸。可以理解，本实施例重点说明的是包括像素电路基板100及在其第一表面100a设置信号处理芯片200和DRAM芯片600的CMOS图像传感器封装模块，但并不表示本实施例的CMOS图像传感器封装模块仅包括上述部件，像素电路基板100上也可以设置/接合有其它芯片(例如模拟信号处理芯片、模数转换芯片、逻辑芯片等等)，或者设置有其它器件(例如功率器件、双极型器件、电阻、电容等等)，本领域公知的器件和连接关系也可包含在其中。
本实施例的CMOS图像传感器封装模块还包括第一互连结构210，用于电连接信号处理芯片200的第一连接端201和DRAM芯片600的第三连接端601。具体的，所述第一互连结构210包括嵌于所述接合层300的连接块211，所述连接块211与信号处理芯片200的第一连接端201和DRAM芯片600的第三连接端601均接触电连接。参照图5，本发明一个实施例中，连接块211是一个整体的金属块。但本发明不限于此，图6是本发明一实施例的CMOS图像传感器封装模块的剖面示意图，参照图6，在该实施例中，第一互连结构210包括嵌于所述接合层300中的第一连接块2111和嵌于所述接合层300的第二连接块2112，所述第一连接块2111与上述第一连接端201接触电连接，所述第二连接块2112与上述第三连接端601接触电连接，所述第一连接块2111与所述第二连接块2112电连接。第一连接块2111和第二连接块2112例如是电镀或者化学镀形成的金属块。第一连接块2111和第二连接块2112可以分别相对于第一连接端201和第三连接端601设置在接合层300中，也可以连接成一个连接块，如图5中的连接块211，即第一连接块2111和所述第二连接块2112作为同一连接块，并 且所述同一连接块从上述第一连接端201延伸至第三连接端601。第一连接块2111和第二连接块2112的材料可包括铜、镍、锌、锡、银、金、钨和镁中的一种或多种。
参照图5(或图6)，可选实施方式中，所述第一互连结构210还包括互连件103，互连件103设置在像素电路基板100的第一表面100a，互连件103可在接合层300之前形成在第一表面100a上，接合层300中的第一连接块2111与第二连接块2112均与互连件103接触，从而可通过所述互连件103电连接。本实施例中，互连件103可以是以无源方式或有源方式被设置于像素电路基板100第一表面100a的导电元件，可选实施方式中，互连接103还可以与像素电路基板100中读出电路的电路互连端电连接。
进一步的，所述互连件103可包括在第一表面100a形成的互连线，所述互连线的一端通过所述第一连接块2111与上述第一连接端201连接，所述互连线的另一端通过所述第二连接块2112与上述第三连接端601连接。但不限于此，在另一实施例中，所述互连件可包括在第一表面100a形成的互连线及位于所述互连线两端的第一焊垫和第二焊垫，所述第一焊垫通过所述第一连接块2111与信号处理芯片200的第一连接端201连接，所述第二焊垫通过所述第二连接块2112与DRAM芯片600的第三连接端601连接。
参照图5(或图6)，本发明实施例的CMOS图像传感器封装模块还包括第二互连结构220，第二互连结构220设置于所述像素电路基板100和所述接合层300中，以将像素电路基板100的读出电路与信号处理芯片200和DRAM芯片600互连。具体的，第二互连结构220与读出电路的电路互连端(本实施例包括第一电路互连端101和第二电路互连端102)、信号处理芯片200的第二连接端202以及DRAM芯片600的第四连接端602均电连接。由于DRAM芯片600与信号处理芯片200通过第一互连结构210实现了互连，从而本实施例的CMOS图像传感器封装模块通过第一互连结构210和第二互连结构220可以实现DRAM芯片600与信号处理芯片200以及像素电路基板100中任意两者之间的互连，优化了封装结构。通过系统对传输信号的设计，所述CMOS图像传感器封装模块在例如用于图像拍摄时，便于将读出电路输出的数字图像信号先缓存于DRAM芯片，再由DRAM芯片传输至信号处理芯片进行处理，有利于提高对传输的数据以及数字图像信号的处理速度，进而提高图像质量。
第二互连结构220的端部(或者电接触)可以延伸至第二表面100b，以对其连接的信号端进行重新布线。参照图5，本实施例的CMOS图像传感器封装模块还可包括再布线层500(或重布线层，RDL)，其铺设于所述第二表面100b，所述再布线层500与第二互连结构220电连接。所述再布线层500可包括再布线以及与所述再布线电连接的焊垫(I/O pad)。为了避免对感光区Ⅰ入射光的影响，再布线层500优选对应于像素电路基板100的外围区域铺设于所述第二表面100b上。
上述第二互连结构220可包括形成于像素电路基板100和接合层300中的一个以上的电接触、电连接件以及在它们之间形成的电连接线。具体的，本发明一实施例中，第二互连结构可包括设置于所述像素电路基板100中的第一导电插塞111，所述第一导电插塞111的一端接触电连接读出电路的电路互连端(如本实施例中连接第一电路互连端101或第二电路互连端102)，另一端朝向第二表面100b并与再布线层500电连接。本发明一实施例中，第二互连结构包括第二导电插塞112，所述第二导电插塞112的一端接触电连接信号处理芯片200的第二连接端202，另一端朝向第二表面100b并与再布线层500电连接。本发明一实施例中，第二互连结构包括第三导电插塞113，所述第三导电插塞113的一端接触电连接DRAM芯片600的第四连接端602，另一端朝向第二表面100b并与再布线层500电连接。参照图5(或图6)，本实施例中，第二互连结构220包括了上述第一导电插塞111、第二导电插塞112和第三导电插塞113。此外，为了对应连接读出电路的不同的电路互连端，第一导电插塞111可以不止一个。本实施例中，所述第二互连结构220包括两个所述第一导电插塞111，以分别电连接所述第一电路互连端101和所述第二电路互连端102与所述再布线层500。
需要说明的是，附图中再布线层500仅为示例，例如在一些实施例中，再布线层还可与第二互连结构220的各导电插塞(或电连接件)分别连接。第二互连结构220和再布线层500中的每一个以及二者之间的电气连接可以依据具体电路设计，以实现预设的功能，并不以图中所示限定。
上述CMOS图像传感器封装模块还可包括封装层400，封装层400设置于像素电路基板100的第一表面100a上方，且覆盖信号处理芯片200、DRAM芯片600以及第一表面100a上的间隙(例如覆盖在第一互连结构210表面或者暴露的接合层300表面上)。从而封装层400从第一表面100a一侧将信号处理芯 片200、DRAM芯片600以及暴露的第一互连结构210和接合层300均保护了起来。所述封装层400例如是可塑材料，从而在成型过程中能软化或流动以制成一定形状，所述封装层400的材料还可发生化学反应而交联固化。作为示例，所述封装层400的材料包括酚醛树脂、脲醛树脂、甲醛树脂、环氧树脂、不饱和树脂、聚氨酯、聚酰亚胺等热固性树脂中的至少一种，例如环氧树脂。封装层400中可包括填料物质以及各种添加剂(例如固化剂、改性剂、脱模剂、热色剂、阻燃剂等)。
通常在像素电路基板100的第一表面100a内，对应于感光区Ⅰ的面积较大，相对而言于对应外围电路的面积较小，因而为了优化封装效果，在接合层300上可以接合伪芯片(dummy chip)10，并使得封装层400还覆盖伪芯片10，本实施例中，例如对应于感光区Ⅰ接合伪芯片10于像素电路基板100的第一表面100a。可以理解，对应于感光区Ⅰ接合的伪芯片10设置于光入射的反面，本实施例中，光设定为从第二表面100a入射。伪芯片例如是硅芯片，根据像素电路基板100的具体情况以及伪芯片的尺寸选择，可以接合一个或多个伪芯片在感光区Ⅰ，本实施例中伪芯片10有助于控制封装模块的翘曲度。
本实施例的CMOS图像传感器封装模块，像素电路基板100上集成了信号处理芯片200和DRAM芯片600，并且两两实现了互连，优化了封装模块的结构，并且便于将读出电路输出的数字图像信号先缓存于DRAM芯片600，然后再通过DRAM芯片600与信号处理芯片200的互连，将缓存数据以信号处理芯片200的最佳速率输出。利用DRAM的缓存功能，可以充分调动CMOS图像传感器的工作，有利于解决手机连拍速度不快、视频画质不好、视频帧数低等问题，对用户来说，利用DRAM缓存之后，可以利用手机拍摄例如960fps的慢动作视频，并且可以相应的减少在拍摄高速运动物体时所产生的果冻效应，有助于提升成像的效果，提高图像质量。
本实施例还包括一种CMOS图像传感器封装模块的形成方法。可用于制作上述CMOS图像传感器封装模块。
图1是本发明一实施例的CMOS图像传感器封装模块的形成方法中像素电路基板、信号处理芯片和DRAM芯片的剖面示意图。参照图1，本实施例的CMOS图像传感器封装模块的形成方法包括第一步骤，提供像素电路基板100、信号处理芯片200和DRAM芯片600，所述像素电路基板100中设置有感光区Ⅰ和读 出电路区Ⅱ，CMOS图像传感器的像素阵列设置于所述感光区Ⅰ，读出电路设置于所述读出电路区Ⅱ。所述像素电路基板100包括相对的第一表面100a和第二表面100b。信号处理芯片200包括第一连接端201和第二连接端202，DRAM芯片600具有第三连接端601和第四连接端602。CMOS图像传感器例如是背照式的，其中入射光可以从像素电路基板100的第一表面100a或者第二表面100b进入像素阵列的光电二极管，本实施例中，可设定为入射光从第二表面100b进入像素阵列的光电二极管。
关于像素电路基板100、信号处理芯片200以及DRAM芯片600各自的特征可参照上述CMOS图像传感器封装模块中的描述。另外，第一步骤中还可以提供一个或多个伪芯片10，以与信号处理芯片200和DRAM芯片600的接合位置对应接合在像素电路基板100上，以便于控制整个封装模块的翘曲度。
本实施例中，在接合信号处理芯片200和DRAM芯片600与像素电路基板100之前，在所述第一表面100a先形成了互连件103，后续可利用互连件103作为可选择信号处理芯片200和DRAM芯片600的互连部件，并且在采用电镀或者化学镀的工艺在信号处理芯片200和DRAM芯片600之间形成电连接时可以作为电镀或化学镀的种子层。互连件103可以是以无源方式或有源方式被设置于像素电路基板100的第一表面100a的导电元件，可选实施方式中，互连接103可以与像素电路基板100中读出电路的电路互连端电连接。
互连件103可具有多种形式。本发明一实施例中，互连件103是在第一表面100上形成的互连线，所述互连线的形成方法例如是在第一表面100a上沉积金属层并进行图案化处理形成。本发明一实施例中，互连件103包括互连线，还包括位于所述互连线两端的第一焊垫和第二焊垫，以便于通过第一焊垫和第二焊垫分别与信号处理芯片200和DRAM芯片600互连。
图2是本发明一实施例的CMOS图像传感器封装模块的形成方法中利用接合层接合信号处理芯片和DRAM芯片后的剖面示意图。参照图2，本实施例的CMOS图像传感器封装模块的形成方法包括第二步骤，在像素电路基板100的第一表面100a形成接合层300，并在所述接合层300上接合所述信号处理芯片200和所述DRAM芯片600，信号处理芯片200的第一连接端201和第二连接端202、DRAM芯片600的第三连接端601和第四连接端602均朝向所述第一表面100a。具体可以采用键合方式或者黏结方式将信号处理芯片200和DRAM 芯片600与像素电路基板100接合，即接合层300可以是键合材料或者胶黏材料。
信号处理芯片200和DRAM芯片600可对应于像素电路基板100的外围区域例如读出电路区Ⅱ进行接合，且可对应于感光区Ⅰ接合一个或多个伪芯片10在第一表面100a上。此外，本实施例中，可选择在互连件103处将信号处理芯片200和DRAM芯片600进行互连，优选的，在接合时，信号处理芯片200的第一连接端201和DRAM芯片600的第三连接端601相对设置，并均位于互连件103上方。
进一步的，本实施例在接合信号处理芯片200和DRAM芯片600之前，在接合层300中形成了开口300a，所述开口300a至少暴露出互连件103与所述第一连接端201相对的区域(部分)和所述第三连接端601相对的区域(部分)，即，开口300a可以是分开的两个小开口，以分别暴露出上述互连件103的两区域(例如对应的是互连件103的两个焊垫)，开口300a也可以是一个，将上述互连件103全部暴露出来。所述开口300a用于形成第一互连结构以电连接DRAM芯片600和信号处理芯片200。可选的，可以通过仅在部分区域形成接合材料的方法使接合层300中形成开口300a，其中互连件103在接合层300中暴露出来。在另一种实施方式中，可以先形成覆盖互连件103的接合层300，然后再通过例如干法刻蚀工艺去除部分接合层300材料而形成开口300a。
图3是本发明一实施例的CMOS图像传感器封装模块的形成方法中形成第一互连结构后的剖面示意图。参照图3，本实施例的CMOS图像传感器封装模块的形成方法包括第三步骤，形成第一互连结构210，以电连接上述第一连接端201和第三连接端601，所述第一互连结构210包括嵌于所述接合层300的第一连接块和嵌于所述接合层300的第二连接块，所述第一连接块与所述第一连接端201接触电连接，所述第二连接块与所述第三连接端601接触电连接，所述第一连接块与所述第二连接块电连接。本实施例中，开口300a暴露出了全部的互连件103，所述第一连接块和所述第二连接块为连接并形成为整个的连接块211，连接块211从所述第一连接端201延伸至所述第三连接端601，可以理解，第一连接块和第二连接块也可以是如图6中的分开的设置。
如图3所示，连接块211设置于所述开口300a，具体可以利用电镀或化学镀工艺形成，其中，互连件103可以作为电镀或化学镀的种子层。以化学镀工 艺为例，可包括以下步骤：将接合有信号处理芯片200和DRAM芯片600且在接合层300中形成有开口300a的像素电路基板100放置到含有金属离子的溶液(例如化学镀银、镀镍、镀铜等溶液)中，利用强还原剂使金属离子还原成金属而沉积在开口300a中，经过一段反应时间之后，金属材料形成了第一连接块和第二连接块(本实施例中，经过化学镀之后，第一连接块和第二连接块连接为一整体，可看作同一连接块，即图3中的连接块211)，其中，所述第一连接块覆盖互连件103与第一连接端201相对的部分并与第一连接端201接触电连接，所述第二连接块覆盖互连件103与第三连接端601相对的部分并与第三连接端601接触电连接。第一互连结构210包括上述第一连接块和第二连接块，还可以包括互连件103。
通过在互连件103上形成第一连接块和第二连接块的方法将信号处理芯片200的第一连接端201以及DRAM芯片600的第三连接端601电连接，不需要进行引线键合或者在像素电路基板中再连接，有利于缩小封装结构的尺寸，并且对像素电路基板100中的感光层以及外围电路基本上不会造成影响，可以提高封装模块的可靠性。
图4是本发明一实施例的CMOS图像传感器封装模块的形成方法中形成第二互连结构后的剖面示意图。参照图4，本实施例的CMOS图像传感器封装模块的形成方法包括第四步骤，形成第二互连结构220，所述第二互连结构220设置于所述像素电路基板100和所述接合层300中，所述第二互连结构220与所述读出电路的电路互连端、信号处理芯片200的第二连接端202以及DRAM芯片600的第四连接端602均电连接。
本实施例中，为了避免接合在像素电路基板100上的信号处理芯片200和DRAM芯片600受到外部因素(例如水汽、氧气、振动、撞击、刻蚀等等)的影响，接合更稳固，在形成第一互连结构210之后、形成第二互连结构220之前，还可包括在第一表面100a上形成封装层400的步骤。所述封装层400覆盖信号处理芯片200、DRAM芯片600以及第一表面100a上的间隙，即封装层400也可覆盖在暴露出的接合层300、第一互连结构210上。封装层400可包括诸如氧化硅、氮化硅、碳化硅、氮氧化硅等无机绝缘材料，也可包括诸如聚碳酸脂、聚对苯二甲酸乙二醇酯、聚醚砜、聚苯醚、聚酰胺、聚醚酰亚胺、甲基丙烯酸树脂或环聚烯烃系树脂等热塑性树脂，也可包括诸如环氧树脂、酚醛树脂、脲 醛树脂、甲醛树脂、聚氨酯、亚克力树脂、乙烯酯树脂、酰亚胺类树脂、尿素树脂或三聚氰胺树脂等热固性树脂，也可包括诸如聚苯乙烯、聚丙烯腈等有机绝缘材料。封装层400可通过例如化学气相沉积工艺或者注塑工艺形成。在制作封装层400的过程中，还可通过诸如平坦化处理使其顶表面平坦，以在后续形成导电插塞及再布线层的过程中利用封装层作为支撑面。
另外，为了控制封装模块的翘曲度，在形成接合层300之后、形成封装层400之前，还可在所述接合层300上接合一个或多个伪芯片10，进而使得封装层400还覆盖所述伪芯片10。作为示例，信号处理芯片200和DRAM芯片600对应于像素电路基板100的读出电路区接合，入射光被设定为从所述第二表面100一侧进入像素阵列，所述伪芯片10对应于像素电路基板100的感光区接合。
第二互连结构220可包括形成于像素电路基板100和接合层300中的一个以上的电接触、电连接件以及在它们之间形成的电连接线。本实施例中，形成所述第二互连结构220的方法可包括包括从所述第二表面100b一侧执行孔刻蚀工艺和填孔工艺，以形成多个导电插塞(用金属等导电材料填孔)。可选的，所述多个导电插塞包括电连接读出电路的电路互连端的第一导电插塞111，所述第一导电插塞111设置于所述像素电路基板100中。可选的，所述多个导电插塞还可包括用于电连接信号处理芯片200的第二连接端202的第二导电插塞112，和/或用于电连接DRAM芯片600的第四连接端602的第三导电插塞113，所述第二导电插塞112和第三导电插塞113均穿过所述像素电路基板100和所述接合层300。并且，所述多个导电插塞可包括露出于第二表面100b的端部，以与后续形成的再布线层电连接。所述多个导电插塞也可采用公开的方法形成。
参照图4，本实施例中，所述多个导电插塞包括第一导电插塞111、第二导电插塞112和第三导电插塞113，所述第一导电插塞111接触电连接读出电路的电路互连端(如图4中的第一电路互连端101和第二电路互连端102)，所述第二导电插塞112接触电连接信号处理芯片200的第二连接端202，所述第三导电插塞113接触电连接DRAM芯片600的第四连接端602。
图5是本发明一实施例的CMOS图像传感器封装模块的形成方法中形成再布线层后的剖面示意图。参照图5，本实施例的CMOS图像传感器封装模块的形成方法在形成上述第二互连结构220后，还包括第五步骤，形成再布线层500于像素电路基板100的第二表面100b，使所述再布线层500与所述第二互连结 构220电连接。
具体的，所述再布线层500可形成于像素电路基板100第二表面100b一侧的介质层上，并与上述第二互连结构220的多个导电插塞接触，从而与第二互连结构220电连接。再布线层500的形成过程例如是先在像素电路基板100的第二表面100b利用物理气相沉积(PVD)、原子层沉积(ALD)或者化学气相沉积(CVD)等工艺沉积金属层，然后进行图形化处理以形成再布线层500。再布线层500也可以采用公开方法制作。
上述再布线层500进一步可包括再布线以及与所述再布线电连接的焊垫(I/O pad)，再布线层500可以根据设计要求对第二互连结构220(进而对信号处理芯片200、DRAM芯片600和像素电路基板100)的电气连接进行重新布局。与所述再布线电连接的焊垫可用于再布线层与封装模块的外部信号或装置连接，以对再布线传输的电信号进行处理或控制。
经过上述第一步骤至第五步骤，本实施例的CMOS图像传感器封装模块的形成方法在像素电路基板100的第一表面100a上接合了信号处理芯片200和DRAM芯片600，并提供了在像素电路基板100、信号处理芯片200和DRAM芯片600两两之间形成互连的过程，DRAM芯片600可作为缓存存储读出电路的输出数据，并根据信号处理芯片200的工作速率将存储的数据输出至信号处理芯片200，从而在利用所形成的CMOS图像传感器封装模块进行图像拍摄时，有利于提高对传输的数据和数字图像信号的处理速度，进而提高图像质量。此外，将信号处理芯片200和DRAM芯片600接合在像素电路基板100上，像素阵列基板100的设计余量较大，有助于缩小封装模块整体的尺寸。接合设置的信号处理芯片有利于提供更佳的运算能力以及成像质量，在接合前即摒弃了同一晶圆上的缺陷芯片，相对于晶圆级键合方式工艺难度较低。
本发明实施例还提供一种摄像装置，具备本发明实施例所述的CMOS图像传感器封装模块。本发明实施例的摄像装置可以是微型相机、数码相机、也可以是具有微型相机功能的手机、平板、笔记本电脑、智能眼镜、数字头盔、监视器等各种电子设备。本发明实施例的摄像装置，由于采用了本发明实施例的CMOS图像传感器封装模块，有助于实现较小的尺寸以及较佳的图像质量。
本实施例中的方法和结构采用递进的方式描述，在后的方法和结构重点描述说明的是与在前的方法和结构的不同之处，相关之处可以参照理解。
上述描述仅是对本发明较佳实施例的描述，并非对本发明权利范围的任何限定，任何本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改，因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本发明技术方案的保护范围。

Claims (30)

  1. 一种CMOS图像传感器封装模块，其特征在于，包括：
    像素电路基板，其中包括感光区和读出电路区，CMOS图像传感器的像素阵列设置于所述感光区，读出电路设置于所述读出电路区，所述读出电路具有电路互连端，所述像素电路基板包括相对的第一表面和第二表面；
    接合层，铺设于所述第一表面；
    并列位于所述接合层上的信号处理芯片和DRAM芯片，所述信号处理芯片具有朝向所述第一表面的第一连接端和第二连接端，所述DRAM芯片具有朝向所述第一表面的第三连接端和第四连接端；
    第一互连结构，电连接所述第一连接端和所述第三连接端，所述第一互连结构包括嵌于所述接合层的第一连接块和嵌于所述接合层的第二连接块，所述第一连接块与所述第一连接端接触电连接，所述第二连接块与所述第三连接端接触电连接，所述第一连接块与所述第二连接块电连接；
    第二互连结构，设置于所述像素电路基板和所述接合层中，与所述电路互连端、所述第二连接端以及所述第四连接端均电连接；以及
    再布线层，铺设于所述第二表面，所述再布线层与所述第二互连结构电连接。
  2. 如权利要求1所述的CMOS图像传感器封装模块，其特征在于，所述第一互连结构还包括位于所述第一表面上的互连件，所述第一连接块与所述第二连接块通过所述互连件电连接。
  3. 如权利要求2所述的CMOS图像传感器封装模块，其特征在于，所述互连件包括互连线及位于所述互连线两端的第一焊垫、第二焊垫，所述第一焊垫通过所述第一连接块与所述第一连接端连接，所述第二焊垫通过所述第二连接块与所述第三连接端连接。
  4. 如权利要求2所述的CMOS图像传感器封装模块，其特征在于，所述互连件包括互连线，所述互连线的两端分别通过所述第一连接块与所述第一连接端连接、通过所述第二连接块与所述第三连接端连接。
  5. 如权利要求1所述的CMOS图像传感器封装模块，其特征在于，所述第一连接块和所述第二连接块为同一连接块，所述同一连接块从所述第一连接端延伸至所述第三连接端。
  6. 如权利要求1所述的CMOS图像传感器封装模块，其特征在于，所述第二互连结构包括设置于所述像素电路基板中的第一导电插塞，所述第一导电插塞电连接所述电路互连端和所述再布线层。
  7. 如权利要求6所述的CMOS图像传感器封装模块，其特征在于，所述电路互连端包括第一电路互连端和第二电路互连端，所述第二互连结构包括两个所述第一导电插塞，以分别电连接所述第一电路互连端与所述再布线层以及所述第二电路互连端与所述再布线层。
  8. 如权利要求1所述的CMOS图像传感器封装模块，其特征在于，所述第二互连结构包括穿过所述像素电路基板和所述接合层的第二导电插塞，所述第二导电插塞电连接所述第二连接端和所述再布线层。
  9. 如权利要求1所述的CMOS图像传感器封装模块，其特征在于，所述第二互连结构包括穿过所述像素电路基板和所述接合层的第三导电插塞，所述第三导电插塞电连接所述第四连接端和所述再布线层。
  10. 如权利要求1所述的CMOS图像传感器封装模块，其特征在于，所述信号处理芯片和所述DRAM芯片对应于所述读出电路区设置于所述第一表面上。
  11. 如权利要求1所述的CMOS图像传感器封装模块，其特征在于，所述再布线层包括再布线以及与所述再布线电连接的焊垫。
  12. 如权利要求1所述的CMOS图像传感器封装模块，其特征在于，还包括封装层，所述封装层设置于所述第一表面上，所述封装层覆盖所述信号处理芯片、所述DRAM芯片并填充间隙。
  13. 如权利要求12所述的CMOS图像传感器封装模块，其特征在于，还包括伪芯片，所述伪芯片位于所述接合层上，所述封装层还覆盖所述伪芯片。
  14. 如权利要求13所述的CMOS图像传感器封装模块，其特征在于，入射光被设定为从所述第二表面一侧进入所述像素阵列，所述伪芯片对应于所述感光区设置于所述第一表面上。
  15. 如权利要求1所述的CMOS图像传感器封装模块，其特征在于，所述CMOS图像传感器为背照式CMOS图像传感器。
  16. 如权利要求1所述的CMOS图像传感器封装模块，其特征在于，所述接合层包括胶黏材料。
  17. 一种摄像装置，包括如权利要求1至16任一项所述的CMOS图像传感 器封装模块。
  18. 一种CMOS图像传感器封装模块的形成方法，其特征在于，包括：
    提供像素电路基板、信号处理芯片和DRAM芯片，所述像素电路基板包括感光区和读出电路区，CMOS图像传感器的像素阵列设置于所述感光区，读出电路设置于所述读出电路区，所述读出电路具有电路互连端，所述像素电路基板包括相对的第一表面和第二表面，所述信号处理芯片具有第一连接端和第二连接端，所述DRAM芯片具有第三连接端和第四连接端；
    在所述第一表面形成接合层，并在所述接合层上接合所述信号处理芯片和所述DRAM芯片，所述第一连接端、所述第二连接端、所述第三连接端和所述第四连接端均朝向所述第一表面；
    形成第一互连结构，以电连接所述第一连接端和所述第三连接端，所述第一互连结构包括嵌于所述接合层的第一连接块和嵌于所述接合层的第二连接块，所述第一连接块与所述第一连接端接触电连接，所述第二连接块与所述第三连接端接触电连接，所述第一连接块与所述第二连接块电连接；
    形成第二互连结构，设置于所述像素电路基板和所述接合层中，与所述电路互连端、所述第二连接端以及所述第四连接端均电连接；以及
    在所述第二表面形成再布线层，所述再布线层与所述第二互连结构电连接。
  19. 如权利要求18所述的CMOS图像传感器封装模块的形成方法，其特征在于，在形成所述接合层之前，还包括：在所述第一表面上形成互连件，其中，所述第一连接块与所述第二连接块通过所述互连件电连接。
  20. 如权利要求19所述的CMOS图像传感器封装模块的形成方法，其特征在于，所述接合层中具有开口，所述开口暴露出所述互连件与所述第一连接端相对的区域和与所述第三连接端相对的区域。
  21. 如权利要求20所述的CMOS图像传感器封装模块的形成方法，其特征在于，形成所述第一连接块和所述第二连接块的方法包括：
    将设置有所述接合层、所述信号处理芯片和所述DRAM芯片的像素电路基板放置到化学镀溶液中，所述化学镀溶液中包括金属离子和还原剂；以及
    经预定时间后，在所述开口中形成所述第一连接块和所述第二连接块，其中，所述第一连接块覆盖所述互连件与所述第一连接端相对的区域并与所述第一连接端接触电连接，所述第二连接块覆盖所述互连件与所述第三连接端相对 的区域并与所述第三连接端接触电连接。
  22. 如权利要求21所述的CMOS图像传感器封装模块的形成方法，其特征在于，所述开口暴露出所述互连件，所述第一连接块和所述第二连接块为同一连接块，所述同一连接块从所述第一连接端延伸至所述第三连接端。
  23. 如权利要求18所述的CMOS图像传感器封装模块的形成方法，其特征在于，所述第一连接块和所述第二连接块的材料包括铜、镍、锌、锡、银、金、钨和镁中的一种或多种。
  24. 如权利要求18所述的CMOS图像传感器封装模块的形成方法，其特征在于，形成所述第二互连结构的方法包括从所述第二表面一侧执行孔刻蚀工艺和填孔工艺，以形成多个导电插塞。
  25. 如权利要求24所述的CMOS图像传感器封装模块的形成方法，其特征在于，所述多个导电插塞包括第一导电插塞，所述第一导电插塞设置于所述像素电路基板中，并电连接所述电路互连端和所述再布线层。
  26. 如权利要求24所述的CMOS图像传感器封装模块的形成方法，其特征在于，所述多个导电插塞包括第二导电插塞，所述第二导电插塞穿过所述像素电路基板和所述接合层，并电连接所述第二连接端和所述再布线层。
  27. 如权利要求24所述的CMOS图像传感器封装模块的形成方法，其特征在于，所述多个导电插塞包括第三导电插塞，所述第三导电插塞穿过所述像素电路基板和所述接合层，并电连接所述第四连接端和所述再布线层。
  28. 如权利要求18所述的CMOS图像传感器封装模块的形成方法，其特征在于，在形成所述第一互连结构之后、形成所述第二互连结构之前，还包括：在所述第一表面上形成封装层，所述封装层覆盖所述信号处理芯片、所述DRAM芯片并填充间隙。
  29. 如权利要求28所述的CMOS图像传感器封装模块的形成方法，其特征在于，在形成所述接合层之后，还包括：在所述接合层上接合伪芯片；其中所述封装层还覆盖所述伪芯片。
  30. 如权利要求29所述的CMOS图像传感器封装模块的形成方法，其特征在于，所述信号处理芯片和所述DRAM芯片对应于所述读出电路区接合，入射光被设定为从所述第二表面一侧进入所述像素阵列，所述伪芯片对应于所述感光区接合。
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