CN105977255A - 具有为块状半金属的半导体材料的器件及其形成方法 - Google Patents

具有为块状半金属的半导体材料的器件及其形成方法 Download PDF

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CN105977255A
CN105977255A CN201510724065.5A CN201510724065A CN105977255A CN 105977255 A CN105977255 A CN 105977255A CN 201510724065 A CN201510724065 A CN 201510724065A CN 105977255 A CN105977255 A CN 105977255A
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bismuth
source
drain contact
channel structure
contact area
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CN105977255B (zh
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让-皮埃尔·科林格
卡洛斯·H·迪亚兹
杨育佳
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明描述了器件和形成这样的器件的方法，器件具有当为块状时是半金属但是在器件中是半导体的材料。示例性结构包括衬底、第一源极/漏极接触区、沟道结构、栅极电介质、栅电极和第二源极/漏极接触区。衬底具有上表面。沟道结构连接至第一源极/漏极接触区并且位于第一源极/漏极接触区上方，并且沟道结构位于衬底的上表面上方。沟道结构具有在第一源极/漏极接触区之上延伸的侧壁。沟道结构包括含铋半导体材料。栅极电介质为沿着沟道结构的侧壁。栅电极为沿着栅极电介质。第二源极/漏极接触区连接至沟道结构并且位于沟道结构上方。本发明涉及具有为块状半金属的半导体材料的器件及其形成方法。

Description

具有为块状半金属的半导体材料的器件及其形成方法
技术领域
本发明涉及具有为块状半金属的半导体材料的器件及其形成方法。
背景技术
半导体器件用于各种电子应用中，诸如个人电脑、手机、数码相机和其他电子设备。通常通过在半导体衬底上方依次沉积材料的绝缘或介电层、导电层和半导体层并且使用光刻图案化各个材料层以在其上形成电路组件和元件来制造半导体器件。
晶体管是通常形成在半导体器件上的电路组件或元件。除了电容器、电感器、电阻器、二极管、导电线或其他元件之外，可以在半导体器件上形成许多晶体管，这取决于电路设计。场效应晶体管(FET)是一种类型的晶体管。集成电路的整体运行速度，并且因此，使用集成电路的设备的运行速度可以受到集成电路中的晶体管的运行速度的影响。
发明内容
根据本发明的一个实施例，提供了一种结构，包括：衬底，具有上表面；第一源极/漏极接触区；沟道结构，连接至所述第一源极/漏极接触区并且位于所述第一源极/漏极接触区上方，所述沟道结构位于所述衬底的上表面上方，所述沟道结构具有在所述第一源极/漏极接触区之上延伸的侧壁，所述沟道结构包括含铋半导体材料；栅极电介质，沿着所述沟道结构的所述侧壁；栅电极，沿着所述栅极电介质；以及第二源极/漏极接触区，连接至所述沟道结构并且位于所述沟道结构上方。
根据本发明的另一个实施例，提供了一种结构，包括：衬底，包括水平表面，所述水平表面是所述衬底的上表面；第一垂直沟道晶体管，位于所述衬底的所述水平表面上方，所述第一垂直沟道晶体管包括：第一源极/漏极接触区，第一含铋沟道结构，连接至所述第一源极/漏极接触区并且位于所述第一源极/漏极接触区上方，所述第一含铋沟道结构是半导体并且包括n型掺杂剂，所述第一含铋沟道结构垂直于所述水平表面延伸，第一栅极电介质，位于所述第一含铋沟道结构周围，第一栅电极，位于所述第一栅极电介质周围，所述第一栅极电介质设置在所述第一含铋沟道结构和所述第一栅电极之间，和第二源极/漏极接触区，连接至所述第一含铋沟道结构并且位于所述第一含铋沟道结构上方；以及第二垂直沟道晶体管，位于所述衬底的所述水平表面上方，所述第二垂直沟道晶体管包括：第三源极/漏极接触区，第二含铋沟道结构，连接至所述第三源极/漏极接触区并且位于所述第三源极/漏极接触区上方，所述第二含铋沟道结构是半导体并且包括p型掺杂剂，所述第二含铋沟道结构垂直于所述水平表面延伸，第二栅极电介质，位于所述第二含铋沟道结构周围，第二栅电极，位于所述第二栅极电介质周围，所述第二栅极电介质设置在所述第二含铋沟道结构和所述第二栅电极之间，和第四源极/漏极接触区，连接至所述第二含铋沟道结构并且位于所述第二含铋沟道结构上方。
根据本发明的又另一实施例，提供了一种方法，包括：形成第一源极/漏极接触区；在所述第一源极/漏极接触区上方和在衬底上方形成第一栅电极；形成穿过所述第一栅电极至所述第一源极/漏极接触区的第一开口；沿着所述第一开口的第一侧壁形成第一栅极电介质；在所述第一开口中沉积第一含铋材料以形成第一含铋沟道结构，所述第一栅极电介质设置在所述第一栅电极和所述第一含铋沟道结构之间，所述第一含铋沟道结构连接至所述第一源极/漏极接触区；在所述第一含铋沟道结构上方形成第二源极/漏极接触区，并且所述第二源极/漏极接触区连接至所述第一含铋沟道结构；以及结晶所述第一含铋材料，所述结晶包括实施退火。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各个方面。应该强调的是，根据工业中的标准实践，对各种部件没有按比例绘制并且仅仅用于说明的目的。实际上，为了清楚讨论起见，各种部件的尺寸可以被任意增大或缩小。
图1至图9是根据一些实施例的制造互补晶体管结构的中间阶段的截面图。
图10A至图10C是根据一些实施例的图9中的结构的覆盖布局图。
图11是根据一些实施例的图1至图9的工艺的流程图。
图12A至图12H是根据一些实施例的含铋沟道结构和相应的栅极电介质的示例性截面。
图13是根据一些实施例的垂直地集成图1至图9的实施例的一些方面的结构。
图14是根据一些实施例的制造图13的结构的工艺的流程图。
图15至图17是根据一些实施例的在半导体衬底上形成高度掺杂的源极/漏极接触区的第一制造工艺的中间阶段的截面图。
图18是根据一些实施例的图15至图17的工艺的流程图。
图19至图22是根据一些实施例的用于在半导体衬底上形成高度掺杂的源极/漏极接触区的第二制造工艺的中间阶段的截面图。
图23是根据一些实施例的图19至图22的工艺的流程图。
图24至图32是根据一些实施例的制造另一互补晶体管结构的中间阶段的截面图。
图33A至图33C是根据一些实施例的图32中的结构的覆盖布局图。
图34是根据一些实施例的图24至图32的工艺的流程图。
图35至图38根据一些实施例示出了制造互补晶体管结构的中间阶段的截面图。
图39是结合图35至图38示出和描述的工艺的流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。
根据各个实施例提供了诸如晶体管，和更具体地垂直沟道晶体管，的器件及其形成方法。这些器件可以包括为块状形式的半金属但是当引入器件中时是半导体的材料。示出了形成器件的中间阶段。本文中论述了实施例的一些变化。贯穿各个视图和说明性实施例，相同的参考标号用于代表相同的元件。虽然以特定的顺利论述了方法实施例，但是可以以任何逻辑顺序实施各个其他方法实施例并且可以包括本文中论述的更少或更多的步骤。
图1至图9根据一些实施例示出了制造互补晶体管结构的中间阶段的截面图。图10A至图10C示出了图9中的结构的覆盖布局图。图11是结合图1至图9示出和描述的工艺的流程图。将在图1至图9的具体环境中描述图11中示出的步骤。
图1示出了具有第一区42和第二区44的衬底40、位于衬底40上的底层介电层46、位于底层介电层46上的源极/漏极接触区48和50以及位于源极/漏极接触区48和50以及底层介电层46上的第一介电层52。该衬底40可以是任何适当的支持结构，并且可以包括半导体衬底。在一些实施例中，衬底40是半导体衬底，以及在其他实施例中，衬底40包括具有各个介电层的半导体衬底，各个介电层例如在半导体衬底上的层间介电(ILD)层和/或金属间介电(IMD)层。将参考随后的图更详细地解释一些实例。半导体衬底可以是块状半导体衬底、绝缘体上半导体(SOI)衬底、多层或梯度衬底等。半导体衬底的半导体可以包括任何半导体材料，诸如元素半导体，如硅、锗等；化合物或合金半导体，包括SiC、GaAs、GaP、InP、InAs、锑化铟、SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP等或它们的组合。例如，半导体衬底可以进一步为晶圆。第一区42可以用于形成第一类型的器件，诸如n沟道晶体管，并且第二区44可以用于形成第二类型(例如，互补)的器件，诸如P沟道晶体管。
在衬底40上方和上形成底层介电层46。可以通过诸如化学汽相沉积(CVD)、等离子体增强CVD(PECVD)、旋涂等或它们的组合的合适的沉积技术，或者诸如热氧化等的合适的生长技术或它们的组合来形成底层介电层46，并且底层介电层46可以由诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、未掺杂的硅酸盐玻璃(USG)、氮化物、氮氧化物等形成。可以实施化学机械抛光(CMP)以平坦化底层介电层46。
在图1和图11的步骤200中，在底层介电层46上方和上形成源极/漏极接触区48和50。源极/漏极接触区48形成于第一区42中，并且源极/漏极接触区50形成在第二区44中。源极/漏极接触区48和50可以是任何可接受的导电材料，并且一些实施例预期源极/漏极接触区48和50均为金属、金属-半导体化合物等或它们的组合。示例性金属包括铜、金、钴、钛、铝、镍、钨、氮化钛(TiN)等。示例性金属-半导体化合物包括硅化镍(NiSi)、硅化钛(TiSi)、硅化钨(WSi)、硅化钴(CoSi)，钛锗(TiGe)、NiSiGe、NiGe等。可以通过在底层介电层46上沉积一层导电材料和随后将该层导电材料图案化成源极/漏极接触区48和50来形成源极/漏极接触区48和50。在其中导电材料是金属的一些实施例中，可以通过物理汽相沉积(PVD)、原子层沉积(ALD)、CVD等或它们的组合将金属沉积在底层介电层46上。在其中导电材料是金属半导体化合物的一些实施例中，可以通过CVD、PECVD、低压CVD(LPCVD)、蒸发等或它们的组合在底层介电层46上沉积诸如硅(如多晶硅)、多晶锗等的半导体材料并且可以在半导体材料上沉积诸如以上所述的金属。然后可以实施退火以使半导体材料与金属反应以形成半导体-金属化合物。图案化可以使用可接受的光刻和蚀刻工艺，诸如反应离子蚀刻(RIE)、化学蚀刻等。可以使用其他图案化技术。在图示中，源极/漏极接触区48与源极/漏极接触区50分隔开，并且源极/漏极接触区48不电连接至源极/漏极接触区50。在其他实施例中，源极/漏极接触区48和50可以是相同的导电区，并且可以电连接在一起。
在图1中和图11的步骤202中继续，在源极/漏极接触区48和50和底层介电层46上和上方形成第一介电层52。可以通过诸如CVD、PECVD、旋涂等或它们的组合的合适的沉积技术形成第一介电层52，并且第一介电层52可以由诸如氧化硅、PSG、BSG、BPSG、USG、氮化物、氮氧化物等形成。可以实施CMP以平坦化第一介电层52。
在图2和图11的步骤204中，在第一介电层52上以及在第一区42和第二区44中形成栅电极54和56。栅电极54形成在第一区42中并且直接位于源极/漏极接触区48的至少一部分之上，并且栅电极56形成在第二区44中并且直接位于源极/漏极接触区50的至少一部分之上。栅电极54和56可以是任何可接受的导电材料，诸如含金属材料、金属半导体化合物、掺杂的半导体等。在示图中，栅电极54和56是含金属材料，诸如TiN、TaN、TaC、Co、Ru、Al、W等或它们的组合。可以通过在第一介电层52上沉积导电材料层和随后将导电材料层图案化成栅电极54和56来形成栅电极54和56。在示图中，可以通过PVD、ALD、CVD等或者它们的组合在第一介电层52上沉积含金属材料。图案化可以使用可接受的光刻和蚀刻工艺，诸如RIE等。可以使用其他图案化技术。在其他实施例中，栅电极54和56是掺杂的半导体材料，诸如n掺杂的多晶硅或p掺杂的多晶硅。
在图2和图11的步骤206中，在栅电极54和56以及第一介电层52上形成第二介电层58。可以通过诸如CVD、PECVD、旋涂等或它们的组合的合适的沉积技术来形成第二介电层58，并且第二介电层58可以由诸如氧化硅、PSG、BSG、BPSG、USG、氮化物、氮氧化物等的介电材料形成。可以实施CMP以平坦化第二介电层58。
在图3和图11的步骤208中，图案化第二介电层58、栅电极54和56以及第一介电层52以形成沟道开口60和62。沟道开口60形成为穿过第二介电层58、栅电极54和第一介电层52至第一区42中的源极/漏极接触区48。通过沟道开口60暴露源极/漏极接触区48的至少一部分。沟道开口62形成为穿过第二介电层58、栅电极56和第一介电层52至第二区44中的源极/漏极接触区50。通过沟道开口62暴露源极/漏极接触区50的至少一部分。可以通过使用诸如RIE、各向同性等离子体蚀刻等的可接受的光刻和蚀刻工艺来形成沟道开口60和62。
在图4和图11的步骤210中，分别在沟道开口60和62中形成栅极电介质64和66。在一些实施例中，栅极电介质64和66各自包括氧化硅、氮化硅或它们的多层。在其他实施例中，栅极电介质64和66各自包括高k介电材料，并在这些实施例中，栅极电介质64和66的k值大于约7.0，并且可以包括金属氧化物或Hf、Al、Zr、La、Mg、Ba、Ti、Zr、Lu和它们的组合的硅酸盐。可以通过分子束沉积(MBD)、ALD、PECVD等或它们的组合来沉积栅极电介质64和66的层。诸如各向异性蚀刻(如等离子体蚀刻)、RIE等的合适的蚀刻工艺可以用于去除栅极电介质64和66的层的基本上水平部分，从而使得栅极电介质64和66的层的垂直部分保留在沟道开口60和62中以形成分别沿着沟道开口60和62的侧壁的栅极电介质64和66。在去除了栅极电介质64和66的层的水平部分之后，通过沟道开口60和62暴露出源极/漏极接触区48和50的至少相应部分。
分别在沟道开口60和62中的栅极电介质64和66的相对内侧壁之间产生尺寸68和70。尺寸68和70可以引起当为块状半金属材料的材料形成在沟道开口60和62中时，将为块状半金属材料的材料转变成半导体材料，这将在下文中进一步论述。
在图5和图6和图11的步骤212中，在第一区42中的沟道开口60中形成n掺杂的含铋沟道结构76，并且在n掺杂的含铋沟道结构76上形成源极/漏极接触区78。在图5中，在第二介电层58上以及在沟道开口60和62中沉积诸如硬掩模的掩模层72。图案化掩模层72以暴露第一区42中的沟道开口60。例如，掩模层72可以由氮化硅、碳化硅、氮氧化硅、碳氮化硅等形成并且可以使用CVD、PECVD、ALD等形成。图案化可以使用可接受的光刻和蚀刻工艺，诸如RIE等。暴露沟道开口60的穿过掩模层72的开口的横向尺寸可以比沟道开口60的相应的横向尺寸更大。
然后在第一区42中的沟道开口60中沉积n掺杂的含铋材料74，同时由于掩模层72而防止n掺杂的含铋材料74沉积在沟道开口62中。示例性含铋材料包括铋(Bi)、掺杂的铋等。铋材料中的示例性n型掺杂剂是碲(Te)。可以通过ALD、CVD等或它们的组合沉积含铋材料74。在沉积含铋材料74期间，含铋材料74可以掺杂有，例如原位掺杂有，n型掺杂剂。含铋材料74中的n型掺杂剂的浓度可以在从约1×1017cm-3至约5×1020cm-3的范围内。作为实例，可以使用下面的前体气体中的一种或多种使用ALD或CVD来沉积铋(Bi)：二乙酸三苯基铋(V)(CH3CO2)2Bi(C6H5)3)、三苯基铋(Bi(C6H5)3)和三(2-甲氧基苯基)铋(CH3OC6H4)3Bi)。作为实例，在使用下面的前体气体中的一种或多种沉积含铋材料期间，可以原位掺杂碲(Te)：无水四溴化碲(TeBr4)和四氯化碲(TeCl4)。
在图6中，去除过量的含铋材料74和掩模层72。可以使用诸如CMP的可接受的平坦化工艺去除过量的含铋材料74。平坦化工艺可以去除过量的含铋材料74和/或掩模层72，直至由n掺杂的含铋材料74形成的源极/漏极接触区78延伸至位于第二介电层58之上适当的高度。在平坦化工艺后，可以使用可接受的蚀刻去除掩模层72的剩余部分，蚀刻诸如对掩模层72的材料具有选择性的湿蚀刻。除了由n掺杂的含铋材料74形成的源极/漏极接触区78之外，在沟道开口60中的n掺杂的含铋材料74的剩余部分形成了第一区42中的n掺杂的含铋沟道结构76。n掺杂的含铋沟道结构76连接至第一区42中的源极/漏极接触区78。
在图7和图8以及图11的步骤214中，在第二区44中的沟道开口62中形成p掺杂的含铋沟道结构84，并且在p掺杂的含铋沟道结构84上形成源极/漏极接触区86。在图7中，将诸如硬掩模的掩模层80沉积在第二介电层58上、源极/漏极接触区78上以及沟道开口62中。图案化掩模层80以暴露第二区44中的沟道开口62。掩模层80可以由例如氮化硅、碳化硅、氮氧化硅、碳氮化硅等形成并且可以使用CVD、PECVD、ALD等形成。图案化可以使用可接受的光刻和蚀刻工艺，诸如RIE等。暴露沟道开口62的穿过掩模层80的开口的横向尺寸可以比沟道开口62的相应的横向尺寸更大。
然后，在第二区44中的沟道开口62中沉积p掺杂的含铋材料82。示例性含铋材料包括铋(Bi)、掺杂的铋等。铋材料中的示例性p型掺杂剂是锡(Sn)。可以通过ALD、CVD等或它们的组合沉积含铋材料82。在沉积含铋材料82期间，含铋材料82可以掺杂有，例如原位掺杂有，p型掺杂剂。含铋材料82中的p型掺杂剂的浓度可以在从约1×1017cm-3至约5×1020cm-3的范围内。作为实例，可以使用下面的前体气体中的一种或多种使用ALD或CVD来沉积铋(Bi)：二乙酸三苯基铋(V)(CH3CO2)2Bi(C6H5)3)、三苯基铋(Bi(C6H5)3)和三(2-甲氧基苯基)铋(CH3OC6H4)3Bi)。作为实例，在使用下面的前体气体中的一种或多种沉积含铋材料期间，可以原位掺杂锡(Sn)：SnH4、SnH3Cl、SnH2Cl2、SnHCl3、SnH3、SnH2Cl、SnHCl2、SnH2、HSnCl、SnH、SnCl4、SnCl3、SnCl2和SnCl。
在图8中，去除过量的含铋材料82和掩模层80。可以使用诸如CMP的可接受的平坦化工艺去除过量的含铋材料82。平坦化工艺可以去除过量的含铋材料82和/或掩模层80，直至由p掺杂的含铋材料82形成的源极/漏极接触区86延伸至位于第二介电层58之上适当的高度。在平坦化工艺后，可以使用可接受的蚀刻去除掩模层80的剩余部分，蚀刻诸如对掩模层80的材料具有选择性的湿蚀刻。除了由p掺杂的含铋材料82形成的源极/漏极接触区86之外，在沟道开口62中的p掺杂的含铋材料82的剩余部分形成了第二区44中的p掺杂的含铋沟道结构84。p掺杂的含铋沟道结构84连接至第二区44中的源极/漏极接触区50。
虽然结合图5至图8描述的工艺被描述为按照特定的顺序，但是例如，可以在n掺杂的含铋沟道结构76之前形成p掺杂的含铋沟道结构84。例如，可以在图11中的步骤212之前实施步骤214。
此外，在图8和图11的步骤216中，在源极/漏极接触区78和86以及在第二介电层58上形成第三介电层88。可以通过诸如CVD、PECVD、旋涂等或它们的组合的合适的沉积技术形成第三介电层88，并且第三介电层88可以由诸如氧化硅、PSG、BSG、BPSG、USG、氮化物、氮氧化物等的介电材料形成。可以实施CMP以平坦化第三介电层88。
在图9和图11的步骤218中，形成至n沟道晶体管94和P沟道晶体管96中的相应组件的接触件90a、90b、90c、92a、92b和92c。用于接触件90a、90b、90c、92a、92b和92c的开口形成为穿过相应的第三介电层88、第二介电层58和第一介电层52。可以使用可接受的光刻和蚀刻技术形成开口。在开口中形成诸如扩散阻挡层、粘合层等的衬垫和导电材料。衬垫可以包括钛、氮化钛、钽、氮化钽等。导电材料可以是铜、铜合金、银、金、钨、铝、镍等。可以实施诸如CMP的平坦化工艺以从第三介电层88的表面去除过量的材料。剩余的衬垫和导电材料在开口中形成接触件90a、90b、90c、92a、92b和92c。接触件90a物理连接和电连接至第一区42中的源极/漏极接触区48。接触件90b物理连接和电连接至第一区42中的栅电极54。接触件90c物理连接和电连接至第一区42中的源极/漏极接触区78。接触件92a物理连接和电连接至第二区44中的源极/漏极接触区50。接触件92b物理连接和电连接至第二区44中的栅电极56。接触件92c物理连接和电连接至第二区44中的源极/漏极接触区86。接触件92a和92b可以均为源极接触件。接触件90b和92b可以均为栅极接触件。接触件90c和92c可以均为漏极接触件。
在图11的步骤220中和在形成接触件90a、90b、90c、92a、92b和92c之后，可以对图9的结构进行退火以使该结构(包括n掺杂的含铋沟道结构76和p掺杂的含铋沟道结构84)中的含铋材料结晶。由于铋的熔点较低，例如271.4℃，退火可以是低温退火以用于结晶。在一些实施例中，在400℃或更小，诸如300℃或更小，并且更特别地在275℃下实施低温退火并且持续时间在从约0.01秒到约300秒的范围内。
图9进一步示出了区域10A、10B和10C，分别在图10A、10B和10C中以覆盖布局示出区域10A、10B和10C。布局图10A、10B和10C示出了图9中的更详细的组件。从图10B可以看出，栅电极54和56分别包裹环绕n掺杂的含铋沟道结构76和p掺杂的含铋沟道结构84。因此晶体管94和96可以被称为垂直沟道、全环栅器件。图10A、10B和10C进一步示出了图9中示出的截面9-9。
图12A至图12H示出了诸如在图10B和图10C中可以分别具有的n掺杂的含铋沟道结构76和/或p掺杂的含铋沟道结构84(称为“沟道结构76/84”)和栅极电介质64和/或66(称为“栅极电介质64/66”)的示例性截面。在图12A中，沟道结构76/84可以具有圆形截面，其中，栅极电介质64/66外衬于该截面。在图12B中，沟道结构76/84可以具有椭圆形截面，其中，栅极电介质64/66外衬于该截面。在图12C中，沟道结构76/84可以具有圆角方形截面，其中，栅极电介质64/66外衬于该截面。在图12D中，沟道结构76/84可以具有圆角矩形截面，其中，栅极电介质64/66外衬于该截面。在图12E中，沟道结构76/84可以具有方形截面，其中，栅极电介质64/66外衬于该截面。在图12F中，沟道结构76/84可以具有矩形截面，其中，栅极电介质64/66外衬于该截面。在图12G中，沟道结构76/84可以具有三角形截面，其中，栅极电介质64/66外衬于该截面。在图12H中，沟道结构76/84可以具有六边形截面，其中，栅极电介质64/66外衬于该截面。沟道结构76/84可以具有其他截面。本领域普通技术人员将容易理解，可以通过形成沟道开口60和62来形成该截面。
图13示出了根据一些实施例的图1至图9的实施例的各方面的垂直集成。图14是结合图13描述的工艺的流程图。将在图13的具体环境中描述图14中示出的步骤。
在图13和图14的步骤222中，对半导体衬底100进行前段制程(FEOL)处理。半导体衬底100可以是块状半导体衬底、绝缘体上半导体(SOI)衬底的有源层、多层或梯度衬底等。半导体衬底100的半导体材料可以是元素半导体，诸如硅、锗等；化合物或合金半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟、SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP或它们的组合。FEOL工艺可以形成器件102，诸如位于半导体衬底100中和/或上的晶体管、二极管、电容器、电阻器等。任何可接受的FEOL处理用于用于形成这样的器件102以用于给定的应用。
进一步在图13和图14的步骤224中，在半导体衬底100上形成第一互连结构104。第一互连结构104可以包括位于半导体衬底100上的一个或多个介电层中的一个或多个金属化图案。第一互连结构104可以至少部分地将器件102电连接在一起以形成集成电路。任何可接受的处理可用于形成这样的第一互连结构104。
进一步在图13和图14中的步骤226中，在第一互连结构104上形成第一互补含铋沟道晶体管结构106。第一晶体管结构106包括组件并且可以如结合图1至图9和图11的步骤200至218示出和论述的那样形成。第一互连结构104的最上面的介电层可以是在图1至图9中论述的底层介电层46。可以在第一互连结构104中形成电连接至第一晶体管结构106中的源极/漏极接触区48和50的通孔(未标注)。
进一步在图13和图14中的步骤228中，在第一互补含铋沟道晶体管结构106上形成第二互连结构108。第二互连结构108可以包括位于第一晶体管结构106上的一个或多个介电层中的一个或多个金属化图案。第二互连结构108可以电连接至第一晶体管结构106中的n沟道晶体管94和p沟道晶体管96，诸如通过穿过第二互连结构108的一个或多个介电层至接触件90a、90b、90c、92a、92b和92c的通孔。可以使用任何可接受的处理形成这样的第二互连结构108。
进一步在图13和图14的步骤230中，在第二互连结构108上形成第二互补含铋沟道晶体管结构110。第二晶体管结构110包括组件并且可以如结合图1至图9和图11的步骤200至218示出和论述的那样形成。第二互连结构108的最上面的介电层可以是在图1至图9中论述的底层介电层46。可以在第二互连结构108中形成电连接至第二晶体管结构110中的源极/漏极接触区48和50的通孔(未标注)。
进一步在图13和图14中的步骤232中，在第二互补含铋沟道晶体管结构110上形成第三互连结构112。第三互连结构112可以包括位于第二晶体管结构110上的一个或多个介电层中的一个或多个金属化图案。第三互连结构112可以电连接至第二晶体管结构110中的n沟道晶体管94和p沟道晶体管96，诸如通过穿过第三互连结构112的一个或多个介电层至接触件90a、90b、90c、92a、92b和92c的通孔。可以使用任何可接受的处理形成这样的第三互连结构112。
更多或更少的互补含铋沟道、垂直晶体管结构可以垂直地集成到图13中示出的实施例中，诸如通过重复或省略一些论述的步骤。本领域普通技术人员将容易理解如何实现这样的集成。
在图14的步骤234中，可以对图13的结构进行退火以使位于互补含铋沟道晶体管结构106和110中的含铋材料结晶。退火可以是低温退火。在一些实施例中，在400℃或更小，诸如300℃或更小，并且更特别地在275℃下实施低温退火并且持续时间在从约0.01秒到约300秒的范围内。在已经形成所有的互补含铋沟道晶体管结构之后，对多个互补含铋沟道晶体管结构可以实施一次退火。由于诸如位于n掺杂的含铋沟道结构76和p掺杂的含铋沟道结构84中的含铋材料当被熔融时通常体积不膨胀，所以当对含铋材料进行退火时，含铋材料可以完全封闭而不会由于含铋材料而造成例如开裂的重大风险。其他实施方式预期实施多次退火。
图15至图17，图19至图22，图24至图32根据一些实施例示出了制造另一互补晶体管结构的中间阶段的截面图。图15至图17示出了在半导体衬底120上形成高度掺杂的源极/漏极接触区162和166的第一方法。图18是结合图15至图17描述和示出的工艺的流程图，并且将在图15至图17的具体环境中描述在图18中示出的步骤。图19至图22示出了用于在半导体衬底120上形成高度掺杂的源极/漏极接触区162和166的第二方法。图23是结合图19至图22示出和描述的工艺的流程图，并且将在图19至图22的具体环境中描述在图23中示出的步骤。图24至图32示出了在半导体衬底120上形成高度掺杂的源极/漏极接触区162和166之后的形成互补晶体管结构的方法，诸如在图15至图17或图19至图22中所示。图34是结合图24至图32示出和描述的工艺的流程图，并且将在图24至图32的具体环境中描述在图34中示出的步骤。
结合图15至图18中的工艺，在图15和图18的步骤240中，在半导体衬底120的第一区122和第二区124之间的半导体衬底120中形成隔离区126。半导体衬底120可以是块状半导体衬底、绝缘体上半导体(SOI)衬底、多层或梯度衬底等。半导体衬底120的半导体可以包括任何半导体材料，诸如元素半导体，如硅、锗等；化合物或合金半导体，包括SiC、GaAs、GaP、InP、InAs、锑化铟、SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP等或它们的组合。例如，半导体衬底120可以进一步为晶圆。在一些实施例中，半导体衬底120是硅晶圆。
形成从半导体衬底的顶面延伸至半导体衬底120内的隔离区126。隔离区126可以是浅沟槽隔离(STI)区。隔离区126的形成可以包括蚀刻半导体衬底120以形成沟槽，和用介电材料填充沟槽以形成隔离区126。例如，隔离区126可以由通过高密度等离子体沉积的氧化硅形成，但是也可以使用根据各种技术形成的其他介电材料。可以实施诸如CMP的平坦化工艺以去除过量的介电材料以及形成与半导体衬底120的顶面共面的隔离区126的顶面。在其他实施例中，可以通过热氧化以生长诸如氧化硅的介电材料来形成隔离区。
在图16和图18的步骤242中，在半导体衬底120的第二区124上形成掩模128。掩模128不位于半导体衬底120的第一区122上，并且暴露出第一区122。掩模128可以是光刻胶，通过使用旋涂技术来形成光刻胶以及使用可接受的光刻技术来图案化光刻胶。
进一步在图16和在图18的步骤244中，一旦形成掩模128，在半导体衬底120的第一区122中注入p型掺杂剂以形成P掺杂的阱130。示例性p型掺杂剂包括硼(B)和BF2。P掺杂的阱130中的p型掺杂剂的浓度可以在从约1×1016cm-3至约1×1018cm-3的范围内。
进一步在图16和图18的步骤246中，在半导体衬底120的第一区122中的P掺杂的阱130中注入n型掺杂剂以形成n+掺杂区132。示例性n型掺杂剂包括砷(As)和磷(P)。n+掺杂区132中的n型掺杂剂的浓度可以在从约1×1020cm-3至约1×1021cm-3的范围内。
在图17和图18的步骤248中，去除掩模128，诸如当掩模128是光刻胶时通过可接受的灰化工艺去除掩模128。进一步在图17和图18中的步骤250中，在半导体衬底120的第一区122上形成掩模134。掩模134不位于半导体衬底120的第二区124上，并且暴露出第二区124。掩模134可以是光刻胶，通过使用旋涂技术形成光刻胶以及使用可接受的光刻技术来图案化光刻胶。
进一步在图17和图18的步骤252中，一旦形成掩模134，在半导体衬底120的第二区124中注入n型掺杂剂以形成n掺杂的阱136。示例性n型掺杂剂包括砷(As)和磷(P)。n掺杂的阱136中的n型掺杂剂的浓度可以在从约1×1016cm-3至约1×1018cm-3的范围内。
进一步在图17和图18的步骤254中，在半导体衬底120的第二区124中的n掺杂的阱136中注入p型掺杂剂以形成p+掺杂区138。示例性p型掺杂剂包括硼(B)和BF2。p+掺杂区138中的p型掺杂剂的浓度可以在从约1×1020cm-3至约1×1021cm-3的范围内。在图18的步骤256中，去除掩模134，诸如当掩模134是光刻胶时通过可接受的灰化工艺去除掩模134。
结合图19至图23中的工艺，在图19和图23的步骤240中，如图19中，在半导体衬底120的第一区122和第二区124之间的半导体衬底120中形成隔离区126。进一步在图19中和图23的步骤260中，在第一区122和第二区124中凹进半导体衬底120。可以通过可接受的蚀刻工艺实施凹进。
在图20和图23的步骤262中，在半导体衬底120的第二区124上形成诸如硬掩模的掩模140。例如，可以由氮化硅、碳氮化硅、氮氧化硅、氧化硅等形成掩模140，并且可以使用CVD、PECVD、ALD等形成掩模140。通过使用诸如RIE等的可接受的光刻和蚀刻工艺可以将掩模140图案化至第二区124上而不在第一区122上。
在图21和图23的步骤264中，在半导体衬底120上和在半导体衬底120的第一区122中外延地生长P掺杂的外延层142。可以使用金属有机CVD(MOCVD)、分子束外延(MBE)、液相外延(LPE)、汽相外延(VPE)等或它们的组合来外延生长P掺杂的外延层142。P掺杂的外延层142可以包括硅、硅锗、碳化硅、锗、III-V族化合物半导体、II-VI族化合物半导体等。在外延生长期间，可以用诸如硼(B)和BF2的p型掺杂剂原位掺杂来掺杂P掺杂的外延层142，其中，掺杂浓度在从约1×1016cm-3至约1×1018cm-3的范围内。
进一步在图21和图23的步骤266中，在P掺杂的外延层142上和在半导体衬底120的第一区122中外延地生长n+掺杂的外延层144。可以使用MOCVD、MBE、LPE、VPE等或它们的组合外延生长n+掺杂的外延层144。n+掺杂的外延层144可以包括硅、硅锗、碳化硅、锗、III-V族化合物半导体、II-VI族化合物半导体等。在外延生长期间，可以用诸如砷(As)或磷(P)的n型掺杂剂原位掺杂来掺杂n+掺杂的外延层144，其中，掺杂浓度在从约1×1020cm-3至约1×1021cm-3的范围内。
在图22和图23中的步骤268中，从半导体衬底120的第二区124去除掩模140。可以通过对掩模140的材料具有选择性的合适的蚀刻去除掩模140。进一步在图22和图23的步骤270中，在半导体衬底120的第一区122中的n+掺杂的外延层144上形成诸如硬掩模的掩模146。例如，掩模146可以由氮化硅、碳氮化硅、氮氧化硅、氧化硅等形成并且可以使用CVD、PECVD、ALD等形成。可以使用诸如RIE等的合适的光刻和蚀刻工艺将掩模146图案化至第一区122上而不在第二区124上。
进一步在图22和图23的步骤272中，在半导体衬底120上和在半导体衬底120的第二区124中外延地生长n掺杂的外延层148。可以使用MOCVD、MBE、LPE、VPE等或它们的组合来外延生长n掺杂的外延层148。n掺杂的外延层148可以包括硅、硅锗、碳化硅、锗、III-V族化合物半导体、II-VI族化合物半导体等。在外延生长期间，可以用诸如砷(As)或磷(P)的n型掺杂剂原位掺杂来掺杂n掺杂的外延层148，其中，掺杂浓度在从约1×1016cm-3至约1×1018cm-3的范围内。
进一步在图22和图23的步骤274中，在n掺杂的外延层148上和在半导体衬底120的第二区124中外延地生长p+掺杂的外延层150。可以使用MOCVD、MBE、LPE、VPE等或它们的组合外延生长p+掺杂的外延层150。p+掺杂的外延层150可以包括硅、硅锗、碳化硅、锗、III-V族化合物半导体、II-VI族化合物半导体等。在外延生长期间，可以用诸如硼(B)和BF2的p型掺杂剂原位掺杂来掺杂p+掺杂的外延层150，其中，掺杂浓度在从约1×1020cm-3至约1×1021cm-3的范围内。
在图23中的步骤276中，从半导体衬底120的第一区122去除掩模146。诸如CMP的平坦化工艺可以用于去除掩模146，并且可以进一步平坦化n+掺杂的外延层144和p+掺杂的外延层150。
转到图24至图32和图34中的工艺，在图24和在图34的步骤280中，在半导体衬底120中的第一区122和第二区124中形成高度掺杂的源极/漏极接触区162和166。高度掺杂的源极/漏极接触区162可以是n+掺杂的源极/漏极接触区，其可以进一步为如在图15至图18中形成的n+掺杂区132、如在图19至图23中形成的n+掺杂的外延层144等。高度掺杂的源极/漏极接触区166可以是p+掺杂的源极/漏极接触区，其可以进一步为如在图15至图18中形成的p+掺杂区138、如在图19至图23中形成的p+掺杂的外延层150等。此外，掺杂区160和164分别与高度掺杂的源极/漏极接触区162和166相反地掺杂且掺杂浓度小于高度掺杂的源极/漏极接触区162和166的掺杂浓度，位于半导体衬底120中的掺杂区160和164可以分别位于高度掺杂的源极/漏极接触区162和166下方。掺杂区160可以是p掺杂区，其可以进一步为如在图15至图18中形成的p掺杂阱130、如在图19至图23中形成的p掺杂的外延层142等。掺杂区164可以是n掺杂区，其可以进一步为如在图15至图18中形成的n掺杂阱136、如在图19至图23中形成的n掺杂的外延层148等。隔离区168将第一区122从第二区124分隔开，例如，分隔开半导体衬底120中的高度掺杂的源极/漏极接触区162和166。隔离区168可以是如在图15至图23中形成的隔离区126。第一区122可以用于形成第一类型的器件，诸如n沟道晶体管，并且第二区124可以用于形成第二(例如，互补)类型的器件，诸如p沟道晶体管。
继续图24和图34的步骤204，在高度掺杂的源极/漏极接触区域162和166以及隔离区168上方和上形成第一介电层170。可以通过诸如CVD、PECVD、旋涂等或它们的组合的适当的沉积技术形成第一介电层170并且第一介电层170可以由诸如氧化硅、PSG、BSG、BPSG、USG、氮化物、氮氧化物等形成。可以实施CMP以平坦化第一介电层170。
在图25至32中的工艺和形成的结构以及图34的步骤204至220对应于图2至图9和图11的步骤204至220。下文中提供了图25至图32和图34的步骤204至步骤220的简要论述，并且先前结合图2至图9和图11的步骤204至220论述了额外的细节。
在图25和图34的步骤204中，在第一介电层170上和在第一区122和第二区124中形成栅电极54和56。栅电极54形成在第一区122中并且直接位于高度掺杂的源极/漏极接触区162的至少一部分之上，并且栅电极56形成在第二区124中并且直接位于高度掺杂的源极/漏极接触区166的至少一部分之上。此外，在图25和图34中的步骤206中，在栅电极54和56和第一介电层170上形成第二介电层58。
在图26和图34中的步骤208中，图案化第二介电层58、栅电极54和56以及第一介电层170以形成沟道开口60和62。沟道开口60形成为穿过第二介电层58、栅电极54和第一介电层170至第一区122中的高度掺杂的源极/漏极接触区162。通过沟道开口60暴露出高度掺杂的源极/漏极接触区162的至少一部分。沟道开口62形成为穿过第二介电层58、栅电极56和第一介电层170至第二区124中的高度掺杂的源极/漏极接触区166。通过沟道开口62暴露出高度掺杂的源极/漏极接触区166的至少一部分。
在图27和图34的步骤210中，分别在沟道开口60和62中形成栅极电介质64和66。通过沟道开口60和62暴露出高度掺杂的源极/漏极接触区162和166的至少相应部分。
分别在沟道开口60和62中的栅极电介质64和66的相对的内侧壁之间产生尺寸68和70。尺寸68和70可以引起当块状半金属材料的材料形成在沟道开口60和62中时，将为块状半金属材料的材料转变成半导体材料，这将在下文中进一步论述。
在图28和图29和图34的步骤212中，在第一区122中的沟道开口60中形成n掺杂的含铋沟道结构76，并且在n掺杂的含铋沟道结构76上形成源极/漏极接触区78。在图28中，在第二介电层58上沉积诸如硬掩模的掩模层72，并且图案化掩模层72以暴露第一区122中的沟道开口60。暴露沟道开口60的穿过掩模层72的开口的横向尺寸可以比沟道开口60的相应的横向尺寸更大。然后在第一区122中的沟道开口60中沉积n掺杂的含铋材料74，同时由于掩模层72而防止n掺杂的含铋材料74沉积在第二区中的沟道开口62中。
在图29中，去除过量的含铋材料74和掩模层72。可以使用可接受的平坦化工艺去除过量的含铋材料74。平坦化工艺可以去除过量的含铋材料74和/或掩模层72，直至由n掺杂的含铋材料74形成的源极/漏极接触区78延伸至位于第二介电层58之上适当的高度。在平坦化工艺后，可以使用可接受的蚀刻去除掩模层72的剩余部分。除了由n掺杂的含铋材料74形成的源极/漏极接触区域78之外，在沟道开口60中的n掺杂的含铋材料74的剩余部分形成了第一区122中的n掺杂的含铋沟道结构76。n掺杂的含铋沟道结构76连接至第一区122中的高度层掺杂的源极/漏极接触区162。
在图30和图31和图11的步骤214中，在第二区124中的沟道开口62中形成p掺杂的含铋沟道结构84，并且在p掺杂的含铋沟道结构84上形成源极/漏极接触区86。在图30中，将诸如硬掩模的掩模层80沉积在第二介电层58上、源极/漏极接触区78上以及沟道开口62中。图案化掩模层80以暴露第二区124中的沟道开口62。暴露沟道开口62的穿过掩模层80的开口的横向尺寸可以比沟道开口62的相应的横向尺寸更大。然后在第二区124中的沟道开口62中沉积p掺杂的含铋材料82。
在图31中，去除过量的含铋材料82和掩模层80。可以使用可接受的平坦化工艺去除过量的含铋材料82。平坦化工艺可以去除过量的含铋材料82和/或掩模层80，直至由p掺杂的含铋材料82形成的源极/漏极接触区86延伸至位于第二介电层58之上适当的高度。在平坦化工艺后，可以使用可接受的蚀刻去除掩模层80的剩余部分。除了由p掺杂的含铋材料82形成的源极/漏极接触区86之外，在沟道开口62中的p掺杂的含铋材料82的剩余部分形成了第二区124中的p掺杂的含铋沟道结构84。p掺杂的含铋沟道结构84连接至第二区124中的高度掺杂的源极/漏极接触区166。此外，在图31和图34的步骤216中，在源极/漏极接触区78和86以及在第二介电层58上形成第三介电层88。
在图32和图34的步骤218中，形成至n沟道晶体管172和P沟道晶体管174中的相应组件的接触件90a、90b、90c、92a、92b和92c。接触件90a物理连接和电连接至第一区122中的高度掺杂的源极/漏极接触区162。接触件90b物理连接和电连接至第一区122中的栅电极54。接触件90c物理连接和电连接至第一区122中的源极/漏极接触区78。接触件92a物理连接和电连接至第二区124中的高度掺杂的源极/漏极接触区166。接触件92b物理连接和电连接至第二区124中的栅电极56。接触件92c物理连接和电连接至第二区124中的源极/漏极接触区86。接触件90a和92a可以均为源极接触件。接触件90b和92b可以均为栅极接触件。接触件90c和92c可以均为漏极接触件。
在图34的步骤220中和在形成接触件90a、90b、90c、92a、92b和92c之后，可以对图32的结构进行退火以使该结构(包括n掺杂的含铋沟道结构76和p掺杂的含铋沟道结构84)中的含铋材料结晶。由于铋的熔点较低，例如271.4℃，退火可以是低温退火以用于结晶。在一些实施例中，在400℃或更小，诸如300℃或更小，并且更特别地在275℃实施低温退火并且持续时间在从约0.01秒到约300秒的范围内。
图32进一步示出了区域33A、33B和33C，分别在图33A、33B和33C中以覆盖布局示出区域33A、33B和33C。布局图33A、33B和33C示出了图32中的更详细的组件。从图33B可以看出，栅电极54和56分别包裹环绕n掺杂的含铋沟道结构76和p掺杂的含铋沟道结构84。晶体管172和174可以因此被称为垂直沟道、全环栅器件。图33A、33B和33C进一步示出了图32中示出的截面32-32。
图35至图38根据一些实施例示出了制造互补晶体管结构的中间阶段的截面图。图35至图38示出了用于图案化沟道开口60和62的另一工艺的截面图。图39是结合图35至图38示出和描述的工艺的流程图，并且将在图35至图38的具体上下文中描述在图39中示出的步骤。
在图35和图39的步骤280中，如上文结合图24和图34中的步骤280所述，在半导体衬底120中的第一区122和第二区124中形成高度掺杂的源极/漏极接触区162和166。继续图35和图39的步骤290，在半导体衬底120上形成牺牲层180。牺牲层180可以是例如提供良好的蚀刻选择性以图案化沟道开口60和62的任何材料。在一些实施例中，该牺牲层180是半导体材料，诸如通过使用MOCVD、MBE、LPE、VPE等或它们的组合外延地生长的硅、硅锗、锗等。
在图36和图39中的步骤292中，将牺牲层180图案化成分别位于半导体衬底120的第一区122和第二区124中的高度掺杂的源极/漏极接触区162和166上的牺牲沟道结构182和184。该图案化可以使用可接受的光刻和蚀刻工艺，诸如RIE、各向异性等离子体蚀刻等。可以使用其他图案化技术。
在图37和图39中的步骤294中，在高度掺杂的源极/漏极接触区162和166上以及在牺牲沟道结构182和184周围形成第一介电层186。第一介电层186可以通过诸如CVD、PECVD、旋涂等或它们的组合的合适的沉积技术来形成，并且第一介电层186可以由诸如氧化硅、PSG、BSG、BPSG、USG、氮化物、氮氧化物等的介电材料形成。可以首先将第一介电层186沉积为具有大于牺牲沟道结构182和184的高度的厚度。CMP可以用于平坦化第一介电层186，并且选择性蚀刻可以用于将第一介电层186蚀刻至期望的厚度，该期望的厚度处于位于牺牲沟道结构182和184的顶面下方的水平，如图所示。
在图38和图39中的步骤296中，在第一区122和第二区124中的第一介电层186上和在牺牲沟道结构182和184周围形成栅电极54和56。可以通过在第一介电层186上沉积导电材料层至超过牺牲沟道结构182和184的高度的厚度来形成栅电极54和56。然后，诸如通过使用CMP可以平坦化导电材料层。然后，诸如通过使用可接受的光刻和蚀刻工艺(诸如RIE等)可以使导电材料层凹进并且使导电材料层图案化成栅电极54和56。可以使用其他图案化技术。
进一步在图38和图39中的步骤298中，在栅电极54和56和第一介电层186上以及牺牲沟道结构186和184周围形成第二介电层58。可以由适当的沉积技术和利用任何适当的介电材料形成第二介电层58。可以实施CMP以平坦化第二介电层58和通过第二介电层58暴露牺牲沟道结构182和184。
在图39中的步骤300中，去除牺牲沟道结构182和184以形成分别至高度掺杂的源极/漏极接触区162和166的沟道开口60和62。去除可以使用对牺牲沟道结构182和184的材料具有选择性的蚀刻。去除形成了如在图26中所示的沟道开口60和62。如结合图27至图32和步骤210至步骤220中先前所描述的，进行随后的处理。
一些实施例预期具有沟道的晶体管，沟道包括为块状半金属但是为形成在沟道中的半导体的材料。这样的半金属的实例是含铋材料。块状铋是半金属并且具有负带隙能量。当铋的尺寸(诸如截面直径)减小为约53nm或更小时，铋变成半导体材料。随着铋的直径减小至53nm，带隙能量达到约零，并且变成正的，并且随着直径减小至超出53nm，带隙能量保持为正并且增加。对于在约53nm至约5nm之间的直径，带隙能量可以分别在从约0eV至约1eV的范围内。因此，一些实施例预期在图中示出的尺寸68和70是53nm或更小，从而使得含铋沟道结构76和84的相应的尺寸是53nm或更小。这可以使得含铋沟道结构76和84中的含铋材料为半导体。一些实施例预期在图12A至图12H中示出的含铋沟道结构76/84的每个截面的最大尺寸为53nm或更小。
铋具有相对较低的熔点，并且因此可以以非晶或多晶形式容易地沉积并且随后结晶成单晶三角结构。铋的熔点为约271.4℃。在该熔点之上的温度下的退火可以熔化铋或者诸如铋的含铋材料，或者冷却含铋材料，它形成单晶三角结构。由于铋或者含铋材料可以在例如低于400℃和更具体地，低于300℃的这样的低温下结晶，材料的结晶可以容易地集成到传统的处理内并且在传统的处理的温度参数内完成。额外地，晶体管中的含铋材料(例如，n型晶体管94和172中的n掺杂的含铋沟道结构76和源极/漏极接触区78和P型晶体管96和174中的p掺杂的含铋沟道结构84和源极/漏极接触区86)是无结的，例如，在材料内不具有p-n结。因此，在例如形成接触件之后融化和结晶含铋材料将不会引起掺杂剂在含铋材料内的不利扩散。
铋通常具有较高的载流子迁移率。当轻掺杂时，掺杂的铋可以具有接近105cm2/(V×S)的数量级的电子迁移率，或当重掺杂时大于5000cm2/(V×S)的电子迁移率。铋可以具有大于或等于约100nm的电子平均自由程，诸如在从约100nm至约1μm的范围内。此外，铋可以在约束方向上具有较高的有效质量，诸如1.2m0，并且可以具有高能态密度和载流子浓度。铋可以在三角方向上具有较低的有效质量，诸如0.0012m0。铋的这些属性可以使得含铋沟道具有高电流和高速度。
一个实施例是一种结构。该结构包括衬底、第一源极/漏极接触区、沟道结构、栅极电介质、栅电极和第二源极/漏极接触区。衬底具有上表面。沟道结构连接至第一源极/漏极接触区并且位于第一源极/漏极接触区上方，并且沟道结构位于衬底的上表面上方。沟道结构具有在第一源极/漏极接触区之上延伸的侧壁。沟道结构包括含铋半导体材料。栅极电介质为沿着沟道结构的侧壁。栅电极沿着栅极电介质。第二源极/漏极接触区连接至沟道结构并且位于沟道结构上方。
另一个实施例是一种结构。该结构包括衬底、第一垂直沟道晶体管和第二垂直沟道晶体管。衬底包括水平表面，并且水平表面是衬底的上表面。第一垂直沟道晶体管位于衬底的水平表面上方。第一垂直沟道晶体管包括：第一源极/漏极接触区、第一含铋沟道结构、第一栅极电介质、第一栅电极和第二源极/漏极接触区。第一含铋沟道结构连接至第一源极/漏极接触区并且位于第一源极/漏极接触区上方。第一含铋沟道结构是半导体并且包括n型掺杂剂。第一含铋沟道结构垂直于水平表面延伸。第一栅极电介质位于第一含铋沟道结构周围。第一栅电极位于第一栅极电介质周围。第一栅极电介质设置在第一含铋沟道结构和第一栅电极之间。第二源极/漏极接触区连接至第一含铋沟道结构并且位于第一含铋沟道结构上方。第二垂直沟道晶体管位于衬底的水平表面上方。第二垂直沟道晶体管包括：第三源极/漏极接触区、第二含铋沟道结构、第二栅极电介质、第二栅电极和第四源极/漏极接触区。第二含铋沟道结构连接至第三源极/漏极接触区并且位于第三源极/漏极接触区上方。第二含铋沟道结构是半导体并且包括p型掺杂剂。第二含铋沟道结构垂直于水平表面延伸。第二栅极电介质位于第二含铋沟道结构周围。第二栅电极位于第二栅极电介质周围。第二栅极电介质设置在第二含铋沟道结构和第二栅电极之间。第四源极/漏极接触区连接至第二含铋沟道结构并且位于第二含铋沟道结构上方。
进一步的实施例是一种方法。该方法包括：形成第一源极/漏极接触区；在第一源极/漏极接触区上方和在衬底上方形成第一栅电极；形成穿过第一栅电极至第一源极/漏极接触区的第一开口；沿着第一开口的第一侧壁形成第一栅极电介质；在第一开口中沉积第一含铋材料以形成第一含铋沟道结构，第一栅极电介质设置在第一栅电极和第一含铋沟道结构之间，第一含铋沟道结构连接至第一源极/漏极接触区；在第一含铋沟道结构上方形成第二源极/漏极接触区，并且第二源极/漏极接触区连接至第一含铋沟道结构；以及结晶第一含铋材料，结晶包括实施退火。
根据本发明的一个实施例，提供了一种结构，包括：衬底，具有上表面；第一源极/漏极接触区；沟道结构，连接至所述第一源极/漏极接触区并且位于所述第一源极/漏极接触区上方，所述沟道结构位于所述衬底的上表面上方，所述沟道结构具有在所述第一源极/漏极接触区之上延伸的侧壁，所述沟道结构包括含铋半导体材料；栅极电介质，沿着所述沟道结构的所述侧壁；栅电极，沿着所述栅极电介质；以及第二源极/漏极接触区，连接至所述沟道结构并且位于所述沟道结构上方。
在上述结构中，所述含铋半导体材料是掺杂的铋(Bi)。
在上述结构中，所述沟道结构具有位于与所述衬底的所述上表面平行的平面中的截面区域，所述截面区域具有53nm或更小的最大尺寸。
在上述结构中，所述含铋半导体材料掺杂有p型掺杂剂。
在上述结构中，所述含铋半导体材料掺杂有n型掺杂剂。
在上述结构中，所述含铋半导体材料是单晶体。
在上述结构中，所述含铋半导体材料不具有p-n结。
在上述结构中，所述第一源极/漏极接触区位于所述衬底的所述上表面上方，所述第一源极/漏极接触区包括基本上纯金属、半导体-金属化合物或它们的组合。
在上述结构中，所述衬底是半导体衬底，所述第一源极/漏极接触区包括位于所述半导体衬底中的掺杂的半导体区。
在上述结构中，所述衬底包括：半导体衬底；器件，位于所述半导体衬底上；以及互连结构，位于所述半导体衬底上，所述互连结构包括上介电层，所述衬底的所述上表面包括所述上介电层的表面。
根据本发明的另一个实施例，提供了一种结构，包括：衬底，包括水平表面，所述水平表面是所述衬底的上表面；第一垂直沟道晶体管，位于所述衬底的所述水平表面上方，所述第一垂直沟道晶体管包括：第一源极/漏极接触区，第一含铋沟道结构，连接至所述第一源极/漏极接触区并且位于所述第一源极/漏极接触区上方，所述第一含铋沟道结构是半导体并且包括n型掺杂剂，所述第一含铋沟道结构垂直于所述水平表面延伸，第一栅极电介质，位于所述第一含铋沟道结构周围，第一栅电极，位于所述第一栅极电介质周围，所述第一栅极电介质设置在所述第一含铋沟道结构和所述第一栅电极之间，和第二源极/漏极接触区，连接至所述第一含铋沟道结构并且位于所述第一含铋沟道结构上方；以及第二垂直沟道晶体管，位于所述衬底的所述水平表面上方，所述第二垂直沟道晶体管包括：第三源极/漏极接触区，第二含铋沟道结构，连接至所述第三源极/漏极接触区并且位于所述第三源极/漏极接触区上方，所述第二含铋沟道结构是半导体并且包括p型掺杂剂，所述第二含铋沟道结构垂直于所述水平表面延伸，第二栅极电介质，位于所述第二含铋沟道结构周围，第二栅电极，位于所述第二栅极电介质周围，所述第二栅极电介质设置在所述第二含铋沟道结构和所述第二栅电极之间，和第四源极/漏极接触区，连接至所述第二含铋沟道结构并且位于所述第二含铋沟道结构上方。
在上述结构中，所述第一含铋沟道结构的位于与所述水平表面平行的平面中的截面具有53nm或更小的最大尺寸，并且所述第二含铋沟道结构的位于与所述水平表面平行的平面中的截面具有53nm或更小的最大尺寸。
在上述结构中，所述第一含铋沟道结构和所述第二含铋沟道结构均包括单晶含铋材料。
在上述结构中，所述第一源极/漏极接触区和所述第三源极/漏极接触区位于所述衬底的所述水平表面上方，所述第一源极/漏极接触区和所述第三源极/漏极接触区均包括基本上纯金属、半导体-金属化合物或它们的组合。
在上述结构中，所述衬底是半导体衬底，所述第一源极/漏极接触区包括位于所述半导体衬底中的n掺杂区，并且所述第三源极/漏极接触区包括位于所述半导体衬底中的p掺杂区。在上述结构中，所述衬底包括：半导体衬底；器件，位于所述半导体衬底上；以及互连结构，位于所述半导体衬底上，所述互连结构包括上介电层，所述衬底的所述水平表面包括所述上介电层的表面。
根据本发明的又另一实施例，提供了一种方法，包括：形成第一源极/漏极接触区；在所述第一源极/漏极接触区上方和在衬底上方形成第一栅电极；形成穿过所述第一栅电极至所述第一源极/漏极接触区的第一开口；沿着所述第一开口的第一侧壁形成第一栅极电介质；在所述第一开口中沉积第一含铋材料以形成第一含铋沟道结构，所述第一栅极电介质设置在所述第一栅电极和所述第一含铋沟道结构之间，所述第一含铋沟道结构连接至所述第一源极/漏极接触区；在所述第一含铋沟道结构上方形成第二源极/漏极接触区，并且所述第二源极/漏极接触区连接至所述第一含铋沟道结构；以及结晶所述第一含铋材料，所述结晶包括实施退火。
在上述方法中，沉积所述第一含铋材料包括：在沉积所述第一含铋材料期间，用p型掺杂剂或n型掺杂剂掺杂所述第一含铋材料。
在上述方法中，所述退火具有大于271.4℃并且小于或等于400℃的温度。
在上述方法中，还包括：在所述第二源极/漏极接触区上方形成第三源极/漏极接触区；在所述第三源极/漏极接触区上方形成第二栅电极；形成穿过所述第二栅电极至所述第三源极/漏极接触区的第二开口；沿着所述第二开口的第二侧壁形成第二栅极电介质；在所述第二开口中沉积第二含铋材料以形成第二含铋沟道结构，所述第二栅极电介质设置在所述第二栅电极和所述第二含铋沟道结构之间，所述第二含铋沟道结构连接至所述第三源极/漏极接触区；以及在所述第二含铋沟道结构上方形成第四源极/漏极接触区，并且所述第四源极/漏极接触区连接至所述第二含铋沟道结构，其中，结晶所述第一含铋材料进一步结晶所述第二含铋材料，在形成所述第四源极/漏极接触区之后实施所述退火。
上面概述了若干实施例的特征、使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解、他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到、这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下、在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种结构，包括：
衬底，具有上表面；
第一源极/漏极接触区；
沟道结构，连接至所述第一源极/漏极接触区并且位于所述第一源极/漏极接触区上方，所述沟道结构位于所述衬底的上表面上方，所述沟道结构具有在所述第一源极/漏极接触区之上延伸的侧壁，所述沟道结构包括含铋半导体材料；
栅极电介质，沿着所述沟道结构的所述侧壁；
栅电极，沿着所述栅极电介质；以及
第二源极/漏极接触区，连接至所述沟道结构并且位于所述沟道结构上方。
2.根据权利要求1所述的结构，其中，所述含铋半导体材料是掺杂的铋(Bi)。
3.根据权利要求1所述的结构，其中，所述沟道结构具有位于与所述衬底的所述上表面平行的平面中的截面区域，所述截面区域具有53nm或更小的最大尺寸。
4.根据权利要求1所述的结构，其中，所述含铋半导体材料掺杂有p型掺杂剂。
5.根据权利要求1所述的结构，其中，所述含铋半导体材料掺杂有n型掺杂剂。
6.根据权利要求1所述的结构，其中，所述含铋半导体材料是单晶体。
7.根据权利要求1所述的结构，其中，所述含铋半导体材料不具有p-n结。
8.根据权利要求1所述的结构，其中，所述第一源极/漏极接触区位于所述衬底的所述上表面上方，所述第一源极/漏极接触区包括基本上纯金属、半导体-金属化合物或它们的组合。
9.一种结构，包括：
衬底，包括水平表面，所述水平表面是所述衬底的上表面；
第一垂直沟道晶体管，位于所述衬底的所述水平表面上方，所述第一垂直沟道晶体管包括：
第一源极/漏极接触区，
第一含铋沟道结构，连接至所述第一源极/漏极接触区并且位于所述第一源极/漏极接触区上方，所述第一含铋沟道结构是半导体并且包括n型掺杂剂，所述第一含铋沟道结构垂直于所述水平表面延伸，
第一栅极电介质，位于所述第一含铋沟道结构周围，
第一栅电极，位于所述第一栅极电介质周围，所述第一栅极电介质设置在所述第一含铋沟道结构和所述第一栅电极之间，和
第二源极/漏极接触区，连接至所述第一含铋沟道结构并且位于所述第一含铋沟道结构上方；以及
第二垂直沟道晶体管，位于所述衬底的所述水平表面上方，所述第二垂直沟道晶体管包括：
第三源极/漏极接触区，
第二含铋沟道结构，连接至所述第三源极/漏极接触区并且位于所述第三源极/漏极接触区上方，所述第二含铋沟道结构是半导体并且包括p型掺杂剂，所述第二含铋沟道结构垂直于所述水平表面延伸，
第二栅极电介质，位于所述第二含铋沟道结构周围，
第二栅电极，位于所述第二栅极电介质周围，所述第二栅极电介质设置在所述第二含铋沟道结构和所述第二栅电极之间，和
第四源极/漏极接触区，连接至所述第二含铋沟道结构并且位于所述第二含铋沟道结构上方。
10.一种方法，包括：
形成第一源极/漏极接触区；
在所述第一源极/漏极接触区上方和在衬底上方形成第一栅电极；
形成穿过所述第一栅电极至所述第一源极/漏极接触区的第一开口；
沿着所述第一开口的第一侧壁形成第一栅极电介质；
在所述第一开口中沉积第一含铋材料以形成第一含铋沟道结构，所述第一栅极电介质设置在所述第一栅电极和所述第一含铋沟道结构之间，所述第一含铋沟道结构连接至所述第一源极/漏极接触区；
在所述第一含铋沟道结构上方形成第二源极/漏极接触区，并且所述第二源极/漏极接触区连接至所述第一含铋沟道结构；以及
结晶所述第一含铋材料，所述结晶包括实施退火。
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