CN105977284A - 用于鳍式场效应晶体管的源极/漏极区及其形成方法 - Google Patents
用于鳍式场效应晶体管的源极/漏极区及其形成方法 Download PDFInfo
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- CN105977284A CN105977284A CN201510770595.3A CN201510770595A CN105977284A CN 105977284 A CN105977284 A CN 105977284A CN 201510770595 A CN201510770595 A CN 201510770595A CN 105977284 A CN105977284 A CN 105977284A
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- 238000000034 method Methods 0.000 title claims abstract description 73
- 230000005669 field effect Effects 0.000 title description 6
- 125000006850 spacer group Chemical group 0.000 claims abstract description 117
- 239000004065 semiconductor Substances 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 239000002243 precursor Substances 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 165
- 230000015572 biosynthetic process Effects 0.000 description 20
- 230000008569 process Effects 0.000 description 18
- 238000005530 etching Methods 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 230000003647 oxidation Effects 0.000 description 10
- 238000007254 oxidation reaction Methods 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 239000004020 conductor Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 238000000407 epitaxy Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 3
- 230000026267 regulation of growth Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000003792 electrolyte Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- -1 methylsiloxane Chemical class 0.000 description 2
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 238000009279 wet oxidation reaction Methods 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- OQNXPQOQCWVVHP-UHFFFAOYSA-N [Si].O=[Ge] Chemical compound [Si].O=[Ge] OQNXPQOQCWVVHP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 229910000464 lead oxide Inorganic materials 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910017464 nitrogen compound Inorganic materials 0.000 description 1
- 150000002830 nitrogen compounds Chemical class 0.000 description 1
- YEXPOXQUZXUXJW-UHFFFAOYSA-N oxolead Chemical compound [Pb]=O YEXPOXQUZXUXJW-UHFFFAOYSA-N 0.000 description 1
- 230000002085 persistent effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
-
- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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Abstract
一种用于形成半导体器件的方法包括:形成从半导体衬底向上延伸的鳍和在鳍的部分的侧壁上形成牺牲层。该方法还包括在牺牲层上方形成间隔件层和经过牺牲层的底面使鳍的部分凹进。凹进形成设置在间隔件层的侧壁部分之间的沟槽。去除牺牲层的至少部分以及在沟槽中形成源极/漏极区。本发明实施例涉及用于鳍式场效应晶体管的源极/漏极区及其形成方法。
Description
技术领域
本发明实施例涉及用于鳍式场效应晶体管的源极/漏极区及其形成方法。
背景技术
半导体器件用于大量的电子器件中,诸如计算机、手机等。半导体器件包括通过在半导体晶圆上方沉积多种类型的材料薄膜以及图案化材料薄膜以形成集成电路而在半导体晶圆上形成的集成电路。集成电路通常包括场效应晶体管(FET)。
通常,平面FET已用于集成电路。然而,随着现代半导体处理的增加密度和降低覆盖区的需求,当尺寸减小时,平面FET可以通常发生问题。这些问题中的一些包括亚阈值摆幅退化,明显的漏致势垒降低(DIBL),器件特性的波动以及泄漏。已经对鳍式场效应晶体管(finFET)进行了研究以克服这些问题中的一些。
在典型的finFET中,在衬底上方形成垂直鳍结构。这种垂直鳍结构用于在横向方向上形成源极/漏极区和在鳍中形成沟道区。在形成FinFET的垂直方向上,在鳍的沟道区上方形成栅极。随后,可以在finFET上方形成层间电介质(ILD)和多个互连层。
发明内容
根据本发明的一个实施例,提供了一种半导体器件,包括:鳍,从半导体衬底向上延伸;栅极堆叠件,设置在所述鳍的顶面和侧壁上;第一源极/漏极区,位于所述半导体衬底上方并且邻近所述栅极堆叠件;以及第一源极/漏极间隔件,位于所述第一源极/漏极区的侧壁上,其中,所述第一源极/漏极区的部分在所述第一源极/漏极间隔件的底面下方延伸。
根据本发明的另一实施例,还提供了一种用于形成半导体器件的方法,所述方法包括:形成从半导体衬底向上延伸的鳍;在所述鳍的部分的侧壁上形成牺牲层;在所述牺牲层上方形成间隔件层;使所述鳍的所述部分凹进经过所述牺牲层的底面,其中,所述凹进形成设置在所述间隔件层的侧壁部分之间的沟槽;去除所述牺牲层的至少部分;以及在所述沟槽中形成源极/漏极区。
根据本发明的又另一实施例,还提供了一种用于形成半导体器件的方法,所述方法包括:形成第一半导体鳍;形成多个侧壁间隔件,其中,所述第一半导体鳍设置在所述多个侧壁间隔件的第一邻近的侧壁间隔件之间;在所述多个侧壁间隔件的底面下方形成开口;在所述多个侧壁间隔件的所述第一邻近的侧壁间隔件之间形成第一沟槽;以及在所述第一半导体鳍上方的所述第一沟槽中外延地生长第一源极/漏极区,其中,外延地生长所述第一源极/漏极区包括使前体穿过所述开口流入所述第一沟槽内。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是,根据工业中的标准实践,对各种部件没有按比例绘制并且仅仅用于说明的目的。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或缩小。
图1是三维图中的鳍式场效应晶体管(finFET)的实例。
图2至图17C示出了根据一些实施例的制造finFET的中间阶段的截面图和三维视图。
图18示出了根据一些实施例的用于制造finFET的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语,以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而在此使用的空间相对描述符可以同样地作相应的解释。
各种实施例包括鳍上的牺牲层的形成以用于改进源极/漏极外延。随着FinFET器件的尺寸不断减小,具有相对较高的纵横比的鳍的器件用于改进驱动电流。此外,在鳍上形成侧壁间隔件以限定源极/漏极外延区,以及以降低源极/漏极外延短路以用于密集器件区。然而,这些鳍的高纵横比(通过侧壁间隔件的存在而组成)可导致在源极/漏极外延期间,特别是在源极/漏极区的底部中,形成不期望的空隙。
在各个实施例中,在形成源极/漏侧壁间隔件之前,可以在鳍上形成牺牲层。随后,在牺牲层上形成侧壁间隔件。值得注意的是,牺牲层可以设置在侧壁间隔件的底部和下面的器件部件(例如,STI区和/或衬底,鳍从衬底延伸)之间。使鳍的位于侧壁间隔件之间的部分凹进,并且去除牺牲层。可以实施外延工艺以在侧壁间隔件之间生长源极/漏极区。由于在侧壁间隔件和下面的器件部件之间形成牺牲层,所以在去除牺牲层之后,在侧壁间隔件下方形成开口。在外延期间,前体可以从邻近的侧壁间隔件的顶部区域和底部区域(例如,穿过开口)流动。因此,源极/漏极区可以在侧壁间隔件之间多方位地生长,这有利地降低了形成空隙的风险。在所产生的结构中,源极/漏极区的部分可以设置在侧壁间隔件下方。
图1示出了三维图中的finFET 30的实例。finFET 30包括位于衬底32上的鳍36。衬底32包括隔离区38,以及鳍36突出在邻近的隔离区38之上并且从邻近的隔离区38之间突出。栅极电介质40沿着鳍36的侧壁并且位于鳍36的顶面上方,并且栅电极42在栅极电介质40上方。鳍36的被栅极电介质40/栅电极42覆盖的部分可以称为finFET 30的沟道区。源极/漏极区44和46设置在鳍36的相对于栅极电介质40和栅电极42的相对两侧中。图1进一步示出了在后续图中使用的参考截面。截面A-A横跨finFET30的沟道、栅极电介质40和栅电极42。截面B-B横跨finFET 30的源极/漏极区44或46。截面C-C垂直于截面A-A并且沿着鳍36的纵轴并且在例如源极/漏极区44和46之间的电流流动的方向上。为了清楚,后续附图参考这些参考截面。
图2至图17C是根据各个实施例的在制造finFET的各个中间阶段的截面和三维视图,并且图18是在图2至图17C中示出的工艺的工艺流程。图2至图9示出了在图1中示出的参考截面A-A,除了多个finFET和/或具有多个鳍的finFET。在图10A至图17C中,以字符“A”结尾的图被示出为沿着类似的截面A-A;以字符“B”结尾的图被示出为沿着类似的截面B-B;并且以字符“C”结尾的图被示出为沿着类似的截面C-C。此外,在示例性finFET的三维视图中示出以字符“D”结尾的图。
图2至图4示出了从衬底向上延伸的半导体鳍的形成。首先参考图2,示出了具有基底衬底层104的晶圆100。基底衬底层104可以是掺杂的(例如,掺杂有p型或n型掺杂剂)或未掺杂的半导体衬底,诸如块状半导体,绝缘体上半导体(SOI)衬底等。通常地,SOI衬底包括形成在绝缘层上的半导体材料的层。例如,绝缘体层可以是埋氧(BOX)层、氧化硅层等。在通常为硅衬底或玻璃衬底的衬底上提供绝缘层。也可使用诸如多层衬底或梯度衬底的其他衬底。在一些实施例中,衬底层104的半导体材料可以包括硅(Si);锗(Ge);化合物半导体,包括碳化硅,砷化镓,磷化镓,磷化铟,砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或它们的组合。
进一步如图2所示,抗穿通(APT)掺杂剂可以注入在由箭头105所指示的基底衬底层104中。在一些实施例中,可以注入APT掺杂剂以防止在所产生的器件中源极/漏极穿通。注入的APT的类型可以取决于是否n型或p型是所期望的。例如,对于n型器件,可以注入硼,而对于p型器件,可以注入磷或砷。例如,在基底衬底层104中注入的APT掺杂剂的浓度可以为约1×1018/cm3至约3×1019/cm3。
接下来参考图3,可以在基底衬底层104上方任选地形成额外的衬底层106/108。在一些实施例中,可以实施外延以形成各个衬底层106和108。可以使用任何合适的外延工艺,诸如通过金属有机(MO)化学汽相沉积(CVD)、分子束外延(MBE)、液相外延法(LPE)、汽相外延(VPE)、选择性外延生长(SEG)、它们的组合等。
衬底层106和108设置在基底衬底层104上方,其中,衬底层108设置在衬底层106上方。在一些实施例中,衬底层106可以包括SiGe,而衬底层108包括基本上纯Si。在随后的工艺步骤中,可以将衬底层106氧化,并且可以在衬底层108中形成器件的沟道区。在这样的实施例中,衬底层106可以作为衬底层108的未掺杂的沟道区和在基底衬底层104中注入的APT掺杂剂之间的阻挡层。已经观察到,在氧化的SiGe层上形成未掺杂的沟道,可以实现改进的迁移率和器件性能。在实施例中,例如,衬底层106的厚度T1为约5nm至约20nm。因此,如图2所示,示例性衬底102可以包括半导体材料的多个层104,106和108。在其他实施例中,可以省略衬底层106和108。
如图3进一步所示,可以在衬底102上方设置硬掩模110。硬掩模110可以包括一种或多种氧化物(例如,氧化硅)和/或氮化物(例如,氮化硅)层,以防止在图案化期间损坏下面的衬底102。可以使用诸如原子层沉积(ALD)、化学汽相沉积(CVD)、高密度等离子体CVD(HDP-CVD)、物理汽相沉积(PVD)等的任何合适的沉积工艺来形成硬掩模110。
图4示出了衬底102的图案化以形成设置在邻近的沟槽114之间的鳍116。在实施例中,可以在硬掩模110上方毯式沉积光刻胶层(未示出)。然后通过使用光掩模将光刻胶暴露于光来图案化光刻胶。然后,取决于使用的是正性光刻胶还是负性光刻胶来去除光刻胶的曝光部分或未曝光部分。然后,光刻胶的图案可以转印至硬掩模110(例如,使用合适的蚀刻工艺)。随后,在蚀刻工艺期间,将硬掩模110用作图案化掩模,图案化沟槽114至下面的衬底102内。衬底102的蚀刻可以包括可接受的蚀刻工艺,诸如反应离子蚀刻(RIE)、中性束蚀刻(NBE)等或它们的组合。蚀刻可以是各向异性的。随后,例如,在灰化和/或湿剥离工艺中去除光刻胶。因此,在晶圆100中形成鳍116。鳍116从相邻沟槽114之间的基底衬底层104向上延伸。
图5示出了施加于晶圆100的任选的氧化工艺。在这样的实施例中,例如,可以氧化衬底层106以提供包括氧化硅锗的半导体氧化物层106’。可以使用任何合适的氧化工艺,诸如以比衬底层104或108的其他半导体材料(例如,块状Si)更高的速率选择性地氧化衬底层106内的Ge的湿氧化工艺。在一些示例实施例中,湿氧化工艺可包括:将晶圆100维持在约400℃和约600℃的温度下,同时对维持在约1Atm的压力下的晶圆100供应纯水蒸气并且持续时间在约30分钟和约1小时之间。也可以使用其他合适的氧化工艺。
氧化工艺可以充分氧化衬底层106’。在一些实施例中,由于氧化,在衬底层106’的顶面和/或底面处可以形成基本上纯Ge(不单独示出)的残留层。在随后的工艺步骤中,沟道区可以形成在鳍116的位于半导体氧化物层106’上方的部分中,从而增强迁移率和器件性能。氧化工艺可以进一步部分地氧化衬底层104和108,从而导致包括例如SiO的半导体氧化物区108A和104A的形成。随后,例如,可以通过合适的蚀刻工艺去除半导体氧化物区108A和104A。该蚀刻也可以部分地蚀刻半导体氧化物层106’的侧壁。在图6中示出了所产生的结构。
接下来参考图7,可以以诸如氧化硅等的介电材料填充沟槽114。在一些实施例中,可以使用硅烷(SiH4)和氧气(O2)作为反应前驱体,使用高密度等离子体(HDP)CVD工艺形成所产生的STI区域126。在其他实施例中,可以使用次大气压CVD(SACVD)工艺或高纵横比工艺(HARP)来形成STI区域126,其中,工艺气体可以包括正硅酸乙酯(TEOS)和臭氧(O3)。在又其他实施例中,可以使用旋涂介电(SOD)工艺来形成STI区域126,电介质诸如氢倍半硅氧烷(HSQ)或甲基硅氧烷(MSQ)。可以实施退火(或其他合适的工艺)来固化STI区域126的材料。可使用其他工艺和材料。可以使用化学机械抛光(CMP)或其他回蚀刻工艺以使STI区域126的顶面与鳍116的顶面齐平。在CMP/回蚀刻期间或使用其他合适的工艺也可以去除硬掩模110。
此外,在一些实施例中,在用介电材料填充沟槽114之前,STI区域126可以包括形成在沟槽114的侧壁和底面上的共形衬垫(未示出)。在一些实施例中,衬垫可以包括半导体(例如,硅)氮化物、半导体(例如,硅)氧化物、热半导体(例如,硅)氧化物、半导体(例如,硅)氮氧化物、聚合物电介质、它们的组合等。衬垫的形成可以包括任何合适的方法,诸如原子层沉积(ALD)、CVD、高密度等离子体(HDP)CVD、物理汽相沉积(PVD)等。在这样的实施例中,衬垫可以防止(或至少减少)半导体材料在STI区域126的退火期间从鳍116(例如,Si和/或Ge)至周围的STI区域126内的扩散。
接下来,在图8中,凹进STI区域126,从而使得半导体层108的顶部高于STI区域126的顶面。STI区域126的凹进可以包括化学蚀刻工艺,例如,在具有等离子体或者不具有等离子体的情况下,使用氨(NH3)与氢氟酸(HF)或者三氟化氮(NF3)的组合作为反应溶液。当将HF用作反应溶液时,HF的稀释比可以在约1:50到约1:100之间。在凹进之后,暴露鳍116中的半导体层108的顶面和侧壁。因此,在鳍116中形成沟道区120(例如,沿着截面A-A的半导体层108的暴露部分)。在完成的finFET结构中,栅极包裹环绕和覆盖这样的沟道区120(参见例如图1和图17A)的侧壁。在一些实施例中,沟道区120可以设置在半导体氧化物层106’上,并且由于APT掺杂剂仅仅注入至基底衬底层104中,所以沟道区120可以基本上不含任何掺杂剂。可以使用鳍116和沟道区120的其他配置。
图9以及图10A和10B示出了在沟道区120的顶面和侧壁上形成栅极堆叠件140。如上所述,图9和图10A示出了沿着截面A-A(例如,横跨鳍116的沟道区)截取的晶圆100,而图10B示出了沿着截面B-B(例如,横跨鳍116的源极/漏极区)截取的晶圆100。栅极堆叠件140的形成开始于图9中,其中,在鳍116的顶面和侧壁上沉积共形伪氧化物142。在一些实施例中,伪氧化物142可以形成在鳍116的沟道区120和源极/漏极区上方。
接下来,如图10A所示,在伪氧化物142上方形成伪栅极144。例如,伪栅极144可以包括多晶硅,但是也可以使用诸如金属硅化物、金属氮化物等的材料。栅极堆叠件140也可以具有基本上垂直于半导体鳍116(例如,参见图1)的纵向的纵向。
然后,在伪栅极144上方形成硬掩模146。例如,硬掩模146可以包括氮化硅或氧化硅。在一些实施例中,硬掩模146可以是包括,例如,氮化物层和氧化物层的多层。在一些实施例中,栅极堆叠件140可以横跨在多个半导体鳍116和/或STI区域126上方。可以图案化硬掩模146以暴露出鳍116的源极/漏极区(例如,参见图10B)同时覆盖沟道区120。例如,可以使用光刻和蚀刻的组合来完成硬掩模146的图案化。如通过图10A和10B进一步示出的,实施蚀刻以蚀刻栅极堆叠件140的未被硬掩模146覆盖的部分。在蚀刻之后,硬掩模146和栅极堆叠件140可以仍然保留在鳍116的沟道区120(见图10A)上,同时暴露出鳍116的源极/漏极区(见图10B)。
图11A至图11C示出了牺牲层150和间隔件层152在鳍116、栅极堆叠件140和硬掩模146上的形成。在各个实施例中,可以选择牺牲层150和间隔件层152的材料,从而使得可以选择性地去除牺牲层150而不会显著地去除间隔件层152。例如,在实施例中,间隔件层152是氧化物(例如,SiO)同时间隔件层152包括SiOCN。包括低k介电材料的其他介电材料也可以用于牺牲层150和/或间隔件层152。例如,间隔件层152也可包括氮化物、SiCN等。牺牲层150和间隔件层152可以是使用诸如CVD、PECVD等的任何合适的方法形成的共形层。间隔件层152和牺牲层150覆盖硬掩模146的顶面(例如,见图11A)、鳍116的源极/漏极部分的顶面和侧壁(例如,见图11B)、隔离层126的顶面(例如,见图11B至图11C)和栅极堆叠件140的侧壁(例如,见图11C)。牺牲层150设置在间隔件层152的底面上并且将间隔件层152与下面的器件部件(例如,STI区域126)分隔开。在一些实施例中,例如,牺牲层150的厚度T2为约2nm至约10nm,并且间隔件层152的厚度T3为从约3nm至约12nm。
接下来,例如,在图12A至图12D中,可以使用回蚀刻工艺,经过STI区域126的顶面,使鳍116的未被硬掩模146覆盖的部分(例如,鳍116的源极/漏极区)凹进。作为凹进的部分,去除间隔件层152和牺牲层150的顶部以暴露出鳍116。可以从硬掩模146的顶面进一步去除间隔件层152和牺牲层150。在暴露出鳍116之后,对鳍116进行凹进。在一些实施例中,凹进可以去除半导体氧化物层106’和暴露出基底衬底层104。在蚀刻之后,鳍116的暴露部分的顶面低于牺牲层150和间隔件层152。硬掩模146防止在源极/漏极回蚀刻期间的鳍116的栅极结构140或沟道区120的蚀刻。
在所产生的结构中,从蚀刻的间隔件层152形成间隔件154(标记为154A和154B)。在随后的工艺步骤中,间隔件154可以用作侧壁间隔件以限定所产生的器件的栅极以及用于限定源极/漏极外延区。在器件的源极/漏极区中的相邻源极/漏极间隔件154A之间相应地形成沟槽160(例如,见图12B)。此外,栅极堆叠件140可以设置在栅极间隔件154B之间(例如,见图12C)。因为间隔件层152最初地形成为单个共形层,因此间隔件154A可以平滑地连接至间隔件154B,而在它们之间没有形成界面(例如,见图12D的三维视图)。牺牲层150可以设置在间隔件154A/154B的底面下方,并且牺牲层150将间隔件154A/154B与下面的器件层分隔开。沟槽156位于伪栅极堆叠件140的相对两侧上(例如,见图12C)。
图13A至图13D示出了使用任何合适的工艺选择性去除牺牲层150的位于源极/漏极侧壁间隔件154A的侧壁和底面上的部分。例如,在实施例中,使用将HF作为反应化学物质的湿蚀刻工艺去除牺牲层150的部分。在一些实施例中,HF的稀释比可以为约1:100。在另一个实施例中,在原位预清洗工艺中去除牺牲层150的部分(例如,SiCoNi蚀刻以去除半导体衬底102中的原生氧化物层)以用于沟槽160中的源极/漏极区的外延(例如,见图14A至图14D)。在这样的实施例中,相同的外延工具可以去除牺牲层150的部分以及在沟槽160中生长源极/漏极区。可在室温下实施牺牲层150的去除。在一些实施例中,牺牲层150的位于栅极间隔件154的侧壁和底面上的部分可以仍然保留(例如,见图13C和图13D)。在这样的实施例中,在去除(例如,蚀刻)牺牲层150的位于源极/漏极侧壁间隔件154A的侧壁和底面上的部分期间,牺牲层150的仍然保留的部分受到间隔件154B的保护。
间隔件154A连接至栅极间隔件154B并且由栅极间隔件154B结构支撑(例如,见图13D)。因此,牺牲层150的去除形成了位于间隔件154A和下面的器件部件之间的开口158,下面的器件部件诸如STI区域126(例如,见图13B和图13D)。开口158连接至沟槽160。在外延期间,开口158允许前体在间隔件154A下方流动并且在沟槽160中生长源极/漏极区。
在图14A至图14D中,通过在沟槽160中选择性地生长半导体材料而形成外延区162。在一些实施例中,外延区162包括硅、锗(没有硅)、硅锗、磷化硅、硅锗硼等。硬掩模146和间隔件154B可以掩蔽晶圆100的区域以限定用于在衬底层104上(例如,仅在鳍116的暴露部分上)形成外延区162的区域。在外延期间,开口158(见图13B和13D)可以允许前体直接流入沟槽160的底部内。因此,可以从多个方向(例如,从顶部区域和底部区域)用前体填充沟槽160,从而降低外延区162中的空隙的形成。在一些实施例中,使用的前体的类型取决于是否形成NMOS或PMOS器件。例如,对于NMOS器件而言,可以使用气相硅、磷或它们的组合,而对于PMOS器件,可以使用气相硅、锗、硼或它们的组合。
在用外延区162填充沟槽160之后,源极/漏极区的进一步外延生长引起外延区162水平地扩展,并且可以开始形成小平面。在外延步骤之后,在PMOS器件中可以将p型杂质(例如,硼或BF2)注入外延区162或者在NMOS器件中可以将n型杂质(例如,磷或砷)注入外延区162,以形成源极/漏极区,源极/漏极区也使用参考标号162以被示出。可选地,当生长外延区162时可以原位掺杂p型或n型杂质以形成源极/漏极区。
在所产生的器件中,源极/漏极区162位于栅极堆叠件140的相对两侧上并且沿着栅极堆叠件140的侧壁进一步向上延伸(见图14C和14D)。此外,因为通过开口158实施外延,所以源极/漏极区域162的至少部分可以设置在源极/漏极侧壁间隔件154A下方(例如,见图14B)。源极/漏极区162的这些部分可以设置在源极/漏极侧壁间隔件154A和下面的STI区域126之间。在一些实施例中,源极/漏极区域162的高度H1为约30nm至约80nm,并且源极/漏极区162的位于间隔件154A之间的宽度W1为约8nm至约16nm。在一些实施例中,源极/漏极区域162的位于间隔件154A和STI区域126之间的部分的厚度T4可以为约2nm至约10nm。
图14E和图14D示出了根据其他实施例的源极/漏极区162的截面图。图14E和图14D示出了可以沿着图1的截面B-B截取。在通过图14E示出的实施例中,外延工艺可以合并源极/漏极区162的底部。例如,源极/漏极区162的位于间隔件154A下方的部分可以横向延伸并且合并。这些合并的部分162A可以设置在STI区域126上并且覆盖STI区域126。在通过图14F示出的实施例中,外延工艺可以进一步使合并的区域162A沿着STI区域126上方的间隔件154A的侧壁向上生长。在这样的实施例中,合并的区域162A的高度H2可以小于间隔件154A的高度H3的约一半。在一些实施例中,高度H2可以小于高度H3的约三分之一。
图15A至图15C示出了在形成层间电介质164之后的晶圆100。ILD 164可以包括使用例如可流动化学汽相沉积(FCVD)形成的可流动氧化物。可以实施CMP(或其他合适的平坦化工艺)以使ILD 164的顶面、栅极堆叠件140的顶面和栅极间隔件154B的顶面彼此平齐。各个中介层166(例如,缓冲层和/或蚀刻停止层)可以设置在ILD层164与源极/漏极区162之间,栅极堆叠件140和/或栅极间隔件154B之间。
图16A至图16C示出了在暴露鳍116的沟道区120之后的晶圆100的各个视图。暴露沟道区120可以包括例如使用蚀刻工艺从沟道区120的侧壁和顶面去除栅极堆叠件140(包括硬掩模146、伪栅极144和伪氧化物142)。栅极堆叠件140的去除可以限定栅极间隔件154B(见图16C)之间的沟槽168。硬掩模(未示出)可以用于在去除栅极堆叠件140期间掩蔽ILD 164和源极/漏极区162。因此,可以在不图案化ILD 164或源极/漏极区162的情况下去除栅极堆叠件140。也可以去除牺牲层的剩余部分(例如,设置在栅极间隔件154B的侧壁上以及下方的部分)。
接下来,参考图17A至图17B,在沟槽168中形成栅极堆叠件170。例如,在沟槽168中,将栅极电介质172形成为共形层。栅极电介质172可进一步形成在栅极间隔件154B(例如,见图17C)下方。栅极电介质172可以覆盖沟道区120的顶面和侧壁(见图17A)。根据一些实施例,栅极电介质172包括氧化硅、氮化硅或它们的多层。在可选实施例中,栅极电介质172包括高k介电材料。在这样的实施例中,栅极电介质172可以具有大于约7.0的k值,并且可以包括金属氧化物或铪(Hf)、铝(Al)、锆(Zr)、镧(La)、镁(Mg)、钡(Ba)、钛(Ti)、铅(Pb)、它们的组合的硅酸盐等。栅极电介质172的形成方法可以包括分子束沉积(MBD)、ALD、等离子体增强CVD(PECVD)等。
接下来,通过用导电材料填充沟槽168的剩余部分而在栅极电介质172上方形成导电栅电极174。栅电极174可以包括含金属材料,诸如氮化钛(TiN)、氮化钽(TaN)、碳化钽(TaC)、钴(Co)、钌(Ru)、铝(Al)、它们的组合,它们的多层等。栅极电介质172和栅电极174的形成可以充满沟槽160并且覆盖ILD 164的顶面。随后,可以实施平坦化(例如,CMP)以去除栅极电介质172和栅电极174的过量部分。所产生的栅极电介质172和栅电极174的剩余部分形成位于所得到的FinFET的沟道区120上方的栅极堆叠件170。在实施例中,例如,沟道区120的宽度W2为约6nm至约12nm和沟道区120的高度H4为约30nm至约80nm。然后可以使用任何合适的工艺在ILD 164中形成例如,包括镍(Ni)、钨(W)等的诸如源极/漏极接触件(未示出)的额外的部件以与源极/漏极区162电连接。
图18示出了根据一些实施例的用于形成半导体器件(例如,FinFET)的示例性工艺流程200。工艺200开始于步骤202,在步骤202中,形成从半导体衬底(例如,衬底102)向上延伸的鳍(例如,鳍116)。在步骤204中,在鳍的沟道区(例如,沟道区域120)的顶面和侧壁上方形成伪栅极堆叠件(例如,栅极堆叠件140)。在步骤206中,在鳍的暴露部分上形成牺牲层(例如,牺牲层150)。牺牲层可以进一步形成在伪栅极堆叠件的顶面和侧壁上方。
该工艺继续步骤208,在牺牲层上方形成间隔件层(例如,间隔件层152)。间隔件层可以设置在牺牲层的侧壁上,并且牺牲层的部分可以在间隔件层的底面下方延伸。在步骤210中,通过去除间隔件层和牺牲层的顶部暴露出该鳍。去除间隔件层的顶部进一步限定了位于鳍的部分的侧壁上的侧壁间隔件(例如,间隔件154A)和位于伪栅极堆叠件的侧壁上的栅极间隔件(例如,间隔件154B)。
接下来,在步骤212中,通过经过牺牲层的底面使鳍凹进来限定位于侧壁间隔件之间的沟槽(例如,沟槽160)。在步骤214中,去除牺牲层的至少部分。侧壁间隔件连接至栅极间隔件并且由栅极间隔件结构支撑,并且去除牺牲层的部分限定了位于侧壁间隔件下方的开口(例如,开口158)。开口可以连接至沟槽。在步骤216中,在沟槽中外延地生长源极/漏极区(例如,源极/漏极区162)。源极/漏极区的外延可以包括使前体流入侧壁间隔件之间的沟槽内以及穿过开口。因此,外延生长可以从多个方向触发,从而减少了在所产生的源极/漏极区中的空隙。
各个实施例包括在鳍上形成牺牲层和间隔件层以改进源极/漏极外延。在形成间隔件层之前,可以在鳍上形成牺牲层。值得注意的是,牺牲层可以设置在侧壁间隔件的底部和下面的器件部件(例如,邻近鳍设置的STI区域)之间。牺牲层的去除可以在间隔件层下方(例如,在间隔件层和下面的STI区域之间)形成开口。使鳍的位于侧壁间隔件之间的部分凹进,并且去除牺牲层的至少部分。可以实施外延工艺以在侧壁间隔件之间生长源极/漏极区。在外延期间,前体可以从邻近的侧壁间隔件的顶部区域和底部区域(例如,穿过开口)流动。因此,源极/漏极区可以在侧壁间隔件之间多方位地生长,这有利地降低了即使在相对较高的纵横比的鳍中形成空隙的风险。
根据一个实施例,一种半导体器件包括鳍和栅极堆叠件,鳍从半导体衬底向上延伸,栅极堆叠件设置在鳍的顶面和侧壁上。该器件还包括第一源极/漏极区以及第一源极/漏极间隔件,第一源极/漏极区位于半导体衬底上方并且邻近栅极堆叠件,第一源极/漏极间隔件位于第一源极/漏极区的侧壁上。第一源极/漏极区的部分在第一源极/漏极间隔件的底面下方延伸。
根据另一个实施例,一种用于形成半导体器件的方法包括:形成从半导体衬底向上延伸的鳍和在鳍的部分的侧壁上形成牺牲层。该方法还包括在牺牲层上方形成间隔件层和经过牺牲层的底面使鳍的部分凹进。凹进形成设置在间隔件层的侧壁部分之间的沟槽。去除牺牲层的至少部分以及在沟槽中形成源极/漏极区。
根据又一实施例,一种用于形成半导体器件的方法包括:形成半导体鳍和形成多个侧壁间隔件。半导体鳍设置在多个侧壁间隔件的邻近的侧壁间隔件之间。在多个侧壁间隔件的底面下方形成开口和在多个侧壁间隔件的第一邻近的侧壁间隔件之间形成第一沟槽。该方法还包括在第一半导体鳍上方的第一沟槽中外延地生长第一源极/漏极区,其中,外延地生长第一源极/漏极区包括使前体穿过开口流入第一沟槽内。
根据本发明的一个实施例,提供了一种半导体器件,包括:鳍,从半导体衬底向上延伸;栅极堆叠件,设置在所述鳍的顶面和侧壁上;第一源极/漏极区,位于所述半导体衬底上方并且邻近所述栅极堆叠件;以及第一源极/漏极间隔件,位于所述第一源极/漏极区的侧壁上,其中,所述第一源极/漏极区的部分在所述第一源极/漏极间隔件的底面下方延伸。
在上述半导体器件中,还包括:第二源极/漏极区,位于所述半导体衬底上方并且邻近所述栅极堆叠件,其中,所述第一源极/漏极区和所述第二源极/漏极区设置在所述栅极堆叠件的相同侧上;以及第二源极/漏极间隔件,位于所述第二源极/漏极区的侧壁上,其中,所述第二源极/漏极区的部分在所述第二源极/漏极间隔件的底面下方延伸。
在上述半导体器件中,还包括外延区,所述外延区将所述第一源极/漏极区连接至所述第二源极/漏极区。
在上述半导体器件中,所述外延区设置在浅沟槽隔离(STI)区上方,并且所述外延区接触所述浅沟槽隔离(STI)区的顶面,其中,所述STI区设置在所述第一源极/漏极区和所述第二源极/漏极区之间。
在上述半导体器件中,所述外延区沿着所述第一源极/漏极间隔件的侧壁和所述第二源极/漏极间隔件的侧壁向上延伸。
在上述半导体器件中,还包括:栅极间隔件,位于所述栅极堆叠件的侧壁上,其中,所述第一源极/漏极间隔件连接至所述栅极间隔件,并且其中,在所述第一源极/漏极间隔件和所述栅极间隔件之间没有形成界面。
在上述半导体器件中,所述栅极堆叠件包括:栅极电介质,其中,所述栅极电介质的部分设置在所述栅极间隔件的底面下方;以及
栅电极,位于所述栅极电介质上方。
根据本发明的另一实施例,还提供了一种用于形成半导体器件的方法,所述方法包括:形成从半导体衬底向上延伸的鳍;在所述鳍的部分的侧壁上形成牺牲层;在所述牺牲层上方形成间隔件层;使所述鳍的所述部分凹进经过所述牺牲层的底面,其中,所述凹进形成设置在所述间隔件层的侧壁部分之间的沟槽;去除所述牺牲层的至少部分;以及在所述沟槽中形成源极/漏极区。
在上述方法中,在所述沟槽中形成所述源极/漏极区包括外延地生长所述源极/漏极区。
在上述方法中,去除所述牺牲层的所述至少部分限定了位于所述间隔件层下方的开口,并且其中,外延地生长所述源极/漏极区包括使前体穿过所述开口流入所述沟槽内。
在上述方法中,所述鳍邻近浅沟槽隔离(STI)区设置,其中,去除所述牺牲层的所述至少部分在所述间隔件层的底面和所述STI区之间形成所述开口。
在上述方法中,还包括:在所述鳍的沟道区的侧壁和顶面上方形成栅极堆叠件,其中,形成所述牺牲层和所述间隔件层包括在所述栅极堆叠件的侧壁上形成所述牺牲层和所述间隔件层。
在上述方法中,形成所述牺牲层包括在所述鳍的所述部分的顶面和侧壁上沉积所述牺牲层,其中,形成所述间隔件层包括在所述牺牲层的顶面和侧壁上沉积所述间隔件层,并且其中,使所述鳍的所述部分凹进包括通过去除所述牺牲层的顶部和所述间隔件层的顶部来暴露所述鳍的所述部分。
根据本发明的又另一实施例,还提供了一种用于形成半导体器件的方法,所述方法包括:形成第一半导体鳍;形成多个侧壁间隔件,其中,所述第一半导体鳍设置在所述多个侧壁间隔件的第一邻近的侧壁间隔件之间;在所述多个侧壁间隔件的底面下方形成开口;在所述多个侧壁间隔件的所述第一邻近的侧壁间隔件之间形成第一沟槽;以及在所述第一半导体鳍上方的所述第一沟槽中外延地生长第一源极/漏极区,其中,外延地生长所述第一源极/漏极区包括使前体穿过所述开口流入所述第一沟槽内。
在上述方法中,所述的在所述多个侧壁间隔件的底面下方形成开口包括:在所述多个侧壁间隔件和所述第一半导体鳍之间形成牺牲层,其中,所述牺牲层在所述多个侧壁间隔件的所述底面下方延伸;以及去除所述牺牲层的至少部分。
在上述方法中,外延地生长所述第一源极/漏极区进一步包括:使所述前体流入位于所述多个侧壁间隔件的所述第一邻近的侧壁间隔件之间的所述第一沟槽内。
在上述方法中,还包括:形成第二半导体鳍,其中,所述第二半导体鳍设置在所述多个侧壁间隔件的第二邻近的侧壁间隔件之间;限定位于所述多个侧壁间隔件的所述第二邻近的侧壁间隔件之间的第二沟槽;在所述第二半导体鳍上方的所述第二沟槽中外延地生长第二源极/漏极区,其中,外延地生长所述第二源极/漏极区包括:使前体穿过所述开口流入所述第二沟槽内;以及形成外延区,所述外延区连接所述第一源极/漏极区和所述第二源极/漏极区。
在上述方法中,所述外延区沿着所述多个侧壁间隔件的侧壁向上延伸。
在上述方法中,形成所述第一沟槽包括使所述第一半导体鳍凹进经过浅沟槽隔离(STI)区的顶面。
在上述方法中,还包括:在所述第一半导体鳍的部分的顶面和侧壁上形成栅极堆叠件;以及在所述栅极堆叠件的侧壁上形成栅极间隔件,其中,当在所述多个侧壁间隔件的所述底面下方形成开口时,所述多个侧壁间隔件连接至所述栅极间隔件并且由所述栅极间隔件结构支撑。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种半导体器件,包括:
鳍,从半导体衬底向上延伸;
栅极堆叠件,设置在所述鳍的顶面和侧壁上;
第一源极/漏极区,位于所述半导体衬底上方并且邻近所述栅极堆叠件;以及
第一源极/漏极间隔件,位于所述第一源极/漏极区的侧壁上,其中,所述第一源极/漏极区的部分在所述第一源极/漏极间隔件的底面下方延伸。
2.根据权利要求1所述的半导体器件,还包括:
第二源极/漏极区,位于所述半导体衬底上方并且邻近所述栅极堆叠件,其中,所述第一源极/漏极区和所述第二源极/漏极区设置在所述栅极堆叠件的相同侧上;以及
第二源极/漏极间隔件,位于所述第二源极/漏极区的侧壁上,其中,所述第二源极/漏极区的部分在所述第二源极/漏极间隔件的底面下方延伸。
3.根据权利要求2所述的半导体器件,还包括外延区,所述外延区将所述第一源极/漏极区连接至所述第二源极/漏极区。
4.根据权利要求3所述的半导体器件,其中,所述外延区设置在浅沟槽隔离(STI)区上方,并且所述外延区接触所述浅沟槽隔离(STI)区的顶面,其中,所述STI区设置在所述第一源极/漏极区和所述第二源极/漏极区之间。
5.根据权利要求3所述的半导体器件,其中,所述外延区沿着所述第一源极/漏极间隔件的侧壁和所述第二源极/漏极间隔件的侧壁向上延伸。
6.根据权利要求1所述的半导体器件,还包括:
栅极间隔件,位于所述栅极堆叠件的侧壁上,其中,所述第一源极/漏极间隔件连接至所述栅极间隔件,并且其中,在所述第一源极/漏极间隔件和所述栅极间隔件之间没有形成界面。
7.根据权利要求6所述的半导体器件,其中,所述栅极堆叠件包括:
栅极电介质,其中,所述栅极电介质的部分设置在所述栅极间隔件的底面下方;以及
栅电极,位于所述栅极电介质上方。
8.一种用于形成半导体器件的方法,所述方法包括:
形成从半导体衬底向上延伸的鳍;
在所述鳍的部分的侧壁上形成牺牲层;
在所述牺牲层上方形成间隔件层;
使所述鳍的所述部分凹进经过所述牺牲层的底面,其中,所述凹进形成设置在所述间隔件层的侧壁部分之间的沟槽;
去除所述牺牲层的至少部分;以及
在所述沟槽中形成源极/漏极区。
9.根据权利要求8所述的方法,其中,在所述沟槽中形成所述源极/漏极区包括外延地生长所述源极/漏极区。
10.一种用于形成半导体器件的方法,所述方法包括:
形成第一半导体鳍;
形成多个侧壁间隔件,其中,所述第一半导体鳍设置在所述多个侧壁间隔件的第一邻近的侧壁间隔件之间;
在所述多个侧壁间隔件的底面下方形成开口;
在所述多个侧壁间隔件的所述第一邻近的侧壁间隔件之间形成第一沟槽;以及
在所述第一半导体鳍上方的所述第一沟槽中外延地生长第一源极/漏极区,其中,外延地生长所述第一源极/漏极区包括使前体穿过所述开口流入所述第一沟槽内。
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US9923094B2 (en) | 2018-03-20 |
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US9577101B2 (en) | 2017-02-21 |
TWI582990B (zh) | 2017-05-11 |
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