TWI582990B - 鰭式場效電晶體之源極／汲極區域及其形成方法 - Google Patents

鰭式場效電晶體之源極／汲極區域及其形成方法 Download PDF

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TWI582990B
TWI582990B TW104137843A TW104137843A TWI582990B TW I582990 B TWI582990 B TW I582990B TW 104137843 A TW104137843 A TW 104137843A TW 104137843 A TW104137843 A TW 104137843A TW I582990 B TWI582990 B TW I582990B
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江國誠
劉繼文
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台灣積體電路製造股份有限公司
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Description

鰭式場效電晶體之源極/汲極區域及其形成方法
本揭露係關於一種鰭式場效應電晶體。
半導體裝置被廣泛用於多種電子裝置中，例如電腦、行動電話及其他。半導體裝置包含積體電路，其係藉由在半導體晶圓上沉積多種薄膜並將此等薄膜圖案化所形成。積體電路通常包括場效電晶體(field-effect transistor，FET)。
傳統上，將平面FET應用於積體電路。然而，因為現代半導體製程對於密度不斷提升以及縮減覆蓋區的需求，平面FET在縮小尺寸的過程中浮現了諸多問題。其中部分的問題包括次臨界擺幅(sub-threshold swing)劣化、顯著的汲極引致能障下降(drain induced barrier lowering，DIBL)、裝置特性波動以及漏電(leakage)。目前在研究鰭式場效電晶體(finFET)以克服某些上述問題。
在一般的finFET中，於基板上方形成垂直的鰭結構。可利用此種垂直的鰭結構在側向形成源極/汲極區域並在鰭形成一通道區域。在鰭的通道區域上方於垂直方向形成閘極，以形成finFET。接著，可在finFET上方形成一層間介電層(ILD)與複數個互連層。
本揭露的各種實施例包括在鰭上形成犧牲層與間隔 層，以改進源極/汲極磊晶。可在形成間隔層之前，於鰭上形成犧牲層。尤其是，可將犧牲層設置於側壁間隔件的底部和下方裝置構件(如，設置於鰭附近的STI(shallow trench isolation)區域)之間。移除犧牲層可在間隔層下方(如，間隔層與下方STI區域之間)形成開孔。使鰭位於側壁間隔件之間的部分內凹，並移除犧牲層的至少一部分。可進行磊晶製程，以在側壁間隔件之間長成源極/汲極區域。在磊晶過程中，可使前驅物由相鄰側壁間隔件之上方與下方區域(如經由開孔)流入。因此，可於側壁間隔件之間以多個方向生長源極/汲極區域，如此可有利地降低形成空洞之風險，即便是在相對之高寬高比的鰭中亦然。
根據一實施例，半導體裝置包含由半導體基板向上延 伸的鰭，以及設置於鰭的上表面與側壁上之閘極堆疊。該裝置更包含設置於半導體基板上方並鄰近閘極堆疊之第一源極/汲極區域，以及位於第一源極/汲極區域之一側壁上的第一源極/汲極間隔件。第一源極/汲極區域的一部分於第一源極/汲極區域之一底面下方延伸。
根據另一實施例，一種形成半導體裝置之方法包含形 成由半導體基板向上延伸的鰭，以及在鰭之一部分的側壁上形成犧牲層。該方法更包含於犧牲層上形成間隔層，並使鰭的部分內凹至超過犧牲層之底面。上述內凹在間隔層的側壁部分之間形成一溝槽。將犧牲層的至少一部分移除，並於溝槽中形成源極/汲極區域。
根據又一實施例，一種形成半導體裝置之方法包含形 成半導體鰭與形成複數側壁間隔件。該半導體鰭係設置於該複數側壁間隔件中相鄰者之間。在該複數側壁間隔件的底面下形成開孔，並在該複數側壁間隔件中的第一相鄰側壁間隔件之間形成第一溝槽。上述方法更包含在第一溝槽覆中於第一半導體鰭上方磊晶生長第一源極/ 汲極區域，其中磊晶生長第一源極/汲極區域包含使前驅物經由開孔流入第一溝槽中。
30‧‧‧finFET(鰭式場效電晶體)
32‧‧‧基板
36、116‧‧‧鰭
38‧‧‧隔離區域
40、172‧‧‧閘極介電質
42、174‧‧‧閘極電極
44、46‧‧‧源極/汲極區域
100‧‧‧晶圓
102‧‧‧基板
104‧‧‧基座基材層
104A、108A‧‧‧半導體氧化物區域
105‧‧‧箭頭
106、108‧‧‧基材層
106’‧‧‧半導體氧化物層
110、146‧‧‧硬罩
114、160、168‧‧‧溝槽
120‧‧‧通道區域
126‧‧‧STI區域
140、170‧‧‧閘極堆疊
142‧‧‧虛設氧化層
144‧‧‧虛設閘極
150‧‧‧犧牲層
152‧‧‧間隔層
154、154A、154B‧‧‧間隔件
158‧‧‧開孔
162‧‧‧磊晶區域(源極/汲極區域)
162A‧‧‧合併之區域
164‧‧‧層間介電質(ILD)
166‧‧‧中間層
170‧‧‧閘極堆疊
H1、H2、H3、H4‧‧‧高度
T1、T2、T3‧‧‧厚度
W1、W2‧‧‧寬度
自後述詳述說明與附屬圖式，可最佳理解本揭露之各實施例。須注意，依據產業之標準實施方式，各種構件並非依比例繪製。實際上，為了清楚討論，可任意增大或減小各種構件之尺寸。
圖1係一鰭式場效應電晶體(finFET)之一例的立體圖。
圖2至17C係根據某些實施例說明在finFET製備過程之中間階段的剖面圖及立體圖。
圖18係根據某些實施例說明製備finFET之方法的流程圖。
以下揭示內容提供了各種實施例或例示，其能用以實現本揭示內容的不同特徵。下文所述之元件與配置的具體例子係用以簡化本揭示內容。當可想見，此等敘述僅為例示，其本意並非用於限制本揭示內容。舉例而言，在下文的描述中，將第一特徵形成於第二特徵上或上方，可能包含某些實施例其中所述的第一與第二特徵彼此直接接觸；亦可能包含某些實施例其中於上述第一與第二特徵之間還形成其他特徵，而使得第一與第二特徵可能沒有直接接觸。此外，本揭示內容可能會在多個實施例中重複使用元件符號及/或標號。此種重複使用乃是基於簡化與清楚之目的，且其本身不代表所討論的不同實施例及/或組態之間的關係。
再者，在此處可使用空間對應詞彙，例如「之下」、「下方」、「低於」、「之上」、「上方」等類似詞彙，以方便說明圖中所繪示的一元件或特徵相對於另一或多個元件或特徵之間的關係。此等 空間對應詞彙其本意除了圖中所繪示的位向之外，還涵蓋了裝置在使用或操作中所處的多種不同位向。可將所述設備放置於其他位向(如，旋轉90度或處於其他位向)，並可相應解釋本揭露使用的空間對應描述。
本揭露之各種實施例包含在鰭上形成犧牲層，以改善 源極/汲極磊晶。隨著finFET裝置的尺寸不斷縮減，使用具有相對較高寬高比之鰭的裝置來改善驅動電流。再者，於鰭上形成側壁間隔件以界定源極/汲極磊晶區域，以減少密集裝置區域之源極/汲極磊晶短路情形。然而，此種高寬高比的鰭(藉由側壁間隔件的存在而進一步複合)可能會導致在源極/汲極磊晶過程中形成不被期望的空洞，特別是在源極/汲極區域的底部部分。
於各種實施例中，可在形成源極/汲極側壁間隔件之 前，於鰭上形成犧牲層。接著，在犧牲層上形成側壁間隔件。尤其是，可將犧牲層設置於側壁間隔件的底部和下方裝置構件(如，STI區域及/或作為鰭延伸起點的基板)之間。使鰭位於側壁間隔件之間的部分內凹，並移除犧牲層。可進行磊晶製程，以在側壁間隔件之間長成源極/汲極區域。因為犧牲層係形成於側壁間隔件和下方裝置構件之間，故在移除犧牲層之後，將於側壁間隔件下方形成開孔。在磊晶過程中，前驅物可由相鄰側壁間隔件之上方與下方區域(如經由開孔)流入。因此，可於側壁間隔件之間以多個方向生長源極/汲極區域，如此可有利地降低形成空洞之風險，即便是在相對高之寬高比的鰭中亦然。在所獲得的結構中，源極/汲極區域之一部分可設置於側壁間隔件下方。
圖1的立體圖繪示finFET 30之一例。FinFET 30包括 位於基板32上之鰭36。基板32包括隔離區域38，且鰭36由相鄰的隔離區域38之間突起至其上方。閘極介電質40沿著側壁並位於鰭36之上表 面上，而閘極電極42則設置於閘極介電質40上。鰭36被閘極介電質40/閘極電極42覆蓋的部分可稱為finFET 30之通道區域。源極/汲極區域44與46係設置於鰭36相對於閘極介電質40與閘極電極42之兩側上。 圖1進一步說明後續圖式之參照剖面。剖面A-A通過finFET 30的通道、閘極介電質40以及閘極電極42。剖面B-B通過finFET 30的源極/汲極區域44或46。剖面C-C垂直於剖面A-A，且係沿著鰭36之縱軸，且其方向為，例如，源極/汲極區域44及46之間的電流方向。為求簡潔，後續圖式會參照提及此等參照剖面。
圖2至17C係根據各種實施例說明在finFET製備過程 之中間階段的剖面圖及立體圖，而圖18係圖2至17C所述製程之流程圖。圖2至9繪示圖1的參照剖面A-A，不同之處在於其繪示了個finFET及/或具有多個鰭的finFET。在圖10A至17C中，圖號以A結尾的代表該圖係沿著相似的剖面A-A所繪示；圖號以B結尾者代表該圖係沿著相似的剖面B-B所繪示；而圖號以C結尾的代表該圖式是沿著相似的剖面C-C所繪示。再者，圖號以D結尾者代表該圖為例示性finFET之立體圖。
圖2至4繪示形成由基板向上延伸的半導體鰭。首先參 照圖2，繪示了具有基座基材(base substrate)層104之晶圓100。基座基材層104可為半導體基板，例如半導體塊材、絕緣體上覆半導體(SOI)基板或與其相似者，所述基板可經過摻雜(如以p-型或n-型摻雜物)或未摻雜。一般來說，SOI基板包含形成在絕緣層上的一層半導體材料。絕緣層可為，例如，埋入式氧化物(BOX)層、氧化矽層或與其相似者。絕緣層係提供於基板上，通常是矽或玻璃基板。亦可使用其他基板，例如多層基板或梯度基板。於某些實施例中，基材層104的半導體材料可包括矽(Si)、鍺(Ge)、化合物半導體包括碳化矽、鎵砷、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體包 括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或前述之組合。
如圖2進一步所繪示，可將抗穿通(anti-punch through，APT)摻雜物佈植於基座基材層104中，如箭頭105所示。於某些實施例中，可植入APT摻雜物以防止所形成之裝置中的源極/汲極穿通。植入之APT類型取決於欲獲得n-型或p-型裝置。例如，對於n-型裝置可植入硼，而對於p-型裝置則可植入磷或砷。舉例而言，基座基材層104中所植入之APT摻雜物的濃度可為約1x1018/cm3至約3x1019/cm3。
接著參照圖3，可任選地在基座基材層104上形成額外 的基材層106/108。於某些實施例中，可進行多次磊晶以形成各種基材層106及108。可利用任何適當的磊晶製程，例如利用金屬有機化學氣相沉積(MOCVD)、分子束磊晶(MBE)、液相磊晶(LPE)、氣相磊晶(VPE)、選擇性磊晶生長(SEG)、前述之組合或與其相似者。
基材層106及108係設置於基座基材層104上方，其中 基材層108設置於基材層106上方。於某些實施例中，基材層106可包含SiGe，而基材層108包括實質上的純Si。在後續製程步驟中，可將基材層106氧化，並可在基材層108中形成裝置之通道區域。在此等實施例中，基材層106可作為基材層108之未經摻雜的通道區域和佈植於基座基材層104中之APT摻雜物之間的阻障層。已觀察到，在氧化之SiGe層上形成未經摻雜的通道能夠提升遷移率並實現裝置效能。舉例而言，於一實施例中，基材層106的厚度T1為約5nm至約20nm。因此，如圖2所示，一實施例的基板102可包括多個半導體材料層104、106與108。於其他實施例中，可省略基材層106及108。
如圖3進一步所繪示，可將硬罩110設置於基板102上 方。硬罩110可包含一或多種氧化物(如氧化矽)及/或氮化物(如氮 化矽)層，以防止在圖案化過程中損傷下方基板102。可利用任何適當的沉積製程形成硬罩110，例如，原子層沉積(ALD)、化學氣相沉積(CVD)、高密度電漿CVD(HDP-CVD)、物理氣相沉積(PVD)及與其相似者。
圖4繪示將基板102圖案化，以在相鄰的溝槽114之間 形成鰭116。於一實施例中，可將光阻層(圖中未繪示)毯覆式地沉積於硬罩110上。之後可藉由利用光罩使光阻曝光於光線中，以將光阻圖案化。而後可依所用的是正光阻或負光阻，而將光阻曝光或未曝光之部分移除。之後光阻的圖樣可轉移至硬罩110(如，利用適當的蝕刻製程)。其後，在蝕刻製程中，利用硬罩110作為圖案化遮罩，將溝槽114圖案化至下方基板102中。可利用可接受的蝕刻製程而蝕刻基板102，例如反應性離子蝕刻(RIE)、中性束蝕刻(NBE)、與其相似者或其組合。蝕刻可為非等向性。其後，利用例如灰化及/或濕式剝除製程，將光阻移除。因此，在晶圓100中形成了多個鰭116。鰭116由基座基材層104向上延伸，並設置於相鄰的溝槽114之間。
圖5繪示對晶圓100之可選的氧化製程。在此等實施例 中，可將基材層106氧化以提供一半導體氧化物層106’，其包含例如矽鍺氧化物。可利用任何適當的氧化製程，例如一濕式氧化製程，其能夠選擇性地氧化基材層106內的Ge，其氧化速率高於基材層104或108中其他半導體材料(如，矽塊材)的氧化速率。在某些例示性實施例中，濕式氧化製程可包括將晶圓100保持在約400℃至約600℃的溫度間，同時在約1大氣壓的下對晶圓100供應純水蒸汽，時間持續約30分鐘至約1小時。亦可使用其他適當的氧化製程。
氧化製程可將基材層106’完全氧化。於某些實施例 中，因為氧化的緣故，可於基材層106’的頂面及/或底面形成實質上為純Ge之殘留層(並未獨立繪示)。在後續製程步驟中，可於鰭116的 一部分中在半導體氧化物層106’上方形成通道區域，以加強遷移率與裝置效能。氧化製程可進一步部分氧化基材層104及108，以形成半導體氧化物區域108A及104A，其包括例如SiO。其後，可利用例如適當的蝕刻製程，移除此等半導體氧化物區域108A及104A。蝕刻亦可部分蝕刻半導體氧化物層106’之側壁。所得結構如圖6所示。
接著參照圖7，可利用介電材料(例如，氧化矽或與 其相似者)填充溝槽114。於某些實施例中，所獲得之STI區域126可利用高密度電漿(HDP)CVD製程來形成，其使用矽烷(SiH4)與氧氣(O2)作為反應前驅物。於其他實施例中，可利用次大氣壓CVD(SACVD)製程或高寬高比製程(HARP)來形成STI區域126，其中製程氣體可包含四乙氧基矽烷(TEOS)與臭氧(O3)。在又一些實施例中，可利用旋塗介電質(SOD)製程來形成STI區域126，其使用了例如氫矽倍半氧烷(HSQ)或甲基矽倍半氧烷(MSQ)。可進行退火(或其他適當的製程)來固化STI區域126之材料。亦可使用其他製程及材料。可進行化學機械拋光(CMP)或其他回蝕製程以使STI區域126與鰭116的上表面平整。亦可在CMP/回蝕過程中或利用其他適當的製程來移除硬罩110。
再者，於某些實施例中，STI區域126可包括共形內襯(liner)(圖中未繪示)，其係在以介電材料填充溝槽114之前，形成於溝槽114之側壁與底面上。於某些實施例中，內襯可包括半導體(如矽)氮化物、半導體(如矽)氧化物、熱半導體(如矽)氧化物、半導體(如矽)氮氧化物、聚合物介電質、前述之組合及與其相似者。可利用任何適當的方法來形成內襯，例如，原子層沉積(ALD)、CVD、高密度電漿(HDP)CVD、物理氣相沉積(PVD)及與其相似者。在此等實施例中，內襯可防止(或至少減少)在STI區域126的退火過程中，半導體材料從鰭116(如，Si及/或Ge)擴散 至周圍的STI區域126中。
接著於圖8中，使STI區域126內凹，因而使得半導體 層108的上部高於STI區域126的上表面。STI區域126之內凹可包括一化學蝕刻製程，例如，使用氨(NH3)並搭配氫氟酸(HF)或三氟化氮(NF3)作為反應溶液，可使用或不使用電漿。當使用HF作為反應溶液時，HF的稀釋比可界於約1：50至約1：100之間。在內凹後，暴露出鰭116中之半導體層108的上表面與側壁。因而，在鰭116中形成通道區域120(如，沿著剖面A-A之半導體層108的露出部分)。在完成的finFET結構中，閘極會圍繞並覆蓋此等通道區域120之側壁(參照，如圖1及17A)。於某些實施例中，通道區域120可位於半導體氧化物層106’上，且通道區域120可實質上不含任何摻雜物，因為APT摻雜物僅佈植於基座基材層104中。亦可使用其他配置之鰭116與通道區域120。
圖9以及圖10A與10B繪示在通道區域120的上表面與 側壁形成閘極堆疊140。如上文所述，圖9及10A繪示沿著剖面A-A(如，通過鰭116的通道區域)所示之晶圓100，而圖10B繪示沿著剖面B-B(如，通過鰭116的源極/汲極區域)所示之晶圓100。閘極堆疊140的形成從圖9開始，將共形的虛設氧化層142沉積於鰭116的上表面與側壁上。於某些實施例中，可將虛設氧化層142形成為設置於鰭116的通道區域120以及源極/汲極區域上方。
接著如圖10A，將虛設閘極144形成於虛設氧化層142 上方。虛設閘極144可包括，例如多晶矽，但亦可使用其他材料，例如金屬矽化物、金屬氮化物或與其相似者。閘極堆疊140之縱長方向實質上和半導體鰭116的縱長方向互相垂直(參見例如圖1)。
之後在虛設閘極144上方形成硬罩146。硬罩146可包 括例如氮化矽或氧化矽。於某些實施例中，硬罩146可為多層結構， 其包含如一氮化物層與一氧化物層。於某些實施例中，閘極堆疊140可覆蓋於複數個半導體鰭116及/或STI區域126上方。可將硬罩146圖案化以露出鰭116之源極/汲極區域(參見例如圖10B)同時覆蓋住通道區域120。可利用例如光微影與蝕刻之組合，來進行硬罩146之圖案化。如圖10A及10B進一步所示，可進行蝕刻以將未被硬罩146覆蓋之閘極堆疊140部分蝕去。在蝕刻之後，硬罩146與閘極堆疊140仍可留存在鰭116之通道區域120上(參見圖10A)但將鰭116之源極/汲極區域暴露出(參見圖10B)。
圖11A至11C繪示在鰭116、閘極堆疊140與硬罩146上 形成犧牲層150與間隔層152。於各種實施例中，可選擇犧牲層150與間隔層152之材料，以使犧牲層150可選擇性地移除而不實質上移除間隔層152。例如，於一實施例中，間隔層152為氧化物(如，SiO)而間隔層152包含SiOCN。犧牲層150及/或間隔層152亦可使用其他介電材料，包括低介電常數介電材料。例如，間隔層152亦可包括氮化物、SiCN或與其相似者。犧牲層150及間隔層152可為利用任何適當的方法(例如CVD，PECVD或與其相似者)所形成的共形層。間隔層152及犧牲層150覆蓋硬罩146的上表面(參見例如圖11A)、鰭116之源極/汲極部分的上表面與側壁(參見例如圖11B)、隔離層126的上表面(參見例如圖11B-11C)以及閘極堆疊140之側壁(參見例如圖11C)。犧牲層150係設置於間隔層152的底面上，並使間隔層152和下方裝置構件(如，STI區域126)分隔開。舉例而言，於某些實施例中，犧牲層150的厚度T2為約2nm至約10nm，且間隔層152之厚度T3為約3nm至約12nm。
接著在圖12A至12D中，可利用例如回蝕製程，將鰭 116未被硬罩146覆蓋之部分(如，鰭116之源極/汲極區域)內凹直到超過STI區域126之上表面。作為內凹製程的一部分，將間隔層152及 犧牲層150的上部移除以露出鰭116。可進一步由硬罩146之上表面將間隔層152及犧牲層150移除。在暴露出鰭116後，使鰭116內凹。於某些實施例中，內凹可移除半導體氧化物層106’並裸露出基座基材層104。在蝕刻之後，鰭116之露出部分的上表面會低於犧牲層150及間隔層152。在源極/汲極回蝕過程中，硬罩146防止閘極結構140或鰭116之通道區域120被蝕刻。
在所獲得的結構中，被蝕刻的間隔層152形成多個間 隔件154(標記為154A與154B)。在後續製程步驟中，間隔件154可作為側壁間隔件，以界定所得裝置之閘極，亦可用以界定源極/汲極磊晶區域。在裝置的源極/汲極區域中，會相應地在相鄰的源極/汲極間隔件154A之間形成溝槽160(參見例如圖12B)。再者，閘極堆疊140可設置於閘極間隔件154B之間(參見例如圖12C)。因為間隔層152原本係由單一共形層形成，故間隔件154A可以平順地連接至間隔件154B，而兩者之間並未形成任何介面(參見例如圖12D之立體圖)。 犧牲層150可位於間隔件154A/154B之底面下方，且犧牲層150將間隔件154A/154B和下方裝置層隔開。溝槽160位於虛設閘極堆疊140之相對側上(參見例如圖12C)。
圖13A至13D繪示利用任何適當的製程，選擇性地移 除在源極/汲極側壁間隔件154A之側壁與底面上的部分犧牲層150。例如，於一實施例中，可進行使用HF作為反應藥劑之濕式蝕刻製程以移除犧牲層150之部分。在此等實施例中，HF的稀釋比為約1：100。 於另一實施例中，在針對溝槽160之源極/汲極區域的磊晶製程(參見例如圖14A至14D)所做之原位預清潔製程(如，利用SiCoNi蝕刻來移除半導體基板102中之原生氧化物層)中，移除部分的犧牲層150。 在此等實施例中，一相同的磊晶工具可移除部分的犧牲層150以及在溝槽160長成源極/汲極區域。可在室溫下移除犧牲層150。於某些實 施例中，位在閘極間隔件154之側壁與底面上的犧牲層150部分仍可留存(參見例如圖13C及13D)。在此等實施例中，在移除位於源極/汲極側壁間隔件154A之側壁與底面上之犧牲層150部分的過程(如蝕刻)中，犧牲層150留存的部分受到閘極間隔件154B之保護。
間隔件154A連接至閘極間隔件154B且結構上由其支 撐(參見例如圖13D)。因此，移除犧牲層150會在間隔件154A和下方元件構件(例如，STI區域126)之間形成開孔158(參見例如圖13B及13D)。開孔158連接至溝槽160。在磊晶過程中，開孔158允許前驅物在間隔件154A下方流動，並在溝槽160中長成源極/汲極區域。
在圖14A至14D中，藉由在溝槽160中選擇性地長成半 導體材料而形成磊晶區域162。於某些實施例中，磊晶區域162包括矽、鍺(不含矽)、矽鍺、矽磷、矽鍺硼或與其相似者。硬罩146及間隔件152B可遮罩晶圓100的某些區域，以在基材層104上界定用以形成磊晶區域162之區域(如，僅在鰭116之露出部分上)。在磊晶過程中，開孔158(參見圖13B及13D)可允許前驅物直接流入溝槽160之底部。因此，溝槽160可被來自多個方向的前驅物填充(如，從上方以及底部區域)，進而減少磊晶區域162中空洞之形成。於某些實施例中，所使用之前驅物的種類取決於欲形成NMOS或PMOS裝置。例如，對於NMOS裝置，可使用氣態的矽、磷或其組合，而對於PMOS裝置，可使用氣態矽、鍺、硼或其組合。
在溝槽160被磊晶區域162填滿後，源極/汲極區域的 進一步磊晶生長使磊晶區域162水平擴張，且開始形成端面。在磊晶步驟之後，對PMOS裝置可利用p-型雜質(如硼或BF2)來佈植磊晶區域162，或對NMOS裝置可利用n-型雜質(如磷或砷)來佈植磊晶區域162，以形成源極/汲極區域，此處亦標記為元件符號162。或者是，可在磊晶區域162的長成過程中進行p-型或n-型雜質的原位摻 雜，以形成源極/汲極區域。
在所獲得的裝置中，源極/汲極區域162係位於閘極堆 疊140的二相對側上，且進一步沿著閘極堆疊140之側壁向上延伸(參見圖14C及14D)。再者，由於磊晶係經由開孔158而進行，故源極/汲極區域162的至少一部分可位於源極/汲極側壁間隔件154A的下方(參見例如圖14B)。源極/汲極區域162的上述部分可位於源極/汲極側壁間隔件154A和下方STI區域126之間。於某些實施例中，源極/汲極區域162的高度H1為約30nm至約80nm，而源極/汲極區域162在間隔件154A之間的寬度W1為約8nm至約16nm。於某些實施例中，源極/汲極區域162位於間隔件154A與STI區域126之間的部分之厚度T4為約2nm至約10nm。
圖14E及14D繪示根據其他實施例之源極/汲極區域 162的剖面圖。圖14E及14D所示係沿著圖1之切面B-B所得。於圖14E所繪示之實施例中，磊晶製程可將源極/汲極區域162的底部合併。例如，源極/汲極區域162位於間隔件154A下方的部分可側向地延伸並合併。此等合併之區域162A可覆蓋於STI區域126上。於圖14F所示之實施例中，磊晶製程可進一步使合併之區域162A沿著間隔件154A的側壁向上成長並設置於STI區域126上方。在此等實施例中，合併之區域162A的高度H2可小於間隔件154A之高度H3的約二分之一。於某些實施例中，高度H2可小於高度H3的約三分之一。
圖15A至15C繪示形成層間介電質164之後的晶圓 100。ILD 164可包含可流動的氧化物，其係利用例如，可流動化學氣相沉積(FCVD)。可進行CMP(或其他適當的平坦化製程)，以使ILD 164、閘極堆疊140及閘極間隔件154B之上表面彼此齊平。可在ILD層164以及源極/汲極區域162、閘極堆疊140及/或閘極間隔件154B之間形成多種中間層166(如，緩衝層及/或蝕刻停止層)。
圖16A至16C繪示在暴露出鰭116之通道區域120後的 晶圓100之多種圖式。通道區域120的暴露可包括利用例如蝕刻製程，將閘極堆疊140(包括硬罩146、虛設閘極144及虛設氧化層142)從通道區域120之側壁與上表面上移除。閘極堆疊140之移除可界定閘極間隔件154B間之溝槽168(參見圖16C)。在移除閘極堆疊140的過程中，可利用硬罩(圖中未繪示)來遮罩ILD 164及源極/汲極區域162。因此，可移除閘極堆疊140而不將ILD 164或源極/汲極區域162圖案化。亦可移除犧牲層之剩餘部分(如，位於側壁上以及位於閘極間隔件154B下之部分)。
接著參照圖17A至17B，於溝槽168中形成閘極堆疊 170。例如，將閘極介電質172以共形層之形式形成於溝槽168中。可進一步在閘極間隔件154B下方形成閘極介電質172(參見例如圖17C)，閘極介電質172可覆蓋於通道區域120之上表面與側壁上(參見圖17A)。根據某些實施例，閘極介電質172包括氧化矽、氮化矽或尤其組成之多層結構。在替代性的實施例中，閘極介電質172包括高介電常數介電材料。在此等實施例中，閘極介電質172的介電值(k)大於約7.0，且可包含金屬氧化物或鉿(Hf)、鋁(Al)、鋯(Zr)、鑭(La)、鎂(Mg)、鋇(Ba)、鈦(Ti)、鉛(Pb)之矽化物、前述之組合及與其相似者。形成閘極介電質172之方法可包括分子束沉積(MBD)、ALD、電漿強化CVD(PECVD)或與其相似者。
接著以導電性材料填充溝槽168之剩餘部分，以將導 電性閘極電極174形成於閘極介電質172上。閘極電極174可包括含金屬材料，例如氮化鈦(TiN)、氮化鉭(TaN)、碳化鉭(TaC)、鈷(Co)、釕(Ru)、鋁(Al)、前述之組合、其等之多層結構及與其相似者。形成閘極介電質172與閘極電極174時，可使材料溢出溝槽160並覆蓋ILD 164之上表面。其後，可進行平坦化製程(如CMP)，以移 除閘極介電質172及閘極電極174之多餘部分。所獲得之閘極介電質172及閘極電極174的留存部分形成所獲得之finFET中的位於通道區域120上之閘極堆疊170。舉例而言，於一實施例中，通道區域120之寬度W2為約6nm至約12nm且其高度H4為約30nm至約80nm。之後可利用任何適當的製程，在ILD 164中形成額外的構件，例如源極/汲極接點(圖中未繪示)，其包括如鎳(Ni)、鎢(W)或與其相似者，以電性連接至源極/汲極區域162。
圖18繪示根據某些實施例的用以形成半導體裝置(如 finFET)之例示性的製程流程200。製程200由步驟202開始，形成由半導體基板(如基板102)向上延伸之鰭(如鰭116)。在步驟204中，於鰭之通道區域(如通道區域120)的上表面與側壁上形成虛設閘極堆疊(如閘極堆疊140)。在步驟206中，在鰭之露出部分上形成犧牲層(如犧牲層150)。可進一步將犧牲層形成於虛設閘極堆疊之上表面與側壁上。
製程繼續進行到步驟208，將間隔層(如間隔層152) 形成於犧牲層上方。間隔層可位於犧牲層之側壁上，且犧牲層之一部分可在間隔層之底面下延伸。在步驟210中，藉由移除間隔層及犧牲層的上部而暴露出鰭。移除間隔層的上部進一步在鰭之部分部分上界定出側壁間隔件(如間隔件154A)，並在虛設閘極堆疊之側壁上界定出及閘極間隔件(如間隔件154B)。
接著在步驟212中，藉由將鰭內凹至超過犧牲層之底 面，在側壁間隔件之間界定出溝槽(如溝槽160)。在步驟214中，移除犧牲層之至少一部分。側壁間隔件連接至閘極間隔件且結構上由其所支撐，並移除犧牲層之部分，以在側壁間隔件下方界定開孔(如開孔158)。開孔可連接至溝槽。在步驟216中，於溝槽中磊晶長成源極/汲極區域(如源極/汲極區域162)。源極/汲極區域之磊晶可包括使前 驅物流入側壁間隔件之間的溝槽中並流經開孔。因此，磊晶生長可由多個方向啟動，因而能夠減少所獲得之源極/汲極區域內的空洞。
以上內容概述本發明若干實施例之特徵，因而所屬技 術領域中具有通常知識者可更為理解本揭露所揭示內容之各方面。所屬技術領域中具有通常知識者應理解可輕易使用本揭露之內容作為基礎，用於設計或修改其他製程及結構而與本申請案該之實施例具有相同目的及/或達到相同優點。所屬技術領域中具有通常知識者亦應理解此均等架構並未悖離本申請案揭示內容的精神與範圍，且在不悖離本申請案揭示內容之精神及範圍的情況下，所屬技術領域中具有通常知識者可進行各種變化、取代、與替換。
30‧‧‧finFET
32‧‧‧基板
36‧‧‧鰭
38‧‧‧隔離區域
40‧‧‧閘極介電質
42‧‧‧閘極電極
44、46‧‧‧源極/汲極區域

Claims (10)

  1. 一種半導體裝置，包含：一鰭，由一半導體基板向上延伸；一閘極堆疊，設置於該鰭之一上表面與側壁上；一第一源極/汲極區域，設置於該半導體基板上方並鄰近該閘極堆疊；以及一第一源極/汲極間隔件，設置於該第一源極/汲極區域之一側壁上，其中該第一源極/汲極區域之一部分於該第一源極/汲極間隔件之一底面下延伸。
  2. 如請求項1所述之半導體裝置，更包含：一第二源極/汲極區域，設置於該半導體基板上方並鄰近該閘極堆疊，其中該第一與第二源極/汲極區域係設置於該閘極堆疊之一相同側上；以及一第二源極/汲極間隔件，位於該第二源極/汲極區域之一側壁上，其中該第二源極/汲極區域之一部分於該第二源極/汲極間隔件之一底面下延伸。
  3. 如請求項2所述之半導體裝置，更包含一磊晶區域，其將該第一源極/汲極區域連接至該第二源極/汲極區域。
  4. 如請求項3所述之半導體裝置，其中該磊晶區域係設置於一淺溝槽隔離(shallow trench isolation,STI)區域之一上表面上方並與其接觸，其中該STI區域係設置於該第一源極/汲極區域與該第二源極/汲極區域之間。
  5. 如請求項3所述之半導體裝置，其中該磊晶區域沿著該第一源極/汲極間隔件與該第二源極/汲極間隔件之側壁向上延伸。
  6. 如請求項1所述之半導體裝置，更包含一閘極間隔件，位於該閘 極堆疊之一側壁上，其中該第一源極/汲極間隔件係連接至該閘極間隔件，且其中該第一源極/汲極間隔件與該閘極間隔件之間並未形成介面。
  7. 如請求項6所述之半導體裝置，其中該閘極堆疊包含：一閘極介電質，其中該閘極介電質之一部分係設置於該閘極間隔件之一底面下方；以及一閘極電極，設置於該閘極介電質上方。
  8. 一種形成半導體裝置之方法，包含：形成一鰭，其係由一半導體基板向上延伸；形成一犧牲層，其係位於該鰭之一部分的側壁上；形成一間隔層，其係設置於該犧牲層上方；內凹該鰭之該部分使其超過該犧牲層之一底面，其中該內凹於該間隔層的側壁部分之間形成一溝槽；移除該犧牲層之至少一部分；以及形成一源極/汲極區域於該溝槽中。
  9. 一種形成半導體裝置之方法，包含：形成一第一半導體鰭；形成複數側壁間隔件，其中該第一半導體鰭係設置於該複數側壁間隔件中的第一相鄰側壁間隔件之間；形成位於該複數側壁間隔件之一底面下的開孔；形成一第一溝槽，其係設置於該複數側壁間隔件中的該第一相鄰側壁間隔件之間；以及磊晶生長一第一源極/汲極區域，其係設置於該第一溝槽中並設置於該第一半導體鰭上方，其中磊晶生長該第一源極/汲極區域包含使一前驅物經由該開孔流入該第一溝槽內。
  10. 如請求項9所述之形成半導體裝置之方法，其中形成位於該複數 側壁間隔件之一底面下方的開孔包含：形成一犧牲層，其係設置於該複數側壁間隔件與該第一半導體鰭之間，其中該犧牲層於該複數側壁間隔件之該底面下延伸；以及移除該犧牲層之至少一部分。
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