TWI495107B - 半導體裝置之接觸結構、金氧半導體場效電晶體、及半導體裝置之製造方法 - Google Patents

半導體裝置之接觸結構、金氧半導體場效電晶體、及半導體裝置之製造方法 Download PDF

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TWI495107B
TWI495107B TW102138196A TW102138196A TWI495107B TW I495107 B TWI495107 B TW I495107B TW 102138196 A TW102138196 A TW 102138196A TW 102138196 A TW102138196 A TW 102138196A TW I495107 B TWI495107 B TW I495107B
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Taiwan
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layer
dielectric layer
semiconductor
substrate
opening
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TW102138196A
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TW201419544A (zh
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Sung Li Wang
Ding Kang Shih
Chin Hsiang Lin
Sey Ping Sun
Clement Hsingjen Wann
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Taiwan Semiconductor Mfg Co Ltd
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Description

半導體裝置之接觸結構、金氧半導體場效電晶體、及半導體裝置之製造方法
本發明係關於積體電路製作，且特別地關於一種具有接觸結構(contact structure)之半導體裝置。
隨著半導體工業演進至奈米技術製程節點以追求更高之裝置密度、更佳之表現與更低之成本，來自於製造與設計問題的挑戰進而發展出了如鰭型場效電晶體(FinFET)之三維設計(3D design)之半導體裝置。典型之鰭型場效電晶體係藉由如蝕刻去除基板之矽層之一部以形成延伸自基板之一垂直薄型”鰭部”(或鰭結構)。鰭型場效電晶體之通道係形成於此垂直鳍部之內。而閘極係形成(如包覆)於此鳍部之三個側邊之上。具有位於通道之兩側邊上之閘極可自通道之此兩側邊控制此通道。鳍型場效電晶體之未來挑戰則包括了降低短通道效應以及更高之電流量。
然而，於互補型金氧半導體製作(CMOS fabrication)中應用鰭型場效電晶體之構件與製程仍遭遇了眾多挑戰。舉例來說，應變材料(strained materials)的矽化物的形成(silicide formation)於鳍型場效電晶體之源極/汲極區造成了高接觸電阻(high contact resistance)，進而劣化了裝置表現。
依據一實施例，本發明提供了一種半導體裝置之接觸結構，包括：一基板，包括一主表面以及位於該主表面下方之一溝槽；一應變材料，填滿該溝槽，其中該應變材料之晶格常數不同於該基板之晶格常數；一層間介電層，具有位於該應變材料上之一開口，其中該開口包括了數個介電側壁以及一應變材料底部；一半導體層，位於該開口之該些介電側壁與該應變材料底部上；一介電層，位於該半導體層上；以及一金屬層，填滿該介電層之一開口。
依據另一實施例，本發明提供了一種金氧半導體場效電晶體，包括：一基板，包括一主表面；一閘極堆疊物，位於該基板之該主表面上；一溝槽，位於鄰近該閘極堆疊物之該主表面之下；一淺溝槽隔離物，設置於該溝槽相對於該閘極堆疊物之一側上，其中淺溝槽隔離區係位於該基板內；以及一接觸結構，包括：一應變材料，填滿該溝槽，其中該應變材料之晶格常數不同於該基板之晶格常數；一層間介電層，具有位於該應變材料上之一開口，其中該開口包括了數個介電側壁以及一應變材料底部；一半導體層，位於該開口之該些介電側壁與該應變材料底部上，其中該半導體層具有介於0.3-1.5奈米之厚度；一介電層，位於該半導體層上，其中該介電層具有介於1-10奈米之厚度；以及一金屬層，填滿該介電層之一開口。
依據又一實施例，本發明提供了一種半導體裝置 之製造方法，包括：提供包括一主表面以及位於該主表面之下之一溝槽之一基板；磊晶成長一應變材料於該溝槽內，其中該應變材料之晶格常數不同於該基板之晶格常數；形成一層間介電層於該應變材料上；形成一開口於該層間介電層內，以露出該應變材料之一部；形成一半導體氧化物層於該開口之內部並延伸至該層間介電層之上；形成一第一金屬層於該半導體氧化物層；加熱該基板，以形成一半導體層與一介電層於該半導體氧化物層上；以及形成一第二金屬層於該介電層之一開口內。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下。
100‧‧‧製造方法
102、104、106、108、110、112、114、116‧‧‧步驟
20‧‧‧基板
20s‧‧‧主表面
200‧‧‧半導體裝置
202‧‧‧鳍結構
204‧‧‧淺溝槽隔離區
204a‧‧‧淺溝槽隔離區
204b‧‧‧淺溝槽隔離區
206‧‧‧源極與汲極溝槽
206a‧‧‧源極與汲極溝槽
206b‧‧‧源極與汲極溝槽
208‧‧‧應變材料
210‧‧‧閘極堆疊物
212‧‧‧閘介電層
214‧‧‧閘電極層
216‧‧‧側壁間隔物
218‧‧‧層間介電層
220‧‧‧開口
220a‧‧‧介電側壁
220b‧‧‧應變材料底部
222‧‧‧半導體氧化物層
224‧‧‧第一金屬層
226‧‧‧半導體層
228‧‧‧介電層
230‧‧‧開口
232‧‧‧第二金屬層
234‧‧‧接觸結構
t1 ‧‧‧第一厚度
t2 ‧‧‧第一厚度
t3 ‧‧‧第一厚度
t4 ‧‧‧第一厚度
第1圖為一流程圖，顯示了依據本發明之一實施例之一種半導體裝置之接觸結構之製造方法。
第2-12圖為一系列剖面示意圖，分別顯示了依據本發明之一實施例之包括一接觸結構之一種半導體裝置於製造中之不同階段中的情形。
可以理解的是，於下文中提供了用於施行本發明之不同特徵之多個不同實施例，或範例。基於簡化本發明之目的，以下描述了元件與設置情形之特定範例。然而，此些元件與設置情形僅作為範例之用而非用於限制本發明。此外，本發明於不同實施例中可能重複使用標號及/或文字。如此之重複 情形係基於簡化與清楚之目的，而非用於限定不同實施例及/或討論形態內的相對關係。再者，於描述中關於於一第二元件之上或上之第一元件的形成可包括了第一元件與第二元件係為直接接觸之實施情形，且亦包括了於第一元件與第二元件之間包括了額外元件之實施情形，因而使得第一元件與第二元件之間並未直接接觸。再者，本文中將於不同實施例可能重複使用標號及/或文字。此些重複情形係基於簡化與清楚之目的，而非限定介於此些不同實施例及/或討論型態之間的關係。
請參照第1圖，顯示了為依據本發明之一實施例之半導體裝置之接觸結構之一種製造方法100之流程圖。製造方法100起始於步驟120，提供包括一主表面以及位於主表面下之一溝槽之一基板。製造方法100接著進行步驟104，於溝槽內成長一應變材料，其中應變材料的晶格常數不同於基板的晶格常數。製造方法100接著進行步驟106，形成一層間介電層(ILD)於應變材料上。製造方法100接著進行步驟108，於層間介電層內形成露出應變材料之一部之一開口。製造方法100接著進行步驟110，形成一半導體氧化物層於開口內並延伸於層間介電層上。製造方法100接著進行步驟112，於半導體氧化物層上形成一第一金屬層。製造方法100接著進行步驟114，加熱基板以形成一半導體層與位於半導體層上之一介電層。製造方法100接著進行步驟116，於介電層之一開口內形成一第二金屬層。本發明之半導體裝置之多個實施例的製作可參照如第1圖所示之製造方法100所完成。
第2-12圖為一系列剖面示意圖，顯示了依據本發明 之多個實施例之包括接觸結構234之半導體裝置200於製造時之多個階段中之情形。於本實施例中，半導體裝置200係為一鰭型場效電晶體(FinFET)。此鰭型場效電晶體可為任一型之鳍基(fin-based)之多重閘電晶體。於部分之其他實施例中，半導體裝置200係為一平面型金氧半導體場效電晶體(planar MOSFET)。其他電晶體結構及類似結構亦屬於本發明之範疇。此半導體裝置200可設置於一微處理器、記憶體、及/或積體電路之內。
值得注意的是，於部分實施例中，如第1圖所示之操作並無法形成一完整半導體裝置200。而完整的半導體裝置200可採用互補型金氧半導體技術製程所製造形成。如此，可以理解的是可於如第1圖所示之製造方法之前、之中或之後施行額外製程，而可僅於此處簡單描述部分之其他製程。此外，基於較易了解本發明概念之目的，第2-12圖係為簡化過之圖示。舉例來說，雖然如圖式中繪示了半導體裝置200，可以理解的是積體電路可包括如電阻、電容、電感、熔絲等之數個其他裝置。
請參照第2圖及第1圖內之步驟102，提供包括一主表面20s之一基板20。於至少一實施例中，基板20包括一結晶矽基板(例如晶圓)。依照設計需求(如P型基板或N型基板)，基板20可包括多個摻雜區。於部分實施例中，此些摻雜區可摻雜有P型摻質或N型摻質。舉例來說，此些摻雜區可摻雜如硼或BF2 之P型摻質，或如磷或砷之N型摻質例，及/或其組合。此些摻雜區可用於N型之鳍型場效電晶體或平面型金氧半導體電晶 體之內，或用於P型之鰭型場效電晶體或平面型金氧半導體電晶體之內。
基板20亦可由其他之適當半導體材料所形成，例如為鑽石或鍺等元素態半導體材料、如砷化鎵、碳化矽、砷化銦、或磷化銦之化合物半導體材料，或如碳化矽鍺、磷化砷銦或磷化鎵銦之合金半導體材料。再者，基板20可包括一磊晶層(epi-layer)而經過應變以改善其表現，及/或可包括絕緣層上覆矽結構(SOI structure)。
於圖示之實施例中，基板20可更包括一鳍結構202。形成於基板20上之鳍結構202包括了一或多個鳍部(fin)。於所示之實施例中，基於簡化之目的，鳍結構202包括了單一鳍部。此鳍部包括任一適當材料，鳍部可包括如矽、鍺、或化合物半導體之材料。鳍結構202可更包括設置於鳍部上之一上蓋層(未顯示)，而此上蓋層可為一矽上蓋層(silicon-capping layer)。
鳍結構202係由任一之適當製程所形成，其包括了多個沉積、微影、及/或蝕刻製程的施行。微影製程之一範例可包括形成一光阻層(阻劑)以覆蓋基板20(例如為位於一矽層上)、曝光光阻以形成一圖案、施行一曝光後烘焙製程、以及顯影此光阻以形成包括此光阻之一遮蔽元件。可接著採用反應性離子蝕刻製程及/或其他適當製程以蝕刻矽層。於一實施例中，可採用圖案化與蝕刻矽基板20之一部以形成鳍結構202之此些矽鳍部。於另一實施例中，鳍結構202之矽鳍部的形成可形成採用圖案化與蝕刻沉積於一絕緣層上之一半導體層(例如 一絕緣層上覆矽基板之一絕緣-矽堆疊結構之一上方矽層)所形成。於其他實施例中，鳍結構係由形成一介電層於一基板上、於介電層內形成數個開口溝槽、以及於基板內之溝槽內磊晶成長以形成鳍部所形成。
於圖示實施例中，於基板20內形成有數個隔離區以定義與電性隔離鳍結構202之不同鳍部。於一範例中，此些隔離區包括了淺溝槽隔離區204(包括了204a與204b)。此些隔離區可包括氧化矽、氮化矽、氮氧化矽、氟摻雜矽玻璃(FSG)、低介電常數介電材料及/或其組合。且於本實施例中，此些隔離區之淺溝槽隔離區可藉由任一適當製程所形成。於一範例中，淺溝槽隔離區204的形成可包括採用一介電材料填入(例如採用化學氣相沉積)位於鳍部間之溝槽內。於部分實施例中，所填入之溝槽可具有一多層膜結構，例如為包括為氮化矽或氧化矽所填滿之熱氧化物襯層。
請繼續參照第2圖，於淺溝槽隔離區204之間的基板20之主表面20s(例如鳍結構202之頂面)上形成一閘極堆疊物210。雖然於本圖式中閘極堆疊物210僅延伸於鳍部的頂面上，熟悉此技術者可理解於裝置之另一平面內(未顯示於圖內)，閘極堆疊物210係沿著鳍結構202之側壁而延伸。於部分實施例中，閘極堆疊物210包括一閘介電層212與位於閘介電層212上之一閘電極層214。於部分實施例中，一對側壁間隔物係形成於閘極堆疊物210之兩個側壁上。於圖示實施例中，閘極堆疊物210可採用任一適當製程所形成，包括了下述描述之製程。
於一範例中，閘介電層212與閘電極層214係依序 沉積於基板20上。於部分實施例中，閘介電層212可包括氧化矽、氮化矽、氮氧化矽或高介電常數(high-k)介電材料。高介電常數介電材料包括了金屬氧化物。金屬氧化物的範例包括鋰、鈹、鎂、鈣、鍶、釔、鋯、鉿、鋁、鑭、鈽、鐠、釹、釤、銪、釓、鋱、鏑、鈥、鉺、銩、鐿、鎦及其混合物所組成族群之一氧化物。於本實施例中，閘介電層212為具有介於約10-30奈米之一厚度之一高介電常數介電層。閘介電層212可藉由任一適當製程所製程，例如為原子層沉積、化學氣相沉積、物理氣相沉積、熱氧化法、紫外光-臭氧氧化法或其組合。閘介電層212可更包括一中間層(未顯示)，以減少介於閘介電層212與鳍結構202之間的毀損情形。此中間層可更包括氧化矽。
於部分實施例中，閘電極層214可包括單一膜層或多重膜層。於至少一實施例中，閘電極層214包括了多晶矽。再者，閘電極層214可為具有均勻或非均勻摻雜情形之經摻雜多晶矽。於另一實施例中，閘電極層214包括了由鎢、銅、鈦、銀、鋁、鋁鈦、氮化鈦鋁、碳化鉭、碳氮化鉭、氮矽化鉭、錳、與鋯之所組成之族群之一金屬。於其他實施例中，閘電極層214包括擇自由氮化鈦、氮化鎢、氮化鉭與釕所組成族群之一金屬。於本實施例中，閘電極層214包括了介於30-60奈米之一厚度。閘電極層214可採用任一適當製程所形成，例如為原子層沉積、化學氣相沉積、物理氣相沉積、電鍍或其組合。
接著，藉由如旋轉塗佈一適當製程於閘電極層214上形成一層光阻(未顯示)，並藉由一適當微影圖案方法以圖案化之而形成一圖案化之之光阻構件。於至少一實施例中，圖案 化之光阻構件之寬度係介於5-45奈米之間。可接著藉由一乾蝕刻製程轉移圖案化之光阻構件的圖案至下方膜層(即閘電極層214與閘介電層212)內以形成閘極堆疊物210。接著移除光阻。
請繼續參照第2圖，半導體裝置200更包括形成於閘極堆疊物210與基板20上且覆蓋閘堆疊物210的側壁之一介電層。此介電層可包括氧化矽、氮化矽或氮氧化矽。此介電層包括一單一膜層或多重膜層結構。此介電層可由原子層沉積、化學氣相沉積、物理氣相沉積或其他適當技術所形成。此介電層包括介於5-15奈米之厚度。接著，可於介電層上施行非等向性蝕刻，以形成位於閘極堆疊物210之兩側邊上之一對側壁間隔物216。
請參照第3圖以及第1圖內之步驟102，接著凹陷部分之鳍結構202(即閘極堆疊物210與側壁間隔物216形成於其上以外的部分)以形成鄰近於閘極堆疊物210且低於基板20之主表面20s之數個源極與汲極溝槽206(包括了206a與206b)。於圖示實施例中，此些源極與汲極溝槽206分別位於閘極堆疊物210與淺溝槽隔離區204之一之間。如此，此些源極與汲極溝槽206a係鄰近於閘極堆疊物210，而淺溝槽格離區204a係設置於源極與汲極溝槽206a之相對於閘極堆疊物210之一側上。如此，源極與汲極溝槽206b係鄰近於閘極堆疊物210，而淺溝槽隔離區204b係設置於源極與汲極溝槽206b相對於閘極堆疊物210之一側。
於圖示之實施例中，係採用閘極堆疊物210及間隔物216之側壁作為硬罩幕，並施行一偏壓蝕刻製程以凹陷未為 保護的或露出的基板20之主表面20s，以形成此些源極與汲極溝槽206。於一實施例中，此蝕刻製程可於介於約1-1000mTorr之一壓力、介於約50-1000瓦特之一功率、介於約20-500伏特之一偏壓、介於約40-60℃之一溫度等參數下採用溴化氫及或氯氣作為蝕刻氣體而施行。此外，於圖示實施例中，可調整於蝕刻製程中所使用之偏壓，以使得蝕刻反應已達到源極與汲極溝槽206之期望輪廓的較佳控制。
如第4圖及第1圖內步驟104所示，於形成位於基板20之主表面20s下方之源極與汲極溝槽206後，如第4圖內所示結構可藉由磊晶成長一應變材料208於此些源極汲極溝槽206內所形成，其中應變材料208之晶格常數不同於基板20之晶格常數。因此，半導體裝置200之通道區係經過應變或施加有應力，藉以增強裝置之載子遷移率(carrier mobility)。
於部分實施例中，應變材料208包括了矽、鍺、矽鍺、碳化矽、磷化矽、或III-V族半導體材料。於圖示實施例中，可施行一預先潔淨製程，藉由氫氟酸或其他適當溶液以潔淨源極與汲極溝槽206。接著，如矽鍺之應變材料208藉由一低壓化學氣相沉積製程而選擇性地成長以填滿源極與汲極溝槽206。於一實施例中，應變材料208之一上表面係低於主表面20s(未顯示)。於另一實施例中，填入於源極與汲極溝槽206的應變材料208向上延伸而高於主表面20s。於圖示實施例中，此低壓化學氣相沉積法係於介於400-800℃之一溫度與約1-15Torr之一壓力下施行，採用了SiH2 Cl2 、HCl、GeH4 、B2 H6 與H2 作為反應氣體。
製程至此，已形成了具有位於源極與汲極溝槽206內應變材料208之基板20。於部分應用中，位於應變材料208上之矽化物區可藉由坦覆地沉積如鎳、鈦、鈷、及其組合之一薄金屬材料層而形成。接著加熱基板20，以使得矽與連接之金屬進行反應。於此反應之後，於含矽材料與金屬之間形成了一層金屬矽化物。接著採用僅去除金屬但不會去除金屬矽化物之蝕刻劑以選擇性地移除未反應之金屬。然而，介於金屬矽化物與應變材料208之間的費米能階形成了固定之一蕭基壁壘高度(Schottky barrier height、SBH)。此固定之蕭基壁壘高度造成了半導體裝置之源極汲極區的高接觸電阻，並因此劣化了裝置表現。
如此，參照第5-12圖之下述製程可形成包括一導電介電層之一接觸結構，以取代金屬矽化物區。此導電介電層可作為替代高電阻值金屬矽化物之一低電阻值中間層。如此，接觸結構可使得半導體裝置之源極汲極區具有低接觸電阻值，進而增進了裝置表現。
如第5、6圖以及第1圖內步驟106所示情形，為了製造半導體裝置200之一接觸結構(例如如第12圖內所示之一接觸結構234)，如第5圖所示之結構的製作可藉由形成一層間介電層218於應變材料208、閘極堆疊物210、此對側壁間隔物216以及隔離區204之上而形成。
層間介電層208包括一介電材料。此介電材料可包括氧化矽、氮化矽、氮氧化矽、磷矽玻璃、硼磷矽玻璃、旋轉塗佈玻璃、氟摻雜矽玻璃(FSG)、碳摻雜氧化矽(SiCOH)及/或 其組合。於部分實施例中，層間介電層218可藉由化學氣相沉積、高密度電漿加強型化學氣相沉積、次大氣壓化學氣相沉積、旋轉塗佈、濺鍍、或其他適當方法而形成於應變材料208上。於本實施例中，層間介電層218具有介於約4000-8000埃之一厚度。可以理解的是，層間介電層218可包括一或多個介電材料及/或一或多個介電層。
接著，採用一化學機械研磨(CMP)製程以平坦化層間介電層218直至露出或抵達了閘電極層214的頂面(顯示於第6圖中)。此化學機械研磨製程具有一高度選擇比，以形成閘電極層214與層間介電層218的一大體平坦表面。
接著針對第6圖之半導體裝置200施行一互補型金氧半導體(CMOS)製程，其包括了形成穿過層間介電層218之接觸開口，以提供至半導體裝置200之源極/汲極區之電性接觸情形。請參照第7圖，如第7圖內所示結構的形成可藉由於層間介電層218內形成一開口220，以露出應變材料208之一部(如第1圖內之步驟108)。於一範例中，開口220的形成包括了藉由如旋轉塗佈之一適當製程形成一層光阻(未顯示)於層間介電層218上、藉由一適當微影方法圖案化此光阻層以形成一圖案化光阻構件、蝕刻層間介電層218(例如採用一乾蝕刻、一濕蝕刻、及/或電漿蝕刻製程)以移除層間介電層218之數個部分並露出應變材料208之一部。因此，開口220係位於應變材料208上，其中開口220包括了數個介電側壁220a以及一應變材料底部220b。接著移除圖案化光阻層。
請參照第8圖以及第1圖內步驟110，於形成開口 220於層間介電層218內之後，第8圖內結構可藉由形成一半導體氧化物層222位於開口220之內並使之延伸於層間介電層218與閘極堆疊物210之上所形成。於部分實施例中，半導體氧化物層222可包括氧化矽或氧化鍺，且可藉由如化學氣相沉積、原子層沉積或濺鍍之一方法所形成。於部分實施例中，半導體氧化物層222具有介於約0.6-3奈米之第一厚度t1 。
請參照第9圖以及第1圖內之步驟112，於形成半導體氧化物層222於開口220之內後，如第9圖所示結構可藉由形成一第一金屬層224於半導體氧化物層222上而形成。於部分實施例中，第一金屬層224可包括鈦、鋁、鋯、鉿、鉭、銦、鈹、鎂、鈣、釔、鋇、鍶、鈧、或鎵，且可採用如化學氣相沉積、原子層沉積或濺鍍之一方法所形成。於部分實施例中。第一金屬層224具有介於約0.5-4奈米之第二厚度t2 。
請參照第10圖以及第1圖內之步驟114，於形成第一金屬層224於半導體氧化物層222上之後，如第10圖結構接著藉由加熱基板20以形成一半導體層226以及一介電層228於半導體層226上而形成。於部分實施例中，半導體層226包括矽或鍺。於部分實施例中，半導體層226具有介於約0.3-1.5奈米之第三厚度t3。於部分實施例中，部分填入於開口220內之介電層228具有一開口230。於部分實施例中，介電層228具有介於約1-10奈米之第四厚度t4 ，進而使得介電層228為導電的。本發明之接示情形並非限於一特定操作理論，可以理解的是於本發明之厚度範圍下，由於穿隧電流(tunneling current)因素，因此介電層228為一導電介電層。如此，於下文中介電層228亦可稱 為一導電介電層228。於至少一實施例中，導電介電層228包括氧化鈦或二氧化鈦。於另一實施例中，導電介電層228包括氧化鋁。於又一實施例中，導電介電層228係擇自由鋯、鉿、鉭、銦、鎳、鈹、鎂、鈣、釔、鋇、鍶、鈧、鎵及其混合物所組成族群之一氧化物。於圖示之實施例中，導電介電層228可包括降低固定蕭基阻障高度(SBH)且作為取代高電阻值之金屬矽化物之一低電阻值中間層，進而改善裝置表現。
於熱動力學觀點中，半導體層226較第一金屬層224於含氧環境中為穩定的。如此，第一金屬層224可將與之接觸的半導體氧化物層222轉變成為半導體層226，而第一金屬層224則被氧化而形成了位於半導體層226上之導電介電層228。於圖示實施例中，半導體層226係位於開口220的側壁220a及底部220b上。於部分實施例中，加熱基板20的步驟的施行係藉由暴露基板20於介於200-800℃之溫度之一鈍氣中。於部分實施例中，此鈍氣包括了氮氣、氦氣或氬氣。
請參照第11、12圖以及第1圖內之步驟116，於形成導電介電層228之後，如第11圖所示結構可藉由形成一第二金屬層232於介電層228之開口230內所形成。於圖示之實施例中，第二金屬層232係沉積於導電介電層228上以填滿導電介電層228之開口230。於部分實施例中，第二金屬層232包括鉭、鈦、鉿、鋯、鎳、鎢、鈷、銅或鋁。於部分實施例中，第二金屬層232可藉由化學氣相沉積、物理氣相沉積、電鍍、原子層沉積或其他適當技術所形成。於部分實施例中，第二金屬層232可包括層疊膜層。此層疊膜層可更包括一阻障金屬層(barrier metal layer)、一襯金屬層(liner metal layer)或一濕金屬層(wet metal layer)。再者，第二金屬層232之厚度則可依照開口230之深度而定。因此第二金屬層232可沉積直至大體填滿或過度填滿開口230為止。
接著，施行另一化學機械研磨以平坦化滿出於開口230之第二金屬層232(第12圖)。因此化學機械研磨移除了第二金屬層232之超過開口230之一部，抵達層間介電層218時此化學機械研磨便可停止，因此而形成了一大體平坦表面。
於部分實施例中，關於如第12圖所示範例中，用於半導體裝置200之接觸結構234包括了具有主表面20s與位於主表面20s下之溝槽206之基板20、填滿溝槽206之應變材料208，其中應變材料208之晶格常數不同於基板20之晶格常數、具有位於應變材料208上開口220之層間介電層218，其中開口220包括了介電側壁220a及應變材料底部220b、位於開口220之側壁220a與底部220b上之半導體層226、位於半導體層226上之介電層228、以及填滿介電層228之開口230之金屬層232。
於圖示之實施例中，閘極堆疊物210係採用一閘極優先(gate first)製程所形成。於另一實施例中，閘極堆疊物210可採用閘極最後(gate last)製程所形成，其藉由先形成一假閘極堆疊物。於部分實施例中，閘極最後製程形成了環繞假閘極堆疊物之一層間介電層、移除假閘電極層以於層間介電層內形成一溝槽，接著採用一導電閘電極層填入溝槽。於部分實施例中，閘極最後製程包括環繞形成假閘極堆疊物之一層間介電層、移除假閘電極層以及假閘介電層，以於層間介電層內形成 一溝槽，接著採用一閘介電層與一導電閘電極層填滿開口。
於如第1圖所示之步驟後以及參照如第2-12圖所示範例的施行，可更施行包括了內連製程之後續程序以完成半導體裝置200的製作。可以觀察到的是接觸結構234包括一導電介電層228，其可提供用於內部連結之一低電阻值率路徑，因此提升了裝置表現。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧製造方法
102、104、106、108、110、112、114、116‧‧‧步驟

Claims (10)

  1. 一種半導體裝置之接觸結構，包括：一基板，包括一主表面以及位於該主表面下方之一溝槽；一應變材料，填滿該溝槽，其中該應變材料之晶格常數不同於該基板之晶格常數；一層間介電層，具有位於該應變材料上之一開口，其中該開口包括了數個介電側壁以及一應變材料底部；一半導體層，位於該開口之該些介電側壁與該應變材料底部上；一介電層，位於該半導體層上；以及一金屬層，填滿該介電層之一開口。
  2. 如申請專利範圍第1項所述之半導體裝置之接觸結構，其中該應變材料包括了矽、鍺、矽鍺、碳化矽、磷化矽或III-V族半導體材料。
  3. 如申請專利範圍第1項所述之半導體裝置之接觸結構，其中該半導體層包括矽或鍺。
  4. 如申請專利範圍第1項所述之半導體裝置之接觸結構，其中該介電層包括氧化鈦、二氧化鈦、氧化鋁或為擇自由鋯、鉿、鉭、銦、鎳、鈹、鎂、鈣、釔、鋇、鍶、鈧、鎵及其混合物所組成族群之一氧化物。
  5. 一種金氧半導體場效電晶體，包括：一基板，包括一主表面；一閘極堆疊物，位於該基板之該主表面上；一溝槽，位於鄰近該閘極堆疊物之該主表面之下； 一淺溝槽隔離物，設置於該溝槽相對於該閘極堆疊物之一側上，其中淺溝槽隔離區係位於該基板內；以及一接觸結構，包括：一應變材料，填滿該溝槽，其中該應變材料之晶格常數不同於該基板之晶格常數；一層間介電層，具有位於該應變材料上之一開口，其中該開口包括了數個介電側壁以及一應變材料底部；一半導體層，位於該開口之該些介電側壁與該應變材料底部上，其中該半導體層具有介於0.3-1.5奈米之厚度；一介電層，位於該半導體層上，其中該介電層具有介於1-10奈米之厚度；以及一金屬層，填滿該介電層之一開口。
  6. 如申請專利範圍第5項所述之金氧半導體場效電晶體，其中該應變材料包括了矽、鍺、矽鍺、碳化矽、磷化矽或III-V族半導體材料。
  7. 如申請專利範圍第5項所述之金氧半導體場效電晶體，其中該半導體層包括矽或鍺。
  8. 如申請專利範圍第5項所述之金氧半導體場效電晶體，其中該介電層包括氧化鈦、二氧化鈦、氧化鋁或為擇自由鋯、鉿、鉭、銦、鎳、鈹、鎂、鈣、釔、鋇、鍶、鈧、鎵及其混合物所組成族群之一氧化物。
  9. 如申請專利範圍第5項所述之金氧半導體場效電晶體，其中該金屬層包括了鉭、鈦、鉿、鋯、鎳、鎢、鈷、銅或鋁。
  10. 一種半導體裝置之製造方法，包括： 提供包括一主表面以及位於該主表面之下之一溝槽之一基板；磊晶成長一應變材料於該溝槽內，其中該應變材料之晶格常數不同於該基板之晶格常數；形成一層間介電層於該應變材料上；形成一開口於該層間介電層內，以露出該應變材料之一部；形成一半導體氧化物層於該開口之內部並延伸至該層間介電層之上；形成一第一金屬層於該半導體氧化物層；加熱該基板，以形成一半導體層與一介電層於該半導體氧化物層上；以及形成一第二金屬層於該介電層之一開口內。
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