CN103811550A - 半导体器件的接触结构 - Google Patents

半导体器件的接触结构 Download PDF

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CN103811550A
CN103811550A CN201310034600.5A CN201310034600A CN103811550A CN 103811550 A CN103811550 A CN 103811550A CN 201310034600 A CN201310034600 A CN 201310034600A CN 103811550 A CN103811550 A CN 103811550A
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layer
strain gauge
opening
substrate
gauge material
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CN103811550B (zh
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王菘豊
时定康
林经祥
孙诗平
万幸仁
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明涉及半导体器件的接触结构。一种用于半导体器件的接触结构的示例性结构包括：衬底，包括主面和主面下方的沟槽；填充沟槽的应变材料，应变材料的晶格常数不同于衬底的晶格常数；层间介电层(ILD)，具有位于应变材料上方的开口，开口包括介电侧壁和应变材料底部；半导体层，位于开口的侧壁和底部上；介电层，位于半导体层上方；以及填充介电层开口的金属层。

Description

半导体器件的接触结构
技术领域
本发明涉及集成电路制造，更具体地，涉及具有接触结构的半导体器件。
背景技术
随着半导体工艺追求更高的器件密度、更好的性能以及更低的成本而发展成纳米级技术工艺节点，来自制造和设计问题的挑战促进了诸如鳍式场效应晶体管(FinFET)的半导体器件的三维设计的发展。典型的FinFET制造有从衬底延伸的薄垂直“鳍”(或鳍结构)，例如通过蚀刻掉衬底的硅层的一部分而形成鳍。FinFET的沟道形成在该垂直鳍中。在鳍的三个侧面上方设置栅极(例如环绕栅极)。沟道两侧上的栅极使得栅极从两侧控制沟道。进一步地，FinFET的优点包括减小短沟道效应和具有更大的电流。
然而，在互补金属氧化物半导体(CMOS)制造中实施这种部件和工艺具有挑战性。例如，应变材料上形成的硅化物会造成FinFET的源极/漏极区的高接触阻抗，从而降低了器件性能。
发明内容
根据本发明的一个方面，提供了一种用于半导体器件的接触结构，包括：衬底，包括主面和位于主面下方的沟槽；应变材料，填充沟槽，应变材料的晶格常数不同于衬底的晶格常数；层间介电层(ILD)，具有位于应变材料上方的开口，开口包括介电侧壁和应变材料底部；半导体层，位于开口的侧壁和底部上；介电层，位于半导体层上方；以及金属层，填充介电层的开口。
优选地，半导体层的厚度范围在0.3nm至1.5nm之间。
优选地，介电层的厚度范围在1nm至10nm之间。
优选地，应变材料包括Si、Ge、SiGe、SiC、SiP或III-V族半导体材料。
优选地，半导体层包括Si或Ge。
优选地，介电层包括TiO或TiO2。
优选地，介电层包括Al2O3。
优选地，介电层选自包括Zr、Hf、Ta、In、Ni、Be、Mg、Ca、Y、Ba、Sr、Sc、Ga和它们的混合物的组的氧化物。
优选地，金属层包括Ta、Ti、Hf、Zr、Ni、W、Co、Cu或Al。
根据本发明的另一方面，提供了一种金属氧化物半导体场效应晶体管(MOSFET)，包括：衬底，包括主面；栅极堆叠件，位于衬底的主面上；沟槽，与栅极堆叠件相邻位于主面下方；浅沟槽隔离(STI)区，设置在沟槽与栅极堆叠件相对的一侧，STI区位于衬底内；以及接触结构。接触结构包括：应变材料，填充沟槽，应变材料的晶格常数不同于衬底的晶格常数；层间介电(ILD)层，具有位于应变材料上方的开口，开口包括介电侧壁和应变材料底部；半导体层，位于开口的侧壁和底部上，半导体层的厚度范围在0.3nm至1.5nm之间；介电层，位于半导体层上方，介电层的厚度范围在1nm至10nm之间；和金属层，填充介电层的开口。
优选地，应变材料包括Si、Ge、SiGe、SiC、SiP或III-V族半导体材料。
优选地，半导体层包括Si或Ge。
优选地，介电层包括TiO或TiO2。
优选地，介电层包括Al2O3。
优选地，介电层选自包括Zr、Hf、Ta、In、Ni、Be、Mg、Ca、Y、Ba、Sr、Sc、Ga和它们的混合物的组的氧化物。
优选地，金属层包括Ta、Ti、Hf、Zr、Ni、W、Co、Cu或Al。
根据本发明的又一方面，提供了一种制造半导体器件的方法，包括：提供包括主面和主面下方的沟槽的衬底；在沟槽中外延生长应变材料，应变材料的晶格常数不同于衬底的晶格常数；在应变材料上方形成层间介电(ILD)层；在ILD层中形成开口以露出应变材料的一部分；使半导体氧化物层形成在开口内并在ILD层上方延伸；在半导体氧化物层的上方形成第一金属层；加热衬底以形成半导体层和半导体层上方的介电层；以及在介电层的开口中形成第二金属层。
优选地，通过将衬底暴露于惰性气体来执行加热衬底以形成半导体层和半导体层上方的介电层的步骤。
优选地，惰性气体包括N2、He或Ar。
优选地，在约200℃至约800℃的温度条件下，执行将衬底暴露于惰性气体的步骤。
附图说明
当参照附图阅读时根据以下详细描述更好地理解本发明。需要强调的是，根据工业标准惯例，各种部件没有按照比例绘制，而是仅仅用于说明的目的。事实上，为了清楚地讨论，可以任意增大或减小各个部件的尺寸。
图1是示出根据本发明各个方面的制造半导体器件的接触结构的方法的流程图；以及
图2至图12是根据本发明各个方面的包括接触结构的半导体器件处于各个制造阶段的示意性截面图。
具体实施方式
应该理解，以下发明提供了用于实施本发明的不同特征的许多不同的实施例或实例。以下描述部件和配置的具体实例以简化本发明。当然，这些仅是实例而不用于限制。例如，在下面描述中，第一部件形成在第二部件上方或第二部件上包括第一部件和第二部件形成为直接接触的实施例，并且还可包括附加部件可形成在第一部件和第二部件之间使得第一部件和第二部件可不直接接触的实施例。此外，本发明可在各个实例中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，但其自身并不表明各个实施例之间和/或所讨论配置之间的关系。
参照图1，示出了根据本发明各个方面的制造半导体器件的接触结构的方法100的流程图。方法100以步骤102开始，其中提供包括主面和位于主面下方的沟槽的衬底。方法100继续到步骤104，其中在沟槽中外延生长应变材料，应变材料的晶格常数不同于衬底的晶格常数。方法100继续到步骤106，其中在应变材料上方形成层间介电(ILD)层。方法100继续到步骤108，其中在层间介电层中形成开口以露出应变材料的一部分。方法100继续到步骤110，其中半导体氧化物层形成在开口内并延伸到ILD层上方。方法100继续到步骤112，其中在半导体氧化物层上方形成第一金属层。方法100继续步骤114，其中衬底被加热以形成半导体层和位于半导体层上方的介电层。方法100继续到步骤116，其中第二金属层形成在介电层的开口中。以下讨论根据图1的方法100制造的半导体器件的实施例。
图2至图12是根据本发明各个方面的包括接触结构234的半导体器件200处于各个制造阶段的示意性截面图。如本发明所使用的，术语半导体器件200是指鳍场效应晶体管(FinFET)。FinFET是指任何基于鳍的多栅极晶体管。在一些可选实施例中，术语半导体器件200是指平面金属氧化物半导体场效应晶体管(MOSFET)。其他晶体管结构和类似结构也在本发明预期的范围内。半导体器件200可被包括在微处理器、存储单元和/或其他集成电路(IC)中。
应该注意，在一些实施例中，图1中提到的操作不能产生完整的半导体器件200。可使用互补金属氧化物半导体(CMOS)技术工艺制造完整的半导体器件200。因此，应该理解，可在图1的方法100之前、期间和/或之后提供其他工艺，并且本文可只简要描述一些其他工艺。而且，为了更好地理解本发明的概念，对图2至图12进行了简化。例如，尽管附图示出了半导体器件200，但是应该理解，IC可包括许多其他器件，包括电阻器、电容器、电感器、熔丝等。
参照图2和图1中的步骤102，提供了包括主面20s的衬底20。在至少一个实施例中，衬底20包括晶体硅衬底(例如，晶圆)。根据设计要求，衬底20可包括各种掺杂区(例如，p型衬底或n型衬底)。在一些实施例中，掺杂区可掺有p型或n型掺杂物。例如，掺杂区可掺有p型掺杂物，诸如硼或BF2；n型掺杂物，诸如磷或砷；和/或它们的组合。掺杂区可配置用于n型FinFET或平面MOSFET，或者可选地配置用于p型FinFET或平面MOSFET。
衬底20可以可选地由一些其他适合的元素半导体制成，诸如金刚石或锗；由适合的化合物半导体制成，诸如砷化镓、碳化硅、砷化铟或磷化铟；或由适合的合金半导体制成，诸如碳化硅锗、磷化镓砷或磷化镓铟。另外，衬底20可包括取向附生层(外延层)，可以为了提高性能而被应变，和/或可以包括绝缘体上硅(SOI)结构。
在所示实施例中，衬底20进一步包括鳍结构202。形成在衬底20上的鳍结构202包括一个或多个鳍。在本实施例中，为了简化，鳍结构202包括单个鳍。鳍包括任何适合的材料，例如，鳍可包括硅、锗或化合物半导体。鳍结构202可进一步包括设置在鳍上的覆盖层(未示出)，其可以是硅覆盖层。
使用包括各种沉积工艺、光刻工艺和/或蚀刻工艺的任何适合的工艺来形成鳍结构202。示例性的光刻工艺可包括：形成覆盖衬底20(例如在硅层上)的光刻胶层(抗蚀剂)、曝光光刻胶形成图案、执行曝光后烘烤工艺以及显影光刻胶来形成包括光刻胶的掩膜元件。然后，可使用反应离子蚀刻(RIE)工艺和/或其他适合的工艺来蚀刻硅层。在一个实例中，可图案化并蚀刻硅衬底20的一部分来形成鳍结构202的硅鳍。在另一实例中，可以图案化并蚀刻覆盖绝缘层沉积的硅层(例如，SOI衬底的硅-绝缘体-硅堆叠的上部硅层)来形成鳍结构202的硅鳍。在又一些其他实施例中，通过在衬底上方形成介电层，在介电层中形成开口沟槽并且在沟槽中从衬底外延生长鳍来形成鳍结构。
在所示实施例中，隔离区形成在衬底20内以限定并电隔离鳍结构202中的各个鳍。在一个实例中，隔离区包括浅沟槽隔离(STI)区204(包括204a和204b)。隔离区可包括氧化硅、氮化硅、氮氧化硅、掺氟硅酸盐玻璃(FSG)、低K介电材料和/或它们的组合。可通过任何适合的工艺来形成隔离区(在本实施例中为STI区204)。作为一个实例，STI区204的形成可包括利用介电材料填充鳍之间的沟槽(例如，使用化学汽相沉积工艺)。在一些实施例中，填充的沟槽可具有多层结构，诸如利用氮化硅或氧化硅填充的热氧化物衬垫层。
仍参照图2，栅极堆叠件210形成在STI区204之间的衬底20的主面20s(即，鳍结构202的顶面)上。虽然在附图所示的平面中栅极堆叠件210只在鳍的顶面上延伸，但本领域技术人员应理解在器件的另一平面中(图中未示出)，栅极堆叠件210沿鳍结构202的侧壁延伸。在一些实施例中，栅极堆叠件210包括栅极介电层212和栅极介电层212上方的栅电极层214。在一些实施例中，一对侧壁间隔件216形成在栅极堆叠件210的两侧。在所示实施例中，可利用包括本文所述工艺的任何适合的工艺来形成栅极堆叠件210。
在一个实例中，栅极介电层212和栅电极层214顺序沉积在衬底20上方。在一些实施例中，栅极介电层212可包括氧化硅、氮化硅、氮氧化硅或高介电常数(高k)电介质。高k电介质包括金属氧化物。用于高k电介质的金属氧化物的实例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu和它们的混合物的氧化物。在本实施例中，栅极介电层212是厚度范围在约到约
Figure BDA00002791603800062
之间的高k介电层。可利用诸如原子层沉积(ALD)、化学汽相沉积(CVD)、物理汽相沉积(PVD)、热氧化、UV臭氧氧化或它们的组合的合适工艺来形成栅极介电层212。栅极介电层212可进一步包括界面层(未示出)以减小栅极介电层212和鳍结构202之间的损伤。界面层可包括氧化硅。
在一些实施例中，栅电极层214可包括单层或多层结构。在至少一个实施例中，栅电极层214包括多晶硅。另外，栅电极层214可以以均匀掺杂或非均匀掺杂方式掺杂多晶硅。在可选实施例中，栅电极层214包括从W、Cu、Ti、Ag、Al、TiAl、TiAlN、TaC、TaCN、TaSiN、Mn和Zr的组中选择的金属。在可选实施例中，栅电极层214包括从TiN、WN、TaN和Ru的组中选择的金属。在本实施例中，栅电极层214包括范围在约30nm至60nm之间的厚度。可使用诸如ALD、CVD、PVD、电镀或它们的组合的合适工艺来栅极电极层214。
然后，可通过诸如旋涂的适合工艺在栅电极层214上方形成光刻胶层(未示出)，并且通过适当的光刻图案化方法来图案化光刻胶层以形成图案化的光刻胶部件。在至少一个实施例中，图案化的光刻胶部件的宽度在约5nm至约45nm之间的范围内。然后，可使用干蚀刻工艺将图案化的光刻胶部件转印到下面的层(即，栅电极层214和栅极介电层212)以形成栅极堆叠件210。此后可以剥离光刻胶层。
仍参照图2，半导体器件200进一步包括形成在栅极堆叠件210和衬底20上方并且覆盖栅极堆叠件210侧壁的介电层。介电层可包括氧化硅、氮化硅或氮氧化硅。介电层可包括单层或多层结构。可通过CVD、PVD、ALD或其他适合的技术来形成介电层。介电层包括范围在约5nm至约15nm之间的厚度。然后，对介电层执行各向异性蚀刻以在栅极堆叠件210两侧形成一对侧壁间隔件216。
参照图3和图1中的步骤102，使鳍结构202的一部分(除其上形成栅极堆叠件210和一对侧壁间隔件216的部分)凹进，以形成与栅极堆叠件210相邻位于衬底20的主面20s下方的源极和漏极(S/D)沟槽206(包括206a和206b)。在所示实施例中，每个S/D沟槽206都位于栅极堆叠件210和一个STI区204之间。这样，S/D沟槽206a与栅极堆叠件210相邻，同时STI区204a设置在S/D沟槽206a中与栅极堆叠件210相对的一侧。这样，S/D沟槽206b与栅极堆叠件210相邻，同时STI区204b设置在S/D沟槽206b中与栅极堆叠件210相对的一侧。
在所示实施例中，将栅极堆叠件210和一对侧壁间隔件216用作硬掩膜，执行偏置蚀刻工艺，以使衬底20未受保护或露出的主面20s凹进来形成S/D沟槽206。在一个实施例中，可在压力在约1mTorr至约1000mTorr之间、功率在约50W至约1000W之间、偏压在约20V至约500V之间、温度在约40℃至约60℃之间的条件下，将HBr和/或Cl2用作蚀刻气体来执行蚀刻工艺。而且，在所提供的实施例中，可调整用于蚀刻工艺的偏压，以便更好地控制蚀刻方向来得到S/D沟槽206的期望轮廓。
如图4和图1中的步骤104所示，在衬底20主面20s下方形成S/D沟槽206之后，通过在S/D沟槽206中外延生长应变材料208来制造图4中的结构，其中应变材料208的晶格常数不同于衬底20的晶格常数。因此，半导体器件200的沟道区发生应变或产生应力，以提高器件的载流子迁移率。
在一些实施例中，应变材料208包括Si、Ge、SiGe、SiC、SiP或III-V族半导体材料。在所示实施例中，可执行预清洗工艺来利用HF或其他适合的溶剂清洗S/D沟槽206。然后，通过低压CVD(LPCVD)工艺选择性生长诸如硅锗(SiGe)的应变材料208来填充S/D沟槽206。在一个实施例中，应变材料208的上表面低于主面20s(未示出)。在另一个实施例中，填充S/D沟槽206的应变材料208向上延伸至主面20s上方。在所示实施例中，在温度为约400℃至约800℃、压力在约1Torr至约15Torr之间的条件下，将SiH2Cl2、HCl、GeH4、B2H6和H2用作反应气体来执行LPCVD工艺。
进行到此的工艺提供了在S/D沟槽206中具有应变材料208的衬底20。在一些应用中，可通过毯式沉积诸如镍、钛、钴和它们的组合的金属材料的薄层来形成位于应变材料208上方的硅化物区。然后加热衬底20，这使得硅与其接触的金属发生反应。反应之后，金属硅化物层形成在含硅材料和金属之间。通过使用攻击金属材料但不攻击硅化物的蚀刻剂来选择性去除未反应的金属。然而，金属硅化物和应变材料208之间的费米能级钉扎效应导致固定的肖特基势垒高度(SBH)。这个固定的SBH造成半导体器件S/D区的高接触阻抗，从而降低了器件的性能。
因此，以下参考图5至图12讨论的工艺可形成包括导电介电层以替代硅化物区的接触结构。导电介电层可用作低阻抗中间层来替代高阻抗金属硅化物。这样，接触结构可提供半导体器件S/D区的低接触阻抗，从而提高器件的性能。
如图5和图6以及图1中的步骤106所示，为了制造半导体器件200的接触结构(诸如图12所示的接触结构234)，通过在应变材料208、栅极堆叠件210、一对侧壁间隔件216和隔离区204上方形成层间介电(ILD)层218来制造图5中的结构。
ILD层218包括介电材料。介电材料可包括氧化硅、氮化硅、氮氧化硅、磷硅酸玻璃(PSG)、硼磷硅玻璃(BPSG)、旋涂玻璃(SOG)、氟化硅玻璃(FSG)、掺碳氧化硅(例如，SiCOH)和/或它们的组合。在一些实施例中，可通过CVD、高密度等离子体(HDP)CVD、次常压CVD(SACVD)、旋涂、溅射或其他合适的方法在应变材料208上方形成ILD层218。在本实施例中，ILD层218的厚度范围在约
Figure BDA00002791603800091
至约
Figure BDA00002791603800092
之间。应该理解，ILD层218可包括一种或多种介电材料和/或一个或多个介电层。
随后，使用CMP工艺对ILD层218进行平坦化直至露出或到达栅电极层214的顶面(如图6所示)。CMP工艺具有高选择性来为栅电极层214和ILD层218提供基本平坦的表面。
向图6的半导体器件200应用随后的CMOS工艺步骤，包括形成穿过ILD层218的接触开口来提供与半导体器件200的S/D区的电接触。参照图7，通过在ILD层218中形成开口220露出应变材料208的一部分(图1中的步骤108)来形成图7中的结构。作为一个实例，开口220的形成包括：通过诸如旋涂的适合工艺在ILD层218上方形成光刻胶层(未示出)、通过适当的光刻方法图案化光刻胶层以形成图案化的光刻胶部件、蚀刻露出的ILD层218(例如，通过使用干蚀刻、湿蚀刻和/或等离子体蚀刻工艺)以移除部分ILD层218，来露出应变材料208的一部分。这样，开口220位于应变材料208的上方，其中开口220包括介电侧壁220a和应变材料底部220b。此后，可将图案化的光刻胶层剥离。
参照图8和图1中的步骤110，在ILD层中形成开口220之后，通过使半导体氧化物层222形成在开口220内并在ILD层218和栅极堆叠件210上方延伸来制造图8中的结构。在一些实施例中，半导体氧化物层222可包括氧化硅或氧化锗，并且可使用诸如CVD、ALD或溅射的方法来形成。在一些实施例中，半导体氧化物层222具有范围在约0.6nm至约3nm之间第一厚度t1。
参照图9和图1中的步骤112，在开口220内形成半导体氧化物层222之后，通过在半导体氧化物层222上方形成第一金属层224来制造图9中的结构。在一些实施例中，第一金属层224可包括Ti、Al、Zr、Hf、Ta、In、Ni、Be、Mg、Ca、Y、Ba、Sr、Sc或Ga，并且可使用诸如CVD、ALD或溅射的方法来形成。在一些实施例中，第一金属层224具有范围在约0.5nm至约4nm之间的第二厚度t2。
参照图10和图1中的步骤114，在半导体氧化物层222上方形成第一金属层224之后，通过加热衬底20形成半导体层226和半导体层226上方的介电层228来制造图10的结构。在一些实施例中，半导体层226包括Si或Ge。在一些实施例中，半导体层226具有范围在0.3nm至1.5nm之间的第三厚度t3。在一些实施例中，部分填充开口220的介电层228具有开口230。在一些实施例中，介电层228具有范围在1nm至10nm之间的第四厚度t4，使得介电层228导电。虽然本发明不受具体操作理论的限制，但是应该相信，在所公开的厚度范围条件下，由于存在隧穿电流，所以介电层228是导电介电层。这样，介电层228在下文被称为导电介电层228。在至少一个实施例中，导电介电层228包括TiO或TiO2。在可选实施例中，导电介电层228包括Al2O3。在可选实施例中，导电介电层228选自包含Zr、Hf、Ta、In、Ni、Be、Mg、Ca、Y、Ba、Sr、Sc、Ga和它们的混合物的组的氧化物。在所示实施例中，导电介电层228可减小固定SBH并用作低阻抗中间层来替代高阻抗金属硅化物，从而提高器件的性能。
从热力学的角度来讲，在有氧环境中，半导体层226比第一金属层224更稳定。这样，第一金属层224可将与其接触的半导体氧化物层222转换形成半导体层226，同时第一金属层224被氧化形成位于半导体层226上方的导电介电层228。在所示实施例中，半导体层226位于开口220的侧壁220a和底部220b上。在一些实施例中，在约200℃至约800℃的温度下，通过将衬底20暴露于惰性气体来执行加热衬底20的步骤。
参照图11和图12以及图1中的步骤116，在形成导电介电层228之后，通过在介电层228的开口230中形成第二金属层232来制造图11中的结构。在所示实施例中，第二金属层232沉积在导电介电层228上方以填充导电介电层228中的开口230。在一些实施例中，第二金属层232包括Ta、Ti、Hf、Zr、Ni、W、Co、Cu或Al。在一些实施例中，可通过CVD、PVD、电镀、ALD或其他适合的技术来形成第二金属层232。在一些实施例中，第二金属层232可包括层压结构。层压结构可进一步包括势垒金属层、衬垫金属层或润湿金属层。另外，第二金属层232的厚度取决于开口230的深度。第二金属层232因此被沉积直至基本填充或过填充开口230。
然后，在填充开口230之后，执行CMP工艺以对第二金属层232进行平坦化(图12所示)。由于CMP移除了开口230外的部分金属层232，所以CMP工艺可在到达ILD层218时停止，因此提供了基本平坦的表面。
在一些实施例中，参照图12所示的实例，用于半导体器件200的接触结构234包括：衬底20，包括主面20s和主面20s下方的沟槽206；填充沟槽206的应变材料208，应变材料208的晶格常数与衬底20的晶格常数不同；ILD层218，具有位于应变材料208上方的开口220，开口220包括介电侧壁220a和应变材料底部220b；半导体层226，位于开口220的侧壁220a和底部220b上；介电层228，位于半导体层226上方；以及填充介电层228的开口230的金属层232。
在所示实施例中，使用先栅极工艺制造栅极堆叠件210。在可选实施例中，可使用首先形成伪栅极堆叠件的后栅极工艺制造栅极堆叠件210。在一些实施例中，后栅极工艺包括：形成围绕伪栅极堆叠件的ILD层、移除伪栅电极层以在ILD层中形成沟槽、然后用导电栅电极层填充该沟槽。在一些实施例中，后栅极工艺包括：形成围绕伪栅极堆叠件的ILD层、移除伪栅电极层和伪栅极介电层以在ILD层中形成沟槽、然后用栅极介电层和导电栅电极层填充该沟槽。
在图1所示的步骤之后，如参照图2至图12所示实例进一步说明的，执行包括互连工艺的后续工艺来完成半导体器件200的制造。可以看出，包括导电介电层228的接触结构234可提供用于互连的低阻抗路径，因而提高了器件性能。
根据实施例，一种用于半导体器件的接触部件包括：衬底，包括主面和主面下方的沟槽；填充沟槽的应变材料，应变材料的晶格常数与衬底的晶格常数不同；层间介电层(ILD)，具有位于应变材料上方的开口，开口包括介电侧壁和应变材料底部；半导体层，位于开口的侧壁和底部上；介电层，位于半导体层上方；以及填充介电层的开口的金属层。
根据另一实施例，一种金属氧化物半导体场效应晶体管(MOSFET)包括：衬底，包括主面；栅极堆叠件，位于衬底的主面上；沟槽，与栅极堆叠件相邻并位于主面下方；浅沟槽隔离(STI)区，设置在沟槽与栅极堆叠件相对的一侧，其中STI区位于衬底内；以及接触结构。接触结构包括：填充沟槽的应变材料，应变材料的晶格常数不同于衬底的晶格常数；层间介电(ILD)层，具有位于应变材料上方的开口，开口包括介电侧壁和应变材料底部；半导体层，位于开口的侧壁和底部上，半导体层的厚度范围在0.3nm至1.5nm之间；介电层，位于半导体层上方，介电层的厚度在1nm至10nm之间的范围内；填充介电层的开口的金属层。
根据另一实施例，一种制造半导体器件的方法包括：提供包括主面和主面下方的沟槽的衬底；在沟槽中外延生长应变材料，应变材料的晶格常数不同于衬底的晶格常数；在应变材料上方形成层间介电(ILD)层；在ILD层中形成开口以露出应变材料的一部分；使半导体氧化物层形成在开口内并在ILD层上方延伸；在半导体氧化物层上方形成第一金属层；加热衬底以形成半导体层和半导体层上方的介电层；以及在介电层的开口中形成第二金属层。
虽然通过实例和有关优选实施例描述了本发明，但应该理解，本发明并不局限于公开的实施例。相反，其旨在覆盖各种修改和类似的配置(对本领域的技术人员是显而易见的)。因此，所附权利要求的范围应该被给予最广泛解释，以便能包括所有这种修改和类似的配置。

Claims (10)

1.一种用于半导体器件的接触结构，包括：
衬底，包括主面和位于所述主面下方的沟槽；
应变材料，填充所述沟槽，所述应变材料的晶格常数不同于所述衬底的晶格常数；
层间介电层(ILD)，具有位于所述应变材料上方的开口，所述开口包括介电侧壁和应变材料底部；
半导体层，位于所述开口的侧壁和底部上；
介电层，位于所述半导体层上方；以及
金属层，填充所述介电层的开口。
2.根据权利要求1所述的接触结构，其中，所述半导体层的厚度范围在0.3nm至1.5nm之间。
3.根据权利要求1所述的接触结构，其中，所述介电层的厚度范围在1nm至10nm之间。
4.根据权利要求1所述的接触结构，其中，所述应变材料包括Si、Ge、SiGe、SiC、SiP或III-V族半导体材料。
5.根据权利要求1所述的接触结构，其中，所述半导体层包括Si或Ge。
6.根据权利要求1所述的接触结构，其中，所述介电层包括TiO或TiO2。
7.根据权利要求1所述的接触结构，其中，所述介电层包括A12O3。
8.根据权利要求1所述的接触结构，其中，所述介电层选自包括Zr、Hf、Ta、In、Ni、Be、Mg、Ca、Y、Ba、Sr、Sc、Ga和它们的混合物的组的氧化物。
9.一种金属氧化物半导体场效应晶体管(MOSFET)，包括：
衬底，包括主面；
栅极堆叠件，位于所述衬底的主面上；
沟槽，与所述栅极堆叠件相邻位于所述主面下方；
浅沟槽隔离(STI)区，设置在所述沟槽与所述栅极堆叠件相对的一侧，所述STI区位于所述衬底内；以及
接触结构，包括：
应变材料，填充所述沟槽，所述应变材料的晶格常数不同于所述衬底的晶格常数；
层间介电(ILD)层，具有位于所述应变材料上方的开口，所述开口包括介电侧壁和应变材料底部；
半导体层，位于所述开口的侧壁和底部上，所述半导体层的厚度范围在0.3nm至1.5nm之间；
介电层，位于所述半导体层上方，所述介电层的厚度范围在1nm至10nm之间；和
金属层，填充所述介电层的开口。
10.一种制造半导体器件的方法，包括：
提供包括主面和所述主面下方的沟槽的衬底；
在所述沟槽中外延生长应变材料，所述应变材料的晶格常数不同于所述衬底的晶格常数；
在所述应变材料上方形成层间介电(ILD)层；
在所述ILD层中形成开口以露出所述应变材料的一部分；
使半导体氧化物层形成在所述开口内并在所述ILD层上方延伸；
在所述半导体氧化物层的上方形成第一金属层；
加热所述衬底以形成半导体层和所述半导体层上方的介电层；以及
在所述介电层的开口中形成第二金属层。
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US9099494B2 (en) 2015-08-04
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