CN110034070A - 具有嵌入式存储器件的结构、集成电路结构及其制造方法 - Google Patents
具有嵌入式存储器件的结构、集成电路结构及其制造方法 Download PDFInfo
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- CN110034070A CN110034070A CN201811447839.4A CN201811447839A CN110034070A CN 110034070 A CN110034070 A CN 110034070A CN 201811447839 A CN201811447839 A CN 201811447839A CN 110034070 A CN110034070 A CN 110034070A
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Classifications
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- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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Abstract
根据一些实施例,本发明提供了一种制造集成电路的方法。该方法包括在半导体衬底的鳍式有源区上形成源极和漏极;在源极和漏极上沉积层间介电(ILD)层;图案化ILD层以形成分别与源极和漏极对准的第一接触孔和第二接触孔;在第一接触孔中形成介电材料层;以及分别在第一接触孔和第二接触孔中形成第一导电部件和第二导电部件。本发明的实施例还提供了具有嵌入式存储器件的结构和集成电路结构。
Description
技术领域
本发明的实施例一般地涉及半导体技术领域,更具体地,涉及具有嵌入式存储器件的结构、集成电路结构及其制造方法。
背景技术
在集成电路中,可以使用包括光刻图案化、蚀刻、沉积和离子注入的各种制造技术在衬底上形成集成电路图案。由此形成的集成电路包括集成在一起的的各种器件,诸如场效应晶体管、二极管、双极结型晶体管、成像传感器、发光二极管、存储器单元、电阻器和电容器。存储器件可以包括与诸如场效应晶体管的其他器件连接的无源器件,诸如电容器或电阻器。在现有技术中,通过包括蚀刻的各种半导体技术形成诸如电阻器的无源器件。这些技术对无源器件的尺寸的控制有限且不准确,从而导致器件尺寸以及器件性能的较大变化。在一些情况下,器件参数可能在规范之外运行并导致电路失效。而且,由于较大的处理变化和小的部件尺寸,难以在先进的技术节点中实施现有的方法。特别地,当半导体技术进一步向着具有较小部件尺寸(诸如,7nm或更小)的先进技术节点发展时,未对准具有较小容许度并且可能造成泄漏、短路、开路或其他故障缺陷或可靠性问题。因此,本发明提供了一种结构和制造该结构的方法以解决上述问题。
发明内容
根据本发明的一方面,提供了一种制造集成电路的方法,包括:在半导体衬底的鳍式有源区上形成源极和漏极;在所述源极和所述漏极上沉积层间介电(ILD)层;图案化所述层间介电层以形成分别与所述源极和所述漏极对准的第一接触孔和第二接触孔;在所述第一接触孔中形成介电材料层;以及分别在所述第一接触孔和所述第二接触孔中形成第一导电部件和第二导电部件。
根据本发明的另一方面,提供了一种制造集成电路的方法,包括:在半导体衬底的鳍式有源区上形成金属栅极堆叠件;在鳍式有源区上形成源极和漏极;在所述金属栅极堆叠件上形成自对准的硅化物层;在所述源极和所述漏极上形成层间介电(ILD)层;图案化所述层间介电层以形成分别与所述源极和所述漏极对准的第一接触孔和第二接触孔;在所述第一接触孔中形成介电材料层;以及分别在所述第一接触孔和所述第二接触孔中形成第一导电部件和第二导电部件。
根据本发明的又一方面,提供了一种集成电路(IC)结构,包括:鳍式有源区,位于衬底上;金属栅极堆叠件,位于所述鳍式有源区上;源极和漏极,位于所述鳍式有源区上,其中,所述金属栅极堆叠件插入所述源极和所述漏极之间;层间介电(ILD)层,设置在所述源极和所述漏极上;第一导电部件和第二导电部件,形成在所述层间介电层中并且分别在所述源极和所述漏极上对准;以及介电材料层,围绕所述第一导电部件和所述第二导电部件,其中,所述介电材料层连续延伸至所述第一导电部件的底面并将所述第一导电部件与所述源极隔离;以及所述第二导电部件直接接触所述漏极。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1A是在一个实施例中根据本发明的各个方面构造的半导体器件结构的顶视图。
图1B和图1C分别是根据一些实施例的沿着虚线AA′和BB′的图1A的半导体结构的截面图。
图1D是根据一些实施例构造的图1B中的半导体器件结构的栅极堆叠件的截面图。
图2A是根据一些实施例的形成集成电路(IC)结构的方法的流程图。
图2B是根据一些实施例的图2A的方法中的操作的流程图。
图3A和图3B示出根据各个实施例的通过图2A的方法制造的示例性集成电路结构在制造阶段处的截面图。
图4、图5、图6、图7和图8示出根据一些实施例构造的通过图2A的方法制造的示例性集成电路结构在各个制造阶段期间的截面图。
图9A是在一个实施例中根据本发明的各个方面构造的半导体器件结构的顶视图。
图9B和图9C分别是根据一些实施例的沿着虚线AA′和BB′的图9A的半导体结构的截面图。
图10A和图10B是根据一些实施例的图2A的方法中的相应操作的流程图。
图11、图12、图13和图14示出根据一些实施例构造的示例性集成电路结构在各个制造阶段期间的截面图。
图15A是在一个实施例中根据本发明的各个方面构造的半导体器件结构的顶视图。
图15B和图15C分别是根据一些实施例的沿着虚线AA′和BB′的图15A的半导体结构的截面图。
图16A、图16B和图16C是根据各个实施例的图2A的方法中的操作的流程图。
图17、图18、图19、图20和图21示出根据一些实施例构造的示例性集成电路结构在各个制造阶段期间的截面图。
图22A是在一个实施例中根据本发明的各个方面构造的半导体器件结构的顶视图。
图22B和图22C分别是根据一些实施例的沿着虚线AA′和BB′的图22A的半导体结构的截面图。
图23是根据一些实施例的图2A的方法中的操作的流程图。
图24、图25、图26、图27、图28和图29示出根据一些实施例构造的示例性集成电路结构在各个制造阶段期间的截面图。
图30A是在一个实施例中根据本发明的各个方面构造的半导体器件结构的顶视图。
图30B和图30C分别是根据一些实施例的沿着虚线AA′和BB′的图30A的半导体结构的截面图。
图31是根据一些实施例的图2A的方法中的操作的流程图。
图32、图33、图34、图35、图36、图37和图38示出根据一些实施例构造的示例性集成电路结构在各个制造阶段期间的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。应当理解,以下公开内容提供了许多用于实现各个实施例的不同特征的不同实施例或实例。以下将描述组件和布置的具体实例以简化本发明。当然,这些仅仅是实例并不旨在限制本发明。
而且,为了便于描述,在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间关系术语旨在包括器件在使用或操作过程中的不同方位。例如,如果将附图中的器件翻过来,则描述为在其他元件或部件“下面”或“下方”的元件将被定位于在其他元件或部件“之上”。因此,说明性术语“在...下面”可包括在...之上和在...下面的方位。装置可以以其它方式定位(旋转90度或在其他方位),并且通过在本文中使用的空间关系描述符可同样地作相应地解释。
图1A是在一个实施例中根据本发明的各个方面构造的半导体结构(或工件)100的顶视图。图1B是根据一些实施例的沿着虚线AA′的半导体结构100的截面图。图1C是根据一些实施例的沿着虚线BB′的半导体结构100的截面图。参考图1A至图1C和其他图共同地描述半导体结构100及其制造方法。在一些实施例中,半导体结构100包括鳍式有源区并且包括形成在其上的鳍式场效应晶体管(FinFET)。在一些实施例中,半导体结构100可以包括平坦的有源区并且包括形成在其上的平坦的场效应晶体管(FET)。半导体结构100包括可以是n型FET(nFET)或p型FET(pFET)的FET。半导体结构100还包括电连接至FET(诸如电连接至FET的源极)的电容器。作为仅用于说明而非限制的实例,FET是nFET。FET和电容器连接并共同用作诸如电阻式随机存取存储器(RRAM)或动态RAM(DRAM)的存储器件。在一些其他实例中,存储器件是一次性可编程(OTP)存储器(例如,嵌入式OTP存储器)。
半导体结构100包括衬底102。衬底102包括块状硅衬底。可选地,衬底102可包括:元素半导体,诸如晶体结构的硅或锗;化合物半导体,诸如硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;或它们的组合。可能的衬底102还包括绝缘体上硅(SOI)衬底。通过注氧隔离(SIMOX)、晶圆接合和/或其他合适的方法制造SOI衬底。
衬底102还包括形成在衬底102上并且在衬底102上限定各个有源区(诸如有源区106)的各个隔离部件(诸如隔离部件104)。隔离部件104使用诸如浅沟槽隔离(STI)的隔离技术,以限定并电隔离各个有源区。隔离部件104包括氧化硅、氮化硅、氮氧化硅、其他合适的介电材料或它们的组合。通过任何合适的工艺来形成隔离部件104。作为一个实例,形成STI部件包括:进行光刻工艺以暴露衬底的部分;在衬底的暴露部分中蚀刻沟槽(例如,通过使用干蚀刻和/或湿蚀刻);以及用一种或多种介电材料填充沟槽(例如,通过使用化学汽相沉积工艺),并且通过诸如化学机械抛光(CMP)工艺的抛光工艺平坦化衬底并去除介电材料的多余部分。在一些实例中,填充的沟槽可以具有多层结构,诸如热氧化物衬里层和氮化硅或氧化硅的填充层。
有源区106是具有半导体表面的区域,其中形成有各个掺杂部件并且配置为诸如二极管、晶体管的一个或多个器件和/或其他合适的器件。有源区可以包括类似于衬底102的块状半导体材料的(诸如硅)的半导体材料或诸如硅锗(SiGe)、碳化硅(SiC)的不同的半导体材料或通过外延工艺形成在衬底102上的多个半导体材料层(诸如可选的硅和硅锗层),从而用于性能增强(诸如应变效应)以增加载流子迁移率。在本实例中,有源区106具有在X方向上定向的细长形状。
在本实施例中,有源区106是三维的,诸如,在隔离部件104之上突出的鳍式有源区。鳍式有源区从衬底102突出并且具有三维轮廓,从而用于FET的沟道区(或简称为沟道)和栅电极之间更有效的连接。可通过以下步骤来形成鳍式有源区106:选择性蚀刻以凹进隔离部件104,或选择性外延生长以生长具有与衬底102相同或不同的半导体的有源区,或它们的组合。鳍式有源区106还简称为鳍106。
半导体衬底102还包括配置为形成各种器件或器件的组件的各个掺杂部件,诸如n型掺杂阱、p型掺杂阱、源极和漏极、其他掺杂部件或它们的组合。在一个实施例中,半导体结构100包括位于鳍式有源区106上的第一类型掺杂剂的掺杂阱110。掺杂阱110可以通过扩散延伸至位于隔离部件104下面的区域。如上所述仅为了说明,形成在鳍106上的FET是nFET。在这种情况下,掺杂阱110掺杂有p型掺杂剂(因此称为p阱)。掺杂阱110中的掺杂剂(诸如硼)可以通过离子注入或其他合适的技术引入到鳍106中。例如,可以通过包括以下步骤的过程形成掺杂阱110:在衬底102上形成具有开口的图案化的掩模,其中,开口限定用于掺杂阱110的区域;并使用图案化的掩模作为注入掩模实施离子注入以将p型掺杂剂(诸如硼)引入到鳍106中。图案化的掩模可以是通过光刻形成的图案化的抗蚀剂层或者通过沉积、光刻工艺和蚀刻形成的图案硬掩模。在可选实施例中,鳍106上的FET是pFET并且掺杂阱110可以掺杂有诸如磷的n型掺杂剂。
半导体结构100还包括设置在鳍106中并且具有在Y方向上定向的细长形状的栅极堆叠件114。Y方向与X方向正交,并且X和Y方向均限定衬底102的顶面。顶面具有沿着Z方向的法线方向,其中,Z方向与X方向和Y方向都正交。栅极堆叠件114包括栅极介电层116和形成在栅极介电层上的栅电极120。根据一些实例,栅极堆叠件114可以具有在10nm和20nm之间的范围内的高度。
栅极介电层116包括诸如氧化硅的介电材料。在其他实施例中,栅极介电层可选地或额外地包括用于电路性能和制造集成的其他合适的介电材料。例如,栅极介质层116包括诸如金属氧化物、金属氮化物或金属氮氧化物的高k介电材料层。在各个实例中,高k介电材料层包括通过诸如金属有机化学汽相沉积(MOCVD)、物理汽相沉积(PVD)、原子层沉积(ALD)或分子束外延(MBE)的合适的方法形成的金属氧化物:ZrO2、Al2O3和HfO2。栅极介电层还可以包括插入半导体衬底和高k介电材料之间的界面层。在一些实施例中,界面层包括通过ALD、热氧化或紫外线-臭氧氧化形成的氧化硅。
栅电极120包括诸如铝、铜、钨、金属硅化物、金属合金的金属,诸如掺杂的多晶硅的其他适当的导电材料或它们的组合。栅电极120可以包括设计为诸如覆盖层、功函数金属层、阻挡层和填充金属层(诸如铝或钨)的多个导电膜。多个导电膜设计为与nFET(或pFET)匹配的功函数。在一些实施例中,用于nFET的栅电极120包括具有设计为功函数等于或低于4.2eV的组成的功函数金属。在其他情况下,用于pFET的栅电极包括具有设计为功函数等于或大于5.2eV的组成的功函数金属。例如,用于nFET的功函数金属层包括钽、钛铝、氮化钛铝或它们的组合。在其他实例中,用于pFET的功函数金属层包括氮化钛、氮化钽或它们的组合。
栅极堆叠件114还可以包括形成在栅电极120的侧壁上的栅极间隔件122。栅极间隔件122包括氧化硅、氮化硅、氮氧化硅、其他合适的介电材料或它们的组合。栅极间隔件122可以具有多层结构并且可以通过沉积介电材料然后进行各向异性蚀刻(诸如等离子体蚀刻)来形成该栅极间隔件。
通过诸如后栅极工艺等的适当过程形成栅极堆叠件114,其中,首先形成伪栅极,并且然后在形成源极和漏极之后由金属栅极替换该伪栅极。可选地,通过后高k工艺形成栅极堆叠件,其中,在形成源极和漏极之后,分别通过高k介电材料和金属替换栅极介电材料层和栅电极这两者。由于栅极材料和形成,栅极堆叠件114可以具有不同的结构。在图1D中以截面图示出一个示例性栅极堆叠件114。根据一些实施例进一步描述制作栅极堆叠件114的方法。在本实施例中,栅极堆叠件114是通过以下过程形成的金属栅极:在鳍上形成伪栅极堆叠件;形成源极和漏极;在源极和漏极上沉积ILD;然后去除伪栅极堆叠件,生成栅极沟槽;在栅极沟槽中沉积金属栅极材料;并且施加CMP工艺去除多余的栅极材料。在图1D所示的本实施例中,栅极堆叠件114包括具有高k介电材料且为U形的栅极介电层116。栅电极120包括诸如120A、120B和120C的多个层。在进一步的实施例中,栅电极层120A是防止相互扩散和其他集成考虑的覆盖层;栅电极层120B是用于调整功函数的金属层(也称为功函数金属层);以及栅电极层120C是诸如钨、铜、铝、铜铝合金或其他低电阻率金属的填充金属。
半导体结构100包括限定在鳍106上并且位于栅极堆叠件114下面的沟道区124。沟道区124在源极和漏极之间提供电流路径。根据应用和器件规格,沟道区124具有与掺杂阱110(在本实例中为p阱)相同类型的掺杂剂,但具有更大的掺杂浓度。可以通过离子注入来调整沟道区124,以具有合适的掺杂剂浓度,从而获得适当的阈值电压和其他参数。
半导体结构100包括在位于沟道区124(以及栅极堆叠件114)的相对侧上的鳍106上形成的源极/漏极(S/D)部件(或简称为源极和漏极)。S/D部件掺杂有与第一类型掺杂剂相反的第二类型掺杂剂。在这种情况下,S/D部件掺杂有n型掺杂剂(诸如磷)。可以通过离子注入和/或扩散形成S/D部件。可以进一步包括其他处理步骤以形成S/D部件。例如,可以使用快速热退火(RTA)工艺来激活注入的掺杂剂。S/D部件可能具有通过多步注入形成的不同的掺杂轮廓。例如,可以包括诸如轻掺杂漏极(LDD)或双扩散漏极(DDD)的额外的掺杂部件。而且,S/D部件可以具有诸如凸起、凹进或应变的不同的结构。例如,S/D部件的形成可以包括:蚀刻以凹进源极和漏极区;选择性外延生长以形成具有原位掺杂的外延S/D部件;和用于激活的退火。因此,形成的S/D部件是具有应变效应的外延S/D部件,以用于增强载流子迁移率和器件性能。可以通过一个或多个选择性外延生长形成S/D部件,由此可以在源极和漏极区内的鳍上以结晶状态生长硅(Si)部件、硅锗(SiGe)部件、碳化硅(SiC)部件和/或其他合适的半导体部件。为了便于下面的描述,S/D部件分别称为漏极126和源极128。
源极128、漏极126、沟道124和栅极堆叠件114配置为形成FET。在本实施例中,FET是nFET,其仅用于说明的目的而不是限制本发明。在可选实施例中,FET是pFET。
半导体结构100还包括设置在衬底102上的层间介电(ILD)层130。ILD层130包括一种或多种介电材料以向各种器件组件提供隔离功能。ILD层130包括诸如氧化硅、低k介电材料、其他合适的介电材料或它们的组合的介电材料。在一些实例中,低k介电材料包括氟化硅玻璃(FSG)、掺碳氧化硅、干凝胶、气凝胶、非晶氟化碳、聚对二甲苯、BCB(双苯并环丁烯)、聚酰亚胺和/或介电常数大致小于热氧化硅的介电常数的其他合适的介电材料。例如,ILD层130的形成包括沉积和CMP。沉积可以包括旋涂、CVD、其他合适的沉积技术或它们的组合。
半导体结构100还包括设置在栅极堆叠件114和ILD层130上的覆盖层132。覆盖层132覆盖栅极堆叠件114并为栅极堆叠件114提供保护,诸如在后续工艺期间防止被氧化或蚀刻损坏。覆盖层132可以用于诸如蚀刻停止的其他功能。与现有方法相比,覆盖层132提供了诸如沉积而不蚀刻的以消除相应的蚀刻损伤的一些优势。覆盖层132包括诸如氧化硅、氮化硅、氮氧化硅、其他合适的介电材料或它们的组合的介电材料。可以通过诸如CVD或原子层沉积(ALD)的任何合适的沉积技术来形成覆盖层132。在本实施例中,覆盖层132是具有与栅极堆叠件114和ILD层130的顶面共面的底面的平面层。在一些实例中,覆盖层132具有在0.5nm和5nm之间的范围内的厚度。在其他实例中,覆盖层132具有在2nm和4nm之间的范围内的厚度。
半导体结构100还包括设置在覆盖层132上的第二ILD层134。在组分和形成方面,第二ILD层134类似于ILD层130。例如,第二ILD层134可以包括低k介电材料并且可以通过沉积和CMP形成该第二ILD层。
半导体结构100还包括诸如第一接触部件136和第二接触部件138的接触部件以提供电连接。第一接触部件136和第二接触部件138包括诸如金属或金属合金的导电材料,并且形成在ILD层(130和134)中。第一接触部件136与漏极126对准并且直接接合在漏极126上。第二接触部件138与源极128对准但不直接接触源极。第一接触部件和第二接触部件中的每个都包括粘合层140和填充金属142。粘合层140提供诸如粘合和防止相互扩散的各种功能。在本实施例中,粘合层140包括钛和氮化钛。可以通过物理汽相沉积(PVD)、ALD、其他合适的沉积或它们的组合来沉积粘合层140。填充金属142包括钨、铜、铝、铜铝合金、其他合适的导电材料或它们的组合。通过诸如CVD、PVD、镀或它们的组合的任何合适的技术来沉积填充金属142。
半导体结构100还包括围绕第一接触部件和第二接触部件的另一介电材料层146。介电材料层146包括与覆盖层132相同或不同的合适的介电材料。在一些实例中,介电材料层146包括氧化物、氮化物或碳化物、其他合适的介电材料或它们的组合,诸如氧化硅、氮化硅、氮氧化硅、碳化硅。可以通过CVD、ALD或其他合适的技术来沉积介电材料层146。在一些实例中,介电材料层146具有在0.5nm和5nm之间的范围内的厚度。在一些实例中,介电材料层146具有在1nm和2nm之间的范围内的厚度。特别地,根据一些实例,介电材料层146的厚度T和栅极堆叠件114的高度H具有从1/20至1/2范围内的比率T/H。
特别地,介电材料层146在源极128和第二接触部件138之间延伸,并且将源极128与第二接触部件138隔离。介电材料层146的插入源极128和第二接触部件138之间的延伸部分用作夹置于源极128和第二接触部件138之间的电容器。在一些实施例中,源极128、第二接触部件138和介电材料层146的延伸部分用作电容器,其中,第二接触部件138和源极128用作电容器的两个电极。FET和电容器形成诸如RRAM或DRAM或eOTP的存储器件。
接触部件的形成包括:图案化ILD层以形成接触孔;接触孔中沉积介电材料层146;从与漏极对准的接触孔的底面选择性地去除介电材料层146的部分;沉积粘合层140;在接触孔中的粘合层上沉积填充金属142;并且实施CMP工艺以去除ILD层上的多余的填充金属142和粘合层140。选择性去除位于与漏极126相对应的接触孔的底面上的介电材料层146的部分还可以包括:形成图案化的掩模以覆盖至源极128的接触孔而不覆盖至漏极126的接触孔;实施各向异性蚀刻工艺(诸如干蚀刻工艺)以选择性地去除与漏极对准的接触孔内的底部部分;并去除图案化的掩模层。在一个实例中,通过ALD沉积介电材料层146,其中,精确控制相应的厚度。
如图1A和图1C所示,半导体结构100还包括与栅极堆叠件114对准并直接接合在栅极堆叠件114上(诸如接合在栅极堆叠件114的位于隔离部件104上的延伸部分上)的第三接触部件148。可以通过类似的过程形成第三接触部件148,但该过程独立于形成第一接触部件和第二接触部件的过程。
半导体结构100可以包括诸如互连结构的其他部件,其中,互连结构还包括金属线,来自多个金属层以提供水平电连接;和通孔,以提供相邻金属层中的金属线之间的垂直连接。
通过实施所公开的方法和结构,通过沉积形成电阻器(或电容器),并且通过介电材料层146的厚度确定电阻(或电容)。由于可以通过沉积精确地控制厚度,所以可以更精确地控制电阻。此外,该工艺易于实施,并且与先进技术节点(例如7nm技术节点)更加兼容。
图2A是用于制造诸如半导体结构100的半导体结构的方法200的流程图。参考图2A和其他图共同描述方法200和半导体结构。然而,半导体结构100仅是根据一些实施例的由方法200制成的一个结构,并且不是限制性的。从以下描述中可以看出,也可以通过方法200制造其他半导体结构。由于在图1A-图1D中提供了一些描述,所以在下面不再重复这些语言。
参考图2A的框202和图3A,方法200包括在半导体衬底102中形成隔离部件104的操作,从而限定一个或多个有源区106。隔离部件的形成可以包括通过光刻形成图案化的掩模;通过图案化的掩模的开口蚀刻衬底102以形成沟槽;用一种或多种介电材料填充沟槽;并实施CMP工艺。图案化的掩模包括开口以限定用于隔离部件104的区域。图案化的掩模可以是软掩模(诸如光刻胶层)或硬掩模(诸如氧化硅、氮化硅或它们的组合)。通过还包括旋涂、曝光、显影和一个或多个烘焙步骤的光刻工艺形成图案化的光刻胶层。图案化的硬掩模的形成可以包括沉积硬掩模层;通过光刻工艺形成图案化的抗蚀剂层;通过图案化的抗蚀剂层的开口蚀刻硬掩模;并通过湿剥离或等离子体灰化去除图案化的抗蚀剂层。
在可选实施例中,有源区106是具有三维轮廓的鳍式有源区。在这种情况下,如图3B所示,操作202还包括形成在隔离部件104之上突出的鳍式有源区106。半导体结构100可以包括多个鳍式有源区,统称为鳍结构。在一些实施例中,可以通过选择性蚀刻以凹进隔离部件104来形成鳍结构。在一些实施例中,可以通过用一种或多种半导体材料选择性外延生长至有源区来形成鳍结构。在又一些实施例中,可以通过具有选择性蚀刻以凹进和选择性外延生长的混合工艺来形成鳍结构。鳍结构可以具有沿X方向定向的细长形状。外延生长的半导体材料可以包括硅、锗、硅锗、碳化硅或其他合适的半导体材料。选择性蚀刻工艺可以包括湿蚀刻、干蚀刻、其他合适的蚀刻或它们的组合。在以下图中,半导体结构100示出平面有源区106,但应该理解,有源区106可以是鳍式有源区。
如图3A(和图3B)所示,方法200可以包括在鳍106上形成诸如掺杂阱110的掺杂阱的操作。在本实施例中,掺杂阱110是p型掺杂阱(p阱),其中,通过合适的技术(诸如离子注入)将p型掺杂剂(诸如硼)引入到鳍106中。
参考图2A的框204和图3A,方法200进行至在鳍106上形成栅极堆叠件114的操作。栅极堆叠件114的形成包括沉积和图案化,诸如沉积栅极介电层、沉积栅电极材料以及图案化沉积的栅极材料以形成栅极堆叠件。在一些实施例中,操作204形成包括多晶硅的伪栅极堆叠件,并且在形成源极和漏极之后,通过金属栅极堆叠件替换伪栅极堆叠件。例如,通过沉积和图案化工艺形成伪栅堆叠件,其中,图案化工艺还包括光刻工艺和蚀刻工艺。在一个实施例中,形成伪栅极叠堆叠件的过程包括:通过热氧化在鳍上形成热氧化物层;通过CVD沉积多晶硅层;通过光刻工艺形成图案化的掩模层;以及对沉积的伪栅极材料实施蚀刻工艺。图案化的掩模层包括开口以限定用于伪栅极堆叠件的区域。图案化的掩模层可以是在操作202期间利用与形成隔离部件104的硬掩模类似的工艺形成的软掩模(诸如光刻胶层)或硬掩模(诸如氧化硅、氮化硅或它们的组合)。操作204还包括在栅极堆叠件的侧壁上形成栅极间隔件122。栅极间隔件122包括诸如氧化硅、氮化硅或它们的组合的一种或多种介电材料。形成栅极隔离件122可以包括在伪栅极堆叠件上沉积一个或多个介电材料层;并对介电材料层实施各向异性蚀刻工艺。在一些实例中,各向异性蚀刻工艺包括使用合适的蚀刻剂(诸如含氟气体或含氯气体)的干蚀刻。
参考图2A的框206和图3A,方法200包括在鳍106上形成源极128和漏极126的操作。通过栅极堆叠件下面的沟道区124插接源极和漏极。在本实施例中,源极和漏极掺杂有诸如磷的n型掺杂剂。沟道区124掺杂有诸如硼的p型掺杂剂。可以通过多个步骤形成源极和漏极。
在一些实施例中,源极和漏极是外延源极和漏极。可以通过选择性外延生长形成具有应变效应的外延源极和漏极,从而用于增强载流子迁移率和器件性能。通过一个或多个外延生长步骤形成源极和漏极,由此可以在源极和漏极区内(诸如由图案化的硬掩模限定)的鳍上以晶体状态生长硅(Si)部件、硅锗(SiGe)部件、碳化硅(SiC)部件和/或其他合适的半导体部件。在可选实施例中,在外延生长之前,施加蚀刻工艺以凹进源极区和漏极区内的有源区106的部分。蚀刻工艺还可去除设置在源极/漏极区上的任何介电材料(诸如在形成栅极侧壁部件期间)。合适的外延生长工艺包括CVD沉积技术(例如汽相外延(VPE)和/或超高真空CVD(UHV-CVD)、分子束外延)和/或其他合适的工艺。在外延工艺期间可以通过在外延前体中包括含掺杂剂的气体(诸如含磷或含砷气体(或者可选地含p型掺杂剂的气体,如果FET是pFET(例如,含硼或BF2的气体))来原位掺杂源极和漏极。如果未原位掺杂源极和漏极,则可实施注入工艺以将相应的掺杂剂引入到源极和漏极中。在一些其他实施例中,通过外延生长由多于一个半导体材料层形成凸起的源极和漏极。在一些实例中,在鳍106上外延生长硅层或碳化硅层以形成nFET的源极和漏极,或者可选地,在鳍106上外延生长硅锗层以形成pFET的源极和漏极。
参考图2A的框208和图3A,方法200包括在半导体结构100上形成层间介电(ILD)层130的操作。ILD层130包括一种或多种介电材料以向各种器件组件提供隔离功能。ILD层130包括诸如氧化硅、低k介电材料、其他合适的介电材料或它们的组合的介电材料。在一些实例中,低k介电材料包括氟化硅玻璃(FSG)、掺碳氧化硅、干凝胶、气凝胶、非晶氟化碳、聚对二甲苯、BCB(双苯并环丁烯)、聚酰亚胺和/或介电常数小于热氧化硅的介电常数的其他合适的介电材料。例如,ILD层130的形成包括沉积和CMP。沉积可以包括旋涂、CVD、其他合适的沉积技术或它们的组合。
在本实施例中,操作204形成伪栅极堆叠件并在操作208之后通过金属栅极堆叠件进行替换。参考图2A的框210和图3A,方法200包括形成金属栅极堆叠件114以替换伪栅极堆叠件的操作。金属栅极堆叠件的形成包括蚀刻、沉积和CMP。根据一些实例,金属栅极堆叠件114包括具有图1D中所示的结构的栅极介电层116和栅电极120。
参考图2A的框211和图4,方法200可以包括在栅极堆叠件114和ILD层130上形成覆盖层132的操作。覆盖层132包括诸如氧化硅、氮化硅或氮氧化硅的合适的介电材料。可以通过诸如CVD或ALD的合适的沉积技术形成覆盖层132。在本实施例中,覆盖层132是具有与栅极堆叠件114和ILD层130的顶面共面的底面的平面层。在一些实例中,覆盖层132具有在0.5nm和5nm之间的范围内的厚度。在其他实例中,覆盖层132具有在2nm和4nm之间的范围内的厚度。
参考图4,方法200可以包括在覆盖层132上形成另一ILD层134的操作。在组分和形成方面,ILD层134类似于ILD层130。
参考图2A的框212和图5,方法200包括在ILD层中,特别是在ILD层130、覆盖层132和ILD层134中形成接触孔150和152的操作。接触孔150和152分别与漏极126和源极128对准并使其暴露。接触孔的形成包括使用光刻工艺形成图案化的掩模;并通过图案化的掩模的开口进行蚀刻。蚀刻可以包括具有合适的蚀刻剂的一个或多个蚀刻步骤以蚀刻相应的材料层。在本实施例中,蚀刻工艺可以包括干蚀刻、湿蚀刻或它们的组合。图案化的掩模可以是软掩模(诸如光刻胶)或硬掩模(诸如具有足够的蚀刻选择性的介电材料层)。
方法200进行至操作214以在接触孔中形成介电材料层146。在本实施例中,在用于源极128的接触孔152的侧壁和底面上形成介电材料层146,但仅在用于漏极126的接触孔150的侧壁上形成该介电材料层146,其中,接触孔150的底面没有介电材料层146。参考图2B进一步描述操作214,作为包括多个子操作的操作214的流程图。
参考图2B的框218和图6,方法214包括通过合适的沉积技术(诸如ALD或CVD)将介电材料层146沉积在接触孔中和ILD层134上的操作。介电材料层146包括诸如氧化硅、氮化硅、氮氧化硅、碳化硅或它们的组合的合适的介电材料。沉积控制为具有合适的厚度。在接触孔150和152的侧壁和底面上形成介电材料层146。在一些实例中,介电材料层146具有在0.5nm和5nm之间的范围内的厚度。在一些实例中,介电材料层146具有在1nm和2nm之间的范围内的厚度。
参考图2B的框220和图6,方法214包括形成图案化的掩模(软掩模或硬掩模)162以覆盖第二接触孔152而不覆盖第一接触孔150的操作。
参考图2B的框222和图7,方法214包括实施诸如干蚀刻的各向异性蚀刻工艺的操作,以使用图案化的掩模162作为蚀刻掩模去除第一接触孔150中的介电材料层146的底部部分。蚀刻工艺还可以去除介电材料层146的位于ILD层134上的部分。在各向异性蚀刻工艺之后,可以去除图案化的掩模162。
返回参考图2A的框216和图8,方法200包括分别在接触孔150和152中形成接触部件136和138的操作。接触部件的形成包括通过ALD、PVD或它们的组合在接触孔中沉积粘合层140;通过PVD、镀、ALD或它们的组合沉积导电材料142以填充接触孔;并且实施CMP工艺以去除ILD层134上的导电材料。在本实例中,粘合层140包括钛膜和氮化钛膜。根据一些实例,导电材料142包括钨、铜、铝、铝铜合金或它们的组合。
还在单独的工艺中形成至栅极堆叠件114的接触部件148。例如,接触部件148的形成包括:形成具有至栅极堆叠件114的开口的图案化的掩模;蚀刻ILD以形成与栅极堆叠件对准的接触孔;沉积粘合层;沉积导电材料以填充接触孔;并实施CMP工艺。
图9A-图9C提供了根据一些其他实施例的通过方法200形成的半导体结构900。图9A是在一个实施例中根据本发明的各个方面构造的半导体结构900的顶视图。图9B是根据一些实施例的沿着虚线AA′的半导体结构900的截面图。图9C是根据一些实施例的沿着虚线BB′的半导体结构900的截面图。半导体结构900类似于半导体结构100。不再重复类似部件的描述。此外,如图9B所示,半导体结构900中的第二接触部件902与源极128对准并且接合在ILD层130的部分(称为130A)上。源极128通过ILD层130的部分130A与接触部件902分离并隔离。ILD层130的位于第二接触部件902下面的部分130A(与第二接触部件902和源极128共同地)用作电容器。FET和电容器连接在一起并形成诸如RRAM、DRAM或eOTP的存储器件。如图11至图14所示,在不同的制造阶段处,通过2A的方法200形成各种部件。例如,方法200包括形成隔离部件104的操作202;形成源极和漏极的操作206;形成金属栅极堆叠件的操作210;形成接触孔的操作212;形成介电材料层146的操作214等。在这里不再重复类似的语言。特别地,参考图10A和图10B详细描述形成接触孔的操作212和形成介电材料层146的操作214。
在本实施例中,在单独的过程中形成半导体结构900的第一接触部件136和第二接触孔902。在进一步的实施例中,在与形成栅极接触部件148相同的过程中形成第二接触部件902。
参考图10A和图13,方法212包括操作1002,其中,通过与形成图5的接触孔150类似的过程形成第一接触孔150。例如,操作1002包括形成图案化的掩模并使用图案化的掩模作为蚀刻掩模进行蚀刻。特别地,控制蚀刻工艺以蚀刻穿过第一ILD层130,从而使得在第一接触孔150内暴露漏极126。
方法212还包括操作1004,其中,通过共同形成栅极堆叠件114的接触孔148的另一过程形成第二接触孔1302。通过相同的操作1004共同形成栅极接触部件148和接触部件902,而通过另一操作1002形成接触部件136。
操作1004还包括形成具有开口的图案化的掩模,其中,该开口限定用于接触孔的区域;以及对ILD层实施蚀刻工艺以形成与源极128和栅极堆叠件114对准的相应接触孔。控制蚀刻工艺以蚀刻穿过第二ILD层134和覆盖层132,从而使得在相应的接触孔(这里未示出)内暴露栅极堆叠件114。此外,控制蚀刻工艺蚀刻穿透第一ILD层130,从而使得保留在第二接触孔1302中ILD层130的部分具有期望的厚度。在一些实施例中,蚀刻工艺包括使用相应的蚀刻剂的多个蚀刻步骤。例如,施加第一蚀刻步骤来蚀刻第二ILD层134并停止在覆盖层132上;施加第二蚀刻步骤以蚀刻覆盖层132并停止在栅极堆叠件114上;并且施加第三蚀刻步骤以选择性地蚀刻第一ILD层130。在先进技术节点中,由于栅极堆叠件和S/D部件之间的高度差异,与S/D部件的形成分开地形成栅极接触件。在方法212中,将至源极128的第二接触部件902与栅极接触件形成一组而不使用额外的光掩模和光刻工艺,从而导致制造成本降低。
参考图10B和图13,方法200的形成介电材料层146的操作214仅在形成与漏极126对准的第一接触部件136的过程中应用于第一接触孔150。如上所述,通过操作1002形成第一接触孔150还包括形成图案化的掩模和蚀刻。在操作1002之后,操作214继续使用相同的图案化的掩模以在第一接触孔150中形成介电材料层146。特别地,如图13所示,操作214包括子操作1006,用于在第一接触孔150中沉积介电材料层146;以及子操作1008,实施各向异性蚀刻工艺以从第一接触孔150的底面去除介电材料层146,从而使得在接触孔150内暴露漏极126的。之后,如图14所示,通过操作216形成接触部件136、902和148。
图15A-图15C提供了根据一些其他实施例的通过方法200形成的半导体结构1500。图15A是在一个实施例中根据本发明的各个方面构造的半导体结构1500的顶视图。图15B是根据一些实施例的沿着虚线AA′的半导体结构1500的截面图。图15C是根据一些实施例的沿着虚线BB′的半导体结构1500的截面图。半导体结构1500类似于半导体结构100。不再重复类似部件的描述。此外,半导体结构1500中的第二接触部件1502与源极128对准并且接合在电阻部件(或介电部件)1504上。源极128通过电阻部件1504与接触部件1502分离并隔离。FET和电阻部件1504形成诸如eOTP(或可选的RRAM)的存储器件。在一些实施例中,电阻部件1504在组分上不同于介电材料层146。如图17至图21所示,通过方法200形成各种部件。例如,方法200包括形成隔离部件104的操作202;形成源极和漏极的操作206;形成金属栅极堆叠件114的操作210;形成接触孔的操作212;形成介电材料层146的操作214等。这里不再重复类似的语言。特别地,形成介电材料层146的操作(或方法)214包括形成电阻部件1504并且参考图16A对其进行详细描述。
参考图16A的框1602和图20,方法214包括在第一接触孔150和第二接触孔152中沉积介电材料层146的操作。
参考图16A的框1604和图20,方法214包括实施各向异性蚀刻工艺以去除接触孔中的介电材料层146的底部部分的操作。
参考图16A的框1606和图20,方法214包括形成图案化的掩模的操作以不覆盖第二接触孔152而覆盖第一接触孔150。
参考图16A的框1608和图20,方法214包括在第二接触孔152中沉积第二介电材料层(或电阻材料层)1504的操作。第二介电材料层1504包括与第一介电材料层146不同的任何介电材料,并且可以包括氧化硅、氮化硅、氮氧化硅、高k介电材料(诸如金属氧化物、金属氮化物或金属氧氮化物),或它们的组合。沉积工艺可以包括CVD、ALD或其他合适的沉积技术。控制沉积工艺以将第二介电材料层1504沉积为具有期望的厚度。
参考图16A的框1610和图20,方法214包括实施各向异性蚀刻工艺以从第二接触孔152的侧壁去除第二介电材料层1504的操作,从而在第二接触孔152中生成介电部件(仍然用1504标记)。之后,通过操作216包括136、1502和148的接触部件位于相应接触孔中。
在一个可选实施例中,在图16B中提供形成相同结构的方法214并且对其进行详细描述。
参考图16B和图20,方法214包括操作1602,其中,在第一接触孔150和第二接触孔152中沉积第二介电材料层146;操作1604,其中,实施各向异性蚀刻工艺以去除接触孔中的介电材料层146的底部;以及操作1606,类似于图16A中的相应操作,形成图案化的掩模以不覆盖第二接触孔152并覆盖第一接触孔150。
参考图16B的框1612和图20,方法214包括沉积第二介电材料层1504以填充第二接触孔152的操作。第二介电材料层1504包括与第一介电材料层146不同的任何介电材料,并且可以包括氧化硅、氮化硅、氮氧化硅、高k介电材料(诸如金属氧化物、金属氮化物或金属氮氧化物),或它们的组合。沉积工艺可以包括CVD、ALD、旋涂或其他合适的沉积技术。沉积工艺填充第二接触孔152。
参考图16B的框1614和图20,方法214包括实施CMP工艺以从ILD层134去除第二介电材料层1504并平坦化顶面的操作。
参考图16B的框1616和图20,方法214包括实施蚀刻工艺以将第二接触孔152中的第二介电材料层1504凹进至期望厚度的操作,从而在第二接触孔152中生成介电部件1504。
在另一可选实施例中,在图16C中提供形成相同结构的方法214并且在下面对其进行详细描述。
参考图16C和图20,方法214包括操作1602,其中,在第一接触孔150和第二接触孔152中沉积介电材料层146;操作1604,其中,实施各向异性蚀刻工艺以去除接触孔中的介电材料层146的底部;以及操作1606其中,类似于图16A中的相应操作,形成图案化的掩模以不覆盖第二接触孔152而覆盖第一接触孔150。
参考图16C的框1622和图20,方法214包括实施自底向上沉积工艺的操作,该工艺在第二接触孔152的底面上沉积第二介电材料层1504,从而在第二接触孔152中生成电阻器150。自底向上金属沉积工艺从底部向上填充开口,并且没有台阶覆盖问题。自底向上沉积可以包括玻璃簇离子束(GCIB)、引发的CVD(iCVD)、循环沉积蚀刻(CDE)或其他合适的沉积技术。在一些实例中,自底向上沉积工艺是循环沉积蚀刻工艺,其中,同时实施沉积和蚀刻,从而使得由于通过蚀刻去除沉积在第二接触孔152的侧壁上的第二介电材料,所以仅在底面上沉积第二介电材料。
图22A-图22C提供了根据一些其他实施例的由方法200形成的半导体结构2200。图22A是在一个实施例中根据本发明的各个方面构造的半导体结构2200的顶视图。图22B是根据一些实施例沿着虚线AA′的半导体结构2200的截面图。图22C是根据一些实施例的沿着虚线BB′的半导体结构2200的截面图。半导体结构2200类似于半导体结构100。不再重复类似部件的描述。另外,半导体结构2200中的第二接触部件2202与源极128对准并且直接接合在源极128上。在形成和结构方面,第二接触部件2202大致类似于第一接触部件136。如图24至图29所示,通过方法200形成各种部件。例如,方法200包括操作202,其中,形成隔离部件104;操作206,其中,形成源极和漏极;操作210,其中,形成金属栅极堆叠件114;操作212,其中,形成接触孔;操作214,其中,形成介电材料层146等。在这里不再重复类似的语言。特别地,参考图23详细描述形成介电材料层146的操作(或方法)214。
参考图23的框218和图27,方法214包括在第一接触孔150和第二接触孔152中沉积介电材料层146的操作。
参考图23的框2302和图28,方法214包括实施各向异性蚀刻工艺以从第一接触孔和第二接触孔去除介电材料层146的底部部分的操作。各向异性蚀刻工艺还去除ILD层134上的介电材料层146。
图30A-图30C提供了根据一些其他实施例的由方法200形成的半导体结构3000。图30A是在一个实施例中根据本发明的各个方面构造的半导体结构3000的顶视图。图30B是根据一些实施例的沿着虚线AA′的半导体结构3000的截面图。图30C是根据一些实施例的沿着虚线BB′的半导体结构3000的截面图。半导体结构3000类似于半导体结构2200。不再重复类似部件的描述。然而,半导体结构3000包括与栅极堆叠件114自对准的硅化物部件3002。由于栅电极120包括一些具有高电阻的导电材料(诸如图1D中所示的一个),所以硅化物部件3002保护栅极堆叠件114免于在后续工艺期间被氧化或蚀刻损坏,并且还降低了接触电阻。如图32至图38所示,通过方法200形成各种部件。例如,方法200包括形成隔离部件104的操作202;形成源极和漏极的操作206;形成金属栅极堆叠件114的操作210;形成接触孔的操作212;形成介电材料层146的操作214;以及形成接触部件的操作216。这里不再重复类似的语言。特别地,参考图31进一步详细描述形成栅极堆叠件114的操作(或方法)210。
参考图31的框3102和图32,方法210包括通过蚀刻工艺去除伪栅极堆叠件的操作,从而生成栅极沟槽。
参考图31的框3104和图32,如图1D所示,方法210包括通过进一步包括在栅极沟槽中沉积各种栅极材料(诸如高k介电材料、功函数金属和填充金属)的过程形成栅极堆叠件114的操作。
参考图31的框3106和图32,方法210包括通过合适的方法(诸如CVD)在金属栅极堆叠件上沉积硅层的操作。
参考图31的框3108和图32,方法210包括用合适的温度实施热退火工艺,以使硅层和金属电极120发生反应从而直接在栅电极120上形成硅化物部件3002的操作。在一些实施例中,硅化物部件3002可以包括具有不同组分的各个部分,因为栅电极120可以包括多种金属或金属合金。
参考图31的框3110和图32,方法210可以包括实施蚀刻工艺以选择性地从栅极堆叠件114和ILD层134去除未反应的硅的操作。蚀刻工艺可以包括湿蚀刻、干蚀刻或它们的组合。在一些实例中,蚀刻工艺可以使用具有HNO3、H2O和HF的混合物的蚀刻溶液来选择性地去除硅。
在各个实施例中提供了方法200和由方法200制造的半导体结构。方法200可以额外地包括在上述操作之前、期间或之后的其他操作。例如,方法200可进一步包括形成互连结构的操作以电连接诸如源极、漏极、栅极堆叠件、电容器、电阻器或它们的组合的各个部件以形成集成电路。在一些实例中,集成电路包括诸如eOTP、RRAM、DRAM或它们的组合的存储器件。在上面对一些实施例的描述中,为了更好地理解FET的结构,对源极128和漏极126进行了具体且独特的描述,或者具有一个S/D部件的存储器件连接至对准的接触部件并且另一S/D部件与对准的接触部件分离。然而,根据其他实施例,可以交换源极和漏极。在其他实施例中,也可以在半导体结构100、半导体结构900、半导体结构1500和半导体结构2200中形成与半导体结构3000中的金属栅极堆叠114自对准的硅化物部件3002。
在各个实施例中,本发明提供了半导体结构及其制造方法。半导体结构包括FET,其中,在接触孔中形成接触部件之前在接触孔中沉积介电材料。在一些实施例中,介电材料层延伸至接触部件和下面的源极(或者漏极)之间并且用作电容器(或电阻器)。在一些实施例中,FET和电容器形成诸如RRAM、DRAM或eOTP的存储器件。此外,接触孔中的介电材料层还在栅极和源极/漏极部件之间提供隔离,同时减少了泄漏。在一些实施例中,半导体结构包括在金属栅极堆叠件上形成硅化物部件并与栅电极自对准的方法。通过实施各个实施例中的公开的方法,可以存在下述的一些优势。然后,应该理解,本文公开的不同实施例提供不同的优势并且没有特定优势是所有实施例都必需的。作为一个实例,通过沉积在接触孔中形成介电层146,并且通过沉积工艺来控制介电材料层146的厚度。因此,可以更精确地控制介电材料层的电参数(诸如电容或电阻),因为通过沉积可以比蚀刻更精确地控制厚度。在另一实例中,介电材料层146设置在接触孔的侧壁上并且在源极/漏极部件与栅极堆叠件之间提供隔离,防止泄漏。此外,该工艺易于实施,并且与先进技术节点(诸如7nm技术节点)更加兼容。
因此,根据一些实施例,本发明提供了一种制造集成电路的方法。该方法包括在半导体衬底的鳍式有源区上形成源极和漏极;在源极和漏极上沉积层间介电(ILD)层;图案化ILD层以形成分别与源极和漏极对准的第一接触孔和第二接触孔;在第一接触孔中形成介电材料层;以及分别在第一接触孔和第二接触孔中形成第一导电部件和第二导电部件。
在实施例中,所述第一导电部件通过所述介电材料层与所述源极分离。
在实施例中,所述介电材料层的形成包括在所述第一接触孔内的所述源极上直接沉积所述介电材料层;以及形成所述第一导电部件和所述第二导电部件包括直接在所述第一接触孔内的所述介电材料层上形成所述第一导电部件。
在实施例中,形成所述第一导电部件和所述第二导电部件包括:在所述第一接触孔和所述第二接触孔中沉积粘合层;在所述第一接触孔和所述第二接触孔内的所述粘合层上填充导电材料;以及实施化学机械抛光以去除所述层间介电层上的多余导电材料。
在实施例中,制造集成电路的方法还包括在所述鳍式有源区上形成栅极堆叠件并且所述栅极堆叠件插入所述源极和所述漏极之间,其中,所述栅极堆叠件、所述源极和所述漏极配置为场效应晶体管。
在实施例中,所述介电材料层包括氧化硅、氮化硅和氮氧化硅中的一种。
在实施例中,所述粘合层包括钛膜和氮化钛膜;以及所述导电材料包括钨、铜、铝中的一种或它们的组合。
在实施例中,制造集成电路的方法还包括在所述源极和所述漏极上沉积所述层间介电层之前,在所述栅极堆叠件和所述层间介电层上形成介电覆盖层。
在实施例中,在所述第一接触孔中形成所述介电材料层包括:在所述第一接触孔中沉积所述介电材料层;以及实施各向异性蚀刻工艺以去除所述第一接触孔内的所述介电材料层的底部部分,从而使得暴露所述源极。
在实施例中,制造集成电路的方法还包括在所述第一接触孔中形成介电部件,其中,所述介电部件具有直接接触所述源极的底面和直接接触所述第一介电材料层的侧壁。
在实施例中,在所述第一接触孔中形成所述介电部件包括实施自底向上沉积,其中,所述介电部件包括与所述介电材料层不同的介电材料。
在实施例中,制造集成电路的方法还包括:在所述鳍式有源区上形成栅极堆叠件,其中,所述栅极堆叠件包括金属电极;在所述金属电极上沉积硅层;退火以使所述硅层和所述金属电极的金属发生反应,由此在所述金属电极上形成硅化物层;以及蚀刻以去除未反应的硅。
根据其他实施例,本发明提供了一种制造集成电路的方法。该方法包括在半导体衬底的鳍式有源区上形成金属栅极堆叠件;在鳍式有源区上形成源极和漏极;在金属栅极堆叠件上形成自对准的硅化物层;在源极和漏极上形成层间介电(ILD)层;图案化ILD层以形成分别与源极和漏极对准的第一接触孔和第二接触孔;在第一接触孔中形成介电材料层;以及分别在第一接触孔和第二接触孔中形成第一导电部件和第二导电部件。
在实施例中,在所述第一接触孔中形成所述介电材料层包括直接在所述第一接触孔内的所述源极上沉积所述介电材料层;以及形成所述第一导电部件和所述第二导电部件包括在所述第一接触孔内的所述介电材料层上形成所述第一导电部件;以及所述第一导电部件通过所述介电材料层与所述源极分离。
在实施例中,在所述第一接触孔中形成所述介电材料层包括:在所述第一接触孔和所述第二接触孔中沉积所述介电材料层;以及从所述第一接触孔和所述第二接触孔的底面去除所述介电材料层的部分。
在实施例中,制造集成电路的方法还包括在所述第一接触孔中形成电阻材料层,其中,所述电阻材料层被所述介电材料层围绕并且直接接合在所述源极上;以及所述第一导电部件直接接合在所述电阻材料层上。
在实施例中,制造集成电路的方法还包括:在所述介电材料层上形成图案化的掩模层以覆盖所述第一接触孔;以及实施蚀刻工艺以去除所述第二接触孔中的所述介电材料层的底部部分。
在实施例中,形成所述第一导电部件和所述第二导电部件包括:在所述第一接触孔和所述第二接触孔中沉积粘合层;在所述第一接触孔和所述第二接触孔内的所述粘合层上填充导电材料;以及实施化学机械抛光以去除所述层间介电层上的所述导电材料的多余部分。
在实施例中,在所述金属栅极堆叠件上形成自对准的硅化物层包括:在所述栅极堆叠件上沉积硅层;退火以使所述硅层和所述金属栅极堆叠件发生反应,由此在所述金属栅极堆叠件上形成硅化物层;以及蚀刻以去除未反应的硅。
根据一些实施例,本发明提供了一种集成电路。IC结构包括位于衬底上的鳍式有源区;位于鳍式有源区上的金属栅极堆叠件;位于鳍式有源区上的源极和漏极,其中,金属栅极堆叠件插入源极和漏极之间;设置在源极和漏极上的层间介电(ILD)层;形成在ILD层中并且分别在源极和漏极上对准的第一导电部件和第二导电部件;以及围绕第一导电部件和第二导电部件的介电材料层。介电材料层连续地延伸至第一导电部件的底面并且包括插入第一导电部件和源极之间的部分。第二导电部件直接接触漏极。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种制造集成电路的方法,包括:
在半导体衬底的鳍式有源区上形成源极和漏极;
在所述源极和所述漏极上沉积层间介电(ILD)层;
图案化所述层间介电层以形成分别与所述源极和所述漏极对准的第一接触孔和第二接触孔;
在所述第一接触孔中形成介电材料层;以及
分别在所述第一接触孔和所述第二接触孔中形成第一导电部件和第二导电部件。
2.根据权利要求1所述的制造集成电路的方法,其中,所述第一导电部件通过所述介电材料层与所述源极分离。
3.根据权利要求2所述的制造集成电路的方法,其中,
所述介电材料层的形成包括在所述第一接触孔内的所述源极上直接沉积所述介电材料层;以及
形成所述第一导电部件和所述第二导电部件包括直接在所述第一接触孔内的所述介电材料层上形成所述第一导电部件。
4.根据权利要求3所述的制造集成电路的方法,其中,形成所述第一导电部件和所述第二导电部件包括:
在所述第一接触孔和所述第二接触孔中沉积粘合层;
在所述第一接触孔和所述第二接触孔内的所述粘合层上填充导电材料;以及
实施化学机械抛光以去除所述层间介电层上的多余导电材料。
5.根据权利要求4所述的制造集成电路的方法,还包括在所述鳍式有源区上形成栅极堆叠件并且所述栅极堆叠件插入所述源极和所述漏极之间,其中,所述栅极堆叠件、所述源极和所述漏极配置为场效应晶体管。
6.根据权利要求5所述的制造集成电路的方法,其中,所述介电材料层包括氧化硅、氮化硅和氮氧化硅中的一种。
7.根据权利要求6所述的制造集成电路的方法,其中,
所述粘合层包括钛膜和氮化钛膜;以及
所述导电材料包括钨、铜、铝中的一种或它们的组合。
8.根据权利要求5所述的制造集成电路的方法,还包括在所述源极和所述漏极上沉积所述层间介电层之前,在所述栅极堆叠件和所述层间介电层上形成介电覆盖层。
9.一种制造集成电路的方法,包括:
在半导体衬底的鳍式有源区上形成金属栅极堆叠件;
在鳍式有源区上形成源极和漏极;
在所述金属栅极堆叠件上形成自对准的硅化物层;
在所述源极和所述漏极上形成层间介电(ILD)层;
图案化所述层间介电层以形成分别与所述源极和所述漏极对准的第一接触孔和第二接触孔;
在所述第一接触孔中形成介电材料层;以及
分别在所述第一接触孔和所述第二接触孔中形成第一导电部件和第二导电部件。
10.一种集成电路(IC)结构,包括:
鳍式有源区,位于衬底上;
金属栅极堆叠件,位于所述鳍式有源区上;
源极和漏极,位于所述鳍式有源区上,其中,所述金属栅极堆叠件插入所述源极和所述漏极之间;
层间介电(ILD)层,设置在所述源极和所述漏极上;
第一导电部件和第二导电部件,形成在所述层间介电层中并且分别在所述源极和所述漏极上对准;以及
介电材料层,围绕所述第一导电部件和所述第二导电部件,其中,
所述介电材料层连续延伸至所述第一导电部件的底面并将所述第一导电部件与所述源极隔离;以及
所述第二导电部件直接接触所述漏极。
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