TW202127662A - 半導體裝置 - Google Patents
半導體裝置 Download PDFInfo
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- TW202127662A TW202127662A TW109121788A TW109121788A TW202127662A TW 202127662 A TW202127662 A TW 202127662A TW 109121788 A TW109121788 A TW 109121788A TW 109121788 A TW109121788 A TW 109121788A TW 202127662 A TW202127662 A TW 202127662A
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- semiconductor layer
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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Abstract
此處揭露半導體裝置與其製造方法。例示性的半導體裝包括基板;多個半導體層,位於基板上,其中半導體層沿著通常垂直於基板的上表面之方向堆疊並彼此分隔;介電結構,位於半導體層上並與半導體層分隔;以及閘極結構,包覆半導體層的每一者,閘極結構具有閘極介電層與閘極層,其中閘極介電層夾設於閘極層與介電結構之間,且介電結構位於閘極層的至少一部分上。
Description
本發明實施例一般關於半導體裝置與其製作方法,更特別關於鰭狀場效電晶體如全繞式閘極場效電晶體的製作方法。
導入多閘極裝置可增加閘極-通道耦合並降低關閉狀態電流,以改善閘極控制。多閘極裝置之一為全繞式閘極裝置。全繞式閘極裝置通常指的是閘極結構或其部分形成於通道區的多側上(比如圍繞通道區的一部分)之任何裝置。全繞式閘極裝置與習知的互補式金氧半製作製程相容,因此可大幅縮小電晶體。然而製作全繞式閘極裝置的方法存在挑戰。舉例來說,習知的全繞式閘極裝置中,在蝕刻虛置閘極時可能損傷或切除頂度的通道半導體層,造成高電阻或甚至頂部的通道半導體層中的通道開路,因此劣化全繞式閘極裝置的效能。
本發明一實施例提供之半導體裝置包括基板;多個半導體層,位於基板上,其中半導體層沿著通常垂直於基板的上表面之方向堆疊並彼此分隔;介電結構,位於半導體層上並與半導體層分隔;以及閘極結構,包覆半導體層的每一者,閘極結構具有閘極介電層與閘極層,其中閘極介電層夾設於閘極層與介電結構之間,且介電結構位於閘極層的至少一部分上。
本發明一實施例提供之半導體裝置包括基板;多個半導體層,位於基板上,其中半導體層沿著通常垂直於基板上表面的方向堆疊並彼此分隔;保護介電結構,位於半導體層上並與半導體層分隔;閘極結構,包覆每一半導體層;以及蝕刻停止層,位於保護介電結構與半導體層上,且蝕刻停止層的下表面直接接觸保護介電結構的上表面。
本發明一實施例提供之半導體裝置的形成方法,包括接收結構,其包含基板與交錯的第一半導體層與第二半導體層之堆疊位於基板上,其中堆疊的頂層為第一半導體層,且包括的材料不同於第二半導體層與基板;形成保護介電層於堆疊上,其中保護介電層的下表面直接接觸堆疊之頂層的上表面;選擇性移除第一半導體層,使第二半導體層與保護介電層懸空於基板上;以及在選擇性移除第一半導體層之後,形成金屬閘極堆疊包覆第二半導體層與保護介電層。
下述內容提供的不同實施例或實例可實施本發明的不同結構。下述特定構件與排列的實施例係用以簡化本發明內容而非侷限本發明。舉例來說,形成第一構件於第二構件上的敘述包含兩者直接接觸的實施例,或兩者之間隔有其他額外構件而非直接接觸的實施例。
此外,本發明之多個實例可重複採用相同標號以求簡潔,但多種實施例及/或設置中具有相同標號的元件並不必然具有相同的對應關係。此外,結構形成於另一結構上、連接至另一結構、及/或耦接至另一結構的敘述包含兩者直接接觸的實施例,或兩者之間隔有其他額外結構而非直接接觸的實施例。此外,空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件,而非侷限於圖示方向。此外,當數值或數值範圍的描述有「約」、「近似」、或類似用語時,除非特別說明否則其包含所述數值的+/-10%。舉例來說,用語「約5 nm」包含的尺寸範圍介於4.5 nm至5.5 nm之間。
本發明實施例一般關於半導體裝置與其製作方法,更特別關於鰭狀場效電晶體如全繞式閘極場效電晶體的製作方法。
在全繞式閘極裝置中,單一裝置的通道區可包含彼此物理分隔的多個半導體材料層。在一些例子中,裝置的閘極位於裝置的半導體層之上、沿著裝置的半導體層側部、且甚至位於裝置的半導體層之間。此設置可將更多半導體材料置於與閘極相鄰處,進而改善穿過通道區的載子控制。與鰭狀場效電晶體裝置相較,全繞式閘極裝置更大幅縮小閘極長度以改善效能與密度。
本發明實施例一般關於全繞式閘極裝置的形成方法,其中保護介電層位於頂部的通道半導體層上。在蝕刻虛置閘極的製程時,保護介電層可保護頂部的通道半導體層免於損傷,因此緩解習知半導體裝置中的高電阻或通道開路的問題。此外,保護介電層可作為移除金屬閘極結構頂部的蝕刻停止層,以減少不同晶圓之間的閘極高度差異。此外,習知的全繞式閘極裝置通常在頂部的通道半導體層具有金屬閘極結構的較厚部分,且在通道半導體層之間具有金屬閘極結構的較薄部分。然而本發明實施例的全繞式閘極裝置具有保護介電層,且包括實質上相同的金屬閘極輪廓(材料與厚度)以包覆每一通道半導體層(包括頂部的通道半導體層上的部份)。因此本發明實施例中的全繞式閘極裝置可在不同的通道半導體層提供一致的臨界電壓,因此可實質上同時開啟或關閉不同通道。
圖1顯示本發明一些實施例中,形成半導體裝置如裝置200的方法100之流程圖。方法100僅用於舉例而非侷限本發明實施例至請求項未實際記載處。在方法100之前、之中、與之後可進行額外步驟,且方法的額外實施利可置換、省略、或調換一些所述步驟。方法100將搭配其他圖式說明如下,且其他圖式顯示裝置200於方法100的中間階段的多種剖視圖與上視圖。具體而言,圖2A至20A顯示本發明一些實施例中,裝置200在圖1的方法之中間階段的三維透視圖。圖2B至20B顯示本發明一些實施例中,裝置200在圖1的方法之中間階段中,沿著平面B-B' (X-Z平面)的剖視圖。圖2C至20C顯示本發明一些實施例中,裝置200在圖1的方法之中間階段中,沿著平面C-C' (Y-Z平面)的剖視圖。
裝置200可為積體電路或其部分的製程所製作的中間裝置,其可包含靜態隨機存取記憶體及/或其他邏輯電路、被動構件(如電阻、電容、與電感)、與主動構件(如p型場效電晶體、n型場效電晶體、鰭狀場效電晶體、金氧半場效電晶體、互補式金氧半電晶體、雙極電晶體、高電壓電晶體、高頻電晶體、及/或其他記憶體單元)。裝置200可為積體電路的核心區(通常視作邏輯區)、記憶體區(如靜態隨機存取記憶體區)、類比區、周邊區(通常視作輸入/輸出區)、虛置區、其他合適區、或上述之組合的一部分。在一些實施例中,裝置200可為積體電路晶片的一部分,或單晶片系統或其部分。本發明實施例不限於任何特定數目的裝置或裝置區,或任何特定的裝置設置。已簡化圖2A至2C到圖20A至20C,以利清楚理解本發明實施例的發明概念。額外結構可添加至裝置200中,且裝置200的其他實施例可置換、調整、或省略一些下述結構。
如圖1及2A至2C所示,步驟105接收裝置200。裝置200包含基板202與基板200上的半導體層的堆疊210。堆疊210包括交錯的第一半導體層210A與第二半導體層210B。
在圖2A至2C所示的實施例中,基板202為含矽的基體基板。在其他實施例或額外實施例中,基體基板包含另一半導體(如鍺)、半導體化合物(如碳化矽、磷化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、銻化銦、氧化鋅、硒化鋅、硫化鋅、碲化鋅、及/或碲化鎘)、半導體合金(如矽鍺、碳磷化矽、磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、及/或磷砷化鎵銦)、或III-V族材料、其他II-VI族材料、或上述之組合。在一些實施例中,基板202可包含銦錫氧化物玻璃、絕緣層上矽基板、增進效能的應變及或應力、磊晶區、摻雜區、及/或其他合適的結構與層狀物。具體而言,基板202可包含主動區(如鰭狀主動區)與隔離區,以及多種主動與被動裝置如p型場效電晶體、n型場效電晶體、多閘極場效電晶體如鰭狀場效電晶體或全繞式閘極場效電晶體、金氧半場效電晶體、互補式金氧半電晶體、雙極電晶體、高電壓電晶體、高頻電晶體、靜態隨機存取記憶體單元、其他記憶體單元、電阻、電容、電感、或上述之組合。
如圖2A至2C所示,堆疊210位於基板202上。在所述實施例中,堆疊210包括交錯的半導體層,比如組成為第一半導體材料的第一半導體層210A,與組成為第二半導體材料的第二半導體層210B,且第一半導體材料與第二半導體材料不同。堆疊210中交錯的第一半導體層210A與第二半導體層210B之半導體材料不同,用以提供不同的氧化速率及/或不同的蝕刻選擇性。舉例來說,第一半導體層210A包括矽鍺,而第二半導體層210B包括矽。因此堆疊210的配置自下至上為交錯的矽鍺/矽/矽鍺/矽/矽鍺…層。在一些實施例中,堆疊中頂部的半導體層材料可或可不與底部的半導體層材料相同。舉例來說,對包含交錯的矽鍺層與矽層的堆疊而言,底部的半導體層包括矽鍺,而頂部的半導體層可為含矽或矽鍺的半導體層。在所述堆疊210中,底部的半導體層包含矽鍺,而頂部的半導體層亦包含矽鍺。
在一些實施例中,第二半導體層210B包括矽,其可未摻雜或實質上不具有摻質。在一些實施例中,在形成第二半導體層210B時不刻意進行摻雜。在一些實施例中,第二半導體層210B可摻雜p型摻質如硼或硼化合物(如硼、11B、或二氟化硼)、鎵、或上述之組合以用於p型通道,或摻雜n型摻質如磷(如磷或31P)、砷、或上述之組合以用於n型通道。堆疊210中的半導體層數目取決於裝置200的設計。舉例來說,堆疊210可包含一至十層各種型態的第一半導體層210A或第二半導體層210B。在一些實施例中,堆疊210中不同的第一半導體層210A及第二半導體層210B在Z方向中具有相同厚度。在一些實施例中,堆疊210中不同的第一半導體層210A及第二半導體層210B具有不同厚度。在所述實施例中,每一第一半導體層210A在Z方向中具有高度H1,且每一第二半導體層210B在Z方向中具有高度H2。高度H1與高度H2分別為約3 nm至約15 nm。
堆疊210包括交錯的第一半導體層210A與第二半導體層210B,且可採用任何合適製程形成堆疊210於基板202上。在一些實施例中,第一半導體層210A及/或第二半導體層210B可由合適的磊晶製程形成,比如分子束磊晶製程、化學氣相沉積製程(如有機金屬化學氣相沉積)、及/或其他合適的磊晶成長製程。
如圖1、3A至3C、與4A至4C所示,步驟110形成保護介電層212於堆疊210上。如圖3A至3C所示,保護介電層212沉積於堆疊210之頂部的半導體層(比如頂部的矽鍺層如第一半導體層210A)上。在一些實施例中,保護介電層212包括介電材料如氧化鉿、氧化鉿矽、氧化鉿鋯、氧化鋯、氮氧化矽、氮化矽、碳氮化矽、碳氧化矽、碳氮氧化矽、其他介電材料、或上述之組合。在一些實施例中,保護介電層212在Z方向中具有高度H3。控制保護介電層212的高度H3,使金屬閘極與源極/汲極接點之間的寄生電容不會增加太多。舉例來說,高度H3為約2 nm至30 nm。在所述實施例中,整個保護介電層212的高度H3實質上一致。在一些實施例中,保護介電層212可由任何合適製程沉積,比如化學氣相沉積、物理氣相沉積、原子層沉積、其他沉積製程、或上述之組合。
步驟110可在沉積保護介電層212之後,形成硬遮罩層214於保護介電層212上。在一些實施例中,硬遮罩層214包括任何合適材料,比如氧化矽、碳氧化矽、碳化矽、碳氮化矽、氮化矽、碳氮氧化矽、其他合適材料、或上述之組合。硬遮罩層214沉積於保護介電層212上的方法可為合適的沉積製程,包括物理氣相沉積、化學氣相沉積、原子層沉積、旋轉塗佈、其他沉積製程、或上述之組合。
如圖4A至4C所示,步驟115圖案化基板202的頂部、堆疊210 (包括交錯的第一半導體層210A與第二半導體層210B)、保護介電層212,以形成自基板202延伸的鰭狀結構。步驟115包括多個步驟。舉例來說,形成圖案化的光阻層於硬遮罩層214上。圖案化光阻層,以自光阻層露出堆疊210上的硬遮罩層214的一部分。在後續步驟中,經由光阻層蝕刻硬遮罩層214以形成圖案化的硬遮罩層。接著以圖案化的硬遮罩層作為遮罩,並蝕刻保護介電層212、堆疊210、與基板202的頂部,以形成自基板202延伸的鰭狀結構。如圖4A至4C所示,基板202目前包括圖案化的鰭狀頂部,以及未圖案化的底部。鰭狀結構包括圖案化的保護介電層212、堆疊210、與基板202的鰭狀頂部。保護介電層212在X方向中的寬度W1,實質上等於第一半導體層210A與第二半導體層210B在X方向中的寬度。保護介電層212在Y方向(比如閘極長度方向)中的寬度W2,實質上等於第一半導體層210A與第二半導體層210B在Y方向中的寬度。鰭狀結構定義裝置200的主動區。形成鰭狀結構的蝕刻製程可包含一或多道乾蝕刻製程、濕蝕刻製程、或其他合適的蝕刻技術。步驟115接著以任何合適製程(如蝕刻製程或化學機械研磨)移除硬遮罩層214。
如圖1與圖5A至5C所示,步驟120形成隔離結構218以分開裝置200的主動區。在一些實施例中,介電材料(如氧化矽及/或氮化矽)沿著鰭狀結構的側壁沉積於基板202的底部上,介電材料的沉積方法可為化學氣相沉積、電漿輔助化學氣相沉積、物理氣相沉積、熱氧化、或其他技術。接著使介電材料的頂部凹陷(比如以蝕刻或化學機械研磨等方法),以形成隔離結構218。在一些實施例中,隔離結構218的上表面,與堆疊210的下表面(比如底部的第一半導體層210A之下表面)共平面或低於堆疊210的下表面。在一些實施例中,在使介電材料凹陷以形成隔離結構218的製程時,可稍微移除保護介電層212。隔離結構218可隔離裝置200的多種主動區。
如圖1、6A至6C、與7A至7C所示,步驟125形成虛置閘極堆疊225於鰭狀結構的通道區上。在圖6A至6C中,虛置閘極層沉積於保護介電層212、堆疊210、與隔離結構218上。在所述實施例中,界面層220位於保護介電層212、堆疊210、與隔離結構218上,且可包含任何合適材料如含矽的氧化物,比如氧化矽、氮氧化矽、氧化鉿矽、或其他含矽的氧化物材料。虛置閘極層222位於界面層220上,且包含多晶矽。虛置閘極層222可為單一介電層或多層。硬遮罩層224為於虛置閘極層222上,且可包含任何合適材料如氧化矽、氮化矽、或上述之組合。可進行沉積製程以形成界面層220、虛置閘極層222、與硬遮罩層224於基板上。沉積製程包含化學氣相沉積、物理氣相沉積、原子層沉積、鍍製法、其他合適方法、或上述之組合。
在圖7A至7C中,圖案化虛置閘極層以形成含有界面層220、虛置閘極層222、與硬遮罩層224的虛置閘極堆疊225。進行微影圖案化與蝕刻製程以圖案化界面層220、虛置閘極層222、與硬遮罩層224,以形成虛置閘極堆疊225於鰭狀結構的通道區上。微影圖案化製程包括塗佈光阻(比如旋轉塗佈)、軟烘烤、對準光罩、曝光後烘烤、顯影光阻、沖洗、乾燥(比如硬烘烤)、其他合適製程、或上述之組合。蝕刻製程包括乾蝕刻、濕蝕刻、其他蝕刻法、或上述之組合。在所述實施例中,虛置閘極堆疊225位於鰭狀結構的通道區上,進而夾設於鰭狀結構的個別源極/汲極區之間。虛置閘極堆疊作為後續形成的金屬閘極堆疊之占位物。虛置閘極堆疊225沿著X方向延伸,且可越過超過一個鰭狀結構(未圖示)。
如圖1、8A至8C、與9A至9C所示,步驟130沿著虛置閘極堆疊225的側壁形成閘極間隔物226。首先如圖8A至8C所示,間隔物層226’順應性地形成於基板上,包括形成隔離結構218、虛置閘極堆疊225、與含保護介電層212及堆疊210的鰭狀結構上。在一些實施例中,間隔物層226’可包含矽、氧、碳、氮、其他合適材料、或上述之組合,比如氧化矽、氮化矽、氮氧化矽、碳氮化矽、碳氧化矽、碳氮氧化矽、或類似物。在一些例子中,間隔物層226’包括多層結構,比如含氮化矽的第一介電層與含氧化矽的第二介電層。在一些實施例中,間隔物層226’的厚度為約1 nm至10 nm。間隔物層226’的形成方法可為任何合適方法,比如原子層沉積、化學氣相沉積、物理氣相沉積、其他合適方法、或上述之組合。在所述實施例中,間隔物層226’的形成方法為熱原子層沉積製程。之後如圖9A至9C所示,對間隔物層226'進行蝕刻製程以形成閘極間隔物226。蝕刻製程可為非等向的蝕刻製程,只移除X-Y平面中的間隔物層226'的部份。沿著Z方向的間隔物層226'維持實質上不變,並形成閘極間隔物226。在一些實施例中,閘極間隔物226在X方向或Y方向中的厚度為約1 nm至10 nm。
如圖9A至9C所示,步驟130對鰭狀結構的源極/汲極區中的保護介電層212與堆疊210的部分,進行另一蝕刻(視作源極/汲極蝕刻)。沿著閘極間隔物226進行源極/汲極蝕刻以形成源極/汲極溝槽228。源極/汲極蝕刻製程可為乾蝕刻、濕蝕刻、或上述之組合。控制源極/汲極蝕刻製程的時間,使源極/汲極溝槽中露出堆疊210的第一半導體層210A與第二半導體層210B的每一者之側壁。在一些實施例中,源極/汲極蝕刻製程稍微移除基板202的上表面。如圖9A與9C所示,源極/汲極溝槽228包括閘極間隔物226、保護介電層212、以及含有交錯的第一半導體層210A與第二半導體層210B之堆疊210的側壁所形成的側壁,以及由基板202的上表面所形成的下表面。
如圖1、10A至10C、與11A至11C所示,步驟135形成內側間隔物230於保護介電層212與頂部的第二半導體層210B之間以及相鄰的第二半導體層210B之間。如圖10A至10C所示,可由合適的蝕刻製程選擇性移除源極/汲極溝槽228中露出的第一半導體層210A的部份,以形成間隙229於保護介電層212與頂部的第二半導體層210B之間,以及相鄰的第二半導體層210B之間,使第二半導體層210B的部分(邊緣)懸空於源極/汲極溝槽228中。蝕刻製程時間可控制第二半導體層210B的移除量。在一些實施例中,選擇性移除第一半導體層210A的量為約2 nm至15 nm。如上所述的實施例,第一半導體層210A包括矽鍺,而第二半導體層210B包括矽。綜上所述,步驟135的蝕刻製程可選擇性移除矽鍺層如第一半導體層210A,而不移除或實質上不移除矽層如第二半導體層210B。在一些實施例中,蝕刻製程為選擇性等向蝕刻製程(比如選擇性乾蝕刻製程或選擇性濕蝕刻製程)。在一些實施例中,選擇性濕蝕刻製程可包括氫氟酸、氟氣、或氫氧化銨等蝕刻劑。在所述實施例中,第一半導體層210A包括矽鍺而第二半導體層210B包括矽,且選擇性移除矽鍺的步驟可包括矽鍺的氧化製程之後移除氧化矽鍺。舉例來說,矽鍺的氧化製程可包括形成與圖案化多種遮罩層,使氧化控制為針對矽鍺層。在其他實施例中,由於第一半導體層210A與第二半導體層210B的組成不同,矽鍺的氧化製程為選擇性氧化。在一些實施例中,可暴露裝置200至濕式氧化製程、乾式氧化製程、或上述之組合,以進行矽鍺的氧化製程。之後可由蝕刻劑如氫氧化銨或稀釋氫氟酸移除氧化的半導體層(包括氧化矽鍺)。
之後如圖11A至11C所示,內側間隔物230形成於保護介電層212與頂部的第二半導體層210B之間並形成於第二半導體層210B之間。內側間隔物230的材料可與閘極間隔物226的材料類似。舉例來說,內側間隔物230包括氧化矽、氮氧化矽、氮化矽、碳氮化矽、碳氧化矽、碳氮氧化矽、或上述之組合。在一些實施例中,內側間隔物材料沉積於源極/汲極溝槽228以及間隙229中,且沉積方法可為任何合適的沉積製程如化學氣相沉積、物理氣相沉積、原子層沉積、或上述之組合。接著沿著閘極間隔物226的側壁移除內側間隔物材料,直到源極/汲極溝槽228中露出第二半導體層210B的側壁。保留的內側間隔物材料形成內側間隔物230。在一些實施例中,內側間隔物230在Y方向中的寬度為約2 nm至15 nm,其為第一半導體層210A的選擇性蝕刻量。因此如圖11A與11C所示,源極/汲極溝槽228包含閘極間隔物226、保護介電層212、第二半導體層210B、與內側間隔物230的側壁所形成的側壁。
如圖1與12A至12C所示,步驟140成長磊晶的源極/汲極結構240於裝置200的源極/汲極區中。在多種實施例中,磊晶的源極/汲極結構240可包含半導體材料(如矽或鍺)、半導體化合物(如矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、或銻化銦)、半導體合金(如磷砷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、及/或磷砷化鎵銦)、或上述之組合。磊晶的源極/汲極結構240的上表面可高於或齊平頂部的矽層如第二半導體層210B的上表面。
可實施磊晶製程以磊晶成長磊晶的源極/汲極結構240。磊晶製程可包含化學氣相沉積(如氣相磊晶、超高真空化學氣相沉積、低壓化學氣相沉積、及/或電漿輔助化學氣相沉積)、分子束磊晶、其他合適的選擇性磊晶成長製程、或上述之組合。磊晶製程可採用氣相或液相的前驅物。磊晶的源極/汲極結構240可摻雜n型摻質及/或p型摻質。在一些實施例中,磊晶的源極/汲極結構240摻雜硼、二氟化硼、碳、其他p型摻質、或上述之組合,可形成硼化矽鍺的磊晶的源極/汲極結構或碳化矽鍺的磊晶的源極/汲極結構。在一些實施例中,磊晶的源極/汲極結構240摻雜磷、砷、其他n型摻質、或上述之組合,可形成磷化矽的磊晶的源極/汲極結構、碳化矽的磊晶的源極/汲極結構、或碳磷化矽的磊晶的源極/汲極結構。在一些實施例中,磊晶的源極/汲極結構240可包含多個磊晶半導體層,且不同的磊晶半導體層包含的摻質量不同。在一些實施例中,磊晶的源極/汲極結構240包括的材料及/或摻質可達通道區所需的拉伸應力及/或壓縮應力。在一些實施例中,可在沉積時添加雜質至磊晶製程的源材料,以摻雜磊晶的源極/汲極結構240。在一些實施例中,在沉積製程後以離子佈植製程摻雜磊晶的源極/汲極結構240。在一些實施例中,進行退火製程以活化磊晶的源極/汲極結構240 (如重摻雜源極/汲極區及/或輕摻雜源極/汲極區)中的摻質。
如圖1與13A至13C所示,步驟145形成接點蝕刻停止層252與層間介電層254於裝置200上。接點蝕刻停止層252可包含任何合適的介電材料,比如氧化矽、氮氧化矽、氮化矽、碳氮化矽、碳氧化矽、或碳氮氧化矽,且其形成方法可為任何合適方法如原子層沉積、化學氣相沉積、物理氣相沉積、其他合適方法、或上述之組合。如圖13A與13C所示,接點蝕刻停止層252沿著閘極間隔物226並覆蓋隔離結構218與磊晶的源極/汲極結構240。在一些實施例中,接點蝕刻停止層252具有順應性的輪廓於磊晶的源極/汲極結構240上(比如在磊晶的源極/汲極結構240的上表面與側壁表面上具有大致相同的厚度)。在一些實施例中,接點蝕刻停止層252的厚度為約1 nm至10 nm。層間介電層254形成於接點蝕刻停止層252上。層間介電層254包括低介電常數的介電材料,比如四乙氧基矽烷的氧化物、未摻雜的矽酸鹽玻璃、或摻雜的氧化矽(如硼磷矽酸鹽玻璃、摻雜氟的矽酸鹽玻璃、磷矽酸鹽玻璃、或硼矽酸鹽玻璃)、其他合適的介電材料、或上述之組合。層間介電層254可包含多個介電材料的多層結構,且其形成方法可為沉積製程如化學氣相沉積、可流動的化學氣相沉積、旋轉塗佈玻璃、其他合適方法、或上述之組合。在一些實施例中,步驟145亦包括進行化學機械研磨製程,以平坦化裝置200的上表面。化學機械研磨製程亦移除虛置閘極堆疊225的硬遮罩層224。如此一來,自裝置200的上表面露出虛置閘極層222 (如多晶層)。
如圖1與圖14A至14C所示,步驟150移除虛置閘極堆疊225 (含虛置閘極層222與界面層220),以形成露出鰭狀結構之通道區的閘極溝槽256。在一些實施例中,移除虛置閘極堆疊225 (含虛置閘極層222與界面層220)的方法包括一或多道蝕刻製程,比如濕蝕刻、乾蝕刻、反應性離子蝕刻、或其他蝕刻技術。在習知半導體裝置中不具有保護介電層212的保護,因此可能損傷或切除頂部的通道半導體層,造成半導體裝置的高電阻或甚至通道開路。然而在本發明實施例中,保護介電層212形成於堆疊210上,以在移除虛置閘極的製程時保護堆疊210的半導體層免於損傷。如圖14A至14C所示,移除虛置閘極堆疊之後,閘極溝槽256中露出保護介電層212與堆疊210之交錯的第一半導體層210A及第二半導體層210B。
如圖1與15A至15C所示,步驟155進行露出通道的製程,以自閘極溝槽256移除第一半導體層210A。如此一來,保護介電層212與第二半導體層210B懸空於鰭狀結構的通道區中。懸空的第二半導體層210B一起視作奈米結構。每一第二半導體層210B可視作通道半導體層。在一些實施例中,稍微蝕刻或不蝕刻通道半導體層如第二半導體層210B,端視裝置200的設計而定。舉例來說,可稍微蝕刻第二半導體層210B以形成線狀(用於奈米線的全繞式閘極電晶體)、片狀(用奈米片的全繞式閘極電晶體)、或其他幾何形狀(用於其他奈米結構的全繞式閘極電晶體)。如圖15B所示,保護介電層212與懸空的第二半導體層210B在X方向中具有寬度W3。在一些實施例中,寬度W3為約5 nm至約80 nm。
在步驟155中,由選擇性蝕刻製程移除第一半導體層210A,並調整選擇性蝕刻製程以只移除第一半導體層210A,且保護介電層212、第二半導體層210B、與內側間隔物230維持實質上不變。選擇性蝕刻可為選擇性濕蝕刻、選擇性乾蝕刻、或上述之組合。在一些實施例中,選擇性濕蝕刻製程可包括氫氟酸或氫氧化銨的蝕刻劑。在一些實施例中,選擇性移除第一半導體層210A的步驟可包含氧化製程(比如形成氧化的第一半導體層210A,其包含氧化矽鍺),之後移除氧化物(如移除氧化矽鍺)。如圖15B及15C所示,保護介電層212與頂部的通道半導體層如第二半導體層210B之間的空間258,與相鄰的通道半導體層如第二半導體層210B之間的空間260具有實質上相同的尺寸。換言之,空間258的高度H4與空間260的高度H4實質上相同。在一些實施例中,高度H4為約4 nm至15 nm。
如圖1、16A至16C、與17A至17C所示,步驟160形成金屬閘極堆疊268於鰭狀結構的通道區中。金屬閘極堆疊268包括多層,比如包覆每一通道半導體層如第二半導體層210B的閘極界面層262、形成於閘極界面層262上的閘極介電層264、形成於閘極介電層264上的金屬閘極266、其他合適層狀物、或上述之組合。金屬閘極堆疊268包覆鰭狀結構的通道區中每一懸空的通道半導體層如第二半導體層210B以及保護介電層212。
如圖16A至16C所示,閘極界面層262形成於通道半導體層如第二半導體層210B周圍,並形成於基板202的上表面上。在一些實施例中,閘極界面層262只形成於矽材上,因此閘極界面層262不形成於保護介電層212周圍。在一些實施例中,閘極界面層262的材料可包含氧化矽、氮氧化矽、氧化鉿矽、其他合適材料、或上述之組合。可進行沉積製程以形成包覆懸空的第二半導體層210B以及位於基板202上的閘極界面層262。沉積製程包括化學氣相沉積、物理氣相沉積、原子層沉積、高密度電漿化學氣相沉積、有機金屬化學氣相沉積、遠端電漿化學氣相沉積、電漿輔助化學氣相沉積、低壓化學氣相沉積、原子層化學氣相沉積、常壓化學氣相沉積、鍍製法、其他合適方法、或上述之組合。在一些實施例中,閘極界面層262在Z方向中的厚度為約0 nm至3 nm。
如圖16A至16C所示,閘極介電層264形成於閘極界面層262與隔離結構218上,並包覆保護介電層212。閘極介電層264可為高介電常數的介電層,比如氧化鉿、氧化鉿矽、氧化鉿鋯、氧化鋯、其他合適材料、或上述之組合。閘極介電層264的沉積方法可為合適的沉積製程,比如化學氣相沉積、物理氣相沉積、原子層沉積、高密度電漿化學氣相沉積、有機金屬化學氣相沉積、遠端電漿化學氣相沉積、電漿輔助化學氣相沉積、低壓化學氣相沉積、原子層化學氣相沉積、常壓化學氣相沉積、鍍製法、其他合適方法、或上述之組合。在一些實施例中,閘極介電層264在Z方向中的厚度為約1 nm至約5 nm。
如圖17A至17C所示,閘極266位於閘極介電層264上並填入閘極溝槽256。在一些實施例中,閘極266可包含功函數金屬層形成於閘極介電層264上,以及基體導電層形成於功函數金屬層上。功函數金屬層可包含任何合適材料,比如氮化鈦、氮化鉭、釕、鉬、鎢、鉑、鈦、鋁、碳化鉭、碳氮化鉭、氮化鉭矽、氮化鈦矽、其他合適材料、或上述之組合。在一些實施例中,功函數金屬層包括相同型態或不同型態(比如均為n型功函數金屬或均為p型功函數金屬)的多個材料層,以達所需的臨界電壓。基體導電層可包含鋁、銅、鎢、鈷、釕、其他合適的導電材料、或上述之組合。金屬閘極堆疊268可包含其他材料層,比如阻障層、黏著層、硬遮罩層、及/或蓋層(未圖示)。金屬閘極堆疊268的金屬閘極266與多種其他層之形成方法可為任何方法,比如化學氣相沉積、原子層沉積、物理氣相沉積、鍍製法、化學氧化、熱氧化、其他合適方法、或上述之組合。
如圖1與圖18A至18C所示,步驟165以平坦化製程如化學機械研磨製程移除保護介電層212上的金屬閘極堆疊268的部分。在一些實施例中,平坦化時可稍微移除保護介電層212。在習知化學機械研磨金屬閘極的製程中,以製程時間控制金屬閘極的移除深度。不同晶圓上的金屬閘極之移除深度差異可能很大。然而在本發明實施例中,化學機械研磨止於保護介電層212。換言之,保護介電層212作為化學機械研磨製程所用的停止層。由於停止層控制,不同晶圓上的金屬閘極凹陷深度更一致。此外,由於保護介電層212與頂部的通道半導體層如第二半導體層210B之間的空間尺寸,與通道半導體層如第二半導體層210B之間的空間尺寸實質上相同,每一通道半導體層如第二半導體層210B (包括頂部的通道半導體層如第二半導體層210B)上的金屬閘極部分實質上相同(比如材料與厚度相同)。因此裝置200之每一通道(包括頂部的通道)的臨界電壓一致,進而改善裝置200的效能。
如圖18A所示,保護介電層212在Y方向中延伸穿過閘極間隔物226以接觸接點蝕刻停止層252,且保護介電層212在X方向中插入金屬閘極堆疊268的頂部268T。換言之,金屬閘極堆疊268包括溝槽於頂部,保護介電層212位於溝槽中,且保護介電層212的上表面與金屬閘極堆疊268的上表面實質上共平面。
如圖1、19A至19C、與20A至20C所示,步驟170形成多種接點蝕刻停止層、層間介電層、接點、與通孔於基板202上。如圖19A至19C所示,源極/汲極接點270形成於裝置200的源極/汲極區中的磊晶的源極/汲極結構240上。在一些實施例中,每一源極/汲極接點270可包含金屬插塞於磊晶的源極/汲極結構上。每一源極/汲極接點270亦可包含矽化物層於金屬插塞與磊晶的源極/汲極結構240之間。可視情況形成矽化物層,以進一步降低源極/汲極電阻。在一些實施例中,源極/汲極接點270包括單一金屬材料。在一些其他實施例中,源極/汲極接點270包含多個金屬層。源極/汲極接點270的材料可包含任何合適的導電材料,比如鈦、氮化鈦、鎳、鉬、鉑、鈷、釕、鎢、氮化鉭、銅、其他合適的導電材料、或上述之組合。源極/汲極接點270的形成方法可為任何合適製程,比如微影製程、蝕刻製程、物理氣相沉積、化學氣相沉積、原子層沉積、電鍍、無電鍍、其他合適沉積製程、或上述之組合。之後可由平坦化製程如化學機械研磨製程移除多餘導電材料,以平坦化裝置200的上表面。
如圖20A至20C所示,方法100進行額外製程以完成製作裝置200。舉例來說,步驟170可形成多種接點、通孔(如閘極通孔276及/或源極/汲極通孔278)、層間介電層(如接點蝕刻停止層272與層間介電層274)、線路、與多層內連線結構於基板202上,且上述結構設置為連接多種結構以形成含有一或多個多閘極裝置的功能電路。
圖20C顯示具有多個奈米結構的裝置200之剖視圖。如圖20C所示,每一奈米結構包括多個通道半導體層如第二半導體層210B位於基板202上。通道半導體層如第二半導體層210B沿著通常垂直於基板的上表面之方向(如Z方向)堆疊且彼此分隔。保護介電層212位於奈米結構上並與奈米結構分隔。保護介電層212在X-Y平面中的形狀與尺寸,分別與通道半導體層如第二半導體層210B在X-Y平面中的形狀與尺寸實質上相同。保護介電層212的高度H3為約2 nm至30 nm。每一通道半導體層如第二半導體層210B的高度H2為約3 nm至15 nm。每一金屬閘極堆疊268包括包覆個別奈米結構中的每一通道半導體層(如第二半導體層210B)之閘極介電層(比如閘極界面層262及/或閘極介電層264),以及位於閘極介電層上的金屬閘極266。如圖20C所示,閘極介電層(如閘極介電層264)夾設於金屬閘極266與保護介電層212之間並直接接觸保護介電層212,且保護介電層212位於金屬閘極266的至少一部分上。保護介電層212與頂部的通道半導體層如第二半導體層210B之間的距離如高度H4,以及相鄰的通道半導體層如第二半導體層210B之間的距離如高度H4實質上相同,比如約4 nm至15 nm。內側間隔物230位於保護介電層212與頂部的通道半導體層如第二半導體層210B之間,並位於相鄰的通道半導體層如第二半導體層210B之間。接點蝕刻停止層272沉積於保護介電層212上,且接點蝕刻停止層272的下表面直接接觸保護介電層212的上表面。源極/汲極接點270位於裝置200的源極/汲極區中的磊晶的源極/汲極結構240上。源極/汲極通孔278位於源極/汲極接點270上,並穿過層間介電層274與接點蝕刻停止層272。
圖21A至21C與22A至22C係一些實施例中,包括自對準接點介電層280之半導體的裝置300。方法100所形成的裝置300,與圖2A至2C到圖18A至18C所示的裝置200具有實質上相同的三維圖與剖視圖。之後如圖21A至21C所示,步驟165形成自對準接點介電層280於金屬閘極266上。在一些實施例中,以合適製程如濕蝕刻、乾蝕刻、或上述之組合的蝕刻製程,移除金屬閘極266的頂部268T。之後可將介電材料置於凹陷的金屬閘極266與保護介電層212上。在一些實施例中,介電材料可包括氮化矽、氧化矽、氮氧化矽、碳氧化矽、碳氮氧化矽、其他介電材料、或上述之組合。接著進行化學機械研磨製程以移除多餘介電材料,直到露出保護介電層212的上表面。保留的介電材料形成自對準接點介電層280。如圖21A與21B所示,保護介電層212在X方向中插入自對準接點介電層280。自對準接點介電層280的上表面與保護介電層212實質上共平面。
如圖22A至22C所示,進行額外製程以完成製作裝置300。舉例來說,步驟170形成多種接點(如源極/汲極接點270)於裝置300的源極/汲極區中磊晶的源極/汲極結構240上;形成層間介電層(如接點蝕刻停止層272與層間介電層274)於自對準接點介電層280與保護介電層212上,使自對準接點介電層280與保護介電層212的上表面直接接觸層間介電層的下表面;並形成多種通孔(如閘極通孔276與源極/汲極通孔278)、線路、與多層內連線結構於基板202上,其設置為連接多種結構以形成含一或多個多閘極裝置的功能電路。
本發明的一或多個實施例可提供許多優點至半導體裝置與其形成製程,但不限於此。舉例來說,本發明實施例提供的半導體裝置具有保護介電層於垂直堆疊的通道半導體層上,因此在虛置閘極蝕刻製程時可保護頂部的通道半導體層免於損傷。因此可緩解習知的半導體裝置中高電阻或通道開路的問題。此外,化學機械研磨金屬閘極的製程時,保護介電層可作為停止層,使不同晶圓之間的閘極移除差異,小於習知時控的化學機械研磨或回蝕刻製程。此外,保護介電層可讓頂部的通道半導體層上的金屬閘極部分,與相鄰的通道半導體層之間的金屬閘極部分具有相同尺寸。如此一來,半導體裝置的頂部通道與其他通道之臨界電壓,比習知半導體裝置的頂部通道與其他通道之臨界電壓更一致。因此本發明實施例中的保護介電層,可減少製造方法的缺陷,並改善半導體裝置的效能。
本發明提供許多不同實施例。此處接露具有保護介電層的半導體裝置與其製作方法。例示性的半導體裝置包括基板;多個半導體層,位於基板上,其中半導體層沿著通常垂直於基板的上表面之方向堆疊並彼此分隔;介電結構,位於半導體層上並與半導體層分隔;以及閘極結構,包覆半導體層的每一者,閘極結構具有閘極介電層與閘極層,其中閘極介電層夾設於閘極層與介電結構之間,且介電結構位於閘極層的至少一部分上。
在一些實施例中,介電結構的下表面與半導體層的頂層之上表面之間的距離,與相鄰的半導體層之間的距離實質上相同。在一些實施例中,介電結構的側表面與下表面直接接觸閘極介電層。在一些實施例中,介電結構的上表面與閘極結構的上表面實質上共平面。在一些實施例中,每一半導體層為奈米片或奈米線。
在一些實施例中,半導體裝置更包括沿著閘極結構的側壁之閘極間隔物;以及沿著閘極間隔物的側壁之接點蝕刻停止層,其中介電結構延伸穿過閘極間隔物以接觸接點蝕刻停止層。在一些實施例中,半導體裝置更包括內側間隔物於介電結構與半導體層的頂層之間,其中介電結構的下表面直接接觸內側間隔物的上表面。在一些實施例中,半導體裝置更包括自對準接點介電層形成於閘極結構上,其中自對準接點介電層與介電結構在沿著垂直於閘極長度方向的方向中分隔。
另一半導體裝置包括基板;多個半導體層,位於基板上,其中半導體層沿著通常垂直於基板上表面的方向堆疊並彼此分隔;保護介電結構,位於半導體層上並與半導體層分隔;閘極結構,包覆每一半導體層;以及蝕刻停止層,位於保護介電結構與半導體層上,且蝕刻停止層的下表面直接接觸保護介電結構的上表面。
在一些實施例中,閘極結構的頂部包括溝槽,保護介電結構形成於溝槽中,且蝕刻停止層的下表面直接接觸閘極結構的上表面。在一些實施例中,在垂直於閘極長度的方向中,保護介電結構的寬度與半導體層的寬度實質上相同。
在一些實施例中,半導體裝置更包括自對準接點介電層位於閘極結構上,其中蝕刻停止層的下表面直接接觸自對準接點介電層的上表面。
例示性的半導體裝置的形成方法包括接收結構,其包含基板與交錯的第一半導體層與第二半導體層之堆疊位於基板上,其中堆疊的頂層為第一半導體層,且包括的材料不同於第二半導體層與基板;形成保護介電層於堆疊上,其中保護介電層的下表面直接接觸堆疊之頂層的上表面;選擇性移除第一半導體層,使第二半導體層與保護介電層懸空於基板上;以及在選擇性移除第一半導體層之後,形成金屬閘極堆疊包覆第二半導體層與保護介電層。
在一些實施例中,上述方法更包括平坦化金屬閘極堆疊以露出保護介電層。在一些實施例中,上述方法更包括使金屬閘極堆疊的頂部凹陷;沉積導電材料於凹陷的金屬閘極堆疊與保護介電層上;以及平坦化導電材料,以露出保護介電層。在一些實施例中,方法更包括沉積層間介電層於金屬閘極堆疊與保護介電層上。
在一些實施例中,形成保護介電層的步驟包括:沉積保護介電層於堆疊的頂層上;沉積硬遮罩於保護介電層上;圖案化硬遮罩;採用硬遮罩作為蝕刻遮罩,並蝕刻保護介電層與堆疊;以及移除硬遮罩。在一些實施例中,形成金屬閘極堆疊的步驟包括沉積閘極介電層以包覆第二半導體層與保護介電層;以及沉積閘極層於閘極介電層上。
在一些實施例中,上述方法更包括在選擇性移除第一半導體層之前,形成虛置閘極結構於保護介電層與堆疊上;沿著虛置閘極結構的側壁形成閘極間隔物;形成磊晶的源極/汲極結構以連接至第二半導體層;以及移除虛置閘極結構以露出保護介電層與堆疊。在一些其他實施例中,上述方法更包括:移除保護介電層與堆疊的一部分,以形成溝槽露出基板;自溝槽選擇性移除第一半導體層的部分,以形成間隙;以及形成內側間隔物於間隙中。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明作基礎,設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解,這些等效置換並未脫離本發明精神與範疇,並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
B-B',C-C':平面
H1,H2,H3,H4:高度
W1,W2,W3:寬度
100:方法
105,110,115,120,125,130,135,140,145,150,155,160, 165,170:步驟
200,300:裝置
202:基板
210:堆疊
210A:第一半導體層
210B:第二半導體層
212:保護介電層
214,224:硬遮罩層
218:隔離結構
220:界面層
222:虛置閘極層
225:虛置閘極堆疊
226:閘極間隔物
226':間隔物層
228:源極/汲極溝槽
229:間隙
230:內側間隔物
240:磊晶的源極/汲極結構
252,272:接點蝕刻停止層
254,274:層間介電層
256:閘極溝槽
258,260:空間
262:閘極界面層
264:閘極介電層
266:金屬閘極
268:金屬閘極堆疊
268T:頂部
270:源極/汲極接點
276:閘極通孔
278:源極/汲極通孔
280:自對準接點介電層
圖1係本發明一些實施例中,製造半導體裝置的方法之流程圖。
圖2A、3A、4A、5A、6A、7A、8A、9A、10A、11A、12A、13A、14A、15A、16A、17A、18A、19A、與20A顯示本發明一些實施例中,半導體裝置在圖1的方法之中間階段的三維透視圖。
圖2B、3B、4B、5B、6B、7B、8B、9B、10B、11B、12B、13B、14B、15B、16B、17B、18B、19B、與20B顯示本發明一些實施例中,半導體裝置在圖1的方法之中間階段沿著Y-Z平面的剖視圖。
圖2C、3C、4C、5C、6C、7C、8C、9C、10C、11C、12C、13C、14C、15C、16C、17C、18C、19C、與20C顯示本發明一些實施例中,半導體裝置在圖1的方法之中間階段沿著X-Z平面的剖視圖。
圖21A與22A顯示本發明一些實施例中,半導體裝置在圖1的方法之中間階段的三維透視圖。
圖21B與22B顯示本發明一些實施例中,半導體裝置在圖1的方法之中間階段沿著Y-Z平面的剖視圖。
圖21C與22C顯示本發明一些實施例中,半導體裝置在圖1的方法之中間階段沿著X-Z平面的剖視圖。
100:方法
105,110,115,120,125,130,135,140,145,150,155,160,165,170:步驟
Claims (1)
- 一種半導體裝置,包括: 一基板; 多個半導體層,位於該基板上,其中該些半導體層沿著通常垂直於該基板的上表面之一方向堆疊並彼此分隔; 一介電結構,位於該些半導體層上並與該些半導體層分隔;以及 一閘極結構,包覆該些半導體層的每一者,該閘極結構具有一閘極介電層與一閘極層,其中該閘極介電層夾設於該閘極層與該介電結構之間,且該介電結構位於該閘極層的至少一部分上。
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US11282935B2 (en) | 2019-09-26 | 2022-03-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate-all-around device with protective dielectric layer and method of forming the same |
KR20210055139A (ko) | 2019-11-06 | 2021-05-17 | 삼성전자주식회사 | 반도체 소자 |
US11257903B2 (en) * | 2019-11-27 | 2022-02-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for manufacturing semiconductor structure with hybrid nanostructures |
KR20210124731A (ko) * | 2020-04-07 | 2021-10-15 | 삼성전자주식회사 | 게이트 스페이서를 갖는 반도체 소자들 |
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TW202310066A (zh) * | 2021-08-30 | 2023-03-01 | 美商應用材料股份有限公司 | 環繞式閘極電晶體中的源極汲極形成 |
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US8823065B2 (en) | 2012-11-08 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of semiconductor device |
US9105490B2 (en) | 2012-09-27 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of semiconductor device |
US8772109B2 (en) | 2012-10-24 | 2014-07-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and method for forming semiconductor contacts |
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US9614056B2 (en) * | 2014-10-28 | 2017-04-04 | Globalfoundries Inc. | Methods of forming a tri-gate FinFET device |
US9520482B1 (en) | 2015-11-13 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting metal gate |
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US11158544B2 (en) * | 2019-03-15 | 2021-10-26 | International Business Machines Corporation | Vertical stacked nanosheet CMOS transistors with different work function metals |
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