TW202201782A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW202201782A
TW202201782A TW110106461A TW110106461A TW202201782A TW 202201782 A TW202201782 A TW 202201782A TW 110106461 A TW110106461 A TW 110106461A TW 110106461 A TW110106461 A TW 110106461A TW 202201782 A TW202201782 A TW 202201782A
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Taiwan
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source
layer
drain
semiconductor
epitaxial
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TW110106461A
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English (en)
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陳定業
李威養
林家彬
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台灣積體電路製造股份有限公司
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Priority claimed from US17/127,343 external-priority patent/US11855225B2/en
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202201782A publication Critical patent/TW202201782A/zh

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Abstract

此處揭露半導體裝置與其形成方法。例示性的半導體裝置包括多個半導體層位於基板上，其中半導體層向上堆疊並彼此分開，每一半導體層包括第一部分位於基板的第一通道區中與第二部分位於基板的第二通道區中；多個磊晶層，形成於第一通道區與第二通道區之間的源極/汲極區中，其中磊晶層彼此分開，且每一磊晶層形成於每一半導體層的第一部分與第二部分之間；以及導電結構，包覆每一磊晶層。

Description

半導體裝置
本發明實施例通常關於半導體裝置與其製作方法，更特別關於製作場效電晶體如全繞式閘極場效電晶體的方法。
積體電路產業已經歷指數成長。已導入多閘極裝置以增加閘極-通道耦合並減少關閉狀態電流，進而改善閘極控制。多閘極裝置之一為全繞式閘極裝置(亦視作奈米結構裝置)。全繞式閘極裝置通常指的是閘極結構或其部分形成於通道區的多側上(比如圍繞通道區的一部分)的任何裝置。全繞式閘極電晶體可大幅減少電晶體的尺寸。然而尺寸縮小亦增加處理與製造積體電路的複雜度。在習知的全繞式閘極裝置中，雖然通道的半導體層彼此分開，但磊晶的源極/汲極結構為基體結構。由於基體源極/汲極結構的尺寸，基體源極/汲極結構的充放電時間較長且電容較大。因此劣化半導體裝置的效能。因此需改善半導體裝置。
在一實施例中，提供半導體裝置。半導體裝置包括多個半導體層位於基板上。半導體層向上堆疊並彼此分開。每一半導體層包括第一部分位於基板的第一通道區中，與第二部分位於基板的第二通道區中。半導體裝置亦可包括多個磊晶層，形成於第一通道區與第二通道區之間的源極/汲極區中。磊晶層彼此分開，且每一磊晶層形成於每一半導體層的第一部分與第二部分之間。導電結構包覆每一磊晶層。
本發明另一實施例提供半導體裝置。半導體裝置可包括第一半導體層位於基板的第一通道區上，以及第二半導體層位於基板的第二通道區上。第一半導體層向上堆疊且彼此分開，且第二半導體層向上堆疊並彼此分開。半導體裝置可包含磊晶層形成於基板的源極/汲極區之中以及第一半導體層的一者與第二半導體層的一者之間，導電結構以包覆源極/汲極區中的磊晶層，以及底部結構形成於導電結構與基板之間。磊晶層的下表面高於基板的上表面。
本發明又一實施例提供半導體裝置的形成方法。方法可包括交錯形成第一半導體層與第二半導體層於基板上，其中第一半導體層與第二半導體層包含不同材料，且沿著實質上垂直於基板上表面的方向向上堆疊；形成虛置閘極結構於第一半導體層與第二半導體層上；沿著虛置閘極結構的側壁形成源極/汲極溝槽，使源極/汲極溝槽截斷第一半導體層與第二半導體層；以及形成磊晶層於源極/汲極溝槽中截斷的第一半導體層之間，其中沿著實質上垂直於基板上表面的方向分開磊晶層。
下述詳細描述可搭配圖式說明，以利理解本發明的各方面。值得注意的是，各種結構僅用於說明目的而未按比例繪製，如本業常態。實際上為了清楚說明，可任意增加或減少各種結構的尺寸。
下述內容提供的不同實施例或例子可實施本發明實施例的不同結構。特定構件與排列的實施例係用以簡化本揭露而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。
此外，本發明之多種實例可重複採用相同標號以求簡潔，但多種實施例及/或設置中具有相同標號的元件並不必然具有相同的對應關係。此外，本發明實施例之結構形成於另一結構上、連接至另一結構、及/或耦接至另一結構中，結構可直接接觸另一結構，或可形成額外結構於結構及另一結構之間。此外，空間性的相對用語如「下方」、「其下」、「下側」、「上方」、「上側」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。此外，當數值或數值範圍的描述有「約」、「近似」、或類似用語時，除非特別說明否則其包含所述數值的+/-10%。舉例來說，用語「約5 nm」包含的尺寸範圍為4.5 nm至5.5 nm。
在全繞式閘極裝置中，單一裝置的通道區可包含彼此物理分隔的多個半導體材料層。在一些例子中，裝置的閘極位於裝置的半導體層上、沿著半導體的側部、且甚至位於半導體層之間。在習知的全繞式閘極裝置中，磊晶的源極/汲極結構為磊晶成長於半導體裝置的源極/汲極區中的基體結構。由於磊晶的源極/汲極結構之充放電與磊晶的源極/汲極結構的尺寸相關，大尺寸的基體磊晶結構需要較長的充放電時間並造成大電容。在本發明實施例中，基於全繞式閘極裝置的特定通道輪廓(比如通道半導體層彼此物理分開)，磊晶源極/汲極結構可成長於通道半導體層的對應部分之間(如橋狀物)。橋狀的磊晶的源極/汲極層可有效作為磊晶的源極/汲極結構但尺寸較小。與基體磊晶結構相較，較小尺寸的磊晶結構所需的充放電時間較短且電容較小。接著形成源極/汲極接點以包覆每一磊晶層。此外，可形成底部的介電結構於源極/汲極接點與基板之間，以減少兩者之間的漏電流。因此可增加半導體裝置的速度並減少電容。如此一來，可改善半導體裝置的效能。
圖1顯示本發明一些實施例中，製造半導體的裝置200之方法100的流程圖。方法100僅為舉例而非侷限本發明實施例至請求項未實際記載處。在方法100之前、之中、與之後可進行額外步驟，且方法的額外實施例可置換、省略、或調換一些所述步驟。方法100將搭配其他圖式說明如下，且其他圖式顯示裝置200在方法100的中間步驟時的多種三維圖與剖視圖。具體而言，圖2為本發明一些實施例中，裝置200的初始結構之三維圖。圖3A至16A係本發明一些實施例中，裝置200在方法100的中間階段沿著圖2所示的剖面A-A’ (如Y-Z平面)的剖視圖。圖3B至16B係本發明一些實施例中，裝置200在方法100的中間階段沿著圖2所示的剖面B-B’ (如X-Z平面)的剖視圖。
裝置200可為處理積體電路或其部分時所製作的中間裝置，其可包含靜態隨機存取記憶體及/或其他邏輯電路、被動構件(如電阻、電容器、或電感)、與主動構件(如p型場效電晶體、n型場效電晶體、金氧半場效電晶體、互補式金氧半電晶體、雙極電晶體、高電壓電晶體、高頻電晶體、及/或其他記憶體單元。裝置200可為積體電路的核心區(通常視作邏輯區)、記憶體區(如靜態隨機存取記憶體區)、類比區、周邊區(通常視作輸入/輸出區)、虛置區、其他合適區、或上述之組合的一部分。在一些實施例中，裝置200可為積體電路晶片的一部分、單晶片系統、或其部分。本發明實施例不限於任何特定數目的裝置或裝置區，或任何特定裝置設置。
如圖1、2、3A、及3B所示，步驟102形成裝置200的初始半導體結構。如圖2、3A、及3B所示，裝置200包括基板202。在所述實施例中，基板202為基體矽基板。在其他實施例或額外實施例中，基板202包括另一單晶半導體如鍺、半導體化合物、半導體合金、或上述之組合。在其他實施例中，基板202為絕緣層上半導體基板，比如絕緣層上矽基板、絕緣層上矽鍺基板、或絕緣層上鍺基板。基板202可摻雜不同摻質，以形成多種摻雜區於其中。舉例來說，基板202可包括含n型摻雜基板區(如n型井)的p型場效電晶體區，與含p型摻雜基板區(如p型井)的n型場效電晶體區。
裝置200包含交錯的半導體層形成於基板202上，比如含有第一半導體材料的半導體層210A與含有第二半導體材料的半導體層210B，且第一半導體材料與第二半導體材料不同。半導體層210A及210B的不同半導體材料，具有不同的氧化速率及/或不同的蝕刻選擇性。在一些實施例中，半導體層210A的第一半導體材料與基板202相同。舉例來說，半導體層210A包括矽(如基板202)，且半導體層210B包括矽鍺。因此可由下至上排列交錯的矽鍺/矽/矽鍺/矽…層。在一些實施例中，頂部半導體層的材料可或可不與底部的半導體層的材料相同。在一些實施例中，在形成半導體層210A時，不刻意進行摻雜。在一些其他實施例中，半導體層210A可摻雜p型摻質或n型摻質。半導體層210A及210B的數目取決於裝置200的設計需求。舉例來說，半導體層210A及210B的數目可各自為一至十層。在一些實施例中，不同的半導體層210A及210B在Z方向中可具有相同厚度。在一些其他實施例中，不同半導體層210A及210B可具有不同厚度。如圖3B所示，每一半導體層210A在Z方向中可具有厚度H1，而每一半導體層210B在Z方向中可具有厚度H2。在一些實施例中，厚度H1為約5 nm至約20 nm，而厚度H2為約5 nm至約20 nm。在一些實施例中，半導體層210A及/或210B的形成方法可為合適的磊晶製程。舉例來說，半導體層包括矽鍺層與矽層交錯形成於基板202上，其形成方法可為分子束磊晶製程、化學氣相沉積製程如有機金屬化學氣相沉積製程、及/或其他合適的磊晶成長製程。
之後可圖案化交錯的半導體層210A及210B，以形成半導體的堆疊210。在一些實施例中，可對半導體層210A及210B進行多種光阻微影與蝕刻製程，以形成圖示之鰭狀的堆疊210。舉例來說，先形成圖案化的光阻遮罩於裝置200上。圖案化的光阻遮罩覆蓋鰭狀物的位置依據裝置200的設計需求。之後採用圖案化的光阻遮罩並進行一或多道蝕刻製程，以移除半導體層210A及210B的露出部分。半導體層210A與半導體層210B的保留部分可形成鰭狀的堆疊210。在一些實施例中，亦移除基板202的頂部。蝕刻製程可包含乾蝕刻、濕蝕刻、其他合適的蝕刻製程、或上述之組合。此外，接著採用任何合適方法移除光阻遮罩。
之後形成隔離結構於堆疊210之間的溝槽中，以分開並隔離裝置200的主動區。在一些實施例中，一或多種介電材料如氧化矽及/或氮化矽沿著堆疊210的側壁沉積於基板202上。介電材料的沉積方法可為化學氣相沉積如電漿輔助化學氣相沉積、物理氣相沉積、熱氧化、或其他技術。之後可使介電材料凹陷(比如以蝕刻及/或化學機械研磨等方法)，以形成隔離結構204。在一些實施例中，隔離結構204的上表面低於最底部的半導體層210B的下表面或與其共平面，如圖3A所示，
之後形成虛置閘極結構220於堆疊210上。每一虛置閘極結構220可作為後續形成金屬閘極結構所用的占位物。在一些實施例中，虛置閘極結構220沿著Y方向延伸，並越過個別的堆疊210。虛置閘極結構220覆蓋堆疊210的通道區，其夾設於源極區與汲極區(均視作源極/汲極區)之間。每一虛置閘極結構220可包含多種虛置層，比如界面層(未圖示)、虛置閘極212 (含多晶矽)、一或多個硬遮罩層214及216 (含介電材料如氮化矽、碳氮化矽、氧化矽、或類似物)、及/或其他合適層狀物。虛置閘極結構220的形成方法為沉積製程、微影製程、蝕刻製程、其他合適製程、或上述之組合。舉例來說，沉積不同虛置層於堆疊210上。接著進行微影製程以形成遮罩覆蓋堆疊210的通道區。之後可採用微影遮罩並蝕刻不同虛置層，以形成虛置閘極結構220。此外，可採用任何合適方法移除微影遮罩。
接著形成閘極間隔物層218’於裝置200上，比如形成於隔離結構204上、沿著虛置閘極結構220的側壁與上表面、以及沿著堆疊210的側壁與上表面。在一些實施例中，閘極間隔物層218’包括介電材料如氧化矽、氮化矽、氮氧化矽、碳化矽、其他介電材料、或上述之組合。閘極間隔物層218’的形成方法可為沉積製程如原子層沉積、化學氣相沉積、物理氣相沉積、或其他合適製程。
如圖1、4A、4B、5A、及5B所示，步驟104非等向蝕刻間隔物層218’以形成閘極間隔物218。如圖4A及4B所示，進行非等向蝕刻以移除X-Y平面(基板202的上表面所在的平面)中的間隔物層218’的部分。間隔物層的保留部分轉變成閘極間隔物218。非等向蝕刻包含濕蝕刻、乾蝕刻、或上述之組合。如圖5A及5B所示，步驟104以合適的蝕刻製程移除源極/汲極區中沿著堆疊210的側壁的間隔物218。如圖5B所示，相鄰的沿著虛置閘極結構220的間隔物218之間的距離W1可為約30 nm至約50 nm。
之後如圖1、6A、及6B所示，步驟106形成源極/汲極溝槽222於堆疊210的源極/汲極區中。在一些實施例中，以源極/汲極蝕刻製程沿著閘極間隔物218的側壁使堆疊210凹陷，以形成源極/汲極溝槽222。源極/汲極蝕刻製程可為乾蝕刻製程(如反應性離子蝕刻)、濕蝕刻製程、或上述之組合。控制源極/汲極蝕刻製程的時間，使每一半導體層210A及210B的側壁暴露於源極/汲極溝槽222中。換言之，如圖6B所示，源極/汲極溝槽222截斷半導體層210A及210B。每一半導體層210A分成兩個或更多個對應部分。以圖6B為例，半導體層部分210A-1對應半導體層部分210A-2，半導體層部分210A-1’對應半導體層部分210A-2’，而半導體層部分210A-1”對應半導體層部分210A-2”。
如圖1、7A、及7B所示，步驟108形成內側間隔物224於半導體層210A的邊緣部分之間。在一些實施例中，以合適的蝕刻製程選擇性移除源極/汲極溝槽222中露出的半導體層210B的部分(邊緣)，以形成間隙於半導體層210A的邊緣部分之間。換言之，半導體層210A的邊緣部分懸空於源極/汲極溝槽222中。由於半導體層210A (如矽)及210B (如矽鍺)的氧化速率及/或蝕刻選擇性不同，只移除半導體層210B的露出部分(邊緣)，而半導體層210A維持實質上不變。在一些實施例中，選擇性移除半導體層210B的露出部分的方法，可包含氧化製程與之後的選擇性蝕刻製程。舉例來說，先選擇性氧化半導體層210B的邊緣部分，使其包含氧化矽鍺的材料。接著以合適的蝕刻劑如氫氧化銨或氫氟酸進行選擇性蝕刻製程以移除氧化矽鍺。可控制氧化製程與選擇性蝕刻製程的時間，以只選擇性移除半導體層210B的邊緣部分。
之後形成內側間隔物224以填入半導體層210A之間的間隙。內側間隔物224包括與閘極間隔物218的材料類似之介電材料，比如氧化矽、氮化矽、氮氧化矽、碳化矽、或上述之組合。內側間隔物的介電材料可沉積於源極/汲極溝槽222中，以及半導體層210A的邊緣之間的間隙中，且其沉積方法可為化學氣相沉積、物理氣相沉積、原子層沉積、或上述之組合。接著沿著閘極間隔物218的側壁移除多餘介電材料，直到源極/汲極溝槽222中露出半導體層210A的側壁。
如圖1、8A、8B、9A、及9B所示，步驟110使源極/汲極溝槽222進一步凹陷，並形成底部結構226於源極/汲極溝槽222的進一步凹陷部分中。如圖8A及8B所示，進一步蝕刻源極/汲極溝槽222，以移除基板202的頂部，並使源極/汲極溝槽222的下表面低於最下側的半導體層210B的下表面。在一些實施例中，進一步蝕刻源極/汲極溝槽222的深度H3為約20 nm至約40 nm。
如圖9A及9B所示，底部結構226形成於源極/汲極溝槽222的進一步凹陷部分中。在一些實施例中，底部結構226包括不同於第二半導體層的材料之未摻雜的磊晶材料，比如碳化矽、砷化鎵、類似物、半導體合金、或上述之組合。磊晶材料未摻雜而具有高電阻，且可緩解預期之外的漏電流。底部結構226磊晶成長於源極/汲極溝槽222的進一步凹陷部分中的方法可為化學氣相沉積(如氣相磊晶、超高真空化學氣相沉積、低壓化學氣相沉積、及/或電漿輔助化學氣相沉積)、分子束磊晶、其他合適的選擇性磊晶成長製程、或上述之組合。如圖9A及9B所示，底部結構226的上表面低於最底部的半導體層210A (含半導體層部分210A-1”及210A-2”)的下表面。在一些實施例中，底部結構226的上表面與最下側的半導體層210B之下表面 (如基板202的上表面)實質上共平面。在一些其他實施例中，底部結構226的上表面高於最下側的半導體層210B的下表面 (如基板202的上表面)。如圖9B所示，底部結構226在Z方向中具有厚度H4。在一些實施例中，厚度H4為約20 nm至約60 nm，其可為半導體層210A或210B的厚度H1或H2的約1倍至約10倍。底部結構226不可過薄，否則無法提供足夠電阻而可能發生預期之外的漏電流。底部結構226不可過厚，否則可能增加預期之外的電容。
如圖1、10A、及10B所示，步驟112磊晶成長源極/汲極層230於源極/汲極溝槽222中的半導體層210A的對應部分之間。在一些實施例中，磊晶的源極/汲極層230包括半導體材料(如矽或鍺)、半導體化合物(如矽鍺、碳化矽、砷化鎵、或類似物)、半導體合金、或上述之組合。可實施磊晶製程以磊晶成長源極/汲極層230。磊晶製程可包含化學氣相沉積(比如氣相磊晶、超高真空化學氣相沉積、低壓化學氣相沉積、及/或電漿輔助化學氣相沉積)、分子束磊晶、其他合適的選擇性磊晶成長製程、或上述之組合。在一些實施例中，進行循環沉積/蝕刻製程以形成源極/汲極層230。舉例來說，當磊晶成長半導體材料時，可提供蝕刻氣體如氯氣至成長製程中。因此結晶晶格僅成長於X方向中，以在Z方向中形成而不合併源極/汲極層230。如圖10B所示，結晶層形成於半導體層210A的對應部分之側壁之間，並連接源極/汲極溝槽222中的半導體層210A之對應部分。換言之，結晶層形成橋於源極/汲極溝槽222中的半導體層210A之對應部分之間。舉例來說，結晶層磊晶成長於半導體層部分210A-1及210A-2之間、半導體層部分210A-1’及210A-2’之間、以及半導體層部分210A-1”及210A-2”之間，並形成橋狀的磊晶半導體層如源極/汲極層230於上述部分之間。在一些實施例中，當源極/汲極層230的形成方法為循環沉積/蝕刻製程時，實施蝕刻氣體會造成源極/汲極層的中間部分厚度小於源極/汲極層的邊緣部分厚度。如圖10B所示，磊晶的源極/汲極層230沿著方向D成長，而方向D與X方向具有角度α。在一些實施例中，角度α小於約45度，使磊晶的源極/汲極層230不會在中間分開。
在第一半導體層的厚度H1 (比如源極/汲極層230的邊緣部分厚度)與第一半導體層的對應部分之間的距離W1 (比如源極/汲極溝槽222在X方向的寬度)具有合適比例H1/W1時，可磊晶成長結晶層以形成彼此物理分開的磊晶的源極/汲極層230。換言之，在Z方向中形成而不合併磊晶的源極/汲極層230。此外，半導體層在Y方向中的距離(如半導體層210B的厚度H2)亦有助於確保隔離磊晶的源極/汲極層230。合適的比例H/W亦可為磊晶的源極/汲極層230之厚度(在Z方向中)與長度(在X方向中)的比例。在一些實施例中，合適的比例H/W可為約0.1至約0.6。若比例過大，則源極/汲極層可在Z方向中合併。若比例過小，則源極/汲極層可能會在中間中斷。如圖10B所示，每一磊晶的源極/汲極層230在Z方向中的厚度H1為約5 nm至約20 nm，每一磊晶的源極/汲極層230在X方向中的長度如距離W1為約30 nm至約50 nm，且第一半導體層210A之間在Z方向中的距離如厚度H2為約5 nm至約20 nm。如圖10B所示，底部空洞228形成於最底側的磊晶的源極/汲極層230與底部結構226之間。如圖10B所示，每一磊晶的源極/汲極層230的中間部分至少具有磊晶的源極/汲極層230的厚度如深度H3。在一些實施例中，厚度如深度H3為每一磊晶的源極/汲極層230之邊緣部分的厚度H1的約20%至約100%。厚度如深度H3過小則磊晶的源極/汲極層230易破損。由於循環沉積/蝕刻製程的固有成長角度α，厚度如深度H3不會超過100%的厚度H1。
在習知的全繞式閘極裝置中，磊晶的源極/汲極結構為形成於全繞式閘極裝置的源極/汲極區中的基體結構。然而本發明實施例基於全繞式閘極裝置之分開的通道半導體層(比如半導體層210A)，源極/汲極結構磊晶成長於源極/汲極區中，如分開的磊晶層(比如橋狀的磊晶的源極/汲極層)位於通道半導體層的對應部分之間。與習知的基體源極/汲極結構相較，本發明的磊晶結構(如分開的磊晶的源極/汲極層)的尺寸減少。如此一來，可減少磊晶結構的充放電時間，並增加半導體裝置的速度。此外，較小尺寸的磊晶結構與習知的基體尺寸的磊晶結構相較，造成的電容較小。因此可改善半導體裝置效能。
如圖1、11A、11B、12A、12B、13A、及13B所示，步驟114進行金屬閘極置換製程以將虛置閘極結構220置換成金屬閘極結構240。金屬閘極置換製程包括多種製程步驟。以圖11A及11B為例，層間介電層232形成於基板202上。舉例來說，層間介電層232沿著閘極間隔物218、位於隔離結構204上、並位於磊晶的源極/汲極層230周圍。在一些實施例中，層間介電層232包括低介電常數(小於3.9)的介電材料，比如四乙氧基矽烷的氧化物、未摻雜的矽酸鹽玻璃、或摻雜氧化矽(如硼磷矽酸鹽玻璃、氟矽酸鹽玻璃、磷矽酸鹽玻璃、或硼矽酸鹽玻璃)、其他合適介電材料、或上述之組合。層間介電層232的形成方法可為沉積製程如化學氣相沉積、可流動的化學氣相沉積、旋轉塗佈玻璃、其他合適方法、或上述之組合。
之後移除虛置閘極結構220以形成閘極溝槽234，並露出堆疊210的通道區。在一些實施例中，移除虛置閘極結構220的方法包括一或多種蝕刻製程，比如濕蝕刻、乾蝕刻、反應性離子蝕刻、或其他蝕刻技術。在一些實施例中，步驟114亦移除層間介電層232與閘極間隔物218的頂部。接著露出閘極溝槽234中的半導體層210A及210B。
之後如圖12A及12B所示，自閘極溝槽234選擇性移除半導體層210B。由於半導體層210A及210B的材料不同，半導體層210B的移除方法可與移除半導體層210B的邊緣部分的選擇性氧化與蝕刻製程類似。在一些實施例中，步驟114稍微蝕刻或不蝕刻半導體層210A。因此半導體層210A懸空於堆疊210的通道區中，並沿著Z方向向上堆疊。Z方向通常垂直於基板202的上表面(如X-Y平面)。懸空的半導體層210A亦可視作通道的半導體層210A。
接著如圖13A及13B所示，形成金屬閘極結構240於堆疊210的通道區中。金屬閘極結構240包覆每一懸空的半導體層210A。在一些實施例中，每一金屬閘極結構240可包含閘極介電層242以包覆每一通道的半導體層210A、金屬閘極244位於閘極介電層242上、以及其他合適層狀物。閘極介電層242包含高介電常數的介電材料，比如氧化鉿、氧化鉿矽、矽酸鉿、氮氧化鉿矽、氧化鉿鑭、氧化鉿鉭、氧化鉿鈦、氧化鉿鋯、氧化鉿鋁、氧化鋯、二氧化鋯、氧化鋯矽、氧化鋁、氧化鋁矽、三氧化二鋁、氧化鈦、二氧化鈦、氧化鑭、氧化鑭矽、三氧化二鉭、五氧化二鉭、氧化釔、鈦酸鍶、氧化鋇鋯、鈦酸鋇、鈦酸鋇鍶、氮化矽、氧化鉿-氧化鋁合金、其他合適的高介電常數的介電材料、或上述之組合。在一些實施例中，閘極介電層242的沉積方法可為化學氣相沉積、物理氣相沉積、原子層沉積、及/或其他合適方法。在一些實施例中，每一金屬閘極244包含一或多個功函數金屬層與基體金屬。功函數金屬層設置為調整對應電晶體的功函數，以達所需的臨界電壓。基體金屬設置以作為功能閘極結構的主要導電部分。在一些實施例中，功函數金屬層的材料可包含鈦鋁、碳化鈦鋁、碳化鉭鋁、氮化鈦鋁、氮化鈦、氮化鎢矽、氮化鉭、碳氮化鎢、鉬、其他材料、或上述之組合。基體金屬可包含鋁、鎢、銅、或上述之合金。金屬閘極244的多種層狀物之形成方法可為任何合適方法，比如化學氣相沉積、原子層沉積、物理氣相沉積、電鍍、化學氧化、熱氧化、其他合適方法、或上述之組合。之後可施加一或多道平坦化製程如化學機械研磨，以移除多餘導電材料並平坦化裝置200的上表面。
如圖1、14A、14B、15A、及15B所示，步驟116形成源極/汲極接點250以包覆每一磊晶的源極/汲極層230。如圖14A及14B所示，以光微影製程與濕蝕刻製程移除源極/汲極區中的層間介電層232，以形成接點溝槽246。在一些實施例中，沿著源極/汲極區中的內側間隔物224與閘極間隔物218保留層間介電層232的一部分。層間介電層232的保留部分在X方向中的厚度實質上等於閘極間隔物218的厚度。因此接點溝槽246中露出磊晶的源極/汲極層230。如上所述，磊晶的源極/汲極層230在Z方向中彼此分開。此外，最底部的磊晶的源極/汲極層230與底部結構226隔有底部空洞228。
如圖15A及15B所示，接著沉積導電材料於接點溝槽246中，可形成源極/汲極接點250以包覆每一磊晶的源極/汲極層230。在一些實施例中，導電材料包括鋁、鎢、銅、其他合適導電材料、或上述之組合。導電材料的沉積方法可為化學氣相沉積、原子層沉積、物理氣相沉積、電鍍、化學氧化、熱氧化、其他合適方法、或上述之組合。在一些實施例中，矽化物層252可形成於源極/汲極接點250與源極/汲極層230之間。在一些實施例中，矽化物層252包括鈦矽化物、鎳矽化物、鉑矽化物、鈷矽化物、鉬矽化物、鈦鉑矽化物、鎳鉑矽化物、其他合適金屬矽化物、或上述之組合。在一些其他實施例中，可在形成源極/汲極接點250之前形成矽化物層252。舉例來說，可沉積金屬層於源極/汲極區中的源極/汲極層230周圍。接著加熱金屬層(如退火製程)，使其與源極/汲極層230反應形成矽化物層252。之後沉積源極/汲極接點250的導電材料於源極/汲極區中。在一些實施例中，矽化物層252可視作源極/汲極接點250的一部分。此外，可施加一或多道平坦化製程如化學機械平坦化，以移除多餘的導電材料並平坦化裝置200的上表面。如圖15A及15B所示，源極/汲極接點250包覆源極/汲極區中的每一磊晶的源極/汲極層230。閘極間隔物218、內側間隔物224、與層間介電層232分開源極/汲極接點250與金屬閘極結構240。此外，填入底部空洞228的源極/汲極接點250的最底部與基板202隔有底部結構226，因此可緩解源極/汲極接點250與基板202之間的漏電流問題。如圖15B所示，源極/汲極接點250 (或矽化物層252)在X方向中具有寬度W2。當寬度W2過大，則源極/汲極接點與金屬閘極結構240之間的隔離過小，造成預期之外的寄生電容。當寬度W2過小，則源極/汲極接點電阻過大。在一些實施例中，寬度W2約為閘極間隔物218之間的寬度如距離W1的約40%至約90%，端視裝置200的設計而定。
如圖1、16A、及16B所示，步驟118進行後續製程以完成製作裝置200。舉例來說，可形成多種接點及/或通孔270及272、金屬線路(未圖示)、以及其他多層內連線結構如層間介電層260及/或蝕刻停止層於裝置200上，其設置為連接多種結構以形成含有不同半導體裝置的功能電路。
本發明的一或多個實施例提供許多優點至半導體裝置與其形成製程，但不侷限於此。舉例來說，本發明實施例提供的半導體裝置包括磊晶的源極/汲極層成長於通道的半導體層之對應部分之間，並形成通道的半導體層之對應部分之間的橋狀物。形成源極/汲極接點以包覆分開的每一磊晶的源極/汲極層，且源極/汲極接點與基板隔有底部的介電結構。分開的磊晶的源極/汲極層可減少磊晶結構的尺寸，因此可減少電容並增加充放電速度。因此可改善半導體裝置的效能。
本發明提供許多不同實施例。在一實施例中，提供半導體裝置。半導體裝置包括多個半導體層位於基板上。半導體層向上堆疊並彼此分開。每一半導體層包括第一部分位於基板的第一通道區中，與第二部分位於基板的第二通道區中。半導體裝置亦可包括多個磊晶層，形成於第一通道區與第二通道區之間的源極/汲極區中。磊晶層彼此分開，且每一磊晶層形成於每一半導體層的第一部分與第二部分之間。導電結構包覆每一磊晶層。
在一些實施例中，半導體裝置可更包括金屬閘極結構以包覆每一半導體層。金屬閘極結構包括金屬閘極堆疊以包覆每一半導體層，以及內側間隔物沿著金屬閘極堆疊的側壁。在一些實施方式中，半導體裝置可更包括層間介電層沿著內側間隔物的側壁形成，其中導電結構接觸層間介電層。在一些例子中，半導體裝置更包括底部結構位於導電結構與基板之間，且底部結構包括未摻雜的磊晶材料。在 些實施例中，半導體裝置可更包括隔離結構以分開半導體裝置的主動區並接觸底部結構的側壁。在一些實施方式中，底部結構的上表面低於最下側的半導體層的下表面。在一些例子中，每一半導體層的厚度與每一半導體層的第一部分與第二部分之間的每一磊晶層的長度之比例為約0.1至約0.6。
本發明另一實施例提供半導體裝置。半導體裝置可包括第一半導體層位於基板的第一通道區上，以及第二半導體層位於基板的第二通道區上。第一半導體層向上堆疊且彼此分開，且第二半導體層向上堆疊並彼此分開。半導體裝置可包含磊晶層形成於基板的源極/汲極區之中以及第一半導體層的一者與第二半導體層的一者之間，導電結構以包覆源極/汲極區中的磊晶層，以及底部結構形成於導電結構與基板之間。磊晶層的下表面高於基板的上表面。
在一些實施例中，底部結構包括未摻雜的磊晶材料，且底部結構的上表面高於基板的上表面或與基板的上表面實質上共平面。在一些實施例中，磊晶層的中間部分厚度小於磊晶層的邊緣部分厚度。在一些實施例中，導電結構包括矽化物層圍繞磊晶層，以及基體金屬位於矽化物層上。
本發明又一實施例提供半導體裝置的形成方法。方法可包括交錯形成第一半導體層與第二半導體層於基板上，其中第一半導體層與第二半導體層包含不同材料，且沿著實質上垂直於基板上表面的方向向上堆疊；形成虛置閘極結構於第一半導體層與第二半導體層上；沿著虛置閘極結構的側壁形成源極/汲極溝槽，使源極/汲極溝槽截斷第一半導體層與第二半導體層；以及形成磊晶層於源極/汲極溝槽中截斷的第一半導體層之間，其中沿著實質上垂直於基板上表面的方向分開磊晶層。
在一些實施例中，形成源極/汲極溝槽的步驟包括：沿著虛置閘極結構的側壁蝕刻，直到露出最下側的第二半導體層的側壁，以形成源極/汲極溝槽；選擇性移除第二半導體層的邊緣部分；以及形成內側間隔物以填入移除的第二半導體層的邊緣部分。在一些實施方式中，形成源極/汲極溝槽的步驟可更包括進一步蝕刻源極/汲極溝槽，使源極/汲極溝槽的下表面低於基板的上表面；以及形成含未摻雜的磊晶材料之底部結構於進一步蝕刻的源極/汲極溝槽中。在一些例子中，底部結構的上表面低於最下側的第一半導體層的下表面。在一些實施例中，方法可更包括沉積層間介電層以包覆源極/汲極溝槽中的磊晶層，其中層間介電層的下表面接觸底部結構的上表面；以及將虛置閘極結構置換成金屬閘極結構。在一些例子中，方法更包括移除層間介電層的一部分，以露出源極/汲極溝槽中的磊晶層。在一些實施例中，方法更包括形成接點結構以包覆源極/汲極溝槽中每一露出的磊晶層，其中接點結構的下表面接觸底部結構的上表面。在一些實施方式中，形成接點結構的步驟包括沉積導電材料層以圍繞露出的磊晶層；進行退火製程以形成矽化物層；以及沉積導電材料於矽化物層上以形成接點結構。在一些實施例中，磊晶層的形成方法為循環沉積蝕刻製程。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明精神與範疇，並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
α:角度 A-A',B-B':剖面 D:方向 H1,H2,H4:厚度 H3:深度 W1:距離 W2:寬度 100:方法 102,104,106,108,110,112,114,116,118:步驟 200:裝置 202:基板 204:隔離結構 210:堆疊 210A,210B:半導體層 210A-1,210A-1',210A-1",210A-2,210A-2’,210A-2”:半導體層部分 212:虛置閘極 214,216:硬遮罩層 218:閘極間隔物 218':閘極間隔物層 220:虛置閘極結構 222:源極/汲極溝槽 224:內側間隔物 226:底部結構 228:底部空洞 230:源極/汲極層 232:層間介電層 234:閘極溝槽 240:金屬閘極結構 242:閘極介電層 244:金屬閘極 246:接點溝槽 250:源極/汲極接點 252:矽化物層 270,272:接點及/或通孔 260:層間介電層
圖1係本發明一些實施例中，製造半導體裝置的方法之流程圖。 圖2係本發明一些實施例中，初始半導體裝置的三維透視圖。 圖3A至16A係本發明一些實施例中，半導體裝置在圖1的方法之中間階段沿著三維圖中的剖線A-A’的剖視圖。 圖3B至16B係本發明一些實施例中，半導體裝置在圖1的方法之中間階段沿著三維圖中的剖線B-B’的剖視圖。
100:方法
102,104,106,108,110,112,114,116,118:步驟

Claims (1)

  1. 一種半導體裝置，包括： 多個半導體層，位於一基板上，其中該些半導體層向上堆疊並彼此分開，每一該些半導體層包括一第一部分位於該基板的一第一通道區中與一第二部分位於該基板的一第二通道區中； 多個磊晶層，形成於該第一通道區與該第二通道區之間的一源極/汲極區中，其中該些磊晶層彼此分開，且每一該些磊晶層形成於每一該些半導體層的該第一部分與該第二部分之間；以及 一導電結構，包覆每一該些磊晶層。
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