CN113130484A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN113130484A
CN113130484A CN202110190045.XA CN202110190045A CN113130484A CN 113130484 A CN113130484 A CN 113130484A CN 202110190045 A CN202110190045 A CN 202110190045A CN 113130484 A CN113130484 A CN 113130484A
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layer
source
semiconductor
drain
epitaxial
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CN202110190045.XA
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Inventor
陈定业
李威养
林家彬
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US17/127,343 external-priority patent/US11855225B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN113130484A publication Critical patent/CN113130484A/zh
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    • H01L29/66409—Unipolar field-effect transistors
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Abstract

本公开实施例提供一种半导体装置。半导体装置包括多个半导体层、多个外延层以及导电结构。多个半导体层位于基板上，其中半导体层向上堆叠并彼此分开，每一半导体层包括第一部分位于基板的第一通道区中与第二部分位于基板的第二通道区中；多个外延层形成于第一通道区与第二通道区之间的源极/漏极区中，其中外延层彼此分开，且每一外延层形成于每一半导体层的第一部分与第二部分之间；导电结构包覆每一外延层。

Description

半导体装置
技术领域
本发明实施例通常涉及半导体装置与其制作方法，尤其涉及制作场效晶体管如全绕式栅极场效晶体管的方法。
背景技术
集成电路产业已经历指数成长。已导入多栅极装置以增加栅极-通道耦合并减少关闭状态电流，进而改善栅极控制。多栅极装置之一为全绕式栅极装置(亦视作纳米结构装置)。全绕式栅极装置通常指的是栅极结构或其部分形成于通道区的多侧上(比如围绕通道区的一部分)的任何装置。全绕式栅极晶体管可大幅减少晶体管的尺寸。然而尺寸缩小亦增加处理与制造集成电路的复杂度。在公知的全绕式栅极装置中，虽然通道的半导体层彼此分开，但外延的源极/漏极结构为基体结构。由于基体源极/漏极结构的尺寸，基体源极/漏极结构的充放电时间较长且电容较大。因此劣化半导体装置的效能。因此需改善半导体装置。
发明内容
本公开的目的在于提供一种半导体装置，以解决上述至少一个问题。
在一实施例中，提供半导体装置。半导体装置包括多个半导体层位于基板上。半导体层向上堆叠并彼此分开。每一半导体层包括第一部分位于基板的第一通道区中，与第二部分位于基板的第二通道区中。半导体装置亦可包括多个外延层，形成于第一通道区与第二通道区之间的源极/漏极区中。外延层彼此分开，且每一外延层形成于每一半导体层的第一部分与第二部分之间。导电结构包覆每一外延层。
本发明另一实施例提供半导体装置。半导体装置可包括第一半导体层位于基板的第一通道区上，以及第二半导体层位于基板的第二通道区上。第一半导体层向上堆叠且彼此分开，且第二半导体层向上堆叠并彼此分开。半导体装置可包含外延层形成于基板的源极/漏极区之中以及第一半导体层的一者与第二半导体层的一者之间，导电结构以包覆源极/漏极区中的外延层，以及底部结构形成于导电结构与基板之间。外延层的下表面高于基板的上表面。
本发明又一实施例提供半导体装置的形成方法。方法可包括交错形成第一半导体层与第二半导体层于基板上，其中第一半导体层与第二半导体层包含不同材料，且沿着实质上垂直于基板上表面的方向向上堆叠；形成虚置栅极结构于第一半导体层与第二半导体层上；沿着虚置栅极结构的侧壁形成源极/漏极沟槽，使源极/漏极沟槽截断第一半导体层与第二半导体层；以及形成外延层于源极/漏极沟槽中截断的第一半导体层之间，其中沿着实质上垂直于基板上表面的方向分开外延层。
附图说明
图1为本发明一些实施例中，制造半导体装置的方法的流程图。
图2为本发明一些实施例中，初始半导体装置的三维透视图。
图3A至图16A为本发明一些实施例中，半导体装置在图1的方法的中间阶段沿着三维图中的剖线A-A’的剖视图。
图3B至图16B为本发明一些实施例中，半导体装置在图1的方法的中间阶段沿着三维图中的剖线B-B’的剖视图。
附图标记如下：
α:角度
A-A',B-B':剖面
D:方向
H1,H2,H4:厚度
H3:深度
W1:距离
W2:宽度
100:方法
102,104,106,108,110,112,114,116,118:步骤
200:装置
202:基板
204:隔离结构
210:堆叠
210A,210B:半导体层
210A-1,210A-1',210A-1",210A-2,210A-2’,210A-2”:半导体层部分
212:虚置栅极
214,216:硬掩模层
218:栅极间隔物
218':栅极间隔物层
220:虚置栅极结构
222:源极/漏极沟槽
224:内侧间隔物
226:底部结构
228:底部空洞
230:源极/漏极层
232:层间介电层
234:栅极沟槽
240:金属栅极结构
242:栅极介电层
244:金属栅极
246:接点沟槽
250:源极/漏极接点
252:硅化物层
270,272:接点及/或通孔
260:层间介电层
具体实施方式
下述详细描述可搭配附图说明，以利理解本发明的各方面。值得注意的是，各种结构仅用于说明目的而未按比例绘制，如本业常态。实际上为了清楚说明，可任意增加或减少各种结构的尺寸。
下述内容提供的不同实施例或例子可实施本发明实施例的不同结构。特定构件与排列的实施例是用以简化本公开而非局限本发明。举例来说，形成第一构件于第二构件上的叙述包含两者直接接触，或两者之间隔有其他额外构件而非直接接触。
此外，本发明的多种实例可重复采用相同标号以求简洁，但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。此外，本发明实施例的结构形成于另一结构上、连接至另一结构及/或耦接至另一结构中，结构可直接接触另一结构，或可形成额外结构于结构及另一结构之间。此外，空间性的相对用语如“下方”、“其下”、“下侧”、“上方”、“上侧”或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。此外，当数值或数值范围的描述有“约”、“近似”或类似用语时，除非特别说明否则其包含所述数值的+/-10％。举例来说，用语“约5nm”包含的尺寸范围为4.5nm至5.5nm。
在全绕式栅极装置中，单一装置的通道区可包含彼此物理分隔的多个半导体材料层。在一些例子中，装置的栅极位于装置的半导体层上、沿着半导体的侧部、且甚至位于半导体层之间。在公知的全绕式栅极装置中，外延的源极/漏极结构为外延成长于半导体装置的源极/漏极区中的基体结构。由于外延的源极/漏极结构的充放电与外延的源极/漏极结构的尺寸相关，大尺寸的基体外延结构需要较长的充放电时间并造成大电容。在本发明实施例中，基于全绕式栅极装置的特定通道轮廓(比如通道半导体层彼此物理分开)，外延源极/漏极结构可成长于通道半导体层的对应部分之间(如桥状物)。桥状的外延的源极/漏极层可有效作为外延的源极/漏极结构但尺寸较小。与基体外延结构相较，较小尺寸的外延结构所需的充放电时间较短且电容较小。接着形成源极/漏极接点以包覆每一外延层。此外，可形成底部的介电结构于源极/漏极接点与基板之间，以减少两者之间的漏电流。因此可增加半导体装置的速度并减少电容。如此一来，可改善半导体装置的效能。
图1显示本发明一些实施例中，制造半导体的装置200的方法100的流程图。方法100仅为举例而非局限本发明实施例至权利要求未实际记载处。在方法100之前、之中、与之后可进行额外步骤，且方法的额外实施例可置换、省略或调换一些所述步骤。方法100将搭配其他附图说明如下，且其他附图显示装置200在方法100的中间步骤时的多种三维图与剖视图。具体而言，图2为本发明一些实施例中，装置200的初始结构的三维图。图3A至图16A为本发明一些实施例中，装置200在方法100的中间阶段沿着图2所示的剖面A-A’(如Y-Z平面)的剖视图。图3B至图16B为本发明一些实施例中，装置200在方法100的中间阶段沿着图2所示的剖面B-B’(如X-Z平面)的剖视图。
装置200可为处理集成电路或其部分时所制作的中间装置，其可包含静态随机存取存储器及/或其他逻辑电路、无源构件(如电阻、电容器或电感)、与有源构件(如p型场效晶体管、n型场效晶体管、金属氧化物半导体场效晶体管、互补式金属氧化物半导体晶体管、双极晶体管、高电压晶体管、高频晶体管及/或其他存储器单元。装置200可为集成电路的核心区(通常视作逻辑区)、存储器区(如静态随机存取存储器区)、模拟区、周边区(通常视作输入/输出区)、虚置区、其他合适区或上述的组合的一部分。在一些实施例中，装置200可为集成电路芯片的一部分、单晶片系统或其部分。本发明实施例不限于任何特定数目的装置或装置区，或任何特定装置设置。
如图1、图2、图3A及图3B所示，步骤102形成装置200的初始半导体结构。如图2、图3A及图3B所示，装置200包括基板202。在所述实施例中，基板202为基体硅基板。在其他实施例或额外实施例中，基板202包括另一单晶半导体如锗、半导体化合物、半导体合金或上述的组合。在其他实施例中，基板202为绝缘层上半导体基板，比如绝缘层上硅基板、绝缘层上硅锗基板或绝缘层上锗基板。基板202可掺杂不同掺质，以形成多种掺杂区于其中。举例来说，基板202可包括含n型掺杂基板区(如n型井)的p型场效晶体管区，与含p型掺杂基板区(如p型井)的n型场效晶体管区。
装置200包含交错的半导体层形成于基板202上，比如含有第一半导体材料的半导体层210A与含有第二半导体材料的半导体层210B，且第一半导体材料与第二半导体材料不同。半导体层210A及210B的不同半导体材料，具有不同的氧化速率及/或不同的蚀刻选择性。在一些实施例中，半导体层210A的第一半导体材料与基板202相同。举例来说，半导体层210A包括硅(如基板202)，且半导体层210B包括硅锗。因此可由下至上排列交错的硅锗/硅/硅锗/硅…层。在一些实施例中，顶部半导体层的材料可或可不与底部的半导体层的材料相同。在一些实施例中，在形成半导体层210A时，不刻意进行掺杂。在一些其他实施例中，半导体层210A可掺杂p型掺质或n型掺质。半导体层210A及210B的数目取决于装置200的设计需求。举例来说，半导体层210A及210B的数目可各自为一至十层。在一些实施例中，不同的半导体层210A及210B在Z方向中可具有相同厚度。在一些其他实施例中，不同半导体层210A及210B可具有不同厚度。如图3B所示，每一半导体层210A在Z方向中可具有厚度H1，而每一半导体层210B在Z方向中可具有厚度H2。在一些实施例中，厚度H1为约5nm至约20nm，而厚度H2为约5nm至约20nm。在一些实施例中，半导体层210A及/或210B的形成方法可为合适的外延工艺。举例来说，半导体层包括硅锗层与硅层交错形成于基板202上，其形成方法可为分子束外延工艺、化学气相沉积工艺如有机金属化学气相沉积工艺及/或其他合适的外延成长工艺。
之后可图案化交错的半导体层210A及210B，以形成半导体的堆叠210。在一些实施例中，可对半导体层210A及210B进行多种光刻胶光刻与蚀刻工艺，以形成图示的鳍状的堆叠210。举例来说，先形成图案化的光刻胶掩模于装置200上。图案化的光刻胶掩模覆盖鳍状物的位置依据装置200的设计需求。之后采用图案化的光刻胶掩模并进行一或多道蚀刻工艺，以移除半导体层210A及210B的露出部分。半导体层210A与半导体层210B的保留部分可形成鳍状的堆叠210。在一些实施例中，亦移除基板202的顶部。蚀刻工艺可包含干蚀刻、湿蚀刻、其他合适的蚀刻工艺或上述的组合。此外，接着采用任何合适方法移除光刻胶掩模。
之后形成隔离结构于堆叠210之间的沟槽中，以分开并隔离装置200的有源区。在一些实施例中，一或多种介电材料如氧化硅及/或氮化硅沿着堆叠210的侧壁沉积于基板202上。介电材料的沉积方法可为化学气相沉积如等离子体辅助化学气相沉积、物理气相沉积、热氧化或其他技术。之后可使介电材料凹陷(比如以蚀刻及/或化学机械研磨等方法)，以形成隔离结构204。在一些实施例中，隔离结构204的上表面低于最底部的半导体层210B的下表面或与其共平面，如图3A所示，
之后形成虚置栅极结构220于堆叠210上。每一虚置栅极结构220可作为后续形成金属栅极结构所用的占位物。在一些实施例中，虚置栅极结构220沿着Y方向延伸，并越过个别的堆叠210。虚置栅极结构220覆盖堆叠210的通道区，其夹设于源极区与漏极区(均视作源极/漏极区)之间。每一虚置栅极结构220可包含多种虚置层，比如界面层(未图示)、虚置栅极212(含多晶硅)、一或多个硬掩模层214及216(含介电材料如氮化硅、碳氮化硅、氧化硅或类似物)及/或其他合适层状物。虚置栅极结构220的形成方法为沉积工艺、光刻工艺、蚀刻工艺、其他合适工艺或上述的组合。举例来说，沉积不同虚置层于堆叠210上。接着进行光刻工艺以形成掩模覆盖堆叠210的通道区。之后可采用光刻掩模并蚀刻不同虚置层，以形成虚置栅极结构220。此外，可采用任何合适方法移除光刻掩模。
接着形成栅极间隔物层218’于装置200上，比如形成于隔离结构204上、沿着虚置栅极结构220的侧壁与上表面以及沿着堆叠210的侧壁与上表面。在一些实施例中，栅极间隔物层218’包括介电材料如氧化硅、氮化硅、氮氧化硅、碳化硅、其他介电材料或上述的组合。栅极间隔物层218’的形成方法可为沉积工艺如原子层沉积、化学气相沉积、物理气相沉积或其他合适工艺。
如图1、图4A、图4B、图5A及图5B所示，步骤104非等向蚀刻间隔物层218’以形成栅极间隔物218。如图4A及图4B所示，进行非等向蚀刻以移除X-Y平面(基板202的上表面所在的平面)中的间隔物层218’的部分。间隔物层的保留部分转变成栅极间隔物218。非等向蚀刻包含湿蚀刻、干蚀刻或上述的组合。如图5A及图5B所示，步骤104以合适的蚀刻工艺移除源极/漏极区中沿着堆叠210的侧壁的间隔物218。如图5B所示，相邻的沿着虚置栅极结构220的间隔物218之间的距离W1可为约30nm至约50nm。
之后如图1、图6A及图6B所示，步骤106形成源极/漏极沟槽222于堆叠210的源极/漏极区中。在一些实施例中，以源极/漏极蚀刻工艺沿着栅极间隔物218的侧壁使堆叠210凹陷，以形成源极/漏极沟槽222。源极/漏极蚀刻工艺可为干蚀刻工艺(如反应性离子蚀刻)、湿蚀刻工艺或上述的组合。控制源极/漏极蚀刻工艺的时间，使每一半导体层210A及210B的侧壁暴露于源极/漏极沟槽222中。换言之，如图6B所示，源极/漏极沟槽222截断半导体层210A及210B。每一半导体层210A分成两个或更多个对应部分。以图6B为例，半导体层部分210A-1对应半导体层部分210A-2，半导体层部分210A-1’对应半导体层部分210A-2’，而半导体层部分210A-1”对应半导体层部分210A-2”。
如图1、图7A及图7B所示，步骤108形成内侧间隔物224于半导体层210A的边缘部分之间。在一些实施例中，以合适的蚀刻工艺选择性移除源极/漏极沟槽222中露出的半导体层210B的部分(边缘)，以形成间隙于半导体层210A的边缘部分之间。换言之，半导体层210A的边缘部分悬空于源极/漏极沟槽222中。由于半导体层210A(如硅)及210B(如硅锗)的氧化速率及/或蚀刻选择性不同，只移除半导体层210B的露出部分(边缘)，而半导体层210A维持实质上不变。在一些实施例中，选择性移除半导体层210B的露出部分的方法，可包含氧化工艺与之后的选择性蚀刻工艺。举例来说，先选择性氧化半导体层210B的边缘部分，使其包含氧化硅锗的材料。接着以合适的蚀刻剂如氢氧化铵或氢氟酸进行选择性蚀刻工艺以移除氧化硅锗。可控制氧化工艺与选择性蚀刻工艺的时间，以只选择性移除半导体层210B的边缘部分。
之后形成内侧间隔物224以填入半导体层210A之间的间隙。内侧间隔物224包括与栅极间隔物218的材料类似的介电材料，比如氧化硅、氮化硅、氮氧化硅、碳化硅或上述的组合。内侧间隔物的介电材料可沉积于源极/漏极沟槽222中，以及半导体层210A的边缘之间的间隙中，且其沉积方法可为化学气相沉积、物理气相沉积、原子层沉积或上述的组合。接着沿着栅极间隔物218的侧壁移除多余介电材料，直到源极/漏极沟槽222中露出半导体层210A的侧壁。
如图1、图8A、图8B、图9A及图9B所示，步骤110使源极/漏极沟槽222进一步凹陷，并形成底部结构226于源极/漏极沟槽222的进一步凹陷部分中。如图8A及图8B所示，进一步蚀刻源极/漏极沟槽222，以移除基板202的顶部，并使源极/漏极沟槽222的下表面低于最下侧的半导体层210B的下表面。在一些实施例中，进一步蚀刻源极/漏极沟槽222的深度H3为约20nm至约40nm。
如图9A及图9B所示，底部结构226形成于源极/漏极沟槽222的进一步凹陷部分中。在一些实施例中，底部结构226包括不同于第二半导体层的材料的未掺杂的外延材料，比如碳化硅、砷化镓、类似物、半导体合金或上述的组合。外延材料未掺杂而具有高电阻，且可缓解预期之外的漏电流。底部结构226外延成长于源极/漏极沟槽222的进一步凹陷部分中的方法可为化学气相沉积(如气相外延、超高真空化学气相沉积、低压化学气相沉积及/或等离子体辅助化学气相沉积)、分子束外延、其他合适的选择性外延成长工艺或上述的组合。如图9A及图9B所示，底部结构226的上表面低于最底部的半导体层210A(含半导体层部分210A-1”及210A-2”)的下表面。在一些实施例中，底部结构226的上表面与最下侧的半导体层210B的下表面(如基板202的上表面)实质上共平面。在一些其他实施例中，底部结构226的上表面高于最下侧的半导体层210B的下表面(如基板202的上表面)。如图9B所示，底部结构226在Z方向中具有厚度H4。在一些实施例中，厚度H4为约20nm至约60nm，其可为半导体层210A或210B的厚度H1或H2的约1倍至约10倍。底部结构226不可过薄，否则无法提供足够电阻而可能发生预期之外的漏电流。底部结构226不可过厚，否则可能增加预期之外的电容。
如图1、图10A及图10B所示，步骤112外延成长源极/漏极层230于源极/漏极沟槽222中的半导体层210A的对应部分之间。在一些实施例中，外延的源极/漏极层230包括半导体材料(如硅或锗)、半导体化合物(如硅锗、碳化硅、砷化镓或类似物)、半导体合金或上述的组合。可实施外延工艺以外延成长源极/漏极层230。外延工艺可包含化学气相沉积(比如气相外延、超高真空化学气相沉积、低压化学气相沉积及/或等离子体辅助化学气相沉积)、分子束外延、其他合适的选择性外延成长工艺或上述的组合。在一些实施例中，进行循环沉积/蚀刻工艺以形成源极/漏极层230。举例来说，当外延成长半导体材料时，可提供蚀刻气体如氯气至成长工艺中。因此结晶晶格仅成长于X方向中，以在Z方向中形成而不合并源极/漏极层230。如图10B所示，结晶层形成于半导体层210A的对应部分的侧壁之间，并连接源极/漏极沟槽222中的半导体层210A的对应部分。换言之，结晶层形成桥于源极/漏极沟槽222中的半导体层210A的对应部分之间。举例来说，结晶层外延成长于半导体层部分210A-1及210A-2之间、半导体层部分210A-1’及210A-2’之间以及半导体层部分210A-1”及210A-2”之间，并形成桥状的外延半导体层如源极/漏极层230于上述部分之间。在一些实施例中，当源极/漏极层230的形成方法为循环沉积/蚀刻工艺时，实施蚀刻气体会造成源极/漏极层的中间部分厚度小于源极/漏极层的边缘部分厚度。如图10B所示，外延的源极/漏极层230沿着方向D成长，而方向D与X方向具有角度α。在一些实施例中，角度α小于约45度，使外延的源极/漏极层230不会在中间分开。
在第一半导体层的厚度H1(比如源极/漏极层230的边缘部分厚度)与第一半导体层的对应部分之间的距离W1(比如源极/漏极沟槽222在X方向的宽度)具有合适比例H1/W1时，可外延成长结晶层以形成彼此物理分开的外延的源极/漏极层230。换言之，在Z方向中形成而不合并外延的源极/漏极层230。此外，半导体层在Y方向中的距离(如半导体层210B的厚度H2)亦有助于确保隔离外延的源极/漏极层230。合适的比例H/W亦可为外延的源极/漏极层230的厚度(在Z方向中)与长度(在X方向中)的比例。在一些实施例中，合适的比例H/W可为约0.1至约0.6。若比例过大，则源极/漏极层可在Z方向中合并。若比例过小，则源极/漏极层可能会在中间中断。如图10B所示，每一外延的源极/漏极层230在Z方向中的厚度H1为约5nm至约20nm，每一外延的源极/漏极层230在X方向中的长度如距离W1为约30nm至约50nm，且第一半导体层210A之间在Z方向中的距离如厚度H2为约5nm至约20nm。如图10B所示，底部空洞228形成于最底侧的外延的源极/漏极层230与底部结构226之间。如图10B所示，每一外延的源极/漏极层230的中间部分至少具有外延的源极/漏极层230的厚度如深度H3。在一些实施例中，厚度如深度H3为每一外延的源极/漏极层230的边缘部分的厚度H1的约20％至约100％。厚度如深度H3过小则外延的源极/漏极层230易破损。由于循环沉积/蚀刻工艺的固有成长角度α，厚度如深度H3不会超过100％的厚度H1。
在公知的全绕式栅极装置中，外延的源极/漏极结构为形成于全绕式栅极装置的源极/漏极区中的基体结构。然而本发明实施例基于全绕式栅极装置的分开的通道半导体层(比如半导体层210A)，源极/漏极结构外延成长于源极/漏极区中，如分开的外延层(比如桥状的外延的源极/漏极层)位于通道半导体层的对应部分之间。与公知的基体源极/漏极结构相较，本发明的外延结构(如分开的外延的源极/漏极层)的尺寸减少。如此一来，可减少外延结构的充放电时间，并增加半导体装置的速度。此外，较小尺寸的外延结构与公知的基体尺寸的外延结构相较，造成的电容较小。因此可改善半导体装置效能。
如图1、图11A、图11B、图12A、图12B、图13A及图13B所示，步骤114进行金属栅极置换工艺以将虚置栅极结构220置换成金属栅极结构240。金属栅极置换工艺包括多种工艺步骤。以图11A及图11B为例，层间介电层232形成于基板202上。举例来说，层间介电层232沿着栅极间隔物218、位于隔离结构204上、并位于外延的源极/漏极层230周围。在一些实施例中，层间介电层232包括低介电常数(小于3.9)的介电材料，比如四乙氧基硅烷的氧化物、未掺杂的硅酸盐玻璃或掺杂氧化硅(如硼磷硅酸盐玻璃、氟硅酸盐玻璃、磷硅酸盐玻璃或硼硅酸盐玻璃)、其他合适介电材料或上述的组合。层间介电层232的形成方法可为沉积工艺如化学气相沉积、可流动的化学气相沉积、旋转涂布玻璃、其他合适方法或上述的组合。
之后移除虚置栅极结构220以形成栅极沟槽234，并露出堆叠210的通道区。在一些实施例中，移除虚置栅极结构220的方法包括一或多种蚀刻工艺，比如湿蚀刻、干蚀刻、反应性离子蚀刻或其他蚀刻技术。在一些实施例中，步骤114亦移除层间介电层232与栅极间隔物218的顶部。接着露出栅极沟槽234中的半导体层210A及210B。
之后如图12A及图12B所示，自栅极沟槽234选择性移除半导体层210B。由于半导体层210A及210B的材料不同，半导体层210B的移除方法可与移除半导体层210B的边缘部分的选择性氧化与蚀刻工艺类似。在一些实施例中，步骤114稍微蚀刻或不蚀刻半导体层210A。因此半导体层210A悬空于堆叠210的通道区中，并沿着Z方向向上堆叠。Z方向通常垂直于基板202的上表面(如X-Y平面)。悬空的半导体层210A亦可视作通道的半导体层210A。
接着如图13A及图13B所示，形成金属栅极结构240于堆叠210的通道区中。金属栅极结构240包覆每一悬空的半导体层210A。在一些实施例中，每一金属栅极结构240可包含栅极介电层242以包覆每一通道的半导体层210A、金属栅极244位于栅极介电层242上以及其他合适层状物。栅极介电层242包含高介电常数的介电材料，比如氧化铪、氧化铪硅、硅酸铪、氮氧化铪硅、氧化铪镧、氧化铪钽、氧化铪钛、氧化铪锆、氧化铪铝、氧化锆、二氧化锆、氧化锆硅、氧化铝、氧化铝硅、三氧化二铝、氧化钛、二氧化钛、氧化镧、氧化镧硅、三氧化二钽、五氧化二钽、氧化钇、钛酸锶、氧化钡锆、钛酸钡、钛酸钡锶、氮化硅、氧化铪-氧化铝合金、其他合适的高介电常数的介电材料或上述的组合。在一些实施例中，栅极介电层242的沉积方法可为化学气相沉积、物理气相沉积、原子层沉积及/或其他合适方法。在一些实施例中，每一金属栅极244包含一或多个功函数金属层与基体金属。功函数金属层设置为调整对应晶体管的功函数，以达所需的临界电压。基体金属设置以作为功能栅极结构的主要导电部分。在一些实施例中，功函数金属层的材料可包含钛铝、碳化钛铝、碳化钽铝、氮化钛铝、氮化钛、氮化钨硅、氮化钽、碳氮化钨、钼、其他材料或上述的组合。基体金属可包含铝、钨、铜或上述的合金。金属栅极244的多种层状物的形成方法可为任何合适方法，比如化学气相沉积、原子层沉积、物理气相沉积、电镀、化学氧化、热氧化、其他合适方法或上述的组合。之后可施加一或多道平坦化工艺如化学机械研磨，以移除多余导电材料并平坦化装置200的上表面。
如图1、图14A、图14B、图15A及图15B所示，步骤116形成源极/漏极接点250以包覆每一外延的源极/漏极层230。如图14A及14B所示，以光刻工艺与湿蚀刻工艺移除源极/漏极区中的层间介电层232，以形成接点沟槽246。在一些实施例中，沿着源极/漏极区中的内侧间隔物224与栅极间隔物218保留层间介电层232的一部分。层间介电层232的保留部分在X方向中的厚度实质上等于栅极间隔物218的厚度。因此接点沟槽246中露出外延的源极/漏极层230。如上所述，外延的源极/漏极层230在Z方向中彼此分开。此外，最底部的外延的源极/漏极层230与底部结构226隔有底部空洞228。
如图15A及图15B所示，接着沉积导电材料于接点沟槽246中，可形成源极/漏极接点250以包覆每一外延的源极/漏极层230。在一些实施例中，导电材料包括铝、钨、铜、其他合适导电材料或上述的组合。导电材料的沉积方法可为化学气相沉积、原子层沉积、物理气相沉积、电镀、化学氧化、热氧化、其他合适方法或上述的组合。在一些实施例中，硅化物层252可形成于源极/漏极接点250与源极/漏极层230之间。在一些实施例中，硅化物层252包括钛硅化物、镍硅化物、铂硅化物、钴硅化物、钼硅化物、钛铂硅化物、镍铂硅化物、其他合适金属硅化物或上述的组合。在一些其他实施例中，可在形成源极/漏极接点250之前形成硅化物层252。举例来说，可沉积金属层于源极/漏极区中的源极/漏极层230周围。接着加热金属层(如退火工艺)，使其与源极/漏极层230反应形成硅化物层252。之后沉积源极/漏极接点250的导电材料于源极/漏极区中。在一些实施例中，硅化物层252可视作源极/漏极接点250的一部分。此外，可施加一或多道平坦化工艺如化学机械平坦化，以移除多余的导电材料并平坦化装置200的上表面。如图15A及15B所示，源极/漏极接点250包覆源极/漏极区中的每一外延的源极/漏极层230。栅极间隔物218、内侧间隔物224、与层间介电层232分开源极/漏极接点250与金属栅极结构240。此外，填入底部空洞228的源极/漏极接点250的最底部与基板202隔有底部结构226，因此可缓解源极/漏极接点250与基板202之间的漏电流问题。如图15B所示，源极/漏极接点250(或硅化物层252)在X方向中具有宽度W2。当宽度W2过大，则源极/漏极接点与金属栅极结构240之间的隔离过小，造成预期之外的寄生电容。当宽度W2过小，则源极/漏极接点电阻过大。在一些实施例中，宽度W2约为栅极间隔物218之间的宽度如距离W1的约40％至约90％，端视装置200的设计而定。
如图1、图16A及图16B所示，步骤118进行后续工艺以完成制作装置200。举例来说，可形成多种接点及/或通孔270及272、金属线路(未图示)以及其他多层内连线结构如层间介电层260及/或蚀刻停止层于装置200上，其设置为连接多种结构以形成含有不同半导体装置的功能电路。
本发明的一或多个实施例提供许多优点至半导体装置与其形成工艺，但不局限于此。举例来说，本发明实施例提供的半导体装置包括外延的源极/漏极层成长于通道的半导体层的对应部分之间，并形成通道的半导体层的对应部分之间的桥状物。形成源极/漏极接点以包覆分开的每一外延的源极/漏极层，且源极/漏极接点与基板隔有底部的介电结构。分开的外延的源极/漏极层可减少外延结构的尺寸，因此可减少电容并增加充放电速度。因此可改善半导体装置的效能。
本发明提供许多不同实施例。在一实施例中，提供半导体装置。半导体装置包括多个半导体层位于基板上。半导体层向上堆叠并彼此分开。每一半导体层包括第一部分位于基板的第一通道区中，与第二部分位于基板的第二通道区中。半导体装置亦可包括多个外延层，形成于第一通道区与第二通道区之间的源极/漏极区中。外延层彼此分开，且每一外延层形成于每一半导体层的第一部分与第二部分之间。导电结构包覆每一外延层。
在一些实施例中，半导体装置可还包括金属栅极结构以包覆每一半导体层。金属栅极结构包括金属栅极堆叠以包覆每一半导体层，以及内侧间隔物沿着金属栅极堆叠的侧壁。在一些实施方式中，半导体装置可还包括层间介电层沿着内侧间隔物的侧壁形成，其中导电结构接触层间介电层。在一些例子中，半导体装置还包括底部结构位于导电结构与基板之间，且底部结构包括未掺杂的外延材料。在些实施例中，半导体装置可还包括隔离结构以分开半导体装置的有源区并接触底部结构的侧壁。在一些实施方式中，底部结构的上表面低于最下侧的半导体层的下表面。在一些例子中，每一半导体层的厚度与每一半导体层的第一部分与第二部分之间的每一外延层的长度的比例为约0.1至约0.6。
本发明另一实施例提供半导体装置。半导体装置可包括第一半导体层位于基板的第一通道区上，以及第二半导体层位于基板的第二通道区上。第一半导体层向上堆叠且彼此分开，且第二半导体层向上堆叠并彼此分开。半导体装置可包含外延层形成于基板的源极/漏极区之中以及第一半导体层的一者与第二半导体层的一者之间，导电结构以包覆源极/漏极区中的外延层，以及底部结构形成于导电结构与基板之间。外延层的下表面高于基板的上表面。
在一些实施例中，底部结构包括未掺杂的外延材料，且底部结构的上表面高于基板的上表面或与基板的上表面实质上共平面。在一些实施例中，外延层的中间部分厚度小于外延层的边缘部分厚度。在一些实施例中，导电结构包括硅化物层围绕外延层，以及基体金属位于硅化物层上。
本发明又一实施例提供半导体装置的形成方法。方法可包括交错形成第一半导体层与第二半导体层于基板上，其中第一半导体层与第二半导体层包含不同材料，且沿着实质上垂直于基板上表面的方向向上堆叠；形成虚置栅极结构于第一半导体层与第二半导体层上；沿着虚置栅极结构的侧壁形成源极/漏极沟槽，使源极/漏极沟槽截断第一半导体层与第二半导体层；以及形成外延层于源极/漏极沟槽中截断的第一半导体层之间，其中沿着实质上垂直于基板上表面的方向分开外延层。
在一些实施例中，形成源极/漏极沟槽的步骤包括：沿着虚置栅极结构的侧壁蚀刻，直到露出最下侧的第二半导体层的侧壁，以形成源极/漏极沟槽；选择性移除第二半导体层的边缘部分；以及形成内侧间隔物以填入移除的第二半导体层的边缘部分。在一些实施方式中，形成源极/漏极沟槽的步骤可还包括进一步蚀刻源极/漏极沟槽，使源极/漏极沟槽的下表面低于基板的上表面；以及形成含未掺杂的外延材料的底部结构于进一步蚀刻的源极/漏极沟槽中。在一些例子中，底部结构的上表面低于最下侧的第一半导体层的下表面。在一些实施例中，方法可还包括沉积层间介电层以包覆源极/漏极沟槽中的外延层，其中层间介电层的下表面接触底部结构的上表面；以及将虚置栅极结构置换成金属栅极结构。在一些例子中，方法还包括移除层间介电层的一部分，以露出源极/漏极沟槽中的外延层。在一些实施例中，方法还包括形成接点结构以包覆源极/漏极沟槽中每一露出的外延层，其中接点结构的下表面接触底部结构的上表面。在一些实施方式中，形成接点结构的步骤包括沉积导电材料层以围绕露出的外延层；进行退火工艺以形成硅化物层；以及沉积导电材料于硅化物层上以形成接点结构。在一些实施例中，外延层的形成方法为循环沉积蚀刻工艺。
上述实施例的特征有利于本技术领域中技术人员理解本发明。本技术领域中技术人员应理解可采用本发明作基础，设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中技术人员亦应理解，这些等效置换并未脱离本发明精神与范畴，并可在未脱离本发明的精神与范畴的前提下进行改变、替换或更动。

Claims (1)

1.一种半导体装置，包括：
多个半导体层，位于一基板上，其中多个所述半导体层向上堆叠并彼此分开，每一多个所述半导体层包括一第一部分位于该基板的一第一通道区中与一第二部分位于该基板的一第二通道区中；
多个外延层，形成于该第一通道区与该第二通道区之间的一源极/漏极区中，其中多个所述外延层彼此分开，且每一多个所述外延层形成于每一多个所述半导体层的该第一部分与该第二部分之间；以及
一导电结构，包覆每一多个所述外延层。
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