CN113161353A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN113161353A
CN113161353A CN202110096447.3A CN202110096447A CN113161353A CN 113161353 A CN113161353 A CN 113161353A CN 202110096447 A CN202110096447 A CN 202110096447A CN 113161353 A CN113161353 A CN 113161353A
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semiconductor
layer
region
gate
core
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王培宇
王培勋
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开实施例提供一种半导体装置，半导体装置包括第一半导体带，自基板凸起；第二半导体带，自基板凸起；隔离材料，围绕第一半导体带与第二半导体带；纳米片结构，位于第一半导体带上，其中纳米片结构与第一半导体带隔有含栅极材料的第一栅极结构，其中第一栅极结构部分地围绕纳米片结构；以及第一半导体通道区与第二半导体通道区，位于第二半导体带上，其中第一半导体通道区与第二半导体通道区隔有含栅极材料的第二栅极结构，其中第二栅极结构延伸于第二半导体带的上表面上。

Description

半导体装置
技术领域
本发明实施例涉及半导体装置，尤其涉及全绕式栅极场效晶体管形成于第一区中，鳍状场效晶体管形成于第二区中，且鳍状场效晶体管各自包含两个通道区(双通道区)的半导体装置。
背景技术
半导体装置用于多种电子应用，比如个人电脑、手机、数字相机、与其他电子设备。半导体装置的制作方法一般为依序沉积绝缘或介电层、导电层、与半导体层的材料于半导体基板上，并采用光刻与蚀刻技术图案化多种材料层，以形成电路构件与单元于半导体基板上。
半导体产业持续缩小最小结构尺寸，以持续改善多种电子构件(如晶体管、二极管、电阻、电容器或类似物)的集成密度，以让更多构件整合至给定面积中。然而随着最小结构尺寸缩小，将产生需解决的额外问题。
发明内容
本公开实施例的目的在于提供一种半导体装置，以解决上述至少一个问题。
在一实施例中，半导体装置包括：多个半导体带，自基板凸起，其中半导体带包括多个第一半导体带于基板的第一区中，以及多个第二半导体带于基板的第二区中；多个纳米结构，位于第一区的第一半导体带上并对准第一半导体带；多个第一源极/漏极区位于纳米结构的两端；第一栅极结构，部分地围绕纳米结构；多个双通道区，位于第二区的第二半导体带上，其中双通道区的每一个包括第一通道区对准第二半导体带的一个的第一侧，以及第二通道区对准第二半导体的一个的第二侧，其中第一通道区与第二通道区分开；多个第二源极/漏极区，位于双通道区的两端；以及第二栅极结构，位于双通道区上，其中第二栅极结构分开双通道区的每一第一通道区与对应的第二通道区。
在一实施例中，半导体装置包括第一半导体带，自基板凸起；第二半导体带，自基板凸起；隔离材料，围绕第一半导体带与第二半导体带；纳米片结构，位于第一半导体带上，其中纳米片结构与第一半导体带隔有含栅极材料的第一栅极结构，其中第一栅极结构部分地围绕纳米片结构；以及第一半导体通道区与第二半导体通道区，位于第二半导体带上，其中第一半导体通道区与第二半导体通道区隔有含栅极材料的第二栅极结构，其中第二栅极结构延伸于第二半导体带的上表面上。
在一实施例中，半导体装置的形成方法，包括形成外延结构于半导体基板上，其中外延结构包括交错的硅层与硅锗层；使外延结构的一部分凹陷以形成沟槽；将硅锗填入沟槽；图案化沟槽中的硅锗以形成芯；外延成长硅于芯的侧壁上以形成通道区；移除芯；以及形成栅极结构于通道区上，且栅极结构延伸于通道区之间。
本发明的有益效果在于，本发明实施例公开的工艺可形成纳米结构的场效晶体管与鳍状场效晶体管于相同基板上。如此一来，此处所述的工艺可形成混合通道的场效晶体管装置。采用硅锗形成芯，可外延成长每一鳍状场效晶体管所用的两个通道区。在此方式中，鳍状场效晶体管装置可具有两倍的通道区，并增加鳍状场效晶体管的电流容量。此外，采用硅锗可改善工艺一致性，并在形成时减少缺陷的机率。
附图说明
图1-图4、图5A及图5B、图6A及图6B、图7A及图7B、图8A至图8G、图9A至图9G、图10A及图10B、图11A至图11G、图12A至图12G、图13A至图13G为一些实施例中，含有全绕式栅极场效晶体管装置与双通道鳍状场效晶体管的混合通道装置的形成方法的中间阶段的剖视图。
图14A至图14E为一些实施例中，混合通道装置中的全绕式栅极场效晶体管装置的形成方法的中间阶段的剖视图。
图15A至图15D为一些实施例中，混合通道装置中的双通道鳍状场效晶体管的形成方法的中间阶段的剖视图。
具体实施方式
下述详细描述可搭配附图说明，以利理解本发明的各方面。值得注意的是，各种结构仅用于说明目的而未按比例绘制，如本业常态。实际上为了清楚说明，可任意增加或减少各种结构的尺寸。
下述内容提供的不同实施例或例子可实施本发明实施例的不同结构。特定构件与排列的实施例用以简化本公开而非局限本发明。举例来说，形成第一构件于第二构件上的叙述包含两者直接接触，或两者之间隔有其他额外构件而非直接接触。此外，本发明的多种实例可重复采用相同标号以求简洁，但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。除非特别说明，不同附图中的相同或类似标号指的是相同或类似构件，其可采用相同或类似工艺所形成的相同或类似材料。
此外，空间性的相对用语如“下方”、“其下”、“下侧”、“上方”、“上侧”或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。元件亦可转动90°或其他角度，因此方向性用语仅用以说明图示中的方向。
在一些实施例中，半导体装置包括全绕式栅极场效晶体管形成于第一区中，以及鳍状场效晶体管形成于第二区中。鳍状场效晶体管各自包含两个通道区(双通道区)。形成每一鳍状场效晶体管所用的多个通道，可增加操作电流。双通道区的形成方法为形成硅锗的芯，接着外延成长通道区的半导体材料于芯的侧壁上。采用硅锗形成芯，可改善工艺一致性并减少缺陷。
图1至图15D为一些实施例中，含有全绕式栅极场效晶体管装置的区域100与鳍状场效晶体管的区域200的混合通道装置的形成方法其中间阶段的剖视图。全绕式栅极场效晶体管的区域100与鳍状场效晶体管的区域200可为相同结构的不同区域。在图1至15D中，形成全绕式栅极场效晶体管的区域标示为区域100，而形成鳍状场效晶体管的区域标示为区域200。为了清楚说明，以分开附图显示区域100与区域200，但应理解此处所述的区域100与区域200可为相同结构的区域。
如图1所示，提供基板101。基板101可为半导体基板，比如基体半导体(如基体硅)、绝缘层上半导体基板或类似物，其可掺杂(比如掺杂p型掺杂或n型掺杂)或未掺杂。基板101可为晶片如硅晶片。一般而言，绝缘层上半导体基板为半导体材料层形成于绝缘层上。举例来说，绝缘层可为埋置氧化物层、氧化硅层或类似物。提供绝缘层于基板上，通常为硅基板或玻璃基板。亦可采用其他基板如多层基板或组成渐变基板。在一些实施例中，基板101的半导体材料可包含硅、锗、半导体化合物(如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟)、半导体合金(如硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟及/或磷砷化镓铟)或上述的组合。
在图1的一些实施例中，外延材料堆叠104'形成于基板101上。外延材料堆叠104'包括交错的第一半导体层103与第二半导体层105。第一半导体层103的组成为第一半导体材料，而第二半导体层105的组成为不同的第二半导体材料。在所述实施例中，第一半导体材料为硅锗(SixGe1-x，其中x可为0至1)。在一些实施例中，第一半导体材料为硅锗，其包含约20％的锗至约45％的锗(x为约0.8至约0.55)。在所述实施例中，第二半导体材料为硅。其他半导体材料或半导体材料的组合亦属可能。在一些实施例中，第一半导体层103的厚度介于约4nm至约10nm之间。在一些实施例中，第二半导体层105的厚度介于约6nm至约15nm之间。其他厚度亦属可能。外延材料堆叠104’可包含任何数目的层状物。外延材料堆叠104’的最顶层可包含第一半导体材料、第二半导体材料或另一材料。在后续工艺中，可图案化外延材料堆叠104’以形成区域100的全绕式栅极场效晶体管的通道区。具体而言，接着图案化外延材料堆叠104’以形成纳米结构(如纳米线、纳米片或类似物)，而最终的区域100的全绕式栅极场效晶体管的通道区可包含多个纳米结构。
外延材料堆叠104'的形成方法可为在成长腔室中进行的外延成长工艺。在外延成长工艺时，成长腔室循环地暴露至成长第一半导体层103所用的第一组前驱物，接着暴露至成长第二半导体层105所用的第二组前驱物。第一组前驱物包括第一半导体材料(如硅锗)所用的前驱物，而第二组前驱物包括第二半导体材料(如硅)所用的前驱物。外延材料堆叠104'可掺杂或不掺杂，端视全绕式栅极场效晶体管的区域100的设计而定。在一些实施例中，外延材料堆叠104'的总厚度介于约40nm至约70nm之间。
在一些实施例中，第一组前驱物包括硅前驱物(如硅烷)与锗前驱物(如锗烷)，而第二组前驱物包括硅前驱物但省略锗前驱物。因此外延成长工艺可包含连续地使硅前驱物流入成长腔室，接着进行下述循环：(1)在成长第一半导体103时，使锗前驱物流入成长腔室；以及(2)在成长第二半导体层105时，不使锗前驱物流入成长腔室。可重复上述循环，直到形成目标数目的层状物。在完成成长循环之后，可进行平坦化工艺使外延材料堆叠104'的上表面齐平。平坦化工艺可包含化学机械研磨、研磨工艺、回蚀刻工艺、上述的组合或类似工艺。
如图2所示，蚀刻区域200中的外延材料堆叠104'以形成凹陷201。在一些实施例中，形成硬掩模层107于外延材料堆叠104'上，并图案化硬掩模层107以露出区域200中的外延材料堆叠104'。硬掩模层107可包含子层，比如垫氧化物层与视情况形成的上方垫氮化物层。举例来说，垫氧化物层可为含氧化硅的薄膜，其形成方法可采用热氧化工艺。垫氧化物层可作为外延材料堆叠104'与上方的垫氮化物层之间的粘着层。在一些实施例中，垫氮化物层的组成可为氮化硅、氮氧化硅、碳氮化硅、类似物或上述的组合，且其形成方法可采用低压化学气相沉积或等离子体辅助化学气相沉积。在一些实施例中，硬掩模层107的厚度介于约10nm至约30nm之间，但其他厚度亦属可能。
硬掩模107的图案化方法可采用光刻与蚀刻技术。接着采用图案化的硬掩模层107作为蚀刻掩模，用于图案化基板101及/或外延材料堆叠104'的蚀刻工艺，以形成凹陷201于区域200中。图案化的硬掩模层107在蚀刻工艺时，可保护区域100中的外延材料堆叠104'。蚀刻工艺可包含一或多道合适的干蚀刻工艺及/或湿蚀刻工艺。在一些实施例中，蚀刻工艺包括时控蚀刻。在一些实施例中，凹陷201自外延材料堆叠104'的顶部延伸的深度可介于约50nm至约100nm之间。凹陷201可延伸至基板101中。
在图3的一些实施例中，芯材203'形成于凹陷201中。可形成芯材203'以填入凹陷201。举例来说，芯材203'的厚度可大于或等于凹陷201的深度。芯材203'的部分可延伸于硬掩模107上，如图3所示。芯材203'的形成方法可为在成长腔室中进行的外延成长工艺。在外延成长工艺时，成长腔室可暴露至一组前驱物(比如硅烷与锗烷)以成长芯材203'。在一些实施例中，芯材203’为硅锗(SixGe1-x，其中x可为0至1)。在一些实施例中，芯材203’为硅锗，其包含约20％的锗至约45％的锗(比如x为约0.8至约0.55)。形成芯材203'所采用的技术或一组前驱物，可与形成第一半导体层103的第一半导体材料所采用的技术或一组前驱物类似。举例来说，一些实施例的第一半导体层103与芯材203'可均为硅锗，其可具有相同或不同的组成(比如具有相同或不同的x值)。芯材203'可掺杂或未掺杂。
可选择硬掩模层107的材料及/或芯材203'的材料，使芯材203'选择性地成长于凹陷201的表面上而非硬掩模层107的表面上。举例来说，硬掩模层107的组成可为氮化硅或碳氮化硅，而芯材203'的组成可为硅锗，以抑制外延成长芯材203'于硬掩模层107上。在一些例子中，采用硅锗作为芯材203'的选择性外延成长效果，大于采用其他材料如硅作为芯材203'的选择性外延成长效果。在此方式中，采用硅锗作为芯材，其抑制成长芯材203'于硬掩模层107上的效果大于抑制成长芯材203'于芯材203'所用的其他材料(如硅)上的效果。采用硅锗作为芯材203'所形成的芯材203'，可比采用其他材料如硅所形成的芯材203'具有更少缺陷。硅锗的芯材203'可减少成长于硬掩模层107上的芯材203'，可外延成长更厚的芯材203'，并改善芯材203'填入凹陷201的效果。
在图4的一些实施例中，进行平坦化工艺如化学机械研磨工艺或类似工艺，以移除硬掩模层107与多余的芯203。在平坦化工艺之后，外延材料堆叠104'与芯材203'的上表面可共平面。在一些实施例中，可采用蚀刻工艺如干蚀刻工艺或湿蚀刻工艺移除硬掩模层107。
在图5A及图5B的一些实施例中，图案化区域100以形成半导体鳍状物102，并图案化区域200以形成芯结构202’。图5A显示区域100的一部分，其可为图1至4所示的区域100的一部分。图5B显示区域200的一部分，其可为图1至4所示的区域200的一部分。换言之，图5A所示的区域100与图5B所示的区域200可形成于相同基板101上。
未形成半导体鳍状物102于区域100中，可采用光刻与蚀刻技术图案化外延材料堆叠104'与基板101。举例来说，可形成硬掩模(未图示)于区域100中的外延材料堆叠104'上，并形成光刻胶材料于硬掩模上。可采用合适的光刻技术图案化光刻胶材料，接着采用图案化的光刻胶图案化硬掩模。接着采用图案化的硬掩模图案化基板101与外延材料堆叠104'以形成沟槽，进而定义半导体鳍状物102于相邻的沟槽之间。在所述实施例中，每一半导体鳍状物102包括半导体带106，与半导体带106上的图案化的外延材料堆叠104。半导体带106为基板101的图案化部分，且可凸起高于凹陷的基板101。图案化的外延材料堆叠104为外延材料堆叠104’的图案化部分，且可用于在后续工艺中形成纳米结构，因此亦可视作全绕式栅极结构。可自半导体鳍状物102移除硬掩模与光刻胶材料，如图5A所示。在一些实施例中，半导体鳍状物102的宽度W1可介于约10nm至约100nm之间。半导体鳍状物102之后亦可视作鳍状物。
为了形成芯结构202'于区域200中，可采用光刻与蚀刻技术图案化芯材203'与基板101。举例来说，可形成硬掩模(未图示)于区域200中的芯材203'上，并形成光刻胶材料于硬掩模上。在形成上述用于形成半导体鳍状物102的硬掩模时，可一起形成硬掩模。可采用合适的光刻技术图案化光刻胶材料，接着采用图案化的光刻胶以图案化硬掩模。接着采用图案化的硬掩模图案化基板101与芯材203'以形成沟槽，进而定义芯结构202'于相邻沟槽之间。在所述实施例中，每一芯结构202'包括半导体带206，与半导体带206上的芯203。半导体带206为基板101的图案化部分，并高于凹陷的基板101。在后续工艺中，自图案化的芯材203'所形成的芯203可用于形成区域200的鳍状场效晶体管的通道区207。在后续步骤中可移除芯203，因此其可视作虚置结构或牺牲结构。在一些实施例中，芯203的宽度W2介于约5nm至约10nm之间。在一些实施例中，芯203的间距可介于约25nm至约50nm之间。
在一些实施例中，半导体鳍状物102与芯结构202’的形成方法可采用一些或全部相同的光刻或蚀刻步骤。举例来说，可在形成半导体鳍状物102所用的上述硬掩模时，形成及/或图案化用于形成芯结构202’的硬掩模。在一些实施例中，半导体鳍状物102与芯结构202’的形成方法可采用不同的光刻步骤，且可在形成半导体鳍状物102之前形成芯结构202’(或在形成芯结构202’之前形成半导体鳍状物102)。可由任何合适方法图案化半导体鳍状物102及/或芯结构202’。举例来说，可采用一或多道光刻工艺图案化半导体鳍状物102及/或芯结构202'，包括双重图案化或多重图案化工艺。一般而言，双重图案化或多重图案化工艺结合光刻与自对准工艺，其产生的图案间距可小于采用单一的直接光刻工艺所得的图案间距。举例来说，一实施例形成牺牲层于基板上，并采用光刻工艺图案化牺牲层。可采用自对准工艺沿着牺牲层的侧部形成间隔物。接着移除牺牲层，而保留的间隔物之后可用于图案化鳍状物102及/或芯203。
如图5A及图5B所示，形成绝缘材料于区域100与区域200中，以形成隔离区。绝缘材料可为氧化物如氧化硅、氮化物、类似物或上述的组合，且其形成方法可为高密度等离子体化学气相沉积、可流动的化学气相沉积(比如在远端等离子体系统中陈基化学气相沉积为主的材料，之后硬化材料使其转为另一材料如氧化物)、类似方法或上述的组合。亦可采用其他绝缘材料及/或其他形成工艺。在所述实施例中，绝缘材料为可流动的化学气相沉积工艺所形成的氧化硅。一旦形成绝缘材料，即可进行退火工艺。平坦化工艺如化学机械研磨可自半导体鳍状物102或芯结构202'的上表面，移除任何多余的绝缘材料。
接着可使隔离区凹陷以形成浅沟槽隔离区111。由于浅沟槽隔离区111凹陷，半导体鳍状物102与芯结构202’的上侧部分自相邻的浅沟槽隔离区111凸起。浅沟槽隔离区111的上表面可具有平坦表面(如图所示)、凸起表面、凹陷表面(如碟化)或上述的组合。可由合适蚀刻使浅沟槽隔离区111的上表面平坦、凸起及/或凹陷。可采用可接受的蚀刻工艺如对浅沟槽隔离区111的材料具有选择性的蚀刻工艺，使浅沟槽隔离区111凹陷。举例来说，可进行干蚀刻或采用稀氢氟酸的湿蚀刻，使浅沟槽隔离区111凹陷。在图5A及图5B中，浅沟槽隔离区111的上表面与半导体带106及206的上表面齐平。在其他实施例中，浅沟槽隔离区111的上表面低于半导体带106或206的上表面，比如较靠近基板101。在一些实施例中，半导体鳍状物102延伸高于浅沟槽隔离区111的距离介于约40nm至约70nm之间。在一些实施例中，芯203延伸高于浅沟槽隔离区111的距离介于约40nm至约70nm之间。
在图6A及图6B的一些实施例中，外延成长通道区207于芯203上。在形成通道区207之前，可形成硬掩模层108于区域100与区域200上。可采用合适的光刻与蚀刻技术图案化硬掩模层108，以自芯203的侧壁移除硬掩模层108的材料。如图6B所示，图案化之后可保留硬掩模层108的部分于芯结构202'上，以保护芯203并阻挡通道区207的材料外延成长于芯203的上表面上。硬掩模层108可包含介电材料如氮化硅或类似物，且其形成方法可采用合适的沉积法如化学气相沉积或类似方法。硬掩模层108的厚度可介于约3nm至约5nm之间。
在形成硬掩模层108于区域100上之后，可外延成长通道区207于芯203上以形成通道结构202。每一通道结构202包括半导体带206、半导体带206上的芯203、与两个通道区207，其中通道区207在芯203的每一侧壁上。通道区207作为区域200的鳍状场效晶体管的通道区。以此方式形成通道区207，可形成两个通道区207而非一个通道区以用于每一半导体带206，因此可增加鳍状场效晶体管装置(比如具有鳍状场效晶体管的输入/输出装置)所用的通道区数目。以此方式增加通道区的数目，可增加鳍状场效晶体管装置的电流。举例来说，由于形成两个而非一个通道区，鳍状场效晶体管装置的最大电流几乎加倍。通过增加操作电流，可改善鳍状场效晶体管装置的效能。
可自外延成长于芯203的露出材料上的半导体材料形成通道区207。举例来说，一些实施例的通道区207包括硅，其外延成长于含硅锗的芯203上。通道区207可掺杂或未掺杂。通道区207的形成方法可为在成长腔室中进行的外延成长工艺。在外延成长工艺时，成长腔室暴露至成长通道区207所用的一或多种前驱物(如硅烷)。外延成长工艺可包含使前驱物持续流入成长腔室。在一些实施例中，通道区207的厚度W3介于约5nm至约10nm之间。在一些例子中，通道区207的可行厚度W3取决于芯结构202’之间的分隔距离(如间距)。在一些例子中，外延成长通道区207以具有较小的厚度W3，可减少形成于通道区207中的缺陷量。在形成通道区207之后，可移除硬掩模层108，以形成图7A及7B所示的结构。可采用一或多种合适的干蚀刻或湿蚀刻工艺移除硬掩模层108。
在图8A至图8G中，形成虚置栅极结构122于半导体鳍状物102上，并形成虚置栅极结构222于通道结构202上。图8A、图8C及图8E显示区域100中的结构的多种剖视图，而图8B、图8D、图8F及图8G显示区域200中的结构的多种剖视图。图8A及图8C显示区域100的剖视图，其平行于虚置栅极结构122。图8B及图8D显示区域的剖视图，其平行于虚置栅极结构222。图8E显示区域100的剖视图，其垂直于图8A及图8C所示的区域100的附图。图8F及图8G显示区域200的剖视图，其垂直于图8B及图8D所示的区域200的附图。图8A至图8F的每一剖视图将对应标示于其他附图中。举例来说，图8E为图8A及图8C所示的剖面E-E的剖视图。其他附图具有类似的标示剖面。
如图8A至图8G所示，形成虚置栅极结构122于半导体鳍状物102上，并形成虚置栅极结构222于通道结构202上。在一些实施例中，每一虚置栅极结构122及222包括栅极介电层121与栅极123。虚置栅极结构122及222的形成方法可采用一些或全部相同的工艺步骤。为形成虚置栅极结构122及222，可沉积介电层于区域100及200中的结构上，以形成栅极介电层121。举例来说，介电层可为氧化硅、氮化硅、上述的多层或类似物，且其形成方法可为沉积或热成长。接着形成栅极层于栅极介电层121上，以形成栅极123。举例来说，栅极层可包含多晶硅，钽亦可采用其他材料。可沉积栅极层于介电层上，接着以化学机械研磨工艺等方法平坦化栅极层。
接着可沉积掩模层于栅极层上。举例来说，掩模层的组成可为氧化硅、氮化硅、上述的组合或类似物。采用可接受的光刻与蚀刻技术，可图案化掩模层以形成掩模126，如图8A至图8G所示。在一些实施例中，掩模126包含第一掩模126A(如氧化硅或类似物)与第二掩模126B(如氮化硅、碳氮化硅或类似物)。接着由可接受的蚀刻技术将掩模126的图案转移至栅极层与介电层，以形成栅极介电层121与栅极123。栅极123的长度方向实质上垂直于半导体鳍状物102或通道结构202的长度方向。
如图8A至图8G所示，形成栅极间隔物层129'于区域100及200的栅极123与栅极介电层121上。可顺应性地沉积栅极间隔物层129'。栅极间隔物层129'可包含一或多层的氮化硅、碳氮化硅、碳氧化硅、碳氮氧化硅、上述的组合或类似物。在一些实施例中，栅极间隔物层129'包含多个子层，比如第一子层129A'、第二子层129B'、与第三子层129C'。更多或更少的子层亦属可能。举例来说，第一子层129A'(有时视作栅极密封间隔物层)的形成方法可为热氧化或沉积，而第二子层129B'(有时视作主要栅极间隔物层)可顺应性地沉积于第一子层129A'上。在一些实施例中，栅极间隔物层129'的形成方法可采用化学气相沉积、物理气相沉积、原子层沉积、类似方法或上述的组合。
如图9A至图9G所示，蚀刻栅极间隔物层129’以形成栅极间隔物129，并移除全绕式栅极结构如图案化的外延材料堆叠104与通道结构202的部分(即之后形成源极/漏极区133的区域，见图13A至图13G)。图9A至图9G所示的剖视图的剖面，与图8A至图8G所示的个别剖视图的剖面相同。栅极间隔物129的形成方法为非等向蚀刻栅极间隔物层129’。非等向蚀刻可移除栅极间隔物层129’的水平部分，并保留栅极间隔物层129’的垂直部分(比如沿着栅极123的侧壁与栅极介电层121的侧壁)，以形成栅极间隔物129。在此处说明的内容中，栅极间隔物129可视作虚置栅极结构122及222的部分。
接着进行非等向蚀刻工艺，以移除全绕式栅极结构如图案化的外延材料堆叠104(如第一半导体层103与第二半导体层105)的部分与通道结构202的部分。可采用虚置栅极结构122及222作为蚀刻掩模，并进行非等向蚀刻工艺。在一些实施例中，非等向蚀刻工艺包括一或多道干蚀刻工艺。蚀刻工艺露出区域100及200中的下方的半导体带106及206，且可形成凹陷于半导体带106及206中。接着形成源极/漏极区133于半导体带106及206的露出区域上。
接着在图10A及图10B中，进行横向蚀刻工艺使第一半导体层103与芯203的露出部分凹陷。图10A显示图9E所示的区域100的剖视图，且图10B显示图9F所示的区域200的剖视图。在一些实施例中，横向蚀刻工艺可为非等向蚀刻工艺，其对第一半导体材料的选择性高于对其他材料的选择性。对第一半导体层103与芯203具有选择性的横向蚀刻工艺，可使第一半导体层103与芯203自第二半导体层105与半导体带106及206凹陷。举例来说，横向蚀刻工艺包含的蚀刻剂对硅锗的选择性可高于对硅的选择性，其可为含氢氟酸、氟气或类似物的干式工艺，或含臭氧、氢氧化铵或类似物的湿式工艺。
接着如图11A至图11G所示，形成介电材料以填入第一半导体层103与芯203凹陷后留下的空间。图11A至图11G所示的剖视图的剖面，分别与图8A至图8G所示的剖视图的剖面相同。介电材料131可为低介电常数的介电材料，比如氧化硅、氮化硅、碳氮化硅、碳氮氧化硅或类似物，且其形成方法可为合适的沉积法如化学气相沉积、原子层沉积或类似方法。介电材料131可包含多层或单层。举例来说，介电材料131可包含第一层131A与第二层131B，第一层131A可含金属氧化物或上述的低介电常数的介电材料，而第二层131B可含不同于第一层131A的低介电常数的介电材料。在一些实施例中，介电材料的厚度可介于约4nm至约7nm之间。在一些实施例中，介电材料131包含单层的上述低介电常数的介电材料。
如图12A至图12G所示，在沉积介电材料131之后，可进行非等向蚀刻工艺以修整介电材料131。图12A至图12G所示的剖视图的剖面，可与图8A至图8G所示的剖视图的剖面相同。蚀刻工艺移除沉积的介电材料131，使沉积的介电材料131的部分保留于移除第一半导体层103与芯203所形成的凹陷中。在蚀刻工艺之后，沉积的介电材料131的保留部分可形成内侧间隔物如介电材料131，如图12A至图12G所示。内侧间隔物如介电材料131用于隔离金属栅极与后续工艺中所形成的源极/漏极区。
接着如图13A至图13G所示，形成源极/漏极区133于区域100与区域200中的半导体带106上。图13A至图13G所示的剖视图的剖面，分别与图8A至图8G所示的剖视图的剖面相同。在一些实施例中，区域100的子区与区域200的子区可设计为用于n型装置或p型装置，且可由分开步骤形成n型装置的源极/漏极区133与p型装置的源极/漏极区133。可由分开步骤形成区域100的源极/漏极区133与区域200的源极/漏极区133。源极/漏极区133的形成方法可为外延成长材料于半导体带106上，其可采用合适方法如有机金属化学气相沉积、分子束外延、液相外延、气相外延、选择性外延成长、类似方法或上述的组合。外延的源极/漏极区133可具有隆起表面且可具有晶面。在一些例子中，此处所述的工艺可减少相邻的源极/漏极区133产生不想要的合并。可依据欲形成的装置型态，调整源极/漏极区133的材料。在一些实施例中，最终装置为n型装置，而源极/漏极区133包括碳化硅、磷化硅、掺杂磷的碳化硅或类似物。在一些实施例中，最终装置为p型装置，而源极/漏极区133包括硅锗与p型杂质如硼或铟。
注入掺杂至外延的源极/漏极区133之后，可进行退火工艺。注入工艺可包含形成与图案化掩模如光刻胶，以覆盖并保护不需注入的区域100及200的子区。源极/漏极区133的杂质(如掺杂)浓度可为约1E19 cm-3至约1E21cm-3。可注入p型杂质如硼或铟于p型晶体管的源极/漏极区133中。可布值n型杂质如磷或砷至n型晶体管的源极/漏极区133中。在一些实施例中，可在成长时原位掺杂外延的源极/漏极区。
图14A至图14E显示一些实施例中，形成置换栅极143的多种工艺阶段的区域100的剖视图。图14A至图14E所示的剖视图的剖面，可与图13A所示的剖视图的剖面相同。在图14A中，形成接点蚀刻停止层135于图13A所示的结构上，并形成层间介电层137于接点蚀刻停止层135上。接点蚀刻停止层135可作为后续蚀刻工艺中的蚀刻停止层，且可包含合适材料如氧化硅、氮化硅、氮氧化硅、上述的组合或类似物，且其形成方法可为合适方法如化学气相沉积、物理气相沉积、上述的组合或类似方法。层间介电层137形成于接点蚀刻停止层135之上与虚置栅极结构122周围。在一些实施例中，层间介电层137的组成为介电材料如氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、硼磷硅酸盐玻璃、未掺杂的硅酸盐玻璃或类似物，且其沉积方法可为任何合适方法如化学气相沉积、等离子体辅助化学气相沉积或可流动的化学气相沉积。
在图14B中，可进行平坦化工艺如化学机械研磨工艺以移除栅极123上的接点蚀刻停止层135的部分。如图14B所示，平坦化工艺后的层间介电层137的上表面可与栅极123的上表面齐平。之后在图14C中，以一或多道蚀刻步骤移除虚置栅极结构的栅极123与栅极介电层121，以形成凹陷128于栅极间隔物129之间。
在图14D中，移除第一半导体层103以露出第二半导体层105，使第二半导体层105的中心部分(比如内侧间隔物如介电材料131之间的部分与凹陷128之下的部分)悬空。在移除第一半导体层103之后，第二半导体层105可形成多个纳米结构110。换言之，第二半导体层105在后续工艺中可视作纳米结构110。可由选择性蚀刻工艺移除第一半导体层103，比如对第一半导体材料(如硅锗)的选择性高于对第二半导体材料(如硅)的选择性的干蚀刻或湿蚀刻。举例来说，可采用对硅锗具有选择性的湿蚀刻，比如氢氧化铵与过氧化氢与水的混合物、硫酸与过氧化氢的混合物或类似物。可采用其他合适的工艺及/或材料。值得注意的是，纳米结构110的中心部分悬空，其具有空间134于相邻的纳米结构110之间。上述选择性蚀刻工艺并未露出纳米结构110的其他部分(如栅极间隔物129之下的部分与栅极间隔物129的边界之外的部分，其可视作末端部分)。相反地，内侧间隔物如介电材料131可围绕纳米结构110的这些部分。
接着如图14E所示，形成界面层142于纳米结构110的表面上。界面层142为介电层如氧化物，且其形成方法可为热氧化工艺或沉积工艺。在一些实施例中，进行热氧化工艺以将纳米结构的外部部分转换成氧化物，以形成界面层142。
在形成界面层142之后，形成栅极介电层141于纳米结构110周围。栅极介电层141亦形成于浅沟槽隔离区111的上表面上。在一些实施例中，栅极介电层141包括高介电常数(比如介电常数大于约7.0)的介电材料，且可包含铪、铝、锆、镧、镁、钡、钛、铅或上述的组合的金属氧化物或硅酸盐。举例来说，栅极介电层141可包含氧化铪、氧化锆、铝酸铪、硅酸铪、氧化铝或上述的组合。栅极介电层141的形成方法可包含分子束沉积、原子层沉积、化学气相沉积、等离子体辅助化学气相沉积或类似方法。
接着形成导电材料(亦可视作填充金属)于凹陷128中，以形成栅极143。栅极143的组成可为含金属材料如铜、铝、钨、钌、类似物、上述的组合或上述的多层，且其形成方法可为电镀、无电镀、化学气相沉积、物理气相沉积或其他合适方法。在形成栅极143之后，可进行平坦化工艺如化学机械研磨，以平坦化栅极143的上表面。栅极143至少部分围绕纳米结构110以形成区域100中的全绕式栅极场效晶体管装置。
虽然未图示，在形成导电材料之前，可形成阻挡层与功函数层于栅极介电层141之上与纳米结构110周围。阻挡层可包含导电材料如氮化钛，但亦可改用其他材料如氮化钽、钛、钽或类似物。阻挡层的形成方法可采用化学气相沉积工艺，比如等离子体辅助化学气相沉积。然而可改用其他工艺如溅镀、有机金属化学气相沉积或原子层沉积。一些实施例在形成阻挡层之后，可形成一或多个功函数层(未图示)于阻挡层上。在一些实施例中，可形成n型功函数层于阻挡层之上与纳米结构110周围以用于n型装置，并可形成p型功函数层于阻挡层之上与纳米结构110周围以用于p型装置。n型装置所用的栅极结构中包含的例示性n型功函数金属，可包含钛、银、钽铝、碳化钽铝、氮化钛铝、碳化钽、碳氮化钽、氮化钽硅、锰、锆、其他合适的n型功函数材料或上述的组合。p型装置所用的栅极结构中包含的例示性p型功函数金属，可包含氮化钛、氮化钽、钌、钼、铝、氮化钨、锆硅化物、钼硅化物、钽硅化物、镍硅化物、其他合适的p型功函数材料或上述的组合。功函数层的沉积方法可采用化学气相沉积、物理气相沉积、原子层沉积及/或另一合适工艺。
图15A至图15D为一些实施例中，形成置换的栅极143的多种工艺阶段中的区域200的剖视图。图15A至图15D所示的剖视图的剖面，与图13B所示的剖视图的剖面相同。图15A至图15D中一些或全部的工艺步骤，可与图14A至图14E所示的类似步骤的进行方式相同。在图15A中，以一或多道蚀刻步骤移除虚置栅极结构222的栅极123与栅极介电层121。
在图15B中，移除芯203以露出通道区207，并使每一通道区207分开。在此方式中，可形成两个通道区207于每一半导体带206上。可由选择性蚀刻工艺移除芯203，比如对芯203(如硅锗)的选择性高于对第二半导体材料(如硅)的选择性的干蚀刻或湿蚀刻。选择性蚀刻工艺可与前述的选择性蚀刻工艺类似。如图15C所示，形成界面层142于通道区207的表面上。界面层142为介电层如氧化物，其形成方法可为热氧化工艺或沉积工艺。在一些实施例中，进行热氧化工艺以将通道区的外部部分转换成氧化物，以形成界面层142。
在形成界面层142之后，可形成栅极介电层141于通道区207周围。栅极介电层141亦形成于浅沟槽隔离区111的上表面上。在一些实施例中，栅极介电层141包括高介电常数(比如介电常数大于约7.0)的介电材料，其可与图14E所述的前述材料类似。栅极介电层141的形成方法可采用前述工艺。接着形成导电材料于通道区207上以形成栅极143。栅极143的组成可为上述的含金属材料，且其形成方法可采用上述工艺。在形成栅极143之后，可进行平坦化工艺如化学机械研磨以平坦化栅极143的上表面。在此方式中，可形成双通道鳍状场效晶体管装置于区域200中。
虽然未图示，在形成导电材料之前可形成阻挡层与功函数层于栅极介电层141之上与通道区207周围。阻挡层可与前述的阻挡层类似，且可由类似方式形成。一些实施例在形成阻挡层之后，可形成功函数层(未图示)于阻挡层上。功函数层可与前述的功函数层类似，且可由类似方法形成。
实施例可达一些优点。此处公开的工艺可形成纳米结构的场效晶体管与鳍状场效晶体管于相同基板上。如此一来，此处所述的工艺可形成混合通道的场效晶体管装置。采用硅锗形成芯，可外延成长每一鳍状场效晶体管所用的两个通道区。在此方式中，鳍状场效晶体管装置可具有两倍的通道区，并增加鳍状场效晶体管的电流容量。此外，采用硅锗可改善工艺一致性，并在形成时减少缺陷的机率。
在一实施例中，半导体装置包括：多个半导体带，自基板凸起，其中半导体带包括多个第一半导体带于基板的第一区中，以及多个第二半导体带于基板的第二区中；多个纳米结构，位于第一区的第一半导体带上并对准第一半导体带；多个第一源极/漏极区位于纳米结构的两端；第一栅极结构，部分地围绕纳米结构；多个双通道区，位于第二区的第二半导体带上，其中双通道区的每一个包括第一通道区对准第二半导体带的一个的第一侧，以及第二通道区对准第二半导体的一个的第二侧，其中第一通道区与第二通道区分开；多个第二源极/漏极区，位于双通道区的两端；以及第二栅极结构，位于双通道区上，其中第二栅极结构分开双通道区的每一第一通道区与对应的第二通道区。在一实施例中，纳米结构包括多个半导体纳米线。在一实施例中，每一双通道区的第一通道区与对应的第二通道区分隔的距离为5nm至10nm。在一实施例中，双通道区的第一通道区与对应的第二通道区的相对的侧壁平坦。在一实施例中，第二栅极结构接触双通道区的每一第一通道区与对应的第二通道区之间的第二半导体带的上表面。在一实施例中，双通道区为硅。在一实施例中，第一通道区与第二通道区的宽度为5nm至10nm。在一实施例中，基板的第一区与第二区相邻。
在一实施例中，半导体装置包括第一半导体带，自基板凸起；第二半导体带，自基板凸起；隔离材料，围绕第一半导体带与第二半导体带；纳米片结构，位于第一半导体带上，其中纳米片结构与第一半导体带隔有含栅极材料的第一栅极结构，其中第一栅极结构部分地围绕纳米片结构；以及第一半导体通道区与第二半导体通道区，位于第二半导体带上，其中第一半导体通道区与第二半导体通道区隔有含栅极材料的第二栅极结构，其中第二栅极结构延伸于第二半导体带的上表面上。在一实施例中，第一半导体通道区与第二半导体通道区自第二半导体带垂直延伸的距离介于40nm至约70nm之间。在一实施例中，第一半导体通道区与第二半导体通道区包括半导体硅。在一实施例中，第一半导体通道的第一部分比第二部分更靠近隔离材料，其中第一部分的宽度小于第二部分的宽度。在一实施例中，第一通道区延伸于隔离材料上。在一实施例中，第一半导体通道区与第二半导体通道区的背向表面之间的距离大于第二半导体带的宽度。在一实施例中，第二栅极结构延伸于第一半导体通道区与第二半导体通道区的背向表面上。
在一实施例中，半导体装置的形成方法，包括形成外延结构于半导体基板上，其中外延结构包括交错的硅层与硅锗层；使外延结构的一部分凹陷以形成沟槽；将硅锗填入沟槽；图案化沟槽中的硅锗以形成芯；外延成长硅于芯的侧壁上以形成通道区；移除芯；以及形成栅极结构于通道区上，且栅极结构延伸于通道区之间。在一实施例中，移除芯所采用的蚀刻工艺对硅锗的蚀刻选择性大于对硅的蚀刻选择性。在一实施例中，将硅锗填入沟槽的步骤可将硅锗填满沟槽。在一实施例中，上述方法还包括形成纳米结构，包括图案化外延结构以形成鳍状物；移除鳍状物的硅锗层；以及形成栅极于鳍状物的保留的硅层周围。在一实施例中，通道区相隔的距离介于5nm至约10nm之间。
上述实施例的特征有利于本技术领域中技术人员理解本发明。本技术领域中技术人员应理解可采用本发明作基础，设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中技术人员亦应理解，这些等效置换并未脱离本发明精神与范畴，并可在未脱离本发明的精神与范畴的前提下进行改变、替换或更动。

Claims (1)

1.一种半导体装置，包括：
多个半导体带，自一基板凸起，其中多个所述半导体带包括多个第一半导体带于该基板的一第一区中，以及多个第二半导体带于该基板的一第二区中；
多个纳米结构，位于该第一区的多个所述第一半导体带上并对准多个所述第一半导体带；
多个第一源极/漏极区位于多个所述纳米结构的两端；
一第一栅极结构，部分地围绕多个所述纳米结构；
多个双通道区，位于该第二区的多个所述第二半导体带上，其中多个所述双通道区的每一个包括一第一通道区对准多个所述第二半导体带的一个的第一侧，以及一第二通道区对准多个所述第二半导体的一个的第二侧，其中该第一通道区与该第二通道区分开；
多个第二源极/漏极区，位于多个所述双通道区的两端；以及
一第二栅极结构，位于多个所述双通道区上，其中该第二栅极结构分开多个所述双通道区的每一该第一通道区与对应的该第二通道区。
CN202110096447.3A 2020-02-11 2021-01-25 半导体装置 Pending CN113161353A (zh)

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