TW202218093A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

Info

Publication number
TW202218093A
TW202218093A TW110124757A TW110124757A TW202218093A TW 202218093 A TW202218093 A TW 202218093A TW 110124757 A TW110124757 A TW 110124757A TW 110124757 A TW110124757 A TW 110124757A TW 202218093 A TW202218093 A TW 202218093A
Authority
TW
Taiwan
Prior art keywords
layer
backside
semiconductor
semiconductor layer
source
Prior art date
Application number
TW110124757A
Other languages
English (en)
Inventor
黃柏瑜
桃佳賢
楊復凱
王美勻
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202218093A publication Critical patent/TW202218093A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Geometry (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)

Abstract

揭露半導體裝置與其形成方法。例示性的半導體裝置包括介電層，形成於電源軌上；底部半導體層，形成於介電層上；背側間隔物，沿著底部半導體層的側壁；導電結構，接觸介電層的側壁與背側間隔物的側壁；多個通道半導體層，位於底部半導體層上，其中通道半導體層向上堆疊並彼此分開；金屬閘極結構，包覆每一通道半導體層；以及磊晶的源極/汲極結構，接觸每一通道半導體層的側壁，其中磊晶的源極/汲極結構接觸導電結構，且導電結構接觸電源軌。

Description

半導體裝置
本發明實施例一般關於半導體裝置與其製作方法，更特別關於製作場效電晶體如鰭狀場效電晶體或奈米片裝置的方法。
積體電路產業已經歷指數成長。已導入三維多閘極裝置以改善裝置效能。三維多閘極裝置的一例為鰭狀場效電晶體裝置，另一例為奈米片裝置(亦稱作奈米線裝置、奈米環裝置、閘極圍繞裝置、全繞式閘極裝置、或多通道橋裝置)。三維多閘極裝置的鰭狀物寬度需要窄小以用於控制短通道，使其源極/汲極區小於平面場效電晶體的源極/汲極區。隨著裝置尺寸縮小，可形成電源軌於基板背側。然而現存的電源軌仍面臨多種挑戰，包括線路電阻、對準容許範圍、及/或佈局彈性。因此需要三維閘極裝置與電源軌的新穎結構及形成方法，解決這些問題以增進電路效能與可信度。
本發明實施例提供許多不同實施例。此處揭露具有背側間隔物的半導體裝置與其製作方法。例示性的半導體裝置包括介電層，形成於電源軌上；底部半導體層，形成於介電層上；背側間隔物，沿著底部半導體層的側壁；導電結構，接觸介電層的側壁與背側間隔物的側壁；多個通道半導體層，位於底部半導體層上，其中通道半導體層向上堆疊並彼此分開；金屬閘極結構，包覆每一通道半導體層；以及磊晶的源極/汲極結構，接觸每一通道半導體層的側壁，其中磊晶的源極/汲極結構接觸導電結構，且導電結構接觸電源軌。
另一例示性半導體裝置包括介電層，形成於電源軌上；底部半導體層，形成於介電層上；導電結構，凸起穿過介電層與底部半導體層，其中導電結構的下側部分接觸介電層的側壁；間隔物，形成於導電結構的上側部分與底部半導體層的側壁之間；磊晶的源極結構，形成於半導體裝置的源極區上並接觸導電結構的上表面；以及磊晶的汲極結構，形成於半導體裝置的汲極區上並接觸底部半導體層的上表面。
半導體裝置的形成方法包括磊晶成長犧牲層於基板上；磊晶成長底部半導體層於犧牲層上，其中底部半導體層的材料與犧牲層的材料不同；形成半導體堆疊於底部半導體層上，其中半導體堆疊包括第一半導體層與第二半導體層交錯堆疊於底部半導體層上，且第一半導體層的材料與第二半導體層的材料不同；形成虛置閘極結構於半導體堆疊上；形成源極/汲極溝槽於虛置閘極結構之間，其中源極/汲極溝槽的下表面低於犧牲層的下表面；磊晶成長半導體結構於源極/汲極溝槽中，其中半導體結構與底部半導體層包括相同材料；磊晶成長源極/汲極結構於源極/汲極溝槽中的半導體結構上；移除基板並將犧牲層置換成介電層；移除半導體結構與底部半導體層的一部分，以形成背側溝槽，其中背側溝槽包括沿著介電層的側壁並延伸至源極/汲極結構的下表面之主要部分，以及橫向遠離主要部分並沿著底部半導體層的側壁之側部；形成背側間隔物於背側溝槽的側部中；以及形成導電結構於背側溝槽的主要部分中。
下述詳細描述可搭配圖式說明，以利理解本發明的各方面。值得注意的是，各種結構僅用於說明目的而未按比例繪製，如本業常態。實際上為了清楚說明，可任意增加或減少各種結構的尺寸。
下述內容提供的不同實施例或例子可實施本發明實施例的不同結構。特定構件與排列的實施例係用以簡化本揭露而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。
此外，本發明之多種實例可重複採用相同標號以求簡潔，但多種實施例及/或設置中具有相同標號的元件並不必然具有相同的對應關係。此外，本發明實施例之結構形成於另一結構上、連接至另一結構、及/或耦接至另一結構中，結構可直接接觸另一結構，或可形成額外結構於結構及另一結構之間(即結構未接觸另一結構)。此外，空間性的相對用語如「下方」、「其下」、「下側」、「上方」、「上側」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。此外，當數值或數值範圍的描述有「約」、「近似」、或類似用語時，除非特別說明否則其包含所述數值的+/-10%。舉例來說，用語「約5 nm」包含的尺寸範圍為4.5 nm至5.5 nm。
在三維場效電晶體中，為了減少裝置尺寸與能耗，可形成電源軌於基板背側上。此外，電源軌經由背側通孔連接至磊晶的源極結構。在習知的三維場效電晶體中，為了避免源極至源極或者源極至閘極的漏電流(如背側漏電流)，可沿著通孔溝槽的側壁形成介電保護層。然而保護層會造成金屬填充製程的容許範圍小，因此難以形成背側通孔並減少電源軌對準的容許範圍。保護層亦造成高寄生電阻，因此劣化半導體裝置的效能。
在本發明實施例中，採用背側間隔物取代介電保護層，以避免背側漏電流的問題。背側間隔物比習知的背側間隔物厚，但不占據通孔溝槽的空間，進而比介電保護層提供更佳的隔離效果。背側通孔的側壁可直接接觸背側介電層與背側通孔。可加大背側通孔與磊晶的源極結構之間的矽化物層以及背側通孔的尺寸而無保護層。因此可加大電源軌對準的容許範圍，緩解層疊偏移問題、並降低繞線電阻。因此可改善半導體裝置的效能與可信度。
圖1顯示本發明一些實施例中，製造半導體的裝置200之方法100的流程圖。方法100僅為舉例而非侷限本發明實施例至請求項未實際記載處。在方法100之前、之中、與之後可進行額外步驟，且方法的額外實施例可置換、省略、或調換一些所述步驟。方法100將搭配其他圖式說明如下，其顯示裝置200在方法100的中間步驟時的多種三維圖與剖視圖。具體而言，圖2係本發明一些實施例中，裝置200在圖1的方法之初始階段的三維圖。圖3、4、5、6、7、8、9、10、11、12、13A、14、15、16、17、18、19、20、及21A係本發明一些實施例中，半導體裝置在圖1的中間階段時沿著圖2中的剖面A-A' (如X-Z'平面)的剖視圖。此外，圖13B及21B分別為圖13A及21A的上下翻轉圖。
裝置200可為處理積體電路或其部分時所製作的中間裝置，其可包含靜態隨機存取記憶體及/或其他邏輯電路、被動構件(如電阻、電容器、與電感)、或主動構件(如p型場效電晶體、n型場效電晶體、金氧半場效電晶體、互補式金氧半電晶體、高電壓電晶體、高頻電晶體、及/或其他記憶體單元)。裝置200可為積體電路的核心區(通常視作邏輯區)、記憶體區(如靜態隨機存取記憶體區)、類比區、周邊區(通常視作輸入/輸出區)、虛置區、其他合適區、或上述之組合的一部分。在一些實施例中，裝置200可為積體電路晶片的一部分、單晶片系統、或其部分。本發明實施例不限於任何特定數目的裝置或裝置區，或任何特定裝置設置。舉例來說，雖然圖式中的裝置200為奈米片裝置，本發明實施例亦可用於製作鰭狀場效電晶體或平面場效電晶體裝置。
如圖1、2、及3所示，步驟105形成裝置200的初始半導體結構。如圖2及3所示，裝置200包括基板202。在一些實施例中，基板202為基體矽基板。基板202可改為或額外包含另一單晶半導體如鍺、半導體化合物、半導體合金、或上述之組合。在一些實施例中，基板202為絕緣層上半導體基板，比如絕緣層上矽基板、絕緣層上矽鍺基板、或絕緣層上鍺基板。在所述實施例中，基板202為絕緣層上矽基板。舉例來說，基板202包含矽層202-1及202-3，以及氧化矽層202-2形成於矽層202-1及202-3之間。在自背側型成電源軌之前，移除基板202時的氧化矽層202-2可作為蝕刻停止層。絕緣層上半導體基板的製作方法可為分離佈植氧、晶圓接合、及/或其他合適方法。基板202可摻雜不同摻質以型成多種摻雜區於其中。舉例來說，基板202可包括含n型摻雜基板區(如n型井)的p型場效電晶體區，以及含p型摻雜基板區(如p型井)的n型場效電晶體。在下述圖式中，基板202可簡化為單一層狀物。
裝置200包含交錯的半導體層形成於基板202上。以圖2及3為例，犧牲層204形成於基板202上。在一些實施例中，犧牲層204包括的半導體材料與基板202不同，可在背側製程中提供不同於基板202的氧化速率及/或蝕刻選擇性。在所述實施例中，犧牲層204包括矽鍺，而基板202包括矽。在一些實施例中，犧牲層204磊晶成長於基板202上，且磊晶製程可包含化學氣相沉積(比如氣相磊晶、超高真空化學氣相沉積、低壓化學氣相沉積、有機金屬化學氣相沉積、及/或電漿輔助化學氣相沉積)、分子束磊晶、其他合適的選擇性磊晶成長製程、或上述之組合。
如圖2及3所示，底部半導體層206形成於犧牲層204上。底部半導體層206包括的半導體材料與犧牲層204不同，以在形成背面通孔之前選擇性移除犧牲層204。在一些實施例中，底部半導體層206包括的材料與基板相同(如矽)。在一些實施例中，底部半導體層206的形成方法亦為磊晶成長製程，比如化學氣相沉積(如氣相磊晶、超高真空化學氣相沉積、低壓化學氣相沉積、有機金屬化學氣相沉積、及/或電漿輔助化學氣相沉積)、分子束磊晶、其他合適的選擇性磊晶成長製程、或上述之組合。如圖3所示，底部半導體層206的高度T沿著Z方向。高度T可決定背側間隔物的高度，因此不可過大或過小。舉例來說，若高度T過小，則無足夠空間形成足夠寬度的背側間隔物以良好地隔離背側通孔與底部半導體層206。若高度T過大，則形成背側通孔的金屬填隙製程不易，且背側通孔尺寸加大而造成高電阻。在一些實施例中，高度T為約15 nm至約30 nm。
之後可形成半導體的堆疊210 (包含交錯的半導體層210A及210B)於底部半導體層206上。在一些實施例中，半導體層210A包括第一半導體材料，半導體層210B包括第二半導體材料，且第一半導體材料與第二半導體材料不同。半導體層210A及210B的不同半導體材料具有不同的氧化速率及/或不同的蝕刻選擇性。在一些實施例中，半導體層210B的第二半導體材料與基板202相同。在所述實施例中，半導體層210B包括矽(如基板202)，而半導體層210A包括矽鍺。因此由下至上配置交錯的矽鍺/矽/矽鍺/矽…層於底部半導體層206上。在一些實施例中，頂部半導體層的材料可或可不與底部半導體層的材料相同。在一些實施例中，半導體層210B可不摻雜或實質上無摻雜。換言之，在形成半導體層210B時不刻意進行摻雜。在一些其他實施例中，半導體層210B可摻雜p型摻質或n型摻質。半導體層210A及210B的數目取決於裝置200的設計需求。舉例來說，可包含一至十層的半導體層210A或210B。在一些實施例中，不同的半導體層210A及210B在Z方向中具有相同厚度。在一些其他實施例中，不同的半導體層210A及210B具有不同厚度。在一些實施例中，半導體層210A及/或210B的形成方法為合適磊晶製程。舉例來說，可交錯形成含矽鍺的半導體層與含矽的半導體層於底部半導體層206上，且形成方法可為磊晶成長製程如化學氣相沉積(如氣相磊晶、超高真空化學氣相沉積、低壓化學氣相沉積、有機金屬化學氣相沉積、及/或電漿輔助化學氣相沉積)、分子束磊晶、其他合適的選擇性磊晶成長製程、或上述之組合。
接著圖案化交錯的半導體層210A及210B以形成堆疊210。可形成光阻並對半導體層210A及210B進行蝕刻製程以形成鰭狀的堆疊210，如圖2所示。舉例來說，首先形成圖案化的光阻遮罩於裝置200上。依據裝置200的設計需求，圖案化的光阻遮罩可覆蓋鰭狀部分。之後可採用圖案化的光阻遮罩進行一或多道蝕刻製程，以形成堆疊210。蝕刻製程可包含乾蝕刻、濕蝕刻、其他合適的蝕刻製程、或上述之組合。此外，接著可由任何合適方法(如灰化製程)移除光阻遮罩。在所述實施例中，採用圖案化的光阻遮罩進行一或多道蝕刻製程，可移除半導體層210A及210B以形成鰭狀堆疊210。溝槽形成於堆疊210之間。
之後如圖2所示，形成隔離結構208於堆疊210之間的溝槽中，以分開並隔離裝置200的主動區。在一些實施例中，可沿著堆疊210的側壁沉積一或多種介電材料如氧化矽及/或氮化矽於底部半導體層206上。介電材料的沉積方法可為化學氣相沉積(如電漿輔助化學氣相沉積)、物理氣相沉積、熱氧化、或其他技術。之後可使介電材料凹陷以形成隔離結構208，且凹陷步驟可為蝕刻及/或化學機械研磨。在一些實施例中，隔離結構208的上表面可與堆疊的最下側的半導體層的下表面實質上共平面，或低於堆疊的最下側的半導體層的下表面。
如圖1及4所示，步驟110形成虛置閘極結構220於堆疊210上。每一虛置閘極結構220可作為後續形成金屬閘極結構所用的占位物。虛置閘極結構220沿著Y方向延伸並越過個別的堆疊210。虛置閘極結構220覆蓋堆疊210的通道區，並夾設於源極區與汲極區(均視作源極/汲極區)之間。每一虛置閘極結構220可包含多種虛置層。在所述實施例中，虛置閘極結構220包括界面層212 (比如含氧化矽)位於堆疊210與基板202上、虛置閘極214 (比如含多晶矽)位於界面層212上、以及一或多個硬遮罩層216 (比如含介電材料如氮化矽、碳氮化矽、氧化矽、或類似物)位於虛置閘極214上。在一些實施例中，虛置閘極結構220亦可包含其他合適層。虛置閘極結構220的形成方法可為沉積製程、微影製程、蝕刻製程、其他合適製程、或上述之組合。舉例來說，可沉積不同虛置層於堆疊210上。接著進行微影製程以形成遮罩而覆蓋堆疊210的通道區。之後可採用微影遮罩蝕刻不同的虛置層，以形成虛置閘極結構220。此外，之後可採用任何合適方法(如灰化製程)移除微影遮罩。
如圖1及4所示，沿著堆疊210上的虛置閘極結構220的側壁形成閘極間隔物222。在一些實施例中，閘極間隔物222包括介電材料如氧化矽、氮化矽、氮氧化矽、碳化矽、其他介電材料、或上述之組合。閘極間隔物222的形成方法可為任何合適製程。舉例來說，先沿著虛置閘極結構220與堆疊210的側壁與上表面，沉積含介電材料的間隔物層於隔離結構208上，且沉積方法可為原子層沉積、化學氣相沉積、物理氣相沉積、或其他合適製程。之後可非等向蝕刻間隔物層以移除X-Y平面(如基板202的上表面的平面)中的部分間隔物層。間隔物層的保留部分轉變成閘極間隔物222。
如圖1及5所示，步驟115形成源極/汲極溝槽224於堆疊210的源極/汲極區上。如圖5所示，沿著閘極間隔物222的側壁使堆疊210的源極/汲極區凹陷，以形成源極溝槽224S與汲極溝槽224D (均視作源極/汲極溝槽224)。在所述實施例中，源極溝槽224S形成於堆疊210的源極區上，而汲極溝槽224D形成於堆疊210的汲極區上。可沿著閘極間隔物222進行源極/汲極蝕刻製程，使堆疊210的源極/汲極區凹陷。源極/汲極蝕刻製程可為乾蝕刻(如反應性離子蝕刻)、濕蝕刻、或上述之組合。控制源極/汲極蝕刻製程的時間，使源極/汲極溝槽中的每一半導體層210A及210B的側壁露出。如圖5所示，源極溝槽224S具有沿著X方向的寬度W1。寬度W1取決於裝置200的設計需求。在一些實施例中，寬度W1為約20 nm至約40 nm。
如圖1、6、及7所示，步驟120形成內側間隔物226於半導體層210B的邊緣之間。如圖6所示，可採用合適蝕刻製程選擇性移除源極/汲極溝槽224中的半導體層210A的露出部分(邊緣)，以形成間隙於半導體層210B之間。換言之，半導體層210B的邊緣部分懸空於源極/汲極溝槽224中。由於半導體層210A的材料(如矽鍺)與半導體層210B的材料(如矽)的氧化速率及/或蝕刻選擇性不同，只移除半導體層210A的露出部分(邊緣)，而半導體層210B維持實質上不變。在一些實施例中，選擇性移除半導體層210A的露出部分之方法可包含氧化製程與之後的選擇性蝕刻製程。舉例來說，先選擇性氧化半導體層210A的邊緣部分已包含矽鍺氧化物的材料。接著以合適蝕刻劑如氫氧化銨或氫氟酸進行選擇性蝕刻製程，以移除矽鍺氧化物。可控制氧化製程與選擇性蝕刻製程，以只選擇性移除半導體層210A的邊緣部分。
之後如圖7所示，形成內側間隔物226以填入半導體層210B之間的間隙。內側間隔物226包括介電材料如氧化矽、氮化矽、氮氧化矽、碳化矽、或上述之組合。可沉積內側間隔物的介電材料於源極/汲極溝槽224中，以及半導體層210B的邊緣之間的間隙中，且沉積方法可為原子層沉積、化學氣相沉積、物理氣相沉積、或上述之組合。接著沿著閘極間隔物222移除多餘介電材料，直到源極/汲極溝槽224中露出半導體層210B的側壁。
如圖1及8所示，步驟125使虛置閘極結構220之間的源極溝槽224S進一步凹陷，而汲極溝槽224D實質上不變。在一些實施例中，凹陷製程關於微影與蝕刻製程。舉例來說，首先沉積光阻層於基板上。接著將光阻層暴露於圖案層230，其露出源極溝槽224S並覆蓋汲極溝槽224D。之後進行曝光後烘烤製程並顯影光阻層以形成遮罩層228，其露出虛置閘極結構220之間的源極溝槽224S，並覆蓋汲極溝槽224D。如圖8所示，採用圖案化的遮罩層228作為遮罩，並進行後續的源極/汲極蝕刻製程，使源極溝槽224S進一步凹陷，而汲極溝槽224D維持實質上不變。如圖8所示，源極溝槽224S的下表面低於犧牲層204的下表面，而汲極溝槽224D的下表面高於犧牲層204的上表面。換言之，犧牲層204與底部半導體層206在虛置閘極結構220之間的源極區中分開，且凹陷的源極/汲極溝槽224S中露出犧牲層204與底部半導體層206的側壁。在使源極溝槽224S凹陷之前或之後，可移除圖案層230。
如圖1、9、及10所示，步驟130形成磊晶的源極/汲極結構240於源極/汲極溝槽224中。如圖9所示，首先自源極溝槽224S中的基板202、犧牲層204、與底部半導體層206磊晶成長半導體結構232。半導體結構232包括的材料可提供不同於犧牲層204的材料之氧化速率及/或蝕刻選擇性。舉例來說，半導體結構232包括矽，而犧牲層204包括矽鍺。磊晶製程可包含化學氣相沉積(如氣相磊晶、超高真空化學氣相沉積、低壓化學氣相沉積、有機金屬化學氣相沉積、及/或電漿輔助化學氣相沉積)、分子束磊晶、其他合適的選擇性磊晶成長製程、或上述之組合。在形成半導體結構232之後，接著移除遮罩層228。
之後如圖10所示，分別磊晶成長磊晶的源極結構240S與磊晶的汲極結構240D (均可視作磊晶的源極/汲極結構240)於源極溝槽224S與汲極溝槽224D中。在一些實施例中，每一磊晶的源極/汲極結構240包括半導體材料如矽或鍺，半導體化合物如矽鍺、碳化矽、砷化鎵、或類似物，半導體合金，或上述之組合。一些實施例在磊晶成長源極/汲極結構240之前，磊晶成長未摻雜的矽層234於源極/汲極溝槽224中，以改善源極/汲極結構240的磊晶成長表面。在一些實施例中，矽層234可視作源極/汲極結構240的一部分。可實施磊晶製程以磊晶成長矽層234及/或源極/汲極結構240。磊晶製程可包含化學氣相沉積(如氣相磊晶、超高真空化學氣相沉積、低壓化學氣相沉積、有機金屬化學氣相沉積、及/或電漿輔助化學氣相沉積)、分子束磊晶、其他合適的選擇性磊晶成長製程、或上述之組合。磊晶的源極/汲極結構240可摻雜n型摻質及/或p型摻質。在一些實施例中，磊晶的源極/汲極結構240可包含多個磊晶半導體層，且不同的磊晶半導體層中包含的摻質量不同。
如圖1、11、12、13A、及13B所示，步驟135進行金屬閘極置換製程以將虛置閘極結構220置換成金屬閘極結構250。金屬閘極置換製程包括多種製程步驟。以圖11為例，形成層間介電層242於基板202上。層間介電層242沿著閘極間隔物222並形成於隔離結構208與磊晶的源極/汲極結構240上。在一些實施例中，層間介電層242包括低介電常數(＜3.9)的介電材料，比如四乙氧基矽烷的氧化物、未摻雜的矽酸鹽玻璃、摻雜氧化矽(如硼磷矽酸鹽玻璃、氟矽酸鹽玻璃、磷矽酸鹽玻璃、或硼矽酸鹽玻璃)、其他合適介電材料、或上述之組合。層間介電層242的形成方法可為沉積製程如化學氣相沉積、可流動的化學氣相沉積、旋轉塗佈玻璃、其他合適方法、或上述之組合。在一些實施例中，可進行平坦化製程以移除虛置閘極結構上多餘的層間介電材料與虛置閘極結構的頂部，以露出虛置閘極。
如圖11所示，移除虛置閘極結構220的保留部分以形成閘極溝槽244，其露出堆疊210的通道區。在一些實施例中，移除虛置閘極結構220的方法包括一或多道蝕刻製程，比如濕蝕刻、乾蝕刻(反應性離子蝕刻)、或其他蝕刻技術。接著在閘極溝槽244中露出半導體層210A及210B。
之後如圖12所示，自閘極溝槽244選擇性移除半導體層210A。由於半導體層210A及210B的材料不同，可由與移除半導體層210A的邊緣部分之選擇性氧化與蝕刻製程類似的步驟，移除半導體層210A。在一些實施例中，步驟135稍微蝕刻或不蝕刻半導體層210B。因此半導體層210B懸空於堆疊210的通道區中，並沿著實質上垂直於基板202的上表面(如X-Y平面)的方向(如Z方向)向上堆疊。懸空的半導體層210B亦可視作通道半導體層。
接著如圖13A所示，形成金屬閘極結構250於堆疊210的通道區上。金屬閘極結構250包覆每一懸空的通道半導體層如半導體層210B。在一些實施例中，每一金屬閘極結構250包括閘極介電層252、金屬閘極254、及/或其他金屬閘極層。在一些實施例中，閘極介電層252包括高介電常數(＞3.9)的介電材料，比如氧化鉿、氧化鉿矽、矽酸鉿、氮氧化鉿矽、氧化鉿鑭、氧化鉿鉭、氧化鉿鈦、氧化鉿鋯、氧化鉿鋁、氧化鋯、二氧化鋯、氧化鋯矽、氧化鋁、氧化鋁矽、三氧化二鋁、氧化鈦、二氧化鈦、氧化鑭、氧化鑭矽、三氧化二鉭、五氧化二鉭、氧化釔、鈦酸鍶、氧化鋇鋯、鈦酸鋇、鈦酸鋇鍶、氮化矽、氧化鉿-氧化鋁合金、其他合適的高介電常數的介電材料、或上述之組合。在一些實施例中，閘極介電層252的沉積方法為化學氣相沉積、物理氣相沉積、原子層沉積、及/或其他合適方法。接著將金屬閘極254填入閘極介電層252之間的空間。每一金屬閘極254包括一或多個功函數層與基體金屬。功函數層設置以調整對應電晶體的功函數，以達所需的臨界電壓。基體金屬設置以作為功能閘極結構的主要導電部分。在一些實施例中，功函數金屬層的材料可包含鈦鋁、碳化鈦鋁、碳化鉭鋁、氮化鈦鋁、氮化鈦、氮化鈦矽、氮化鉭、碳氮化鎢、鉬、其他材料、或上述之組合。基體金屬可包含鋁、鎢、銅、或上述之組合。金屬閘極254的多種層狀物知形成方法可為任何合適方法，比如化學氣相沉積、原子層沉積、物理氣相沉積、電鍍、化學氧化、熱氧化、其他合適方法、或上述之組合。之後可進行一或多道研磨製程(比如化學機械研磨)以移除任何多餘的導電材料，並平坦化裝置200的上表面。
接著可形成多種內連線結構(未圖示)於裝置200的頂部(如前側)上。在一些實施例中，多種內連線結構可包含介電的層間介電層、導電的源極/汲極接點、通孔、金屬線路、及/或其他結構，其設置以連接多種結構以形成含有一或多個多閘極裝置的功能電路。之後為了方便處理與說明，可將裝置200上下翻轉以製作背側電源軌。圖13B僅為圖13A的結構之上下反轉圖，其裝置200在上下翻轉的X-Z平面中(比如前側朝下，而背側朝上)。此外，後續的圖14至20與圖21A係上下翻轉的裝置200在X-Z平面中的剖視圖。
如圖1及14所示，步驟140自裝置200的底部(如背側)移除基板202，以露出半導體結構232與犧牲層204。在一些實施例中，移除基板202的方法包含多種製程，比如蝕刻製程(比如濕蝕刻、乾蝕刻、其他蝕刻製程、或上述之組合)與平坦化製程(比如化學機械研磨或其他合適的平坦化製程)。
之後如圖1、15、及16所示，步驟145將犧牲層204置換成底部介電層256。如圖15所示，由於犧牲層204包括的材料(如矽鍺)之選擇性不同於底部半導體層206與半導體結構232的材料(如矽)，可由選擇性蝕刻製程選擇性移除犧牲層204。選擇性蝕刻製程與移除半導體層210A所用的上述遠擇性氧化與蝕刻製程類似。接著如圖16所示，形成底部介電層256以取代犧牲層204。在一些實施例中，底部介電層256包含介電層如氧化矽、氮氧化矽、氮化矽、碳氮氧化矽、碳氮化矽、碳氧化矽、其他介電材料、或上述之組合。可沉積底部介電層256的介電材料於底部半導體層206與半導體結構232的背側上，且沉積方法可為原子層沉積、化學氣相沉積、其他合適沉積製程、或上述之組合。之後可進行平坦化製程如化學機械研磨以移除多餘介電材料而露出半導體結構232。保留的介電材料形成底部介電層256。
如圖1、17、及18所示，步驟150形成背側間隔物260。如圖17所示，可選擇性移除半導體結構232與底部半導體層206接觸半導體結構232的部分(比如底部半導體層206的側部)，以形成背側溝槽258。在一些實施例中，步驟150亦移除源極溝槽中的矽層234與磊晶的源極結構240S的底部，使背側溝槽258的下表面在上下翻轉的方向中，低於底部半導體層206的下表面。換言之，步驟150橫向蝕刻底部半導體層206，且背側溝槽258穿過底部半導體層206。背側溝槽258露出內側間隔物226的一部分以及底部介電層256與底部半導體層206的側壁。此外，背側溝槽258中露出的底部半導體層206的側壁之間的距離，比背側溝槽258中露出的底部介電層256的側壁之間的距離大了寬度D。在所述實施例中，背側溝槽258包括主要部分如通孔溝槽258V以用於形成背側通孔，其沿著底部介電層256的側壁延伸至磊晶的源極結構240S的下表面。背側溝槽258亦包括側部258S沿著底部半導體層206的橫向凹陷的側部。在一些實施例中，背側溝槽258的形成方法可為一步的等向選擇性蝕刻製程。在一些實施例中，背側溝槽258的形成方法為非等向選擇性蝕刻製程，與之後的等向選擇性蝕刻製程。在一些實施例中，選擇性蝕刻溶液可包含氫氧化鉀、氫氧化四甲基銨、其他鹼性溶液、或上述之組合。在所述實施例中，底部半導體層206包括矽，等向蝕刻製程可為採用濃度為約1:5至約1:30的氫氧化銨的選擇性乾蝕刻，其溫度可為約50℃至約70℃，且歷時約120秒至約300秒。選擇性蝕刻製程時間可控制背側溝槽的側部258S的寬度D。
之後如圖18所示，形成背側間隔物260於背側溝槽的側部258S中。因此只自裝置200的背側打開通孔溝槽258V。在一些實施例中，背側間隔物260的材料可提供不同於底部介電層256的材料之氧化速率及/或蝕刻選擇性。舉例來說，背側間隔物260包括的材料可為氧化矽、氮氧化矽、氮化矽、碳氮氧化矽、碳氮化矽、或碳氧化矽。在一些實施例中，可由原子層沉積或其他合適的沉積製程形成背側間隔物260於被側溝槽的側部258S中。如圖18所示，背側間隔物260在上下翻轉的方向中接觸凹陷的底部半導體層206的側壁、底部介電層256的下表面、與內側間隔物226的上表面。因此底部介電層256、背側間隔物260、與內側間隔物226的側壁形成背側溝槽258的側壁。在形成背側間隔物260之後，通孔溝槽258V只包含介電材料。每一背側間隔物260具有沿著X方向的寬度D與沿著Z方向的高度T。此外，背側間隔物260之間沿著X方向的距離為寬度W1 (如通孔溝槽258V的寬度)。控制寬度D使其厚度(例如比習知的介電保護層厚)足以提供後續形成的背側通孔與背側半導體層之間的良好隔離。亦控制寬度D使其厚度不會太大，以避免在形成背側間隔物260的沉積製程時形成空洞。背側間隔物260的高度T取決於底部半導體層206的厚度。如上所述，高度T不可過大，以符合背側通孔造成的電阻與金屬填隙製程的考量。高度T不可過小，以提供足夠空間形成背側間隔物260。在一些實施例中，寬度D為約20%至約25%的通孔溝槽258V的寬度W1，而高度T為約60%至約80%的寬度W1，而寬度D為約25%至約35%的高度T。在一些其他實施例中，寬度D為約4 nm至約10 nm，高度T為約15 nm至約30 nm，且寬度W1為約20 nm至約40 nm。
如圖1、19、及20所示，步驟155形成背側通孔262於通孔溝槽258V中。一些實施例在沉積背側通孔的導電材料之前，可進行預清潔以移除通孔溝槽258V的表面上的氧化物(如表面準備步驟)。舉例來說，採用合適的化學溶液後之後由水沖洗，以清潔通孔溝槽258V。預清潔製程亦可橫向移除底部介電層256的側部，以形成通孔溝槽258V的側壁部分。因此通孔溝槽258V包括背側間隔物260之間的第一部分258V-1，與底部介電層256之間的第二部分258V-2。如圖19所示，第二部分258V-2的寬度W2大於第一部分258V-1的寬度W1。換言之，預清潔製程之後可加大通孔溝槽258V的開口。在一些實施例中，寬度W2比寬度W1大了約25%至約45%。
之後形成背側通孔262於通孔溝槽258V中。在一些實施例中，背側通孔262包括導電材料如鎢、釕、鈷、銅、鉬、鎳、鈦、氮化鈦、氮化鉭、其他導電材料、或上述之組合。在一些實施例中，背側通孔262的導電材料沉積於通孔溝槽258V之中與底部介電層256的背側表面之上的方法，可為任何合適製程。接著進行平坦化製程如化學機械研磨以移除多餘的導電材料並露出底部介電層256。因此保留的導電材料可形成背側通孔262。如圖20所示，背側通孔262包括背側間隔物260之間的第一部分與底部介電層256之間的第二部分，其可連接至後續形成的背側電源軌。背側通孔262的第一部分具有寬度W1，背側通孔262的第二部分具有寬度W2，且寬度W2大於寬度W1。預清潔時間可控制寬度W2，使其不過大或過小。若寬度W2過大，則可能破壞背側隔離而造成背側通孔262的導電材料與底部半導體層206之間的漏電流。若寬度W2過小，則無法加大背側通孔的尺寸以緩解層疊偏移的問題與減少電阻。在一些實施例中，寬度W1為約70%至約80%的寬度W2。在一些其他實施例中，寬度W2為約30 nm至約50 nm，而寬度W1為約20 nm至約40 nm。
如圖20所示，可形成矽化物層264於磊晶的源極結構240S與背側通孔262之間，以進一步降低兩者之間的寄生電阻。在一些實施例中，可進行退火製程以形成矽化物層264於背側通孔262與磊晶的源極結構240S之間。加熱造成磊晶的源極結構240S的組成與背側通孔262反應，使矽化物層264可包含背側通孔262的導電材料與磊晶的源極結構240S的組成，比如鈦矽化物、鈷矽化物、鉬矽化物、或類似物。如圖20所示，矽化物層264直接接觸內側間隔物226的側壁。在一些實施例中，矽化物層264視作背側通孔262的一部分。
如圖1、21A、及21B所示，步驟160形成電源軌270與其他背側內連線結構280於裝置200的背側上。在一些實施例中，電源軌270包括導電材料如銅、鋁、鈷、鎢、鈦、鉭、釕、其他金屬材料、或上述之組合。電源軌270的形成方法可為任何合適方法，比如化學氣相沉積、原子層沉積、物理氣相沉積、電鍍、化學氧化、熱氧化、其他合適方法、或上述之組合。此外，可由裝置200的設計需求採用光阻及/或蝕刻製程以圖案化電源軌270的形狀。因此磊晶的源極結構240S可經由背側通孔262與電源軌270連接至對應的電源(如汲極電源電壓)。圖21B為圖21A的上下翻轉圖，其中裝置200在一般的X-Z平面中(比如前側朝上而背側朝下)。
與習知半導體裝置中沿著背側通孔的側壁之介電保護層相較，本發明實施例的半導體裝置採用背側間隔物以實現導電材料與半導體材料之間的隔離。背側間隔物比習知的介電保護層厚，因此可改善源極與源極之間的隔離或源極與閘極之間的隔離。預清潔製程可加大背側通孔尺寸而無保護介電層，並進一步加大連接至電源軌的部分。因此可緩解形成背側電源軌時的層疊偏移問題，並降低線路電阻。此外，由於不沿著側部形成介電保護層，亦可加大矽化物層264的尺寸。因此可進一步降低電阻。
本發明的一或多個實施例有利於積體電路與其形成製程，但不限於此。舉例來說，本發明實施例提供的半導體裝置包括背側間隔物形成於背側通孔與底部半導體層之間。背側通孔包括第一部分於背側間隔物之間，以及寬度較大的第二部分於底部介電層之間。背側通孔與磊晶的源極結構之間的矽化物層可直接接觸內側間隔物。與習知結構相較，背側通孔與矽化物層的尺寸較大，因此可緩解形成電源軌時的層疊偏移問題並降低電阻。因此可改善半導體裝置的效能與可信度。
本發明實施例提供許多不同實施例。此處揭露具有背側間隔物的半導體裝置與其製作方法。例示性的半導體裝置包括介電層，形成於電源軌上；底部半導體層，形成於介電層上；背側間隔物，沿著底部半導體層的側壁；導電結構，接觸介電層的側壁與背側間隔物的側壁；多個通道半導體層，位於底部半導體層上，其中通道半導體層向上堆疊並彼此分開；金屬閘極結構，包覆每一通道半導體層；以及磊晶的源極/汲極結構，接觸每一通道半導體層的側壁，其中磊晶的源極/汲極結構接觸導電結構，且導電結構接觸電源軌。
在一些實施例中，背側間隔物的下表面接觸介電層的上表面。
在一些實施例中，例示性半導體裝置更包括內側間隔物沿著金屬閘極結構的側壁，其中背側間隔物的上表面接觸內側間隔物的下表面。在一些其他實施例中，導電結構包括矽化物層以接觸磊晶的源極/汲極結構的下表面，且矽化物層橫向接觸內側間隔物。
在一些實施例中，導電結構的第一部分接觸背側間隔物的側壁，導電結構的第二部分接觸介電層的側壁，而第一部分的寬度小於第二部分的寬度。在一些其他實施例中，背側間隔物的下表面接觸導電結構的第二部分的上表面。在一些其他實施例中，導電結構的第一部分的寬度為約70%至約80%的第二部分的寬度。在一些其他實施例中，背側間隔物的深度為約20%至約25%的導電結構的第一部分的寬度。在一些其他實施例中，背側間隔物的高度為約60%至約80%的導電結構的第一部分的寬度。
另一例示性半導體裝置包括介電層，形成於電源軌上；底部半導體層，形成於介電層上；導電結構，凸起穿過介電層與底部半導體層，其中導電結構的下側部分接觸介電層的側壁；間隔物，形成於導電結構的上側部分與底部半導體層的側壁之間；磊晶的源極結構，形成於半導體裝置的源極區上並接觸導電結構的上表面；以及磊晶的汲極結構，形成於半導體裝置的汲極區上並接觸底部半導體層的上表面。
在一些實施例中，底部半導體層的側壁之間的距離，大於介電層的側壁之間的距離。在一些實施例中，間隔物的下表面接觸導電結構的下側部分與介電層的上表面。在一些實施例中，導電結構的上表面高於底部半導體層的上表面。
半導體裝置的形成方法包括磊晶成長犧牲層於基板上；磊晶成長底部半導體層於犧牲層上，其中底部半導體層的材料與犧牲層的材料不同；形成半導體堆疊於底部半導體層上，其中半導體堆疊包括第一半導體層與第二半導體層交錯堆疊於底部半導體層上，且第一半導體層的材料與第二半導體層的材料不同；形成虛置閘極結構於半導體堆疊上；形成源極/汲極溝槽於虛置閘極結構之間，其中源極/汲極溝槽的下表面低於犧牲層的下表面；磊晶成長半導體結構於源極/汲極溝槽中，其中半導體結構與底部半導體層包括相同材料；磊晶成長源極/汲極結構於源極/汲極溝槽中的半導體結構上；移除基板並將犧牲層置換成介電層；移除半導體結構與底部半導體層的一部分，以形成背側溝槽，其中背側溝槽包括沿著介電層的側壁並延伸至源極/汲極結構的下表面之主要部分，以及橫向遠離主要部分並沿著底部半導體層的側壁之側部；形成背側間隔物於背側溝槽的側部中；以及形成導電結構於背側溝槽的主要部分中。
在一些實施例中，移除半導體結構與底部半導體層的部分以形成背側溝槽的步驟，包括等向蝕刻製程。在一些實施例中，背側間隔物包括的介電材料與介電層的材料不同。在一些實施例中，背側溝槽的側部的寬度，為約20%至約25%的背側溝槽的主要部分的寬度。
在一些實施例中，形成導電結構於背側溝槽的主要部分中的步驟包括預清潔背側背側溝槽以橫向移除介電層的側部而加大背側溝槽的開口；以及形成導電結構於背側溝槽中。在一些其他實施例中，背側溝槽的開口加大約25%至約45%。在一些其他實施例中，方法更包括：形成內側間隔物於第一半導體層的側部之間；移除虛置閘極結構與第二半導體層以形成閘極溝槽；形成金屬閘極結構於閘極溝槽中；以及形成矽化物層於導電結構與源極/汲極結構之間，其中矽化物層橫向接觸內側間隔物。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明精神與範疇，並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
A-A':剖面 D,W1,W2:寬度 T:高度 100:方法 105,110,115,120,125,130,135,140,145,150,155,160:步驟 200:裝置 202:基板 202-1,202-3,234:矽層 202-2:氧化矽層 204:犧牲層 206:底部半導體層 208:隔離結構 210:堆疊 210A,210B:半導體層 212:界面層 214:虛置閘極 216:硬遮罩層 220:虛置閘極結構 222:閘極間隔物 224:源極/汲極溝槽 224D:汲極溝槽 224S:源極溝槽 226:內側間隔物 228:遮罩層 230:圖案層 232:半導體結構 240:源極/汲極結構 240D:汲極結構 240S:源極結構 242:層間介電層 244:閘極溝槽 250:金屬閘極結構 252:閘極介電層 254:金屬閘極 256:底部介電層 258:背側溝槽 258S:側部 258V:通孔溝槽 258V-1:第一部分 258V-1:第二部分 260:背側間隔物 262:背側通孔 264:矽化物層 270:電源軌 280:背側內連線結構
圖1係本發明一些實施例中，製造半導體裝置的方法之流程圖。 圖2係本發明一些實施例中，半導體裝置在圖1的方法之初始階段的三維透視圖。 圖3、4、5、6、7、8、9、10、11、12、13A、14、15、16、17、18、19、20、及21A係本發明一些實施例中，半導體裝置在圖1的中間階段時沿著圖2中的剖面A-A'的剖視圖。 圖13B及21B分別為圖13A及21A的上下翻轉圖。
100:方法
105,110,115,120,125,130,135,140,145,150,155,160:步驟

Claims (1)

  1. 一種半導體裝置，包括： 一介電層，形成於一電源軌上； 一底部半導體層，形成於該介電層上； 一背側間隔物，沿著該底部半導體層的側壁； 一導電結構，接觸該介電層的側壁與該背側間隔物的側壁； 多個通道半導體層，位於該底部半導體層上，其中該些通道半導體層向上堆疊並彼此分開； 一金屬閘極結構，包覆每一該些通道半導體層；以及 一磊晶的源極/汲極結構，接觸每一該些通道半導體層的側壁，其中該磊晶的源極/汲極結構接觸該導電結構，且該導電結構接觸該電源軌。
TW110124757A 2020-07-22 2021-07-06 半導體裝置 TW202218093A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/935,368 2020-07-22
US16/935,368 US11276643B2 (en) 2020-07-22 2020-07-22 Semiconductor device with backside spacer and methods of forming the same

Publications (1)

Publication Number Publication Date
TW202218093A true TW202218093A (zh) 2022-05-01

Family

ID=77021168

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110124757A TW202218093A (zh) 2020-07-22 2021-07-06 半導體裝置

Country Status (5)

Country Link
US (3) US11276643B2 (zh)
EP (1) EP3944298A1 (zh)
JP (1) JP2022022169A (zh)
CN (1) CN113725278A (zh)
TW (1) TW202218093A (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102527382B1 (ko) * 2016-06-21 2023-04-28 삼성전자주식회사 반도체 소자
KR20220124426A (ko) * 2021-03-03 2022-09-14 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US20230067804A1 (en) * 2021-08-27 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Tapered Dielectric Layer for Preventing Electrical Shorting Between Gate and Back Side Via
US20230178658A1 (en) * 2021-12-02 2023-06-08 Intel Corporation Recessed inner gate spacers and partial replacement channel in non-planar transistors
US20230290844A1 (en) * 2022-03-14 2023-09-14 Intel Corporation Integrated circuit structures with backside self-aligned penetrating conductive source or drain contact
US20230299157A1 (en) * 2022-03-16 2023-09-21 Intel Corporation Integrated circuit structures with deep via structure
US20230317148A1 (en) * 2022-03-31 2023-10-05 Intel Corporation Epitaxial layers of a transistor electrically coupled with a backside contact metal
US20230411466A1 (en) * 2022-05-24 2023-12-21 International Business Machines Corporation Self-aligned backside contact with increased contact area
US20240071808A1 (en) * 2022-08-29 2024-02-29 Tokyo Electron Limited Methods for forming semiconductor devices with isolation structures
US20240213324A1 (en) * 2022-12-22 2024-06-27 Intel Corporation Elongated contact for source or drain region

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101800438B1 (ko) * 2010-11-05 2017-11-23 삼성전자주식회사 3차원 반도체 장치 및 그 제조 방법
US8816444B2 (en) 2011-04-29 2014-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. System and methods for converting planar design to FinFET design
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US8785285B2 (en) 2012-03-08 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US8860148B2 (en) 2012-04-11 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for FinFET integrated with capacitor
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8823065B2 (en) 2012-11-08 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8772109B2 (en) 2012-10-24 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for forming semiconductor contacts
US9236300B2 (en) 2012-11-30 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs in SRAM cells and the method of forming the same
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
CN109196653B (zh) * 2016-07-01 2022-09-13 英特尔公司 用于具有双侧金属化的半导体器件的背侧接触电阻减小
US9997413B1 (en) * 2017-03-22 2018-06-12 International Business Machines Corporation Stacked vertical devices
US11211328B2 (en) * 2017-10-16 2021-12-28 SK Hynix Inc. Semiconductor memory device of three-dimensional structure
US10833078B2 (en) * 2017-12-04 2020-11-10 Tokyo Electron Limited Semiconductor apparatus having stacked gates and method of manufacture thereof
US10861750B2 (en) * 2018-07-02 2020-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
US11621354B2 (en) * 2018-09-05 2023-04-04 Intel Corporation Integrated circuit structures having partitioned source or drain contact structures
EP3651188B1 (en) * 2018-11-12 2021-05-19 IMEC vzw A method for contacting a buried interconnect rail from the back side of an ic
KR20200142153A (ko) * 2019-06-11 2020-12-22 삼성전자주식회사 반도체 소자
US11094704B2 (en) * 2019-10-31 2021-08-17 Sandisk Technologies Llc Method of forming a three-dimensional memory device and a driver circuit on opposite sides of a substrate
US11362213B2 (en) * 2020-03-31 2022-06-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing a FinFET device with a backside power rail and a backside self-aligned via by etching an extended source trench
US11355601B2 (en) * 2020-03-31 2022-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices with backside power rail and backside self-aligned via

Also Published As

Publication number Publication date
CN113725278A (zh) 2021-11-30
US20230369223A1 (en) 2023-11-16
US11276643B2 (en) 2022-03-15
US20220199530A1 (en) 2022-06-23
JP2022022169A (ja) 2022-02-03
EP3944298A1 (en) 2022-01-26
US20220028786A1 (en) 2022-01-27
US11721626B2 (en) 2023-08-08

Similar Documents

Publication Publication Date Title
TW202218093A (zh) 半導體裝置
TWI743779B (zh) 半導體裝置及其形成方法
US8679925B2 (en) Methods of manufacturing semiconductor devices and transistors
TWI643252B (zh) 半導體裝置的形成方法
TW201830578A (zh) 接觸結構製造方法
US8399315B2 (en) Semiconductor structure and method for manufacturing the same
TW202127662A (zh) 半導體裝置
TW202133348A (zh) 半導體裝置及其形成方法
CN103779224A (zh) Mosfet的制造方法
KR102042718B1 (ko) 핀 전계 효과 트랜지스터 디바이스 및 방법
TW202213468A (zh) 半導體裝置的形成方法
KR20210149571A (ko) 반도체 디바이스 및 방법
KR102610581B1 (ko) 반도체 디바이스 및 방법
TW202218155A (zh) 半導體裝置
TWI783350B (zh) 半導體結構與其形成方法
TW202209414A (zh) 半導體裝置
CN111415907A (zh) 非晶硅结构的制造方法
TW202201782A (zh) 半導體裝置
US11158741B2 (en) Nanostructure device and method
KR102623749B1 (ko) 갭충전 구조물 및 그 제조 방법
TWI835170B (zh) 形成半導體裝置的方法
US20230155005A1 (en) Semiconductor device and method
CN114883265A (zh) 半导体装置
TW202310405A (zh) 半導體裝置結構
TW202215505A (zh) 半導體裝置的形成方法