TWI538211B - 半導體結構及其製造方法 - Google Patents

半導體結構及其製造方法 Download PDF

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TWI538211B
TWI538211B TW102113567A TW102113567A TWI538211B TW I538211 B TWI538211 B TW I538211B TW 102113567 A TW102113567 A TW 102113567A TW 102113567 A TW102113567 A TW 102113567A TW I538211 B TWI538211 B TW I538211B
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layer
region
field effect
metal
dielectric layer
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TW201349510A (zh
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朱鳴
黃仁安
劉繼文
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台灣積體電路製造股份有限公司
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Description

半導體結構及其製造方法
本發明係關於半導體製作，且特別是關於一種積體電路、半導體結構及其製造方法，以改善於其內元件於製作時所可能遭遇之碟化效應與電阻值偏差情形。
於傳統之積體電路(IC)設計中已見有場效電晶體(FET)的使用。基於技術節點的微縮，通常使用高介電常數(high-k)介電材料與金屬以形成場效電晶體之一閘堆疊物(gate stack)。於單一之積體電路晶片內形成不同之金屬閘場效電晶體(metal gate FET)時存在有整合問題，特別是於積體電路晶片內整合有電阻時。其中問題之一為於研磨製程中之碟化效應(dishing effect)。另外之一問題在於，使用了包括蝕刻製程之一閘取代(gate replacement)製程以移除多晶矽閘。然而，所形成之多晶矽電阻可能於上述蝕刻製程中遭到毀損或凹陷，進而造成了此多晶矽電阻之電阻值與其設計目標值之間產生差異。因此，便需要一種整合有高介電常數金屬閘結構之製造方法，以解決上述問題。
依據一實施例，本發明提供了一種積體電路，包括：一半導體基板；一n型場效電晶體，位於該半導體基板上， 具有包括一第一高介電常數介電層、位於該高介電常數介電層上之一上蓋層、位於該上蓋層上之一p型功函數金屬、以及位於該p型功函數金屬上之一多晶矽層之一第一閘堆疊物；以及一p型場效電晶體，位於該半導體基板之上，具有包括該第一高介電常數介電層、位於該高介電常數介電層上之該p型功函數金屬、以及位於該p型功函數金屬上之一金屬材料之一第二閘堆疊物。
依據另一實施例，本發明提供了一種半導體結構，包括：一半導體基板；一n型場效電晶體，位於該半導體基板之上，具有包括一高介電常數介電層、位於該高介電常數介電層上之一上蓋層；位於該上蓋層上之一p型功函數金屬、以及位於該p型功函數金屬上之一多晶矽層之一第一閘堆疊物；一p型場效電晶體，位於該半導體基板之上，具有包括該高介電常數介電層、位於該高介電常數介電層上之一p型功函數金屬、以及位於該p型功函數金屬上之一金屬材料之一第二閘堆疊物；以及一假閘堆疊物，形成於該半導體基板上，具有該高介電常數介電層、位於該高介電常數介電層上之該上蓋層、位於該上蓋層上之該p型功函數金屬、以及位於該p型功函數金屬上之該多晶矽元件。
依據又一實施例，本發明提供了一種半導體結構之製造方法，包括：提供一半導體基板，該半導體基板具有形成一n型場效電晶體之一第一區、形成一p型場效電晶體之一第二區以及形成一假閘堆疊物之一第三區；形成一高介電常數介電層於該第一區、該第二區與第三區內之該半導體基板上；形 成一氧化鑭上蓋層於該第一區與該第二區內之該高介電常數介電層上；形成一氮化鉭層於該第一區與該第二區內之該氧化鑭上蓋層之上以及於該第三區內之該高介電常數介電層之上；形成一多晶矽層於該第一區、該第二區與第三區內之該氮化鉭層之上；圖案化該多晶矽層、該氮化鉭層、該氧化鑭層以及該高介電常數介電層，以於該第一區內形成一第一閘堆疊物、於該第二區內形成一第二閘堆疊物、以及於該第三區內形成一假閘堆疊物；以及採用一金屬材料以替換該第二區內之該多晶矽層。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下。
100‧‧‧製造方法
102、104、106、108、110、112、114、116、118、120‧‧‧步驟
200‧‧‧半導體結構
202‧‧‧半導體基板
204‧‧‧第一區
206‧‧‧第二區
208、210、212‧‧‧元件區
218‧‧‧閘介電層
220‧‧‧上蓋層
222‧‧‧金屬層
224‧‧‧多晶矽層
228a、228b‧‧‧閘堆疊物
228c‧‧‧電阻
228d、228e‧‧‧閘堆疊物
230‧‧‧間隔物
232‧‧‧層間介電層
234‧‧‧圖案化阻劑層
236‧‧‧溝槽
240‧‧‧金屬材料層
242‧‧‧化學機械研磨製程
244‧‧‧矽化物元件
第1圖為一流程圖，顯示了依據本發明之一實施例之一種具有金屬閘與多晶矽閘之半導體裝置之製造方法；第2-7圖為一系列剖面圖，分別顯示了依據本發明之一實施例之一種具有金屬閘與多晶矽閘之半導體裝置之製造方法中之不同階段之製作情形。
可以理解的是，於下文中提供了用於施行本發明之不同特徵之多個不同實施例，或範例。基於簡化本發明之目的，以下描述了元件與設置情形之特定範例。然而，此些元件與設置情形僅作為範例之用而非用於限制本發明。此外，本發 明於不同實施例中可能重複使用標號及/或文字。如此之重複情形係基於簡化與清楚之目的，而非用於限定不同實施例及/或討論形態內的相對關係。再者，於描述中關於於一第二元件之上或上之第一元件的形成可包括了第一元件與第二元件係為直接接觸之實施情形，且亦包括了於第一元件與第二元件之間包括了額外元件之實施情形，因而使得第一元件與第二元件之間並未直接接觸。
第1圖為一流程圖，顯示了依據本發明之一實施例之一種半導體結構之製造方法100。第2-7圖為一系列剖面圖，顯示了依據本發明之一或多個實施例之一種半導體結構200於製造中不同階段之情形。此半導體結構200包括多個閘堆疊物(gate stack)，例如用於形成n型場效電晶體(n-type FET)之一多晶矽閘堆疊物、用於形成p型場效電晶體(p-type FET)之一金屬閘堆疊物。於本實施例中，半導體結構200更包括一多晶矽電阻。在此，半導體結構200與製造方法100可參照第1-7圖而進行解說。
請參照第1、2圖，方法100起使於步驟102，首先提供一半導體基板202。半導體基板202包括矽。或者，半導體基板202包括鍺、矽鍺、或其他之適當半導體材料。半導體基板202亦可包括形成於半導體基板之如淺溝槽隔離(STI)元件之多個隔離結構，以分隔不同元件。
上述淺溝槽隔離元件的形成包括：於半導體基板內蝕刻出一溝槽，以及於溝槽內填入如氧化矽、氮化矽或氮氧化矽之一或多個絕緣材料。經填滿之溝槽可具有如包括一熱氧 化物襯層與填滿溝槽之氮化矽之一多膜層結構。於一實施例中，淺溝槽隔離物元件係藉由使用下述之一製程順序所形成，例如：成長一墊氧化物、形成一低壓化學氣相沈積(LPCVD)之氮化物層、使用阻劑與光罩以圖案化出一淺溝槽隔離開口、於半導體基板內蝕刻出一溝槽、選擇性成長一熱氧化物溝槽襯層以改善溝槽介面、使用化學氣相沈積之氧化物填滿溝槽、使用化學機械平坦程序進行回蝕刻(etch back)、以及去除氮化物以留下淺溝槽隔離元件。
半導體基板202亦包括不同之摻雜元件，例如形成於不同之元件區內之n型井區與p型井區。此些摻雜元件可藉由如離子佈值之適當技術所形成。
於一實施例中，半導體基板202包括用於多個元件之一第一區204，以及用於設置較少功能性元件或設置不具功能性元件之一第二區206。於第一區204內之多個元件包括了多個n型場效電晶體及p型場效電晶體以及一或多個多晶矽電阻(polysilicon resistor)。於本實施例中，第一區204內包括用於形成解說用之一n型場效電晶體之一元件區208、用於形成解說用之一p型場效電晶體之一元件區210以及用於形成高電阻值之一電阻之一元件區212。
請繼續參照第1、2圖，方法100繼續進行步驟104，形成一閘介電層218與一上蓋層220。閘介電層218係形成於半導體基板202之上。於本實施例中，閘介電層218包括一高介電常數(high-k)介電材料。此高介電常數介電材料具有高於熱氧化矽(thermal silicon oxide)之介電常數(為3.9)之一介電常數。 於一範例中，高介電常數介電材料包括氧化鉿(HfO)。於其他之範例中，高介電常數介電材料包括金屬氧化物、金屬氮化物或其組合。於一範例中，高介電常數介電材料之閘介電層218可由化學氣相沈積(CVD)、原子層沈積(ALD)、電漿加強型化學氣相沈積(PECVD)、或電漿加強型原子層沈積(PEALD)所形成。於另一範例中，高介電常數介電材料之閘介電層218可包括介於10-100埃之一厚度。
於另一實施例中，閘介電層218更包括設置於一高介電常數介電材料層與半導體基板202之間一中間層(interfacial layer，未顯示)。於一範例中，此中間層包括由如熱氧化法之一適當技術所形成之氧化矽。此中間層可由如原子層沈積或化學氣相沈積之其他適當技術所形成。
上蓋層220係形成於閘介電層218之上。上蓋層220避免了金屬自閘電極擴散至閘介電層處。於本實施例中，上蓋層220為用於形成n型場效電晶體之眾多功函數材料(work function material)中之一種材料。形成n型場效電晶體之此功函數材料具有一適當功函數，以降低n型場效電晶體之臨界電壓(threshold voltage)。當半導體基板202為一矽基板時，n型場效電晶體之功函數材料之功函數可接近矽的導帶(conduction band)或具有較低之功函數。舉例來說，n型場效電晶體之功函數材料具有約為4.2eV或更低之一功函數。於本實施例中，上蓋層包括氧化鑭(LaO)。上蓋層220係由如化學氣相沈積、物理氣相沈積或其他方法之適當技術所形成。
請參照第1、3圖，方法100接著進行步驟106，採 用包括微影製程之一程序以圖案化上蓋層220。上述微影製程例如包括阻劑圖案化、蝕刻與阻劑去除。阻劑圖案化可更包括塗佈、曝光圖案、曝光後烘烤、以及顯影阻劑等步驟。於上述蝕刻中則使用了一適當蝕刻劑，以選擇性地移除上蓋層220。於本實施例中，當上蓋層220包括氧化鑭薄膜時，蝕刻劑可包括氯化氫(HCl)或弱酸(含二氧化碳之水)。
於一實施例中，上蓋層220於經過圖案化後，將使得圖案化之上蓋層220覆蓋了形成n型場效電晶體之元件區208並露出了形成p型場效電晶體之元件區210。再者，圖案化之上蓋層220亦覆蓋了第二區206，第二區206內可於稍後形成一或多個假閘堆疊物(dummy gate stack)，以改善蝕刻效應之圖案密度(pattern density)。藉由於第二區206內保留氧化鑭層220，可降低於氧化鑭蝕刻製程中關於負載效應之蝕刻偏差情形(etch bias)。
請參照第1、4圖，方法100接著進行步驟108，形成一金屬層222與一多晶矽層224。金屬層224經過選擇而具有用於p型場效電晶體之一適當功函數，其亦稱為p型功函數金屬(或稱為p金屬)。p型功函數金屬係為一金屬或一金屬合金。此p型功函數金屬具有接近於矽之價帶能量(valance band energy，Ev)或更高之功函數，其對於原子核表現出強之電子結合能量。舉例來說，p型功函數金屬具有約為5.2eV或更高之功函數。
金屬層222較佳地經過選擇，使得上蓋層220與金屬層222一起形成了具有接近4.2eV或更少之一功函數之一材料層。於本實施例中，金屬層222包括由如物理氣相沈積之一 適當技術所形成之氮化鈦。於其他實施例中，金屬層222可包括氮化鉭(TaN)、氮化鎢(WN)及其組合。
多晶矽層(或非晶矽層)224可藉由使用矽烷或其他矽基前驅物之化學氣相沈積所形成。非晶矽的沈積可於一較高溫度下施行。依據一實施例，沈積溫度係高於約400 C。多晶矽(或非晶矽)層224可使用包括含摻質氣體之前驅物而臨場地摻雜。
請繼續參照第1、4圖，方法100繼續進行步驟110，圖案化此些閘極材料層以形成多個圖案化之閘堆疊物228，其包括了電晶體之閘堆疊物，一或一個以上之電阻、以及一或一個以上之假閘堆疊物。此些閘極材料層包括了閘介電層218、上蓋層220、p型金屬層222、多晶矽層224。於本實施例中，於元件區208內形成n型場效電晶體之一閘堆疊物228a，其包括了上蓋層220與金屬層222。於元件區210內形成p型場效電晶體之一閘堆疊物228b，且其包括了金屬層222。於元件區212內形成具有相同於p型場效電晶體閘堆疊物228之材料堆疊物之一電阻228c。於第二區206內則形成有具有相同於n型場效電晶體之閘堆疊物228a之材料堆疊物之示範性之兩閘堆疊物228d與228e。
形成閘堆疊物與電阻之圖案化製程包括了一微影圖案化製程。舉例來說，圖案化製程包括了形成一圖案化阻劑層、蝕刻與阻劑去除。於另一實施例中，圖案化製程更包括使用一硬罩幕以做為一蝕刻罩幕。於上述實施例中，係於此些閘材料層之上形成一硬罩幕層；於硬罩幕層上形成一圖案化阻劑 層；針對硬罩幕層施行一第一蝕刻製程以自圖案化罩幕層處轉移上述圖案至硬罩幕層上；以及使用圖案化硬罩幕層做為一蝕刻罩幕以對此些閘材料層施行一第二蝕刻製程。於本實施例中，硬罩幕層包括了氧化矽層以及位於氧化矽層上之氮化矽層。上述氮化矽層與氧化矽層可藉由化學氣相沈積或其他適當技術所形成。
於一實施例中，阻抗性之堆疊物228c係做為一被動元件之用。此被動元件可做為一電阻或做為一多晶矽熔絲之用。於另一實施例中，電阻228c大體設置於半導體基板202之元件區內。或者，電阻228c可部份地位於元件區之上並大體位於淺溝槽隔離元件之上。於另一實施例中，可針對電阻228c施行一離子佈值以導入摻雜離子並調整其電阻值。
請繼續參照第1、4圖，方法100接著繼續步驟112，形成源極元件與汲極元件於半導體基板202之上。於一實施例中，源極元件與汲極元件包括了輕度摻雜汲極區(LDD regions)以及重度摻雜之源極區與汲極區，在此其通稱為源極元件與汲極元件，其係由一或多個佈值製程所形成。當第一區204包括位於元件區208內之n型場效電晶體以及位於元件區210內之p型場效電晶體時，採用適當摻雜元素以分別形成了此n型場效電晶體與p型場效電晶體之源極與汲極區。於一實施例中，採用n型場效電晶體做為說明，藉由使用一輕度摻雜劑量之一離子佈值以形成淺摻雜汲極元件。接著，可藉由介電沈積以及如電漿蝕刻之非等向性蝕刻以形成間隔物230。接著藉由具有一重度摻雜劑量之一離子佈值以形成重度摻雜之源極與汲極元 件。可採用相似但具有相反類型元素之一程序以形成p型場效電晶體之源極元件與汲極元件。
位於電阻228c側壁上之間隔物230可於形成n型場效電晶體與p型場效電晶體之間隔物時同時形成。於形成不同之源極元件與汲極元件之不同摻雜製程中，形成電阻之元件區212係受到如一圖案化阻劑層之一罩幕層所保護。於一範例中，形成n型場效電晶體與p型場效電晶體之多個源極與汲極元件之製程中，n型場效電晶體之淺摻雜汲極元件係藉由一離子佈值所形成，而此時p型場效電晶體與電阻之區域為一圖案化阻劑層所覆蓋；p型場效電晶體之淺摻雜汲極元件係藉由一離子佈值所形成，而此時n型場效電晶體與電阻之區域為一圖案化阻劑層所覆蓋；接著藉由沈積與蝕刻以形成間隔物於n型場效電晶體之閘堆疊物、p型場效電晶體之閘堆疊物以及電阻之上；藉由離子佈值形成n型場效電晶體之源極與汲極元件，而此時p型場效電晶體與電阻之區域係為一圖案化阻劑層所覆蓋；以及藉由離子佈值所形成n型場效電晶體之源極與汲極元件，而此時n型場效電晶體與電阻之區域係為一圖案化阻劑層所覆蓋。
於一實施例中，接著施行一高溫回火程序，以活化位於源極與汲極區以及電阻內不同元件內之元素。於另一實施例中，上述熱回火製程係針對半導體基板202所施行，以更反應上蓋層220與金屬222，進而於元件區208內形成用於n型場效電晶體之一功函數金屬。
請繼續參照第1與4圖，方法100接著進行步驟 114，形成一層間介電層(ILD)232(亦稱為第0層之層間介電層)。層間介電層232為形成於半導體基板202之上。層間介電層232包括氧化矽、低介電常數(low-k)介電材料、其他之適當介電材料或其組合。層間介電層232係由如化學氣相沈積之一適當技術所形成。舉例來說，可施行高密度電漿化學氣相沈積以形成層間介電層232。於一實施例中，此層間介電層232係沈積於半導體基板202之上，並填滿介於電阻與閘堆疊物228a與228b之間的凹口。於其他實施例中，層間介電層係形成於半導體基板上至高於電阻與閘堆疊物之頂面之一程度。
接著針對層間介電層232施行一化學機械研磨(CMP)製程以降低層間介電層232之厚度，並露出電阻與閘堆疊物的頂面。可調整包括研磨漿化學品與研磨壓力之上述化學機械研磨製程之製程條件與參數，以部份移除並平坦化此層間介電層232。
請參照第1與5圖，方法100接著繼續步驟116，將元件區210內之多晶矽閘堆疊物228b替換為金屬閘(metal gate)。先於基板202上形成一圖案化阻劑層234。此圖案化阻劑層234包括露出位於元件區210內之閘堆疊物228b之一或多個開口。
首先，施行一蝕刻程序以移除位於元件區210內之多晶矽或非晶矽之假的閘堆疊物228b。當使用硬罩幕以形成此些閘堆疊物228時，此蝕刻程序亦移除了硬罩幕層。於一實施例中，此蝕刻程序包括了兩個步驟，其中第一步驟係用於移除硬罩幕層，而第二步驟係用於移除位於元件區210內之多晶矽 層224。於移除元件區210內之多晶矽層224後，便於元件區210內形成一溝槽236，其亦稱為一閘溝槽(gate trench)。用於移除位於元件區210內之多晶矽閘堆疊物228b之上述蝕刻製程可應用適當之乾蝕刻、濕蝕刻或其組合。於一範例中，可使用包括硝酸(HNO3)、水(H2O)與氫氟酸(HF)之一蝕刻溶液、或雙氧水(NH4OH)溶液以移除多晶矽。於另一實施例中，可使用氯基電漿(Cl-based plasma)以選擇地移除多晶矽。
接著，於閘溝槽236內形成一或多個金屬材料層240，如第6圖所示。此金屬材料層240大體填滿了此閘溝槽236。依據多個實施例，金屬材料層240包括了鋁、銅、或鎢。形成金屬材料層240之方法可包括物理氣相沉積(PVD)、化學氣相沉積(CVD)、原子層沉積(ALD)、電漿加強型化學氣相沉積(PECVD)、電漿加強型原子層沉積(PEALD)或選轉金屬塗佈方法。或者，金屬材料層240可更包括其他之金屬或金屬合金膜層，例如額外之一上蓋層(capping layer)或一緩衝層(buffer layer)。
請參照第1與6圖，方法100接著進行步驟118，施行一化學機械研磨製程242以移除於層間介電層232上之過量之金屬材料層240。化學機械研磨製程242係經過調整而可有效地研磨金屬材料層240。於元件區208內之n型場效電晶體之閘堆疊物228a係由一閘極優先(gate-first)方法所形成。於元件區212內之電阻228c則亦由閘堆疊物228a所構成。閘堆疊物228a與電阻228c具有可能受到化學機械研磨製程242所毀損之多晶矽表面，因而造成了其高度差異與表現劣化情形。由於假閘堆 疊物(例如閘堆疊物228d、228e)係藉由閘極優先方法所形成而包括了閘堆疊物228a，故其提供了多晶矽表面以及均勻之多晶矽圖案密度。因此，於上述化學機械研磨製程之中，整體之金屬閘密度不會太高，可大體抑制此化學機械研磨製程中之碟化效應。
再者，藉由上述之混合製程的實施，即n型場效電晶體之閘堆疊物係由閘極優先製程所形成，而p型場效電晶體係由閘極最後(gate-last)製程所形成，於元件區208內之n型場效電晶體之閘堆疊物228a可具有適用於n型場效電晶體之經調整之一較佳功函數，而於元件區210內之p型場效電晶體之閘堆疊物228b可具有適用於p型場效電晶體之經調整之一較佳功函數。特別地，當於元件區210內之n型場效電晶體之閘堆疊物228b包括藉由閘極最後製程所形成之經取代之一金屬閘(metal gate)時，位於閘堆疊物228b內之金屬層222並不會出乎預料地經過於形成源極與汲極元件時之熱回火製程的調整。
請參照第1與7圖，方法100接著進行步驟120，形成具有較低接觸電阻值之一矽化物元件244於元件區208內之n型場效電晶體之閘堆疊物228a的多晶矽表面上。矽化物元件244可包括矽化鎳、矽化鈷、矽化鎢、矽化鉭、矽化鈦、矽化鉑、矽化鉺、矽化鈀、及其組合。上述矽化物可藉由包括：沈積一金屬(例如鎳)於基板上；於一較高溫度下反應(例如透過一熱回火製程)上述金屬與多晶矽以形成矽化物；以及接著蝕刻移除未反應之金屬之一製程所形成。可接著施行具有更高溫度但較短時間之另一熱回火製程，以使得所形成之矽化物可自一 高電阻值相轉變至一低電阻值相。於本實施例中，可於基板之上形成一圖案化罩幕層以覆蓋元件區212內之電阻228c，使得電阻228c之表面電阻值不會受到不期望的改變。
雖然並未顯示，可更形成其他元件或進行其他製程步驟以形成不同之元件。於一實施例中，可較佳地設置於元件區212內之一或多個電阻(例如電阻228c)以做為用於其他應用之一多晶矽熔絲(或非晶矽熔絲)。於另一實施例中，此些電阻可依照一陣列方式設置，分別設置於淺溝槽隔離物之上。半導體結構200係為具有複數個電阻以及多種場效電晶體之一積體電路之一部分，其中各n型場效電晶體包括具有高介電常數介電材料以及多晶矽閘電極之一閘堆疊物，而各p型場效電晶體包括具有高介電常數介電材料以及金屬閘電極之一閘堆疊物。於另一實施例中，多晶矽材料層214可於多晶矽沈積時臨場地摻雜硼。於另一實施例中，可調整此臨場摻雜以達成多晶矽材料層224之期望電阻率，因而可省略一或多個離子佈值的施行。
於另一實施例中，p型場效電晶體具有可增強載子遷移率及改善元件表現之一應變結構(strained structure)。於另一實施例中，可於p型場效電晶體之源極區與汲極區之上形成矽鍺，藉以達到較佳之應變效應。於形成如此之應變p型場效電晶體之一範例中，於p型場效電晶體之源極區與汲極區內之矽基板經過一或多個蝕刻步驟而凹陷。接著於此些凹陷之區域內磊晶成長矽鍺，且於磊晶成長之矽鍺元件內形成重度摻雜之源極與汲極。於另一範例中，可於形成淺摻雜汲極元件之後形 成假間隔物(dummy spacer)。上述假間隔物於形成矽鍺元件之後將被移除。接著於位於相關閘堆疊物之側壁上留下具有一不同厚度之間隔物，使得重度摻雜之源極與汲極與矽鍺元件之間一偏差值。舉例來說，主要之間隔物可較假間隔物為厚，使得重度摻雜之源極與汲極係形成於矽鍺元件之上。
於另一實施例中，n型場效電晶體具有可增強載子遷移率及改善元件表現之一應變結構(strained structure)。於另一實施例中，可於n型場效電晶體之源極區與汲極區之上形成碳化矽(SiC)，藉以達到較佳之應變效應。此應變之n型場效電晶體的製作相似於前述之p型場效電晶體的製作。於另一實施例中，p型場效電晶體(或n型場效電晶體)之閘電極可包括具有多重導電膜層之最佳化功函數以及較低的臨界電壓。
於另一實施例中，位於第二區206內之假閘堆疊物可具有不相同之尺寸。舉例來說，此些假閘堆疊物可具有少於或多於n型場效電晶體之閘堆疊物之寬度或p型場效電晶體之閘堆疊物之寬度之一寬度，使得可更彈性地調整圖案密度以降低化學機械研磨之碟化效應。
於電阻、n型場效電晶體與p型場效電晶體形成之前、之中及/或之後可更施行其他製程步驟。舉例來說，可更形成多重膜層之內連物(multilayer interconnection)。此多重膜層內連物包括如介層物(vias)或接觸物(contacts)之垂直內連物，以及包括如金屬導線之水平內連物。此些不同之內連元件可應用包括銅、鎢與矽化物之不同導電材料。於一範例中，可使用雙鑲嵌製程以形成銅相關之多重膜層內連物。於另一範例 中，可於接觸孔中使用鎢以形成鎢插拴。
於另一範例中，高介電常數介電材料可藉由如金屬有機化學氣相沈積(MOCVD)或分子束磊晶(MBE)等製程或其他製程所形成。於一範例中，高介電常數介電材料包括二氧化鉿(HfO2)。於另一範例中，高介電常數介電材料包括氧化鋁(Al2O3)。或者，高介電常數介電材料包括金屬氮化物、金屬矽化物或其他之金屬氧化物。於另一範例中，可於矽基板上藉由如熱氧化法原子層沈積、深紫外線臭氧氧化法或其他之適當方法以形成一層間膜層(例如氧化矽)。
上述之多種圖案化製程可包括藉由一微影製程以形成一圖案化阻劑層。一示範性之微影製程可包括：阻劑之旋轉塗佈、軟烤、光罩對準、曝光、曝光後烘烤、顯影阻劑以及硬烤等製程步驟。上述微影曝光製程亦採用如無光罩微影、電子束微影、離子束直寫、熱微影以及分子轉印等其他適當方法。
本發明之多個實施例具有不同之優點。於一實施例中，多晶矽圖案密度為控制高介電常數金屬閘之閘極最後製程之一重要因子。設計規範中定義有且需要特定程度之多晶矽密度。除了客戶設計中之假圖案之外，須於多晶矽所隔離之數個區域中插入額外之假的多晶矽閘堆疊物。於採用閘極優先製程形成n型場效電晶體(例如閘堆疊物228a)時於第二區206內形成假閘堆疊物(例如閘堆疊物228d與228e)，使得某些相關製程之負載效應(loading effect)可獲得改善。
於另一範例中，上述方法完全相容於高介電常數金屬閘之閘極最後製程，於化學機械研磨製程中，上蓋層之負 載效應以及元件區210內之金屬閘之負載效應皆可獲得改善。
本發明並非限定於包括一場效電晶體以及一多晶矽電阻之半導體裝置之相關應用，而可應用於具有金屬閘堆疊物之其他積體電路中。舉例來說，上述半導體結構可包括動態隨機存取記憶胞(DRAM cell)、影像感測器、電容器、及/或微電子元件(於下文中通稱為微電子元件)。於另一實施例中，上述半導體結構包括了鰭型場效電晶體(FinFET)。當然，本發明之目的亦可應用及/或採用其他類型之電晶體，包括了單一閘電晶體、雙重閘電晶體以及其他之多重閘電晶體，並可應用於包括感測胞、記憶胞、邏輯胞以及其他之多種不同應用中。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
200‧‧‧半導體裝置
204‧‧‧第一區
206‧‧‧第二區
208、210、212‧‧‧元件區
218‧‧‧閘介電層
220‧‧‧上蓋層
222‧‧‧金屬層
224‧‧‧多晶矽層
228a、228b‧‧‧閘堆疊物
228c‧‧‧電阻
228d、228e‧‧‧閘堆疊物
230‧‧‧間隔物
232‧‧‧層間介電層
240‧‧‧金屬材料層
242‧‧‧化學機械研磨製程

Claims (7)

  1. 一種半導體結構，包括：一半導體基板；一n型場效電晶體，位於該半導體基板之上，具有包括一高介電常數介電層、位於該高介電常數介電層上之一上蓋層；位於該上蓋層上之一p型功函數金屬、以及位於該p型功函數金屬上之一多晶矽層之一第一閘堆疊物；一p型場效電晶體，位於該半導體基板之上，具有包括該高介電常數介電層、位於該高介電常數介電層上之一p型功函數金屬、以及位於該p型功函數金屬上之一金屬材料之一第二閘堆疊物；以及一假閘堆疊物，形成於該半導體基板上，具有該高介電常數介電層、位於該高介電常數介電層上之該上蓋層、位於該上蓋層上之該p型功函數金屬、以及位於該p型功函數金屬上之該多晶矽元件。
  2. 如申請專利範圍第1項所述之半導體結構，更包括一電阻，位於該半導體基板上，具有該高介電常數介電層、位於該高介電常數介電層上之該p型功函數金屬、以及位於該p型功函數金屬上之該多晶矽元件。
  3. 如申請專利範圍第1項所述之半導體結構，其中該n型場效電晶體更包括形成於該多晶矽層上之一矽化物元件。
  4. 一種半導體結構之製造方法，包括：提供一半導體基板，該半導體基板具有形成一n型場效電晶體之一第一區、形成一p型場效電晶體之一第二區以及形成 一假閘堆疊物之一第三區；形成一高介電常數介電層於該第一區、該第二區與第三區內之該半導體基板上；形成一氧化鑭上蓋層於該第一區與該第二區內之該高介電常數介電層上；形成一氮化鉭層於該第一區與該第二區內之該氧化鑭上蓋層之上以及於該第三區內之該高介電常數介電層之上；形成一多晶矽層於該第一區、該第二區與第三區內之該氮化鉭層之上；圖案化該多晶矽層、該氮化鉭層、該氧化鑭層以及該高介電常數介電層，以於該第一區內形成一第一閘堆疊物、於該第二區內形成一第二閘堆疊物、以及於該第三區內形成一假閘堆疊物；以及採用一金屬材料以替換該第二區內之該多晶矽層。
  5. 如申請專利範圍第4項所述之該半導體結構之製造方法，其中採用一金屬材料以替換該第二區內之該多晶矽層包括：蝕刻該第二區內之該多晶矽層，形成一閘溝槽；沈積該金屬材料於該閘溝槽內；以及針對該金屬材料施行一化學機械研磨程序。
  6. 如申請專利範圍第4項所述之該半導體結構之製造方法，更包括形成一矽化物於該第一區內之該第一閘堆疊物上。
  7. 如申請專利範圍第4項所述之該半導體結構之製造方法，更包括：於圖案化該多晶矽層、該氮化鉭層、該氧化鑭層以及該高 介電常數介電層之後，藉由一離子佈值以於該半導體基板內形成源極與汲極元件；以及針對該半導體基板施行一熱回火以形成一電阻。
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