TWI824237B - 半導體裝置及其形成方法 - Google Patents
半導體裝置及其形成方法 Download PDFInfo
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- TWI824237B TWI824237B TW110110790A TW110110790A TWI824237B TW I824237 B TWI824237 B TW I824237B TW 110110790 A TW110110790 A TW 110110790A TW 110110790 A TW110110790 A TW 110110790A TW I824237 B TWI824237 B TW I824237B
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- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
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- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
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Abstract
一種半導體裝置,包括:通道構件(members)的垂直堆疊;閘極結構,在通道構件的垂直堆疊上方以及周圍;以及第一源極/汲極部件以及第二源極/汲極部件。垂直堆疊的每個通道構件沿著第一方向在第一源極/汲極部件以及第二源極/汲極部件之間延伸。垂直堆疊的每個通道構件藉由矽化物部件與第一源極/汲極部件隔開。
Description
本發明實施例係有關於一種半導體裝置及其形成方法,且特別關於一種多閘極裝置及其形成方法。
半導體積體電路產業經歷了快速成長。積體電路材料以及設計的技術進步已經產生數個積體電路世代,其中每一世代都比前一世代具有更小且更複雜的電路。在積體電路演進期間,功能密度(亦即,單位晶片面積的互連裝置數目)通常會增加而幾何尺寸(亦即,即可使用製程生產的最小元件(或線))卻減少。此微縮化的過程通常會以增加生產效率與降低相關成本而提供助益。然而,此微縮化也增加了積體電路製造以及製程的複雜性。
例如,隨著積體電路(IC)技術朝向更小的技術節點發展,多閘極裝置已被引入以通過增加閘極-通道耦合(gate-channel coupling)、減小關閉狀態電流(OFF-state current)以及減小短通道效應(short-channel effects, SCEs)來改善閘極控制。多閘極裝置一般來說是指具有設置在通道區的一側以上的閘極結構或其一部份的裝置。鰭式場效電晶體(Fin-like field effect transistors, FinFETs)以及全繞式閘極(gate-all-around, GAA)電晶體(兩者也稱為非平面電晶體)為多閘極裝置的示例,這些裝置已成為高性能以及低漏電流應用的主流並且具有前景的候選裝置(candidates)。FinFET具有上升的(elevated)通道,且閘極包繞通道的一側以上(例如,閘極包繞從基板延伸的半導體材料“鰭片”的頂部以及側壁)。與平面電晶體相比,此種配置提供更好的通道控制,並大幅降低SCEs(特別是通過減少次臨界漏電流(sub-threshold leakage)(即,處於“關閉”狀態的FinFET的源極和汲極之間的耦合))。GAA電晶體的閘極結構可以部份地或完全地圍繞通道區延伸,以提供對通道區兩側或更多側的存取(access)。GAA電晶體的通道區可以由奈米線、奈米片、其他奈米結構及/或其他合適的結構形成。在一些實施方案中,此通道區包含垂直堆疊的多個奈米結構(其水平地延伸,從而提供水平定向的(horizontally-oriented)通道)。
縮小的尺寸也增加多閘極裝置中磊晶源極/汲極部件的接觸電阻。儘管常規的多閘極裝置通常已經足以滿足其預期目的,但是它們並非在全部的方面都令人滿意。
本發明一些實施例提供一種半導體裝置,包括:通道構件(members)的垂直堆疊;閘極結構,在通道構件的垂直堆疊上方以及周圍;以及第一源極/汲極部件以及第二源極/汲極部件,其中垂直堆疊的每個通道構件沿著第一方向在第一源極/汲極部件以及第二源極/汲極部件之間延伸,其中垂直堆疊的每個通道構件藉由矽化物部件與第一源極/汲極部件隔開。
本發明另一些實施例提供一種半導體裝置,包括:複數個通道構件,在基板上沿著第一方向堆疊,每個通道構件沿著第二方向縱向(lengthwise)延伸;閘極結構,在通道構件上方以及周圍;以及第一源極/汲極部件以及第二源極/汲極部件,在基板上,其中通道構件沿著第二方向設置在第一源極/汲極部件以及第二源極/汲極部件之間,其中第一源極/汲極部件以及第二源極/汲極部件包括金屬。
本發明又一些實施例提供一種形成半導體裝置的方法,包括:在基板上形成堆疊,堆疊包括與複數個第二半導體層交錯的複數個第一半導體層;由堆疊形成鰭片結構;蝕刻源極/汲極溝槽以露出第一半導體層以及第二半導體層的側壁;在鰭片結構中選擇性地凹蝕第二半導體層以形成內間隔物凹口;在內間隔物凹口中形成內間隔物部件;在源極/汲極溝槽中露出的第一半導體層上選擇性地沉積磊晶層;在磊晶層上形成金屬矽化物層;以及在源極/汲極溝槽中沉積源極/汲極部件,使源極/汲極部件接觸內間隔物部件以及金屬矽化物層。
以下內容提供了許多不同實施例或範例,以實現本揭露實施例的不同部件。以下描述組件和配置方式的具體範例,以簡化本揭露實施例。當然,這些僅僅是範例,而非意圖限制本揭露實施例。舉例而言,元件的尺寸不限於所揭露的範圍或數值,而是可以取決於製程條件及/或裝置的期望特性。此外,在以下描述中提及於第二部件上方或其上形成第一部件,其可以包含第一部件和第二部件以直接接觸的方式形成的實施例,並且也可以包含在第一部件和第二部件之間形成額外的部件,使得第一部件和第二部件可以不直接接觸的實施例。為了簡單和清楚起見,可以按不同比例任意繪製各種部件。
再者,其中可能用到與空間相對用詞,例如「在……之下」、「下方」、「較低的」、「上方」、「較高的」等類似用詞,是為了便於描述圖式中一個(些)部件或特徵與另一個(些)部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位,以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位),其中所使用的空間相對形容詞也將依轉向後的方位來解釋。再者,用語「大約」、「近似」等類似用語描述數字或數字範圍時,該用語意欲涵蓋的數值是在合理範圍內包含所描述的數字,例如在所描述的數字之+/- 10%之內,或本發明所屬技術領域中具有通常知識者理解的其他數值。例如,用語「大約5奈米」涵蓋從4.5奈米至5.5奈米的尺寸範圍。
本揭露一般來說關於多閘極電晶體以及其製造方法,並且更詳細而言,關於形成薄磊晶層,以最大化通過金屬源極/汲極部件的電流傳導,上述金屬源極/汲極部件的導電性比常規的磊晶源極/汲極部件的導電性高。
多閘極電晶體包括閘極結構形成在通道區的至少兩側上的電晶體。這些多閘極裝置可以包括p型金屬氧化物半導體裝置或n型金屬氧化物半導體裝置。多閘極電晶體的示例包括FinFETs,因其鰭狀結構以及全繞式閘極(GAA)裝置。GAA裝置包括其閘極結構或其一部份形成在通道區的四側(例如,圍繞通道區的一部份)的任何裝置。本揭露實施例的通道區可以具有以下配置:奈米線通道、棒狀(bar-shaped)通道、奈米片通道、奈米結構通道、柱狀(column-shaped)通道、桿狀(post-shaped)通道及/或其他合適的通道配置。根據本揭露的裝置可以具有與單一連續閘極結構相關的一個或多個通道構件(例如,奈米線、奈米片、奈米結構)。然而,本領域一般技術人員將能理解本揭露的教示可以適用於單一通道(例如,單一通道構件、單一奈米線、單一奈米片、單一奈米結構)或任意數量的通道。本領域一般技術人員將能理解可以從本揭露受益的半導體裝置的其他示例。
常規地,在多閘極裝置的源極/汲極區上方形成磊晶源極/汲極部件以與通道構件相接(interface)。磊晶源極/汲極部件形成在源極/汲極開口(或源極/汲極溝槽)中,上述源極/汲極開口形成在主動區的源極/汲極區中。之後使用合適的磊晶成長製程在源極/汲極開口中沉積磊晶源極/汲極部件。用於磊晶源極/汲極部件的磊晶材料從在源極/汲極開口中露出的通道構件表面成長直到填充源極/汲極開口。由於磊晶源極/汲極部件中等的(moderate)導電性,隨著其尺寸持續縮小,磊晶源極/汲極部件的導電性可能會低於預期的導電性。
本揭露提供一些實施例,其中只有薄磊晶層形成在源極/汲極開口中露出的通道構件表面上,從而允許金屬源極/汲極部件可以填充在源極/汲極開口中。通過用金屬源極/汲極部件替換大部份的磊晶源極/汲極部件,本揭露的源極/汲極部件具有降低的接觸電阻。為了形成金屬源極/汲極部件,本揭露的方法在以功能性閘極結構替換虛設閘極堆疊之前,在源極/汲極開口中形成虛設磊晶部件以作為佔位符(placeholder)。之後去除虛設磊晶部件以露出源極/汲極開口中的通道構件表面。之後在露出的通道構件表面上成長薄磊晶層而不填滿源極/汲極開口。之後將金屬矽化物層和金屬源極/汲極部件沉積到源極/汲極開口的其餘部份中。
以下將參考附圖更詳細地描述本揭露的各個方面。第1圖根據本揭露的實施例,繪示由工件形成半導體裝置的方法100。方法100僅是示例,並不旨在將本揭露限制為方法100中明確示出的內容。可以在方法100之前、期間和之後提供額外的步驟,並且對於方法的額外實施例,可以替換、消除或移動所描述的一些步驟。為了簡單起見,本揭露沒有詳細描述所有步驟。以下將配合第2-11圖描述方法100,第2-11圖根據第1圖的方法100的實施例,係半導體裝置在不同製造階段的局部剖面圖。
參照第1圖以及第2圖,方法100包括步驟102,在步驟102中接收工件200。工件200包括在基板202上方的多個交替的半導體層的堆疊204。應當理解,因為在製程結束時由工件200形成半導體裝置,所以可以根據需要將工件200稱為半導體裝置200。工件200包括基板202。在一些實施例中,基板202可以是半導體基板,例如矽基板。基板202可以包括各種膜層,包括形成在半導體基板上的導電層或絕緣層。如本領域中所知,取決於設計要求,基板202可以包括各種摻雜配置。例如,可以在針對不同裝置類型(例如,n型電晶體、p型電晶體)而設計的區域中的基板202上形成不同的摻雜輪廓(例如,n阱、p阱)。合適的摻雜可以包括摻質的離子佈植及/或擴散製程。基板202可以具有隔離部件,插入隔離部件以提供不同裝置類型的區域。基板202也可以包括其他半導體,例如鍺、碳化矽(SiC)、矽鍺(SiGe)或鑽石。替代地,基板202可以包括化合物半導體及/或合金半導體。此外,基板202可以可選地(optionally)包括磊晶層(epi-layer),可以被應變以提高性能,可以包括絕緣體上矽(silicon-on-insulator, SOI)結構及/或可以具有其他合適的增強部件(enhancement features)。在方法100的實施例中,執行抗穿擊(anti-punch through, APT)佈植以在例如裝置的通道區下方的區域中形成,以防止穿擊或不期望的擴散。
工件200包括在基板202上方的複數個交替的半導體層的堆疊204。堆疊204包括以交錯(interleaving)或交替(alternating)的配置從基板202的表面垂直地(例如,沿著z方向)堆疊的第一半導體層206和第二半導體層208。在一些實施例中,以所示的交錯和交替配置磊晶成長第一半導體層206和第二半導體層208。在這樣的實施例中,第一半導體層206和第二半導體層208也可以被稱為第一磊晶層206和第二磊晶層208。在一些實施例中,第一磊晶層206和第二磊晶層208的磊晶成長可以通過分子束磊晶(molecular beam epitaxy, MBE)製程、化學氣相沉積(chemical vapor deposition, CVD)製程、金屬有機化學氣相沉積(metalorganic chemical vapor deposition, MOCVD)製程、其他合適的磊晶成長製程或其組合來沉積。第一磊晶層206的組成不同於第二磊晶層208的組成,以在後續製程期間實現蝕刻選擇性及/或不同的氧化速率。在一些實施例中,第一磊晶層206對蝕刻劑具有第一蝕刻速率,第二磊晶層208對蝕刻劑具有第二蝕刻速率,其中第二蝕刻速率小於第一蝕刻速率。在一些實施例中,第一磊晶層206具有第一氧化速率,第二磊晶層208具有第二氧化速率,其中第二氧化速率小於第一氧化速率。在所描繪的實施例中,第一磊晶層206和第二磊晶層208包括不同的材料、組成原子百分比、組成重量百分比、厚度及/或特性,以在蝕刻製程期間實現期望的蝕刻選擇性,例如實施蝕刻製程以在多閘極裝置,例如GAA裝置,的通道區中形成懸置的通道構件。例如,在第一磊晶層206包括矽鍺並且第二磊晶層208包括矽的情況下,第二磊晶層208的矽蝕刻速率小於第一磊晶層206的矽鍺蝕刻速率。在一個實施例中,第一磊晶層206包括矽鍺(SiGe),第二磊晶層208包括矽(Si)。替代地,在一些實施例中,第一磊晶層206和第二磊晶層208中的任一個可以包括其他材料,例如鍺;化合物半導體,例如碳化矽(silicon carbide)、砷化鎵(GaAs)、磷化鎵(GaP)、磷化銦(InP)、砷化銦(InAs)以及/或銻化銦(InSb);合金半導體,例如矽鍺(SiGe)、磷砷化鎵(GaAsP)、砷化鋁銦(AlInAs)、砷化鋁鎵(AlGaAs)、砷化鎵銦(GaInAs)、磷化鎵銦(GaInP)以及/或磷砷化鎵銦(GaInAsP);或其組合。在一些實施例中,第一磊晶層206和第二磊晶層208大抵不含有摻質(即,具有約0cm-3
至約1×1017
cm-3
的外來(extrinsic)摻質濃度),例如,在磊晶成長製程期間不進行有意圖的摻雜(intentional doping)。
應當理解,如第2圖所示,第一磊晶層206的三(3)層和第二磊晶層208的三(3)層交替設置,其僅出於說明目的,並不旨在限制請求項中具體記載的內容。應當理解,可以在堆疊204中形成任何數量的磊晶層。層的數量取決於半導體裝置200通道構件的期望數量。在一些實施例中,第二磊晶層208的數量在2至10之間。在一些實施例中,所有的第一磊晶層206具有第一厚度,並且所有的磊晶層208具有第二厚度。第一厚度可以不同於第二厚度。如以下更詳細地描述,第二磊晶層208或其部份可以作為隨後形成的多閘極裝置的通道構件,並且可以基於裝置性能來選擇第二厚度。通道區中的第一磊晶層206可以最終被去除並且用於定義隨後形成的多閘極裝置的鄰近通道區之間的垂直距離,並且可以基於裝置性能來選擇第一厚度。因此,第一磊晶層206也可以被稱為犧牲層206,第二磊晶層208也可以被稱為通道層208。
參照第1圖以及第2圖,方法100包括步驟104,步驟104形成鰭片結構205。鰭片結構205可以包括基板部份(即,基板202的一部份)和半導體層堆疊部份(即,堆疊204的其餘部份)。鰭片結構205具有在X方向上定義的長度、在Y方向上定義的寬度以及在Z方向上定義的高度。在一些實施方式中,執行微影及/或蝕刻製程以圖案化堆疊204以形成鰭片結構205。微影製程包括在堆疊204上形成光阻層(例如,通過旋轉塗佈)、執行預曝光烘烤製程、使用遮罩執行曝光製程、執行曝光後烘烤製程以及執行顯影製程。在曝光製程中,光阻層會暴露在輻射能量下(例如紫外線(ultraviolet, UV)、深紫外線(deep UV, DUV)或極紫外線(extreme UV, EUV)),其中遮罩根據遮罩的遮罩圖案及/或遮罩類型(例如,二元遮罩(binary mask)、相移遮罩(phase shift mask)或EUV遮罩)阻擋、穿過及/或反射輻射至光阻層,從而將圖案投影到與遮罩圖案相對應的光阻層上。由於光阻層對輻射能量敏感,因此在顯影製程中,光阻層露出的部份發生化學變化,並且光阻層露出的(或未露出的)部份溶解,取決於光阻層的特性和在顯影製程中使用的顯影液的特性。在顯影之後,圖案化的光阻層包括與遮罩相對應的光阻圖案。蝕刻製程使用圖案化的光阻層作為蝕刻遮罩以去除堆疊204的部份。在一些實施例中,圖案化的光阻層形成在硬遮罩層上方,上述硬遮罩層設置在堆疊204上方,第一蝕刻製程去除硬遮罩層的部份以形成圖案化的硬遮罩層,並且第二蝕刻製程使用圖案化的硬遮罩層作為蝕刻遮罩以去除堆疊204的部份。蝕刻製程可以包括乾式蝕刻製程、濕式蝕刻製程、其他合適的蝕刻製程或其組合。在一些實施例中,蝕刻製程為反應離子蝕刻(reactive ion etching, RIE)製程。在蝕刻製程之後,例如通過光阻剝離製程或其他合適的製程去除圖案化的光阻層(以及在一些實施例中,硬遮罩層)。替代地,鰭片結構205可以通過多重圖案化製程形成,例如雙重圖案化微影(double patterning lithography, DPL)製程(例如,微影-蝕刻-微影-蝕刻(lithography-etch-lithography-etch, LELE)製程、自對準雙重圖案化(self-aligned double patterning, SADP)製程)、間隔物即介電質(spacer-is-dielectric, SID)SADP製程、其他雙重圖案化製程或其組合);三重圖案化製程(例如,微影-蝕刻-微影-蝕刻-微影-蝕刻(lithography-etch-lithography-etch-lithography-etch, LELELE)製程、自對準三重圖案化(self-aligned triple patterning, SATP)製程、其他三重圖案化製程或其組合);其他多重圖案化製程(例如,自對準四重圖案化(self-aligned quadruple patterning, SAQP)製程)或其組合。在一些實施例中,在圖案化堆疊204的同時實施定向自組裝(directed self-assembly, DSA)技術。此外,在一些實施例中,曝光製程可以實施無遮罩微影、電子束(e-beam)寫入及/或離子束寫入以圖案化光阻層。
參照第1圖以及第2圖,方法100包括步驟106,步驟106形成與鰭片結構205鄰近的隔離部件207。在一些實施例中,隔離部件207形成在基板202之上及/或之中,以將鰭片結構205與相似於鰭片結構205的鄰近鰭片結構(未示出)隔離。在一些實施例中,隔離部件207可以包括不同的結構,例如淺溝槽隔離(shallow trench isolation, STI)結構。在這些實施例中,形成隔離部件207的步驟可以包括:通過在形成鰭片結構205之後在工件200上方沉積絕緣體材料、通過化學機械研磨(chemical mechanical polishing, CMP)平坦化工件200以及回蝕絕緣體材料層以形成隔離部件207。在這些實施例中,絕緣材料層可以包括氧化矽、氮化矽、氮氧化矽、摻氟矽酸鹽玻璃(fluorine-doped silicate glass, FSG)、硼矽酸鹽玻璃(borosilicate glass, BSG)、磷矽酸鹽玻璃(phosphoric silicate glass, PSG)、低介電常數介電質、其組合或其他合適的材料。
在一些實施例中,在步驟104處,介電鰭片212可以可選地形成在工件200上方。在形成介電鰭片的示例性製程流程中,在將隔離部件207的絕緣材料層沉積在工件200上並對其頂表面進行平坦化之後,在平坦化的絕緣材料層內形成有與鰭片結構205平行地延伸的狹縫(slit)。因此,隨後將介電鰭片材料沉積到狹縫中。介電鰭片材料不同於形成隔離部件207的絕緣材料層。這允許絕緣材料層在上述隔離部件回蝕製程中被選擇性地蝕刻,從而留下介電鰭片212,上述介電鰭片上升至隔離部件207上方。在一些實施例中,介電鰭片材料可以包括氮化矽、氮碳化矽、碳化矽、氧化鋁、氧化鋯或其他合適的材料。在設置介電鰭片的實施例中,鰭片結構205位於兩個介電鰭片212之間,並且用於分離鄰近裝置的源極/汲極部件。介電鰭片212也可以被稱為虛設鰭片212或混合鰭片212。在一些實施例中,介電鰭片212可具有約5nm至約10nm之間的鰭片厚度F。上述的鰭片厚度F範圍確保介電鰭片212足夠的機械強度,同時介電鰭片212不佔據過多用於形成源極/汲極部件的空間。
參照第1圖以及第2圖,方法100包括步驟108,步驟108在鰭片結構205的通道區205C上方形成虛設閘極堆疊210。在一些實施例中,虛設閘極堆疊210在鰭片結構205的通道區205C上沿著Y方向延伸,上述鰭片結構205的通道區205C沿著X方向縱向(lengthwise)延伸。在形成介電鰭片212的實施例中,虛設閘極堆疊210也形成在介電鰭片212上方,如第2圖所示。在一些實施例中,採用閘極替換製程(或閘極後製製程),其中虛設閘極堆疊210用作功能性閘極結構的佔位符(placeholder),並將其移除且由功能性閘極結構替換。可以具有其他製程和配置。除了通道區205C之外,鰭片結構205還包括沿著X方向設置在通道區205C的兩側上的源極/汲極區205SD。儘管在第2圖中未明確示出,虛設閘極堆疊210可以包括在通道區205C上方的虛設介電層、在虛設介電層上方的虛設電極層以及在虛設電極層上方的閘頂硬遮罩。在一些實施例中,虛設介電層可以由氧化矽形成,並且虛設電極層可以由多晶矽形成。閘頂硬遮罩可以是單層及多層。在一些情況下,閘頂硬遮罩的多層包括在虛設電極層上方的氧化矽層和在氧化矽層上方的氮化矽層。虛設閘極堆疊210的形成可以包括各種製程步驟,例如層沉積、圖案化、蝕刻以及其他合適的製程步驟。示例的層沉積製程包括低壓CVD、CVD、電漿輔助CVD(PECVD)、PVD、ALD、熱氧化、電子束蒸鍍或其他合適的沉積技術或其組合。例如,圖案化製程可以包括微影製程(例如,微影或電子束微影),其可以進一步包括光阻塗佈(例如,旋塗)、軟烘烤、遮罩對準、曝光、曝光後烘烤、光阻顯影、沖洗、乾燥(例如,旋轉乾燥及/或硬烘烤),其他合適的微影技術及/或其組合。在一些實施例中,蝕刻製程可以包括乾式蝕刻(例如RIE蝕刻)、濕式蝕刻及/或其他蝕刻方法。
參照第1圖以及第3圖,方法100包括步驟110,步驟110在工件200上方形成第一介電層214。在一些實施例中,可以使用次大氣壓CVD(subatmospheric CVD, SACVD)、CVD、電漿輔助CVD(PECVD)、ALD或合適的技術沉積第一介電層214。第一介電層214可以包括氧化矽、矽化鉿、碳氧化矽、氧化鋁、矽化鋯、氧氮化鋁、氧化鋯、氧化鉿、氧化鉿鋯、氧化鈦、氧化鋯鋁、氧化鋅、氧化鉭、氧化鑭、氧化釔、碳氮化鉭、氮化矽、碳氮氧化矽、矽、氮化鋯或碳氮化矽。將如下所述,選擇第一介電層214,使得可以選擇性地蝕刻第二介電層(第6圖所示的224),而大抵不損壞第一介電層214。在一些實施例中,在沉積第一介電層214之後,回蝕多餘的第一介電層214並從介電鰭片212(若存在)、鰭片結構205以及虛設閘極堆疊210的頂表面去除,如第3圖所示。在一些實施例中,閘極間隔物216形成在虛設閘極堆疊210的側壁上方。在一些實施例中,用於形成閘極間隔物216的間隔物材料順應性地(conformally)沉積在工件200上方,包括在虛設閘極堆疊210的頂表面和側壁上方,以形成間隔物材料層。為了便於描述在各個區域具有大抵均勻的厚度的膜層,本揭露可以使用術語“順應性地”。閘極間隔物216可以具有單層構造或包括多層。閘極間隔物216可以由與第一介電層214相同的材料並使用相同的製程形成。在一個實施例中,第一介電層214和閘極間隔物216同時形成。亦即,在工件200上沉積第一介電層214之後,可以執行非等向性蝕刻製程以去除頂表面上的多餘的第一介電層214,從而在虛設閘極堆疊210的側壁上形成閘極間隔物216,以及在由隔離部件207、源極/汲極區205SD以及虛設閘極堆疊210定義的空間中形成第一介電層214。
參照第1圖以及第4圖,方法100包括步驟112,步驟112蝕刻鰭片結構205以在鰭片結構205的源極/汲極區205SD中形成源極/汲極凹口218。在步驟112處,選擇性地蝕刻鰭片結構205的源極/汲極區205SD以形成源極/汲極凹口218,而大抵不蝕刻第一介電層214、閘極間隔物216和虛設閘極堆疊210。源極/汲極凹口218也可以被稱為源極/汲極溝槽218。如第4圖所示,通道區205C中的堆疊204的側壁在源極/汲極凹口218中露出。儘管未明確示出,可以使用微影製程和至少一個硬遮罩以執行步驟112處的操作。在一些實施例中,通過乾式蝕刻或合適的蝕刻製程蝕刻鰭片結構205未被虛設閘極堆疊210和閘極間隔物216覆蓋的部份,以形成源極/汲極凹口218。例如,乾式蝕刻製程可以施用含氧氣體、含氟氣體(例如,CF4
、SF6
、CH2
F2
、CHF3
及/或C2
F6
)、含氯氣體(例如,Cl2
、CHCl3
、CCl4
及/或BCl3
)、含溴氣體(例如HBr及/或CHBR3
)、含碘氣體、其他合適的氣體及/或電漿及/或其組合。
參照第1圖以及第5圖,方法100包括步驟114,步驟114形成內間隔物部件220。為了形成第5圖所示的內間隔物部件220,選擇性地和部份地凹蝕在源極/汲極凹口218中露出的犧牲層206,以在通道區205C中形成內間隔物凹口,同時露出的通道層208大抵未被蝕刻。在通道層208大抵由Si組成並且犧牲層206大抵由SiGe組成的實施例中,犧牲層206的選擇性凹蝕可以包括SiGe氧化製程,之後去除SiGe氧化物。在那些實施例中,SiGe氧化製程可以包括使用臭氧。在一些實施例中,選擇性凹蝕可以是選擇性等向性蝕刻製程(例如,選擇性乾式蝕刻製程或選擇性濕式蝕刻製程),並且犧牲層206的凹蝕程度由蝕刻製程的持續時間控制。在一些實施例中,選擇性乾式蝕刻製程可以包括使用一種或多種氟基蝕刻劑,例如氟氣或氫氟碳化物。在一些實施例中,選擇性濕式蝕刻製程可以包括氫氟酸(HF)或NH4
OH蝕刻劑。之後通過CVD、PECVD、SACVD、ALD或其他合適的方法將內間隔物材料沉積在工件200上。在回蝕製程中去除未設置在內間隔物凹口中多餘的內間隔物材料。內間隔物材料可以包括氧化矽、矽化鉿、碳氧化矽、氧化鋁、矽化鋯、氧氮化鋁、氧化鋯、氧化鉿、氧化鉿鋯、氧化鈦、氧化鋯鋁、氧化鋅、氧化鉭、氧化鑭、氧化釔、碳氮化鉭、氮化矽、碳氮氧化矽、矽、氮化鋯或碳氮化矽。
參照第1圖以及第6圖,方法100包括步驟116,步驟116在源極/汲極凹口218中形成虛設源極/汲極部件222。相似於用作功能性閘極結構的佔位符的虛設閘極堆疊210,虛設源極/汲極部件222用作功能性源極/汲極部件的佔位符。亦即,至少在本揭露的一些實施例中,虛設源極/汲極部件222將在隨後的製程中大抵被去除,因此其並非最終結構的一部份。選擇用於虛設源極/汲極部件222的材料,使其可以被選擇性地去除而不會損壞通道區205C中的第一介電層214,閘極間隔物216和通道層208。在一些實施例中,虛設源極/汲極部件222可以由半導體材料形成並且可以包括矽和鍺。在這些實施例中,虛設源極/汲極部件222中的鍺成分允許選擇性地去除虛設源極/汲極部件222,而不會損壞通道區205C中的第一介電層214、閘極間隔物216和通道層208。此外,在這些實施例中,虛設源極/汲極部件222由SiGe形成,並且其鍺濃度在大約20%至大約60%之間。儘管虛設源極/汲極部件222的成分可以與犧牲層206的成分相似,但是此時犧牲層206受到在步驟114處形成的內間隔物部件220的保護,並沒有受到損壞的風險。在一些實施例中,虛設源極/汲極部件222可以摻雜有n型摻質,例如磷(P)和砷(As),或是p型摻質,例如硼(B)。在一些其他實施例中,虛設源極/汲極部件222可以不具有摻質。
參照第1圖以及第6圖,方法100包括步驟118,步驟118將第二介電層224沉積在工件上方。在一些實施例中,第二介電層224包括層間介電(interlayer dielectric, ILD)層。在一些實施例中,第二介電層224包括材料,例如原矽酸四乙酯(tetraethylorthosilicate, TEOS)氧化物;未摻雜的矽酸鹽玻璃或摻雜的氧化矽,例如硼磷矽酸鹽玻璃(borophosphosilicate glass, BPSG)、熔融石英玻璃(fused silica glass, FSG)、磷矽酸鹽玻璃(phosphosilicate glass, PSG)、摻硼矽玻璃(boron doped silicon glass, BSG)及/或其他合適的介電材料。可以通過PECVD製程或其他合適的沉積技術沉積第二介電層224。在一些實施例中,在形成第二介電層224之後,可以對工件200進行退火以改善第二介電層224的完整性(integrity)。在一些實施例中,在沉積第二介電層224之後,可以執行平坦化製程以去除過多的介電材料。例如,平坦化製程包括化學機械平坦化(chemical mechanical planarization, CMP)製程,化學機械平坦化(CMP)製程去除覆蓋在虛設閘極堆疊210上的部份第二介電層224並平坦化工件200的頂表面。在一些實施例中,CMP製程也去除閘極頂硬遮罩並露出虛設電極層。虛設電極層的露出允許虛設閘極堆疊210的去除以及通道層208的釋出。
參照第1圖以及第6圖,方法100包括步驟120,步驟120以功能閘極結構226替換虛設閘極堆疊210。在一些實施例中,步驟120處的操作包括去除虛設閘極堆疊210(包括虛設閘極介電層和虛設電極層),從而在通道區205C上方形成閘極溝槽。去除虛設閘極堆疊210可以包括對虛設閘極堆疊210中的材料具有選擇性的一種或多種蝕刻製程。例如,可以使用對虛設電極層具有選擇性的選擇性濕式蝕刻、選擇性乾式蝕刻或其組合執行虛設閘極堆疊210的去除。通道區205C中的犧牲層206和通道層208在閘極溝槽中露出。在去除虛設閘極堆疊210之後,方法100可以包括用於選擇性地去除通道區205C中通道層208之間的犧牲層206的操作。選擇性去除犧牲層206釋出通道層208以形成通道構件208。應當理解,為簡單起見,相同的附圖標記208用於表示通道構件208。選擇性去除犧牲層206可以通過選擇性乾式蝕刻、選擇性濕式蝕刻或其他選擇性蝕刻製程實現。在一些實施例中,選擇性濕式蝕刻包括APM蝕刻(例如,氫氧化氨-過氧化氫-水的混合物)。在一些實施例中,選擇性去除包括SiGe氧化,之後去除SiGeOx
。例如,可以通過臭氧清潔以提供氧化,之後通過例如NH4
OH的蝕刻劑去除SiGeOx
。
在釋出通道構件208之後,之後在閘極溝槽中形成功能閘極結構226,以包繞每個釋出的通道構件208。在各種實施例中,功能閘極結構226可以包括界面層、形成在界面層之上的高介電常數閘極介電層及/或形成在高介電常數閘極介電層之上的閘極電極層。如本揭露所使用和描述,高介電常數閘極介電質包括具有高介電常數的介電材料,例如,其介電常數大於熱氧化矽的介電常數(〜3.9)。閘極電極層可以包括金屬、金屬合金或金屬矽化物。此外,形成功能閘極結構226的步驟可以包括:沉積以形成各種閘極材料、一個或多個襯層以及一個或多個CMP製程以去除多餘的閘極材料,從而使工件200的頂表面平坦化。在一些實施例中,功能閘極結構226的界面層可以包括介電材料,例如氧化矽、矽酸鉿或氮氧化矽。界面層可以通過化學氧化、熱氧化、原子層沉積(atomic layer deposition, ALD)、化學氣相沉積(chemical vapor deposition, CVD)及/或其他合適的方法形成。功能閘極結構226的高介電常數閘極介電層可以包括高介電常數介電層,例如氧化鉿。替代地,功能閘極結構226的高介電常數閘極介電層可以包括其他高介電常數介電質,例如TiO2
、HfZrO、Ta2
O3
、HfSiO4
、ZrO2
、ZrSiO2
、LaO、AlO、ZrO、TiO、Ta2
O5
、Y2
O3
、SrTiO3
(STO)、BaTiO3
(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba、Sr)TiO3
(BST)、Al2
O3
、Si3
N4
、氧氮化物(SiON)、其組合或其他合適的材料。高介電常數閘極介電層可以通過ALD、物理氣相沉積(physical vapor deposition, PVD)、CVD、氧化及/或其他合適的方法形成。
功能閘極結構226的閘極電極層可以包括單層或多層結構,例如具有選定的功函數的金屬層以提升裝置性能(功函數金屬層)、襯層、潤濕層(wetting layer)、黏著層、金屬合金或金屬矽化物的各種組合。舉例來說,功能閘極結構226的閘極電極層可以包括:Ti、Ag、Al、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、Al、WN、Cu、W、Re、Ir、Co、Ni、其他合適的金屬材料或其組合。在各種實施例中,可以通過ALD、PVD、CVD、電子束蒸鍍或其他合適的製程以形成功能閘極結構226的閘極電極層。此外,對於N-FET以及P-FET電晶體,可以分別單獨形成閘極電極層,N-FET以及P-FET電晶體使用不同金屬層(例如,用於提供不同的n型以及p型功函數金屬層)。在各種實施例中,可以執行CMP製程以從功能閘極結構226的閘極電極層去除過量的金屬,從而提供功能閘極結構226大抵平坦的頂表面。功能閘極結構226包括在通道區205C中插入(interpose)通道構件208的部份。
參照第1圖、第7圖以及第8圖,方法100包括步驟122,步驟122形成源極/汲極開口228以露出通道構件208和內間隔物部件220。源極/汲極開口228可以包括頂部開口228T和底部開口228B。如第8圖所示,當使用圖案化的光阻層作為蝕刻遮罩以蝕刻第二介電層224時,形成頂部開口228T;當選擇性地去除虛設源極/汲極部件222時,形成底部開口228B。在一些實施例中,在步驟122中在分別的蝕刻製程中形成頂部開口228T和底部開口228B。首先參考第7圖,首先蝕刻第二介電層224以形成頂部開口228T。因為第二介電層224具有與第一介電層214和虛設源極/汲極部件222不同的組成,所以可以蝕刻頂部開口228T而大抵不損壞第一介電層214和虛設源極/汲極部件222。形成頂部開口228T露出虛設源極/汲極部件222和第一介電層214的一部份。之後參考第8圖,隨後選擇性地去除虛設源極/汲極部件222以形成底部開口228B。在虛設源極/汲極部件222包括矽鍺的一些實施例中,可以使用相似於在步驟120處用於去除犧牲層206的製程來去除虛設源極/汲極部件222。
參照第1圖以及第9圖,方法100包括步驟124,步驟124在通道構件208的側壁上形成薄磊晶部件230。顧名思義,薄磊晶部件230使用磊晶成長製程,例如氣相磊晶(vapor-phase epitaxy, VPE)、超高真空CVD(ultra-high vacuum CVD, UHV-CVD)或分子束磊晶(molecular beam epitaxy, MBE)形成。因為磊晶成長製程對半導體材料(例如,矽通道構件208)具有選擇性,並且在介電材料(例如,內間隔件部件220、第一介電層214和第二介電層224)上可以忽略(negligible),薄磊晶部件230從通道構件208露出的側表面沿著X方向成長。在一些情況下,形成薄磊晶部件230以具有第一厚度T在大約3nm與大約10nm之間,包括大約5nm與大約8nm之間。如第9圖所示,底部開口228B沿著Y方向具有第一寬度W1、沿著Z方向具有高度H以及沿著X方向具有第二厚度T2。頂部開口228T沿著Y方向具有第二寬度W2。在一些實施例中,第一寬度W1可以在大約20nm至大約70nm之間、高度H可以在大約40nm至大約60nm之間、第二厚度T2可以在大約15nm至大約25nm之間以及第二寬度W2可以在大約30nm至大約70nm之間。可以看出大抵填滿底部開口228B的可能是常規的磊晶部件並具有第二厚度T2。薄磊晶部件230(第一厚度T1在大約3nm與大約10nm之間)比可能的(would-be)常規磊晶部件(第二厚度T2在大約15nm與大約25nm之間)更薄。在一些實施例中,在組成以及尺寸方面,可能的常規磊晶部件可以相似於虛設源極/汲極部件222。
取決於半導體裝置200的導電類型,薄磊晶部件230可以是n型或p型。n型薄磊晶源極/汲極部件230可以包括Si、GaAs、GaAsP、SiP或其他合適的材料。通過引入摻雜物質,包括n型摻質例如磷或砷及/或其他合適的摻質,包括其組合,可以在磊晶製程期間對n型薄磊晶源極/汲極部件230進行原位摻雜。在示例性實施例中,n型裝置中的n型薄磊晶源極/汲極部件230可以包括SiP。p型薄磊晶源極/汲極部件230可以包括Si、Ge、AlGaAs、SiGe、摻硼SiGe或其他合適的材料。通過引入摻雜物質,包括p型摻質例如硼或BF2
及/或其他合適的摻質,包括其組合,可以在磊晶製程期間對p型薄磊晶源極/汲極部件230進行原位摻雜。在示例性實施例中,p型裝置中的p型薄磊晶源極/汲極部件230包括SiGeB。在一些實施方式中,用於形成薄磊晶部件230的磊晶成長製程可能涉及升高的製程溫度,這可能帶來損壞功能閘極結構226的風險。然而,由於薄磊晶部件230很薄並且花費較少的時間形成,上述風險可以被最小化。
參照第1圖以及第10圖,方法100包括步驟126,步驟126在超薄磊晶部件上形成矽化物層234。在示例製程中,金屬層232沉積在薄磊晶部件230和內間隔物部件220的表面上,並且對工件200進行退火,以使薄磊晶部件230中的矽與金屬層232之間發生矽化反應,從而形成矽化物層234。在一些實施方式中,金屬層232可以包括鈦(Ti)、鎳(Ni)、鈷(Co)、鉭(Ta)或鎢(W)。在一實施例中,金屬層232可以由選自鈦(Ti)、鎳(Ni)和鈷(Co)的金屬物質形成。因為在內間隔物部件220和金屬層232之間的界面處幾乎沒有矽化物形成或沒有矽化物形成,所以金屬層232大抵保持其組成並且不會變成金屬矽化物。如第10圖所示,在步驟126處的操作結束時,矽化物層234設置在薄磊晶部件230上,並且金屬層232設置在內間隔物部件220上。由於形成矽化物層234的選擇性特性,矽化物層234僅存在於薄磊晶部件230之上,薄磊晶部件230沿著Z方向彼此隔開,並且矽化物層234也可以被視為並稱為矽化物部件234,其也沿著Z方向彼此隔開。取決於薄磊晶部件230的組成,在步驟126處形成的矽化物層234的組成可以包括金屬矽化物、金屬鍺化物、金屬鎵化物、金屬鋁化物以及n型摻質或p型摻質。當薄磊晶部件230為n型並用於n型半導體裝置時,矽化物層234可以包括矽化鈦、矽化鎳、矽化鈷、矽化鉭、矽化鎢、鎵化鈦、鎵化鎳、鎵化鈷、鎵化鉭、鎵化鎢以及n型摻質,例如磷(P)或砷(As)。當薄磊晶部件230為p型並用於p型半導體裝置時,矽化物層234可以包括矽化鈦、矽化鎳、矽化鈷、矽化鉭、矽化鎢、鍺化鈦、鍺化鎳、鍺化鈷、鍺化鉭、鍺化鎢以及p型摻雜劑,例如硼(B)或鋁(Al)。在一些情況下,矽化物層234可以由選自矽化鈦、矽化鎳和矽化鈷的金屬矽化物物質形成。在未單獨示出的一些替代實施例中,可以選擇性地去除沒有變成矽化物層234的過量金屬層232。在那些替代實施例中,金屬層232不存在於最終的半導體裝置200中。
參照第1圖以及第11圖,方法100包括步驟128,步驟128形成金屬源極/汲極部件236。在步驟128處,底部開口228B的其餘部份(未被薄磊晶部件230、金屬層232和矽化物層234所佔據)用金屬材料填充以形成金屬源極/汲極部件236。在一些實施方式中,金屬材料可以使用物理氣相沉積(PVD)、CVD或ALD沉積,並且可以由鈷(Co)、釕(Ru)或鎢(W)形成。由於金屬源極/汲極部件236由金屬材料形成,因此其具有比磊晶部件更大的導電性,然而磊晶部件重摻雜摻質。因此,金屬源極/汲極部件236可以大幅減小接觸電阻。
參照第1圖、第11圖以及第12圖,方法100包括步驟130,步驟130在金屬源極/汲極部件上方形成源極/汲極接觸件238。在一些實施例中,金屬材料可以沉積在頂部開口228T中以形成源極/汲極接觸件238。在一些實施例中,可以使用相似於形成金屬源極/汲極部件236的製程和金屬材料形成源極/汲極接觸件238。在那些實施例中,源極/汲極接觸件238可以使用PVD、CVD或ALD形成,並且可以由鈷、釕或鎢形成。在一實施例中,步驟128和130處的操作可以合併,並且金屬源極/汲極部件236和源極/汲極接觸件238可以同時形成。亦即,在這樣的實施例中,金屬材料可以沉積到底部開口228B和頂部開口228T中,以形成金屬源極/汲極部件236和源極/汲極接觸件238。
第12圖繪示沿著第11圖中的I-I’剖面的半導體裝置200的局部剖面圖。在第12圖的局部剖面圖中繪示第一多閘極電晶體300和第二多閘極電晶體400。第一多閘極電晶體300和第二多閘極電晶體400分別是GAA電晶體,其中功能閘極結構226包繞第一多閘極電晶體300和第二多閘極電晶體400各別通道區205C中的每個通道構件208。當金屬源極/汲極部件236、矽化物層234和薄磊晶部件230共同被視為多閘極電晶體(例如,第一多閘極電晶體300或第二多閘極電晶體400)的源極/汲極結構時,薄磊晶部件230用作其與通道構件208的界面,並且不佔據源極/汲極結構大部份的體積。矽化物層234用於減小薄磊晶部件230與金屬源極/汲極部件236之間的界面處的接觸電阻。金屬源極/汲極部件236得益於金屬材料的導電性,構成源極/汲極結構大部份的體積,並且用於減小沿著通道構件208與源極/汲極接觸件238之間的導電路徑的接觸電阻。如第12圖所示,薄磊晶部件230設置在通道構件208的側表面上,並且大抵在Y-Z平面上延伸,其法線方向沿著X方向。矽化物層234設置在薄磊晶部件230上,並且大抵平行於薄磊晶部件230延伸。因為從通道構件208選擇性地成長薄磊晶部件230,並且在薄磊晶部件230上選擇性地形成矽化物層234,所以它們藉由內間隔部件220定義的間隔沿著Z方向彼此垂直隔開。金屬層232夾設在內間隔件部件220和金屬源極/汲極部件236之間。在一些實施方式中,金屬層232的組成可以與金屬源極/汲極部件236的組成不同。例如,金屬層232可以包括鈦(Ti)、鉭(Ta)或鎳(Ni),而金屬源極/汲極部件236可以包括鈷(Co)、釕(Ru)或鎢(W)。在一些其他實施方式中,金屬層232和金屬源極/汲極部件236可以包括相同的金屬。例如,金屬層232和金屬源極/汲極部件236兩者可以包括鈷(Co)或鎢(W)。
參照第1圖,方法100包括步驟132,在步驟132中執行進一步的製程。進一步的製程可以包括形成蝕刻停止層(etch stop layers, ESL)、另外的層間介電(ILD)層、蓋層、自對準接觸(self-aligned contact, SAC)介電部件以及互連結構。這些進一步的製程形成到半導體裝置200中的電晶體的連接或互連。
儘管不旨在限制,但是本揭露的一個或多個實施例為半導體裝置及其形成方法提供許多益處。例如,本揭露的實施例提供一種金屬源極/汲極部件,金屬源極/汲極部件使通道區中的通道構件與薄磊晶部件和矽化物層相接。由於金屬源極/汲極部件由導電金屬材料而非摻雜的半導體材料形成,因此其通過降低接觸電阻以提高裝置性能。
根據本揭露的一些實施例,提供一種半導體裝置,包括:通道構件(members)的垂直堆疊;閘極結構,在通道構件的垂直堆疊上方以及周圍;以及第一源極/汲極部件以及第二源極/汲極部件,其中垂直堆疊的每個通道構件沿著第一方向在第一源極/汲極部件以及第二源極/汲極部件之間延伸,其中垂直堆疊的每個通道構件藉由矽化物部件與第一源極/汲極部件隔開。
在一些實施例中,第一源極/汲極部件以及第二源極/汲極部件包括鈷(Co)、釕(Ru)或鎢(W)。
在一些實施例中,矽化物部件包括矽化鈦、矽化鎳或矽化鈷。
在一些實施例中,矽化物部件直接接觸第一源極/汲極部件。
在一些實施例中,更包括:磊晶部件,設置在矽化物部件與垂直堆疊的每個通道構件之間。
在一些實施例中,磊晶部件包括半導體材料,其中磊晶部件包括沿著第一方向的厚度,並且厚度在約3奈米至約10奈米之間。
在一些實施例中,更包括:第一介電鰭片以及第二介電鰭片,其中第一源極/汲極部件以及第二源極/汲極部件沿著垂直於第一方向的第二方向設置在第一介電鰭片以及第二介電鰭片之間。
在一些實施例中,第一源極/汲極部件以及第二源極/汲極部件分別藉由介電層與第一介電鰭片以及第二介電鰭片隔開,其中介電層的組成不同於第一介電鰭片以及第二介電鰭片的組成。
根據本揭露的另一些實施例,提供一種半導體裝置,包括:複數個通道構件,在基板上沿著第一方向堆疊,每個通道構件沿著第二方向縱向(lengthwise)延伸;閘極結構,在通道構件上方以及周圍;以及第一源極/汲極部件以及第二源極/汲極部件,在基板上,其中通道構件沿著第二方向設置在第一源極/汲極部件以及第二源極/汲極部件之間,其中第一源極/汲極部件以及第二源極/汲極部件包括金屬。
在另一些實施例中,金屬包括鈷(Co)、釕(Ru)或鎢(W)。
在另一些實施例中,更包括:複數個矽化物部件,與第一源極/汲極部件接觸,其中通道構件藉由矽化物部件沿著第二方向與第一源極/汲極部件隔開,其中矽化物部件沿著第一方向彼此隔開。
在另一些實施例中,矽化物部件包括矽化鈦、矽化鎳或矽化鈷。
在另一些實施例中,更包括:複數個磊晶部件,與通道構件接觸,其中通道構件藉由磊晶部件沿著第二方向與矽化物部件隔開。
在另一些實施例中,更包括:複數個內間隔物部件,與第一源極/汲極部件接觸,其中通道構件藉由內間隔物部件沿著第一方向彼此部份地隔開。
根據本揭露的又一些實施例,提供一種形成半導體裝置的方法,包括:在基板上形成堆疊,堆疊包括與複數個第二半導體層交錯的複數個第一半導體層;由堆疊形成鰭片結構;蝕刻源極/汲極溝槽以露出第一半導體層以及第二半導體層的側壁;在鰭片結構中選擇性地凹蝕第二半導體層以形成內間隔物凹口;在內間隔物凹口中形成內間隔物部件;在源極/汲極溝槽中露出的第一半導體層上選擇性地沉積磊晶層;在磊晶層上形成金屬矽化物層;以及在源極/汲極溝槽中沉積源極/汲極部件,使源極/汲極部件接觸內間隔物部件以及金屬矽化物層。
在又一些實施例中,更包括:在蝕刻源極/汲極溝槽之後,在源極/汲極溝槽中沉積佔位符(placeholder)磊晶部件;在基板上沉積層間介電層;形成源極/汲極接觸開口以露出佔位符磊晶部件;以及在形成源極/汲極接觸開口之後,在源極/汲極溝槽中去除佔位符磊晶部件。
在又一些實施例中,佔位符磊晶部件包括矽以及鍺。
在又一些實施例中,金屬矽化物層包括矽化鈦、矽化鎳或矽化鈷。
在又一些實施例中,源極/汲極部件包括鈷(Co)、釕(Ru)或鎢(W)。
在又一些實施例中,選擇性地沉積磊晶層的步驟包括沉積磊晶層以具有約3奈米至約10奈米的厚度。
以上概述數個實施例之部件,以便在本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解,他們能輕易地以本發明實施例為基礎,設計或修改其他製程和結構,以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解,此類等效的結構並無悖離本發明的精神與範圍,且他們能在不違背本發明之精神和範圍下,做各式各樣的改變、取代和替換。因此,本發明之保護範圍當視後附之申請專利範圍所界定為準。
100:方法
102:步驟
104:步驟
106:步驟
108:步驟
110:步驟
112:步驟
114:步驟
116:步驟
118:步驟
120:步驟
122:步驟
124:步驟
126:步驟
128:步驟
130:步驟
132:步驟
200:工件
200:裝置
202:基板
204:堆疊
205:鰭片結構
206:半導體層
206:磊晶層
206:犧牲層
207:隔離部件
208:半導體層
208:磊晶層
208:通道構件
208:通道層
210:虛設閘極堆疊
212:混合鰭片
212:虛設鰭片
212:介電鰭片
214:介電層
216:閘極間隔物
218:源極/汲極凹口
218:源極/汲極溝槽
220:內間隔物部件
222:虛設源極/汲極部件
224:介電層
226:功能閘極結構
228:源極/汲極開口
230:薄磊晶部件
232:金屬層
234:矽化物層
236:金屬源極/汲極部件
238:源極/汲極接觸件
300:電晶體
400:電晶體
205C:通道區
205SD:源極/汲極區
228B:底部開口
228T:頂部開口
F:厚度
H:高度
T:厚度
T2:厚度
W1:寬度
W2:寬度
以下將配合所附圖示詳述本揭露之各面向。應注意的是,依據在業界的標準做法,各種特徵並未按照比例繪製且僅用以說明例示。事實上,可能任意地放大或縮小單元的尺寸,以清楚地表現出本揭露的特徵。
第1圖根據本揭露的一或多個方面,繪示用於製造半導體裝置的方法的流程圖。
第2-12圖根據本揭露的一或多個方面,繪示根據第1圖的方法在製造製程期間工件的局部剖面圖。
200:裝置
202:基板
208:通道構件
216:閘極間隔物
220:內間隔物部件
226:功能閘極結構
230:薄磊晶部件
232:金屬層
234:矽化物層
236:金屬源極/汲極部件
238:源極/汲極接觸件
300:電晶體
400:電晶體
205C:通道區
205SD:源極/汲極區
T2:厚度
Claims (15)
- 一種半導體裝置,包括:多個通道構件(members)的一垂直堆疊;一閘極結構,在通道構件的該垂直堆疊上方以及周圍;以及一第一源極/汲極部件以及一第二源極/汲極部件,其中該垂直堆疊的每個通道構件沿著一第一方向在該第一源極/汲極部件以及該第二源極/汲極部件之間延伸,其中該垂直堆疊的該些通道構件藉由複數個矽化物部件與該第一源極/汲極部件隔開,其中該第一源極/汲極部件的一部分在相鄰的該些矽化物部件之間延伸。
- 如請求項1所述之半導體裝置,其中該第一源極/汲極部件以及該第二源極/汲極部件包括鈷(Co)、釕(Ru)或鎢(W)。
- 如請求項1所述之半導體裝置,其中該些矽化物部件包括矽化鈦、矽化鎳或矽化鈷。
- 如請求項1至3中任一項所述之半導體裝置,其中該些矽化物部件直接接觸該第一源極/汲極部件。
- 如請求項1至3中任一項所述之半導體裝置,更包括:一磊晶部件,設置在該些矽化物部件與該垂直堆疊的每個通道構件之間。
- 如請求項5所述之半導體裝置,其中該磊晶部件包括一半導體材料,其中該磊晶部件包括沿著該第一方向的一厚度,並且該厚度在約3奈米至約10奈米之間。
- 如請求項1至3中任一項所述之半導體裝置,更包括:一第一介電鰭片以及一第二介電鰭片,其中該第一源極/汲極部件以及該第二源極/汲極部件沿著垂直於該第一方向的一第二方向設置在該第一介電鰭片以及該第二介電鰭片之間。
- 如請求項7所述之半導體裝置,其中該第一源極/汲極部件以及該第二源極/汲極部件分別藉由一介電層與該第一介電鰭片以及該第二介電鰭片隔開,其中該介電層的組成不同於該第一介電鰭片以及該第二介電鰭片的組成。
- 一種半導體裝置,包括:複數個通道構件,在一鰭片結構上沿著一第一方向堆疊,每個通道構件沿著一第二方向縱向(lengthwise)延伸;一第一隔離部件及一第二隔離部件,沿著一第三方向夾住該鰭片結構,該第三方向垂直於該第一方向及該第二方向;一閘極結構,在該些通道構件上方以及周圍;一閘極間隔物,設置在該閘極結構的側壁上;一第一源極/汲極部件以及一第二源極/汲極部件,在該鰭片結構上;一第一介電部件及一第二介電部件,沿著該第三方向夾住該第一源極/汲極部件;一第一介電鰭片,沿著該第一隔離部件及該第一介電部件的側壁連續地延伸;一第二介電鰭片,沿著該第二隔離部件及該第二介電部件的側壁連續地延伸;以及 一源極/汲極接觸件,設置在該第一源極/汲極部件上,其中該些通道構件沿著該第二方向設置在該第一源極/汲極部件以及該第二源極/汲極部件之間,其中該第一源極/汲極部件以及該第二源極/汲極部件包括一金屬,其中該源極/汲極接觸件直接接觸該閘極間隔物,其中該第一介電部件、該第二介電部件、該第一介電鰭片及該第二介電鰭片的頂表面共平面。
- 如請求項9所述之半導體裝置,更包括:複數個矽化物部件,與該第一源極/汲極部件接觸,其中該些通道構件藉由該些矽化物部件沿著該第二方向與該第一源極/汲極部件隔開,其中該些矽化物部件沿著該第一方向彼此隔開。
- 如請求項10所述之半導體裝置,更包括:複數個磊晶部件,與該些通道構件接觸,其中該些通道構件藉由該些磊晶部件沿著該第二方向與該些矽化物部件隔開。
- 如請求項9所述之半導體裝置,更包括:複數個內間隔物部件,與該第一源極/汲極部件接觸,其中該些通道構件藉由該些內間隔物部件沿著該第一方向彼此部份地隔開。
- 一種形成半導體裝置的方法,包括:在一基板上形成一堆疊,該堆疊包括與複數個第二半導體層交錯的複數個第一半導體層; 由該堆疊形成一鰭片結構;蝕刻一源極/汲極溝槽以露出該些第一半導體層以及該些第二半導體層的多個側壁;在該鰭片結構中選擇性地凹蝕該些第二半導體層以形成多個內間隔物凹口;在該些內間隔物凹口中形成多個內間隔物部件;在該源極/汲極溝槽中露出的該些第一半導體層上選擇性地沉積一磊晶層;在該磊晶層上形成一金屬矽化物層;以及在該源極/汲極溝槽中沉積一源極/汲極部件,使該源極/汲極部件接觸該些內間隔物部件以及該金屬矽化物層。
- 如請求項13所述之形成半導體裝置的方法,更包括:在蝕刻該源極/汲極溝槽之後,在該源極/汲極溝槽中沉積一佔位符(placeholder)磊晶部件;在該基板上沉積一層間介電層;形成一源極/汲極接觸開口以露出該佔位符磊晶部件;以及在形成該源極/汲極接觸開口之後,在該源極/汲極溝槽中去除該佔位符磊晶部件。
- 如請求項14所述之形成半導體裝置的方法,其中該佔位符磊晶部件包括矽以及鍺。
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