TWI763097B - 半導體結構及其形成方法 - Google Patents

半導體結構及其形成方法 Download PDF

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TWI763097B
TWI763097B TW109137187A TW109137187A TWI763097B TW I763097 B TWI763097 B TW I763097B TW 109137187 A TW109137187 A TW 109137187A TW 109137187 A TW109137187 A TW 109137187A TW I763097 B TWI763097 B TW I763097B
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Taiwan
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gate
dielectric
gate dielectric
forming
protruding fin
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TW109137187A
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TW202131389A (zh
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林士堯
高魁佑
陳振平
林志翰
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台灣積體電路製造股份有限公司
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Abstract

一種半導體結構的形成方法，包括在凸出鰭片的第一部分和第二部分上同時形成第一虛置閘極堆疊和第二虛置閘極堆疊，同時移除第一虛置閘極堆疊的第一閘極電極和第二虛置閘極堆疊的第二閘極電極以分別形成第一溝槽和第二溝槽，形成蝕刻遮罩，其中蝕刻遮罩填入第一溝槽和第二溝槽，圖案化蝕刻遮罩以從第一溝槽移除蝕刻遮罩，移除第一虛置閘極堆疊的第一虛置閘極介電質，而蝕刻遮罩保護第二虛置閘極堆疊的第二虛置閘極介電質不被移除，以及在第一溝槽和第二溝槽中分別形成第一替換閘極堆疊和第二替換閘極堆疊。

Description

半導體結構及其形成方法
本發明實施例是關於半導體結構及其形成方法，特別是關於閘極結構。
金屬氧化物半導體(metal-oxide-semiconductor,MOS)元件為積體電路的基礎建構部件。金屬氧化物半導體元件可具有由多晶矽形成的閘極電極，其多晶矽以P型或N型雜質摻雜，使用如離子植入(ion implantation)或熱擴散(thermal diffusion)的摻雜製程摻雜。可調整閘極電極的功函數至矽的能帶邊緣(band-edge)。對於N型金屬氧化物半導體元件，可調整功函數至接近矽的導電能帶(conduction band)。對於P型金屬氧化物半導體元件，可調整功函數至接近矽的價能帶(valence band)。可藉由選擇適當雜質達到調整多晶矽閘極電極的功函數。
具有多晶矽閘極電極的金屬氧化物半導體元件展現出載子空乏效應(carrier depletion effect)，也被稱為多晶矽閘極空乏效應(poly depletion effect)。當施加的電場將載子從靠近閘極介電質的閘極區掃開，會發生多晶矽閘極空乏效應以形成空乏層。在N型摻雜的多晶矽層中，空乏層包括離子化的非 移動施子位置(donor site)，其中在P型摻雜的多晶矽層中，空乏層包括離子化的非移動受子位置(acceptor site)。空乏效應獲得有效閘極介電質厚度的增加，使得在半導體表面創造出反轉層(inversion layer)變得更困難。
多晶矽閘極空乏效應的問題可藉由形成金屬閘極電極來解決，其中在N型金屬氧化物半導體元件和P型金屬氧化物半導體元件中所使用的金屬閘極也可具有能帶邊緣功函數。相應地，所得的金屬閘極包括複數個膜層以符合N型金屬氧化物半導體元件和P型金屬氧化物半導體元件的需求。
金屬閘極的形成一般涉及形成虛置閘極堆疊、移除虛置閘極堆疊以形成溝槽、形成替換閘極堆疊包括金屬閘極延伸進入溝槽、以及進行化學機械拋光(chemical mechanical polish,CMP)製程以移除金屬閘極的多餘部分。
一種半導體結構的形成方法，包括：沉積堆疊的膜層於第一凸出鰭片(protruding fin)上；圖案化堆疊的膜層以形成：第一閘極堆疊，包括：第一閘極介電質，於第一凸出鰭片的中間部分上；以及第一閘極電極，於第一閘極介電質上；以及第二閘極堆疊，包括：第二閘極介電質，於第一凸出鰭片的尾端部分上；以及第二閘極電極，於第二閘極介電質上；移除第一閘極電極和第二閘極電極以分別露出第一閘極介電質和第二閘極介電質；移除第一閘極介電質，其中在移除第一閘極介電質之後，保留第二閘極介電質；形成替換閘極介電質於第一凸出鰭片的中間部分上；以及形成第一替換閘極電極和第二替換閘極電極分別於替換閘極介電質和第二閘極介電質上。
一種半導體結構的形成方法，包括：同時形成第一虛置閘極堆疊 和第二虛置閘極堆疊於凸出鰭片的第一部分和第二部分上；同時移除第一虛置閘極堆疊的第一閘極電極和第二虛置閘極堆疊的第二閘極電極以分別形成第一溝槽和第二溝槽；形成蝕刻遮罩，其中蝕刻遮罩填入第一溝槽和第二溝槽；圖案化蝕刻遮罩以從第一溝槽移除蝕刻遮罩；移除第一虛置閘極堆疊的第一虛置閘極介電質，其中蝕刻遮罩保護第二虛置閘極堆疊的第二虛置閘極介電質不被移除；以及形成第一替換閘極堆疊和第二替換閘極堆疊分別於第一溝槽和第二溝槽中。
一種半導體結構，包括：隔離區，延伸進入半導體基底中；凸出鰭片，於隔離區的部分之間，其中凸出鰭片凸出高於隔離區；第一閘極堆疊，包括：第一閘極介電質，於凸出鰭片的第一部分的第一側壁和第一頂面上，其中第一閘極介電質具有第一厚度；以及第一閘極電極，於第一閘極介電質上；以及第二閘極堆疊，包括：第二閘極介電質，於凸出鰭片的第二部分的第二側壁和第二頂面上，其中凸出鰭片終止於第二閘極堆疊的正下方，且第二閘極介電質具有第二厚度，第二厚度大於第一厚度；以及第二閘極電極，於第二閘極介電質上。
10:晶圓
20:(半導體)基底
22:井區
22B-22B:剖面
24:(淺溝槽)隔離區
24A:頂面
26:半導體條
28:墊氧化物層
30:硬遮罩層
36:(凸出)鰭片
36A:中間(鰭片)部分
36B:尾端(鰭片)部分
36’:(凸出)鰭片
36A’:中間(鰭片)部分
36B’:尾端(鰭片)部分
38:虛置閘極堆疊
38A:虛置閘極堆疊
38B:虛置閘極堆疊
40:虛置閘極介電質(介電層)
42:虛置閘極電極
44:硬遮罩層
46:閘極間隔物
46A,46B,46C:閘極間隔物
50:凹槽
54:磊晶區(源極/汲極區)
56:空洞(氣隙)
58:接觸蝕刻停止層
60:層間介電質
62:溝槽
64:蝕刻遮罩
66:介電層
67A,67B,67C:高介電常數介電層
68A,68B,68C:閘極介電質
70A,70B,70C:閘極電極
72A,72B,72C:(替換)閘極堆疊
74A,74B,74C:鰭式場效電晶體
76:堆疊膜層
78:通道層
80:犧牲膜層
82:內間隔物
86:全繞式閘極電晶體
100C:元件區
100C-100C:剖面
100FE:元件區
100FE-100FE:剖面
100IO:元件區
110:源極/汲極矽化物區
112:源極/汲極接觸插塞
114:閘極接觸插塞
116:硬遮罩
136:凸出鰭片
400:製程流程
402,404,406,408,410,412,414,416,418,420,422,424,426,428:製程
GL1:閘極長度
GL2:閘極長度
LE:長度
T1:厚度
T2:厚度
T3:厚度
T4:厚度
W1:寬度
以下將配合所附圖式詳述本揭露之各面向。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製。事實上，可任意地放大或縮小各種元件的尺寸，以清楚地表現出本揭露實施例的特徵。
第1~3、4A、4B、5A、5B、6A、6B、7A、7B、8A、8B、8C、和9~13圖是根據一些實施例，繪示出形成鰭式場效電晶體(fin field-effect transistor, FinFET)和鰭片尾端(fin-end)閘極結構的中間階段的透視圖、俯視圖、和剖面示意圖。
第14~21、22A、和22B圖是根據一些實施例，繪示出形成全繞式閘極(gate all-around,GAA)電晶體和鰭片尾端閘極結構的中間階段的透視圖、俯視圖、和剖面示意圖。
第23圖是根據一些實施例，繪示出形成鰭式場效電晶體和鰭片尾端閘極結構的製程流程圖。
以下揭露提供了許多的實施例或範例，用於實施本發明的不同部件。組件和配置的具體範例描述如下，以簡化本揭露實施例。當然，這些僅僅是範例，並非用以限定本揭露實施例。舉例來說，敘述中提及第一部件形成於第二部件之上，可包括形成第一和第二部件直接接觸的實施例，也可包括額外的部件形成於第一和第二部件之間，使得第一和第二部件不直接接觸的實施例。另外，本揭露可在各種範例中重複元件符號及/或字母。這樣重複是為了簡化和清楚的目的，其本身並非主導所討論各種實施例及/或配置之間的關係。
再者，此處可使用空間上相關的用語，如「在...之下」、「下方的」、「低於」、「在...上方」、「上方的」和類似用語可用於此，以便描述如圖所示一元件或部件和其他元件或部件之間的關係。這些空間用語企圖包括使用或操作中的裝置的不同方位，以及圖式所述的方位。當裝置被轉至其他方位(旋轉90°或其他方位)，則在此所使用的空間相對描述可同樣依旋轉後的方位來解讀。
根據一些實施例，提供鰭式場效電晶體(fin field-effect transistor,FinFET)、全繞式閘極(gate all-around,GAA)電晶體、和鰭片尾端(fin-end)閘極結構，以及所得結構的形成方法。根據一些實施例，繪示出形成電晶體的中間階段。討論一些實施例的變化。透過各種示意圖和例示性的實施例，使用類似參考符號以指定類似元件。如碳網管(carbon-network-tube)、多橋通道場效電晶體(multi bridge channel field-effect transistor,MBCFET)、奈米片場效電晶體(nanosheet field-effect transistor,NSFET)、奈米結構電晶體(nanostructure transistor)、互補式場效電晶體(complementary field-effect transistor,CFET)、直立式場效電晶體(vertical field-effect transistor,VFET)等電晶體的形成，以及其對應的鰭片尾端閘極結構也可適用於本揭露的實施例。此處所討論的實施例提供範例以製作或使用本揭露的標的，而在所屬技術領域中具有通常知識者可將輕易地理解於所思及的不同實施例範圍內，可具有各種修飾。儘管可討論方法實施例在特定的順序中進行，可進行其他方法實施例於任何符合邏輯的順序。
根據本揭露的一些實施例，在凸出鰭片的中間部分和尾端部分上分別形成第一虛置閘極堆疊和第二虛置閘極堆疊，其可包括虛置閘極電極。凸出鰭片可為凸出半導體鰭片或可包括堆疊膜層(例如，包括半導體層和犧牲層)。移除第一和第二虛置閘極堆疊的第一和第二虛置閘極電極，以分別露出下方的第一虛置閘極介電質和第二虛置閘極介電質。移除覆蓋凸出鰭片的中間部分的第一虛置閘極介電質，而保留覆蓋凸出鰭片的尾端部分的第二虛置閘極介電質不被移除。藉由保留第二虛置閘極介電質不被移除，保護下方的凸出鰭片的尾端部分不被後續製程損害，且保護了鄰近凸出鰭片的尾端部分最接近的源極/汲極區。
第1~3、4A、4B、5A、5B、6A、6B、7A、7B、8A、8B、8C、和9~13圖是根據本揭露的一些實施例，繪示出形成鰭式場效電晶體和鰭片尾端閘極結構的中間階段的剖面示意圖和透視圖。這些圖式中所示製程也示意地反映在第23圖中的製程流程400中。
在第1圖中，提供基底20。基底20可為半導體基底，如主體(bulk)半導體基底、絕緣層上半導體(semiconductor-on-insulator,SOI)基底、或其他類似材料，其可為摻雜(例如以P型或N型摻質)或未摻雜。半導體基底20可為晶圓10的一部分。總體而言，絕緣層上半導體基底為在絕緣層上形成的半導體材料膜層。絕緣層可為，舉例來說，埋入式氧化物(buried oxide,BOX)層、矽氧化物層、或其他類似材料。在基底上提供絕緣層，通常為矽或玻璃基底。也可使用其他基底(如多膜層或梯度基底)。在一些實施例中，半導體基底20的半導體材料可包括矽、鍺、化合物半導體(包括有機矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦)、合金半導體(包括矽鍺、砷磷化鎵、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、及/或砷磷化鎵銦)、或其組合。
進一步參考第1圖，在基底20中形成井區22。個別製程繪示於第23圖的製程流程400中的製程402。根據本揭露的一些實施例，井區22為透過植入P型雜質於基底20中所形成的P型井區，其雜質可為硼、銦、或其他類似材料。根據本揭露的其他實施例，井區22為透過植入N型雜質於基底20中所形成的N型井區，其雜質可為磷、砷、銻、或其他類似材料。所得的井區22可延伸至基底20的頂面。N型或P型雜質濃度可等於或小於1018cm-3，如介於約1017cm-3和1018cm-3的範圍之間。
參考第2圖，形成隔離區24以從基底20的頂面延伸至基底20中。 以下替代地將隔離區24稱為淺溝槽隔離(shallow trench isolation,STI)區。個別製程繪示於第23圖的製程流程400中的製程404。基底20介於鄰近淺溝槽隔離區24之間的部分被稱為半導體條26。為了形成淺溝槽隔離區24，在半導體基底20上形成並接著圖案化墊氧化物層28和硬遮罩層30。墊氧化物層28可為以氧化矽所形成的薄膜。根據本揭露的一些實施例，在熱氧化製程(thermal oxidation process)中形成墊氧化物層28，其中半導體基底20的頂面層被氧化。墊氧化物層28作為半導體基底20和硬遮罩層30之間的黏著層。墊氧化物層28也可作為蝕刻硬遮罩層30的蝕刻停止層。根據本揭露的一些實施例，使用例如低壓化學氣相沉積(low pressure chemical vapor deposition,LPCVD)，以氮化矽形成硬遮罩層30。根據本揭露的其他實施例，藉由矽的熱氮化或電漿輔助化學氣相沉積(plasma enhanced chemical vapor deposition,PECVD)形成硬遮罩層30。在硬遮罩層30上形成並接著圖案化光阻(未繪示)。然後，使用圖案化後的光阻作為蝕刻遮罩圖案化硬遮罩層30以形成硬遮罩30，如第2圖所示。
接著，使用圖案化後的硬遮罩層30作為蝕刻遮罩以蝕刻墊氧化物層28和基底20，接著在基底20中所得的溝槽內填入介電材料。進行平坦化製程(如化學機械拋光(chemical mechanical polish,CMP)製程或機械研磨製程)以移除介電材料的多餘部分，而介電材料的剩餘部分為淺溝槽隔離區24。淺溝槽隔離區24可包括襯物介電質(未繪示)，其可為透過基底20的表面層的熱氧化所形成的熱氧化物。襯物介電質也可為使用例如原子層沉積(atomic layer deposition,ALD)、高密度電漿化學氣相沉積(high-density plasma chemical vapor deposition,HDPCVD)、化學氣相沉積(chemical vapor deposition,CVD)、或類似方法形成沉積的氧化矽層、氮化矽層、或其他類似材料。淺溝槽隔離區24 也包括在襯物介電質上的介電材料，其中可使用流動性化學氣相沉積(flowable chemical vapor deposition,FCVD)、旋轉塗佈、或其他類似方法形成介電材料。根據一些實施例，在襯物介電質上的介電材料可包括氧化矽。
硬遮罩層30的頂面和淺溝槽隔離區24的頂面可實質上彼此齊平。半導體條26介於鄰近的淺溝槽隔離區24之間。根據本揭露的一些實施例，半導體條26為原本基底20的部分，而因此半導體條26的材料與基底20的材料相同。根據本揭露的替代實施例，半導體條26為藉由蝕刻基底20介於淺溝槽隔離區24之間的部分以形成凹槽，並在凹槽中進行磊晶以再成長另一半導體材料所形成的替換條。相應地，形成半導體條26的材料與基底20的材料不同。根據一些實施例，以矽鍺、有機矽、或III-V族化合物半導體材料形成半導體條26。
參考第3圖，凹蝕淺溝槽隔離區24，使得半導體條26的頂部凸出高於淺溝槽隔離區24剩餘部分的頂面24A，以形成凸出鰭片36。個別製程繪示於第23圖的製程流程400中的製程406。可使用乾蝕刻製程進行蝕刻，其中使用例如NF3和NH3作為蝕刻氣體。在蝕刻製程期間，可產生電漿。也可包括氬氣。根據本揭露的替代實施例，使用濕蝕刻製程進行淺溝槽隔離區24的凹蝕。蝕刻化學品可包括例如HF。
在上述實施例中，可藉由任何合適方法圖案化鰭片。舉例來說，可使用一或多個光微影製程(包括雙圖案化或多圖案化製程)圖案化鰭片。總體而言，雙圖案化或多圖案化製程結合光微影和自我對準製程，允許所創造的圖案具有比使用單一或直接光微影製程所獲得的節距更小的節距。舉例來說，在一實施例中，在基底上形成並使用光微影製程圖案化犧牲層。使用自我對準製程沿著圖案化後的犧牲層形成間隔物。然後，移除犧牲層，而可使用剩餘的 間隔物，或心軸(mandrel)，以圖案化鰭片。
參考第4A圖，形成虛置閘極堆疊38以延伸於(凸出)鰭片36的頂面和側壁上。個別製程繪示於第23圖的製程流程400中的製程408。形成製程可包括沉積並圖案化堆疊膜層以形成虛置閘極堆疊38。虛置閘極堆疊38可包括虛置閘極介電質40和於虛置閘極介電質40上的虛置閘極電極42。可使用例如多晶矽形成虛置閘極電極42，而也可使用其他材料。每個虛置閘極堆疊38也可包括在虛置閘極電極42上的一個(或複數個)硬遮罩層44。可以氮化矽(SiN)、氧氮化矽(SiON)、氧碳氮化矽(SiOCN)、氧碳化矽(SiOC)、二氧化矽(SiO2)、有機矽(SiC)、或其他類似材料、或其多膜層形成硬遮罩層44。虛置閘極堆疊38可跨越單一或複數個凸出鰭片36及/或淺溝槽隔離區24。虛置閘極堆疊38也具有長度方向(lengthwise direction)，其垂直於凸出鰭片36的長度方向。
接著，在虛置閘極堆疊38的側壁上形成閘極間隔物46。個別製程亦繪示於第23圖的製程流程400中的製程408。根據本揭露的一些實施例，以介電材料(如氮化矽、碳氮化矽、或其他類似材料)形成閘極間隔物46，其可具有單層結構或包括複數個介電層的多層結構。
第4B圖繪示晶圓10的平面示意圖，其包括凸出鰭片36、虛置閘極堆疊38、以及閘極間隔物46。一些虛置閘極堆疊38(以38A表示)係在凸出鰭片36的中間部分36A上，而另一些虛置閘極堆疊38(以38B表示)係在凸出鰭片36的尾端部分36B上。凸出鰭片36被淺溝槽隔離區24所圍繞。每個虛置閘極堆疊38B可包括第一部分(如所繪示的左邊部分)覆蓋凸出鰭片36的尾端部分，以及第二部分(如所繪示的右邊部分)延伸於凸出鰭片36之外。根據一些實施例，在虛置閘極堆疊38B中的虛置閘極電極42被稱為OD邊緣上多晶矽(polysilicon on OD edge,PODE)，其中「OD」用語代表如凸出鰭片36的主動區。類似地，在凸出鰭片36的左端(未繪示)上，也可有虛置閘極堆疊38B(未繪示)覆蓋虛置閘極堆疊38B的左邊邊緣部分。
然後，進行蝕刻製程以蝕刻凸出鰭片36未被虛置閘極堆疊38和閘極間隔物46覆蓋的部分，所得的結構繪示於第5A圖中。個別製程繪示於第23圖的製程流程400中的製程410。凹蝕可為異向性(anisotropic)，且因此保護鰭片36於虛置閘極堆疊38和閘極間隔物46正下方的部分不被蝕刻。根據一些實施例，凹蝕後的半導體條26的頂面可低於淺溝槽隔離區24的頂面24A。相應地形成凹槽50。凹槽50包括位在虛置閘極堆疊38兩側上的部分，和介於凸出鰭片36剩餘部分之間的部分。
第5B圖繪示在形成凹槽50之後晶圓10的平面示意圖，其中所繪示的部分對應如第4B圖所示的尾端部分，且對應第5A圖所示的結構。
接著，藉由在凹槽50中選擇性地成長(透過磊晶)半導體材料以形成磊晶區(源極/汲極區)54，所得的結構於第6A圖中。個別製程繪示於第23圖的製程流程400中的製程412。取決於所得的鰭式場效電晶體為P型鰭式場效電晶體或N型鰭式場效電晶體，可在磊晶的進行時原位(in-situ)摻雜P型或N型雜質。舉例來說，當所得的鰭式場效電晶體為P型鰭式場效電晶體時，可成長硼化矽鍺(silicon germanium boron,SiGeB)、硼化矽(silicon boron,SiB)、或其他類似材料。相反地，當所得的鰭式場效電晶體為N型鰭式場效電晶體時，可成長磷化矽(silicon phosphorous,SiP)、碳磷化矽(silicon carbon phosphorous,SiCP)、或其他類似材料。根據本揭露的替代實施例，磊晶區54包括III-V族化合物半導體，如砷化鎵(GaAs)、磷化銦(InP)、氮化鎵(GaN)、砷化銦鎵(InGaAs)、 砷化銦鋁(InAlAs)、銻化鎵(GaSb)、銻化鋁(AlSb)、砷化鋁(AlAs)、磷化鋁(AIP)、磷化鎵(GaP)、其組合、或其多膜層。在以磊晶區54填入凹槽50後，磊晶區54的進一步磊晶成長造成磊晶區54水平地擴展，且形成刻面(facet)。磊晶區54的進一步成長也可造成相鄰的磊晶區54彼此合併。可產生空洞(氣隙)56。根據本揭露的一些實施例，當合併後的磊晶區54的頂面仍為波浪狀時，或當合併後的磊晶區54的頂面呈現平坦時，可完成磊晶區54的形成。
在磊晶製程後，可進一步以P型或N型雜質植入磊晶區54，以形成源極和汲極區，其也使用參考符號54表示。根據本揭露的替代實施例，當在磊晶期間以P型或N型雜質原位摻雜磊晶區54時，則跳過植入步驟。
第6B圖繪示部分晶圓10的平面示意圖，其中所繪示的部分對應第6A圖所示的結構。
第7A圖是在接觸蝕刻停止層(contact etch stop layer,CESL)58和層間介電質(inter-layer dielectric,ILD)60的形成後，繪示出結構的透視圖。個別製程繪示於第23圖的製程流程400中的製程414。可以氧化矽、氮化矽、碳氮化矽、或其他類似材料，並可使用化學氣相沉積、原子層沉積、或其他類似方法，形成接觸蝕刻停止層58。層間介電質60可包括使用例如流動性化學氣相沉積、旋轉塗佈、化學氣相沉積、或其他沉積方法所形成的介電材料。層間介電質60可以含氧介電材料形成，其可為矽氧基材料，如氧化矽、磷矽酸玻璃(phospho-silicate glass,PSG)、硼矽酸玻璃(boro-silicate glass,BSG)、硼摻雜磷矽酸玻璃(boron-doped phospho-silicate glass,BPSG)、或其他類似材料。可進行平坦化製程(如化學機械拋光製程或機械研磨製程)以使層間介電質60、虛置閘極堆疊38、和閘極間隔物46的頂面彼此齊平。
第7B圖繪示三個元件區100C、100FE、和100IO的剖面示意圖。元件區100C可為針對形成第一鰭式場效電晶體的核心(邏輯)元件區，其可為核心(邏輯)鰭式場效電晶體。在元件區100C所示的剖面示意圖可由參考在第6B圖中的100C-100C剖面獲得(除了接觸蝕刻停止層58和層間介電質60也繪示在第7B圖中)。元件區100FE可為針對形成鰭片尾端閘極結構的元件區。在元件區100FE中所示的剖面示意圖可由參考在第6B圖中的100FE-100FE剖面獲得(除了加上接觸蝕刻停止層58和層間介電質60)。元件區100IO可為針對形成第二鰭式場效電晶體的元件區，其可為輸入/輸出(input/output,IO)鰭式場效電晶體。應理解的是，在元件區100C和100IO中的電晶體可具有不同的閘極長度(gate length)。舉例來說，根據一些實施例，閘極長度GL1可小於閘極長度GL2。在元件區100IO中所示結構的剖面示意圖可從另一個凸出鰭片136獲得(第8C圖，類似鰭片36)，凸出鰭片136與所繪示的凸出鰭片36分開，而其剖面示意圖是從凸出鰭片136的中間部分所獲得。
應理解的是，儘管使用核心元件區和輸入/輸出元件區作為範例，其他元件區也是可思及的。在第7B圖中，可以共同的製程形成在元件區100C、100FE、和100IO中的閘極介電質40，其因而具有相同厚度。在後續的製程中移除在元件區100C中的閘極介電質40，其因此為虛置閘極介電質。在元件區100IO中的閘極介電質40可作為輸入/輸出鰭式場效電晶體的功能閘極介電質，其因此為主動閘極介電質，而非虛置閘極介電質。在第7B圖中，繪示了淺溝槽隔離區24，而凸出半導體鰭片36和136凸出高於個別相鄰淺溝槽隔離區24的頂面24A。
在形成第7A和7B圖中所示的結構後，以替換閘極替換虛置閘極堆疊38，形成製程如第8A、8B、8C、和9~13圖所示。為了形成替換閘極，首先 移除如第7A和7B圖中所示的硬遮罩層44和虛置閘極電極42，而形成如第8A、8B、和8C圖中所示的溝槽62。第8A圖繪示在移除硬遮罩層44和虛置閘極電極42之後的結構的透視圖。虛置閘極介電質40(第8C圖)則因而露出。個別製程繪示於第23圖的製程流程400中的製程416。第8B圖繪示晶圓10的平面示意圖。
如第8B圖中所示，透過溝槽62露出閘極介電質40。在此階段，閘極介電質40覆蓋凸出鰭片36。在鰭片尾端部分36B上的每個閘極介電質40包括三個部分，其中兩個部分在兩側側壁上並在對應的凸出鰭片尾端部分36B的長度方向(X方向)延伸，而第三部分在對應的鰭片尾端部分36B的寬度方向(widthwise direction)(Y方向)延伸。
第8C圖繪示元件區100C、100FE、和100IO在移除虛置閘極電極之後的剖面示意圖。如第8C圖所示，在元件區100FE中，露出在鰭片尾端的閘極介電質40，而在所繪示的剖面中，閘極介電質40也延伸於凸出鰭片尾端部分36B的側壁上。根據一些實施例，可以共同的製程由元件區100C、100FE、和100IO進行移除硬遮罩層44，且以共同的製程從元件區100C、100FE、和100IO進行移除虛置閘極電極42。
參考第9圖，形成並圖案化蝕刻遮罩64，其可為光阻。圖案化後的蝕刻遮罩64保留於元件區100FE和100IO中，而從元件區100C移除。個別製程繪示於第23圖的製程流程400中的製程418。以蝕刻遮罩64填入在元件區100FE和100IO中的溝槽62。
接著，參考第10圖，進行蝕刻製程以移除在元件區100C中的虛置閘極介電質40。個別製程繪示於第23圖的製程流程400中的製程420。根據一些實施例，蝕刻為異向性。根據替代實施例，蝕刻為等向性(isotropic)。根據一 些實施例，其虛置閘極介電質40係以氧化矽形成或包括氧化矽，可使用NF3和NH3氣體的混合物或HF和NH3氣體的混合物。根據其他實施例，其使用濕蝕刻製程，可使用HF溶液或類似蝕刻劑。當使用異向性蝕刻時，虛置閘極介電質40可具有一些殘留部分剩下，並與閘極間隔物46交疊。在其他實施例中，從元件區100C的溝槽62中完整移除虛置閘極介電質40。在蝕刻製程期間，在元件區100FE和100IO中的閘極介電質40受到保護不被蝕刻。
在蝕刻製程後，移除硬遮罩64以再次露出在元件區100FE和100IO中的閘極介電質40。所得的結構繪示於第11圖中。個別製程繪示於第23圖的製程流程400中的製程422。由於在元件區100C中的閘極間隔物46也暴露於用在元件區100C中蝕刻虛置閘極介電質40的蝕刻劑，可藉由蝕刻劑薄化在元件區100C中的閘極間隔物46(標示為46A)，並比分別在元件區100FE和100IO中的閘極間隔物46B和46C更薄。根據一些實施例，厚度差(T2-T1)可介於約1nm和2nm之間的範圍，其中厚度T1為閘極間隔物46A的厚度，而厚度T2為閘極間隔物46B和46C的厚度。(T2-T1)和厚度T2的比例可介於約0.1和0.3之間的範圍。
接著，參考第12圖，形成閘極堆疊72A、72B、和72C，其分別包括閘極介電質68A、68B、和68C，以及閘極電極70A、70B、和70C。因而形成鰭式場效電晶體74A和鰭式場效電晶體74C，其可分別為核心鰭式場效電晶體和輸入/輸出鰭式場效電晶體。閘極介電質68A可包括介電層66和高介電常數(high-k)介電層67A。在凸出鰭片部分36A的露出表面上形成介電層66，並可以氧化矽形成或包括氧化矽。個別製程繪示於第23圖的製程流程400中的製程424。根據一些實施例，介電層66為介面層(interfacial layer,IL)，其可包括原生氧化物層，如第11圖所示。基於將半導體材料暴露於濕氣和氧，在凸出鰭片 36的露出表面上形成原生氧化物層。根據一些實施例，除了原生氧化物，也可透過化學氧化製程或熱氧化製程形成介電層66。介電層66也可以其他介電材料形成或包括其他介電材料，如氮化矽、氧氮化矽、氧碳氮化矽、氧碳化矽、二氧化矽、有機矽、或其他類似材料。在元件區100FE和100IO中，保留原本的介電層40。
在形成介電層66之後，形成高介電常數介電層67A、67B、和67C。個別製程繪示於第23圖的製程流程400中的製程426。可以高介電常數介電材料(如氧化鉿、氧化鑭、氧化鋁、氧化鋯、或其他類似材料，其組合，或其多膜層)形成高介電常數介電層67A、67B、和67C的每一個。根據本揭露的一些實施例，使用原子層沉積、化學氣相沉積、或其他類似方法形成高介電常數介電層67A、67B、和67C。高介電常數介電層67A、67B、和67C可為相同介電材料的部分，其使用相同材料同時地形成並具有相同的厚度，或以不同材料及/或不同厚度分開地形成。介電層(介面層)66和上方的高介電常數介電層67A一起被稱為閘極介電質68A。在元件區100FE中的介電層40和上方的高介電常數介電層67B一起被稱為閘極介電質68B。在元件區100IO中的介電層40和上方的高介電常數介電層67C一起被稱為閘極介電質68C。可在相同沉積製程中形成高介電常數介電層67A、67B、和67C，且可具有相同厚度。
接著形成閘極電極70A、70B、和70C。個別製程繪示於第23圖的製程流程400中的製程428。根據本揭露的一些實施例，閘極電極70A、70B、和70C的每一個可具有複合結構，包括複數個膜層。根據一些實施例，同時形成閘極電極70A、70B、和70C，並享有共同形成製程，因而具有相同材料膜層和相同厚度。根據替代實施例，可在分開的製程中形成閘極電極70A、70B、和70C， 且可具有相同或不同的結構，而具有相同或不同的材料，以及相同或不同的厚度。
根據一些實施例，閘極電極70A、70B、和70C的每一個可具有擴散阻障層(diffusion barrier layer)、於擴散阻障層上的功函數層(work function layer)、於功函數層上的蓋層(capping layer)、以及於蓋層上的填充金屬區。擴散阻障層可以氮化鈦(TiN)、矽氮化鈦(TiSiN)、或其他類似材料形成，或包括上述材料。功函數層所形成的或所包括的材料的選擇取決於形成在元件區100C和元件區100IO的個別鰭式場效電晶體為N型鰭式場效電晶體或P型鰭式場效電晶體。舉例來說，當鰭式場效電晶體為N型鰭式場效電晶體時，所對應的功函數層可包括鋁基膜層(例如以鋁化鈦(TiAl)、鋁氮化鈦(TiAlN)、鋁碳化鈦(TiAlC)、鋁氮化鉭(TaAlN)、或鋁碳化鉭(TaAlC)，或包括上述材料)。當鰭式場效電晶體為P型鰭式場效電晶體時，所對應的功函數層可包括氮化鈦層和氮化鉭層(TaN)。蓋層(也被稱為阻擋層)可以氮化鈦、氮化鉭、或其他類似材料形成，或包括上述材料。可使用原子層沉積、化學氣相沉積、或其他類似方法沉積擴散阻障層、功函數層、和蓋層。填充金屬區可以鎢、鈷、或其他類似材料形成，或包括上述材料。
在第12圖中，在與元件區100FE和100IO中的介電層40不同的製程中形成介電層66。由於在元件區100IO中的介電層40可用於輸入/輸出元件，其介電層40相對厚，舉例來說，具有介於約10Å和60Å之間的厚度T4。還有，在元件區100FE和100IO中的介電層40的厚度可彼此相等或彼此大抵相等，舉例來說，具有約小於20%的差距。另一方面，可針對核心元件形成介電層66，其厚度T3小於厚度T4。舉例來說，厚度T3可介於約5Å和20Å之間的範圍。厚度T4和厚度 T3的比例係關於在元件區100C和100IO中的元件的性能與可靠度需求。舉例來說，在元件區100C中的元件的有效氧化物厚度(Effective Oxide Thickness,EOT)很低，以達到很快的速度，厚度T3很小，而較大的厚度T4可改善輸入/輸出元件的元件可靠度。相應地，根據一些實施例，厚度T4和厚度T3的比例可介於約4.0和6.0之間的範圍。
第13圖繪示鰭式場效電晶體74A或鰭式場效電晶體74C的透視圖。繪示了閘極接觸插塞114、源極/汲極矽化物區110、源極/汲極接觸插塞112、和硬遮罩116。
在上述形成製程中，舉例來說，如在第10和11圖中所示的製程，當從元件區100C移除介電層40時，並未從鰭片尾端元件區100FE移除介電層40。由於鰭片尾端部分36B的長度LE(第12圖)隨著積體電路的進步而變得越來越小，鰭片尾端部分36B在例如後續的清洗製程中可能會受損。若鰭片尾端部分36B受損，鄰近的源極/汲極區54可能會受損。相應地，將介電層40保留於元件區100FE具有保護下方的凸出鰭片36的尾端部分36B的功能，並保護鄰近的源極/汲極區。
本揭露的實施例可套用在其他凸出結構，且可用於形成其他類型的電晶體，如奈米片電晶體(nano-sheet transistor)、奈米線電晶體(nano-wire transistor)、及/或全繞式閘極電晶體，以及其對應的鰭片尾端閘極結構。第14~21、22A、和22B圖是根據本揭露的一些實施例，繪示出形成全繞式閘極電晶體(其也可為奈米片或奈米線電晶體)和其對應的鰭片尾端閘極結構的中間階段的透視圖、俯視圖、和剖面示意圖。除非另外指明，這些實施例中的組件的材料和形成製程基本上與類似組件相同，其以在前述圖式中所示的前述實施例中的類似元件符號所表示。關於在前述圖式中所示的組件的形成製程和材料的 細節可因而由前述實施例的討論中得知。
參考第14圖，形成凸出鰭片36’，並在凸出鰭片36’的側壁和頂面上形成閘極堆疊38和閘極間隔物46。凸出鰭片36’可包括堆疊膜層76，其包括通道層78(細節請參照第15圖)和犧牲膜層80。通道層78的總數和犧牲膜層80的總數可介於(並包括)例如1和10之間的範圍中。應理解的是，在所示的範例實施例中，儘管犧牲膜層80被繪示為堆疊膜層76的頂層，根據其他實施例，通道層78可為堆疊膜層76的頂層。通道層78和犧牲膜層80的材料彼此不同。根據一些實施例，通道層78係以矽、矽鍺、或其他類似材料形成，或包括上述材料。犧牲膜層80係以矽鍺、磷化矽、氧碳氮化矽、有機矽、或其他類似材料形成，或包括上述材料。每個通道層78和每個犧牲膜層80的厚度可介於約30Å和1000Å之間的範圍中。堆疊膜層76交疊半導體條26。在第14圖中所示的結構的形成製程與第1~3和4A圖中所示的製程類似，除了在進行第1~3圖所示的製程之前，透過例如磊晶預先形成堆疊膜層76。
第15圖繪示了第14圖中所示的結構的俯視圖。此俯視圖也與第4B圖中所示的俯視圖類似，除了在第14圖中的凸出鰭片36’已取代了在第4B圖中的凸出鰭片36。
後續地，進行在第5A、5B、6A、6B、7A、和7B圖中所示的製程以形成源極/汲極區54、接觸蝕刻停止層58、和層間介電質60。所得的結構繪示於第16圖中，其包括分別從相同凸出鰭片36’的中間部分和尾端部分所獲得的剖面示意圖。第16圖繪示了在元件區100C和100FE中的結構的剖面示意圖，其剖面示意圖分別從參考剖面100C-100C和100FE-100FE所獲得，如第15圖所示。在第16圖中，形成內間隔物82。在內間隔物82的範例形成製程中，在第5A圖中所示 的鰭片蝕刻製程之後，露出犧牲膜層80的側壁。進行氧化製程以氧化犧牲膜層80的尾端部分，使得氧化物區形成作為內間隔物82。內間隔物82的材料可取決於犧牲膜層80的材料，且可包括矽鍺、磷化矽、氧碳氮化矽、有機矽、或其他類似材料的氧化物。內間隔物82的寬度W1可介於約3Å和500Å之間的範圍中。
接著，移除硬遮罩44和虛置閘極電極42以形成溝槽62，而所得的結構繪示於第17圖中。在元件區100C和100FE中同時露出閘極介電質40。參考第18圖，形成圖案化後的蝕刻遮罩64以填入在元件區100FE中的溝槽62，而從元件區100C移除蝕刻遮罩64。
接著，從元件區100C移除虛置閘極介電質40，而在元件區100FE中的虛置閘極介電質40受到保護不被移除。所得的結構繪示於第19圖中。然後，移除蝕刻遮罩64，而所得的結構繪示於第20圖中。在後續的製程中，從中間鰭片部分36A’移除犧牲膜層80，而所得的結構繪示於第21圖中。根據一些實施例，內間隔物82未被移除，而將保留在最終的全繞式閘極電晶體中。當移除犧牲膜層80時，內間隔物82可保護源極/汲極區54不受損，且可隔離後續形成的閘極堆疊不會與源極/汲極區54短路。移除犧牲膜層80的結果是，在通道層78之間形成間隔物。
在犧牲膜層80的移除過程中，在溝槽62中剩餘的介電層40保護對應的凸出鰭片36’的鰭片尾端部分36B’不被移除。相應地，在最終的結構中，凸出鰭片36’的鰭片尾端部分36B’維持不被移除。再者，當從中間鰭片部分36A’移除犧牲膜層80時，在尾端部分36B’的犧牲膜層80受到保護不被移除，且將保留在最終的結構中。
在後續的製程中，形成替換閘極堆疊72A和72B。因而形成全繞式 閘極電晶體86。在形成的期間，首先形成介電層66以環繞通道層78，其可包括原生氧化物，以及可能透過通道層78的表面部分的化學氧化或熱氧化所形成的氧化物層。閘極堆疊72A包括介電層66、高介電常數介電層67A、和閘極電極70A。高介電常數介電層67A和閘極電極70A可延伸進入介於通道層78之間的空間。鰭片尾端閘極堆疊72B包括介電層40、高介電常數介電層67B、和閘極電極70B。
第22B圖繪示了從第22A圖中所示的參考剖面22B-22B所獲得的參考剖面，而其參考剖面繪示了全繞式閘極電晶體86的通道和閘極部分。還有，也繪示了在元件區100IO中的結構。
本揭露的實施例具有一些優勢特徵。當從一些元件區(如核心元件區)移除虛置閘極介電質時，形成在凸出鰭片的鰭片尾端部分上的介電層受到保護不被移除。凸出鰭片的鰭片尾端部分上剩餘的介電層保護凸出鰭片的尾端部分不被損害，且凸出鰭片的尾端部分可進一步保護鄰近的源極/汲極區。
根據本揭露的一些實施例，一種半導體結構的形成方法，包括：於第一凸出鰭片上沉積堆疊的膜層；圖案化堆疊的膜層以形成：第一閘極堆疊，包括：於第一凸出鰭片的中間部分上的第一閘極介電質；以及於第一閘極介電質上的第一閘極電極；以及第二閘極堆疊，包括：於第一凸出鰭片的尾端部分上的第二閘極介電質；以及於第二閘極介電質上的第二閘極電極；移除第一閘極電極和第二閘極電極以分別露出第一閘極介電質和第二閘極介電質；移除第一閘極介電質，其中在移除第一閘極介電質之後，保留第二閘極介電質；於第一凸出鰭片的中間部分上形成替換閘極介電質；以及分別於替換閘極介電質和第二閘極介電質上形成第一替換閘極電極和第二替換閘極電極。在一實施例 中，替換閘極介電質形成具有比第一閘極介電質更小的厚度。在一實施例中，移除第一閘極介電質包括形成蝕刻遮罩以覆蓋第二閘極介電質，其中當移除第一閘極介電質時，蝕刻遮罩保護第二閘極介電質；以及移除蝕刻遮罩。在一實施例中，半導體結構的形成方法更包括，當形成第一閘極堆疊時，形成第三閘極堆疊，包括於第二凸出鰭片的額外中間部分上的第三閘極介電質；以及於第三閘極介電質上的第三閘極電極；移除第三閘極電極以露出第三閘極介電質，其中在移除第一閘極介電質之後，保留第三閘極介電質；以及於第三閘極介電質上形成第三替換閘極電極。在一實施例中，半導體結構的形成方法更包括，在形成堆疊的膜層之前，形成延伸進入半導體基底中的隔離區；以及形成第一凸出鰭片凸出高於隔離區，其中隔離區包括在第一凸出鰭片的兩側上的部分。在一實施例中，第一凸出鰭片的整體為半導體。在一實施例中，第一凸出鰭片包括複數個通道層；以及複數個犧牲膜層，其中複數個通道層和複數個犧牲膜層為交替配置以形成額外膜層的堆疊。在一實施例中，半導體結構的形成方法更包括從第一凸出鰭片的中間部分移除複數個犧牲膜層。在一實施例中，當從第一凸出鰭片的中間部分移除複數個犧牲膜層時，在第一凸出鰭片的尾端部分中的複數個犧牲膜層被第二閘極介電質保護不被移除。
根據本揭露的一些實施例，一種半導體結構的形成方法，包括：於凸出鰭片的第一部分和第二部分上同時形成第一虛置閘極堆疊和第二虛置閘極堆疊；同時移除第一虛置閘極堆疊的第一閘極電極和第二虛置閘極堆疊的第二閘極電極以分別形成第一溝槽和第二溝槽；形成蝕刻遮罩，其中蝕刻遮罩填入第一溝槽和第二溝槽；圖案化蝕刻遮罩以從第一溝槽移除蝕刻遮罩；移除第一虛置閘極堆疊的第一虛置閘極介電質，其中蝕刻遮罩保護第二虛置閘極堆疊 的第二虛置閘極介電質不被移除；以及分別於第一溝槽和第二溝槽中形成第一替換閘極堆疊和第二替換閘極堆疊。在一實施例中，第二虛置閘極堆疊延伸於凸出鰭片的第一側壁面、第二側壁面、和第三側壁面上，其中第一側壁面和第二側壁面係沿著凸出鰭片的長度方向，而第三側壁面係沿著凸出鰭片的寬度方向。在一實施例中，第一虛置閘極介電質包括具有第一厚度的第一氧化矽層，而形成第一替換閘極堆疊包括形成具有第二厚度的第二氧化矽層，第二厚度小於第一厚度。在一實施例中，半導體結構的形成方法更包括於第一虛置閘極堆疊的兩側上形成源極區和汲極區；以及於第二虛置閘極堆疊的一側上形成額外源極/汲極區，其中凸出鰭片終止於第二虛置閘極堆疊正下方的位置。在一實施例中，形成蝕刻遮罩包括配放光阻。
根據本揭露的一些實施例，一種半導體結構，包括：延伸進入半導體基底中的隔離區；於隔離區的部分之間的凸出鰭片，其中凸出鰭片凸出高於隔離區；第一閘極堆疊，包括：於凸出鰭片的第一部分的第一側壁和第一頂面上的第一閘極介電質，其中第一閘極介電質具有第一厚度；以及於第一閘極介電質上的第一閘極電極；以及第二閘極堆疊，包括：於凸出鰭片的第二部分的第二側壁和第二頂面上的第二閘極介電質，其中凸出鰭片終止於第二閘極堆疊的正下方，且第二閘極介電質具有第二厚度，第二厚度大於第一厚度；以及於第二閘極介電質上的第二閘極電極。在一實施例中，第一閘極介電質包括第一氧化物層和於第一氧化物層上的第一高介電常數介電層，而第二閘極介電質包括第二氧化物層和於第二氧化物層上的第二高介電常數介電層，且第二氧化物層比第一氧化物層更厚。在一實施例中，第一高介電常數介電層和第二高介電常數介電層係以相同材料所形成。在一實施例中，第二厚度對第一厚度的比 例係介於約4和6之間的範圍。在一實施例中，半導體結構更包括於第一閘極堆疊的側壁上的第一閘極間隔物；以及於第二閘極堆疊的側壁上的第二閘極間隔物，其中第一閘極間隔物比第二閘極間隔物更薄。在一實施例中，第二閘極介電質更延伸於凸出鰭片的第二部分的額外側壁上，且額外側壁的延伸方向與凸出鰭片的長度方向垂直。
以上概述數個實施例之部件，以便在所屬技術領域中具有通常知識者可以更加理解本揭露的觀點。在所屬技術領域中具有通常知識者應理解，他們能輕易地以本揭露實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在所屬技術領域中具有通常知識者也應理解，此類等效的結構並無悖離本揭露的精神與範圍，且他們能在不違背本揭露之精神和範圍下，做各式各樣的改變、取代和替換。
10:晶圓
20:(半導體)基底
24:(淺溝槽)隔離區
36:(凸出)鰭片
36A:中間(鰭片)部分
36B:尾端(鰭片)部分
40:虛置閘極介電質(介電層)
46:閘極間隔物
46A,46B,46C:閘極間隔物
54:磊晶區(源極/汲極區)
58:接觸蝕刻停止層
60:層間介電質
66:介電層
67A,67B,67C:高介電常數介電層
68A,68B,68C:閘極介電質
70A,70B,70C:閘極電極
72A,72B,72C:(替換)閘極堆疊
74A,74B,74C:鰭式場效電晶體
100C:元件區
100FE:元件區
100IO:元件區
136:凸出鰭片
LE:長度
T1:厚度
T2:厚度
T3:厚度
T4:厚度

Claims (14)

  1. 一種半導體結構的形成方法，包括：沉積多個堆疊的膜層於一第一凸出鰭片(protruding fin)上；圖案化該些堆疊的膜層以形成：一第一閘極堆疊，包括：一第一閘極介電質，於該第一凸出鰭片的一中間部分上；以及一第一閘極電極，於該第一閘極介電質上；以及一第二閘極堆疊，包括：一第二閘極介電質，於該第一凸出鰭片的一尾端部分上；以及一第二閘極電極，於該第二閘極介電質上；移除該第一閘極電極和該第二閘極電極以分別露出該第一閘極介電質和該第二閘極介電質；移除該第一閘極介電質，其中在移除該第一閘極介電質之後，保留該第二閘極介電質；形成一替換閘極介電質於該第一凸出鰭片的該中間部分上；以及形成一第一替換閘極電極和一第二替換閘極電極分別於該替換閘極介電質和該第二閘極介電質上。
  2. 如請求項1之半導體結構的形成方法，其中該替換閘極介電質形成具有比該第一閘極介電質更小的厚度。
  3. 如請求項1之半導體結構的形成方法，其中移除該第一閘極介電質包括：形成一蝕刻遮罩以覆蓋該第二閘極介電質，其中當移除該第一閘極介電質 時，該蝕刻遮罩保護該第二閘極介電質；以及移除該蝕刻遮罩。
  4. 如請求項1之半導體結構的形成方法，更包括：當形成該第一閘極堆疊時，形成一第三閘極堆疊，包括：一第三閘極介電質，於一第二凸出鰭片的一額外中間部分上；以及一第三閘極電極，於該第三閘極介電質上；移除該第三閘極電極以露出該第三閘極介電質，其中在移除該第一閘極介電質之後，保留該第三閘極介電質；以及形成一第三替換閘極電極於該第三閘極介電質上。
  5. 如請求項1~4中任一項之半導體結構的形成方法，更包括在形成該些堆疊的膜層之前：形成隔離區延伸進入一半導體基底中；以及形成該第一凸出鰭片凸出高於該隔離區，其中該隔離區包括在該第一凸出鰭片的兩側上的部分。
  6. 如請求項1之半導體結構的形成方法，其中該第一凸出鰭片包括：複數個通道層；以及複數個犧牲膜層(sacrificial film)，其中該些通道層和該些犧牲膜層為交替配置。
  7. 如請求項6之半導體結構的形成方法，更包括從該第一凸出鰭片的該中間部分移除該些犧牲膜層，在該第一凸出鰭片的該尾端部分中的該些犧牲膜層被該第二閘極介電質保護不被移除。
  8. 一種半導體結構的形成方法，包括： 同時形成一第一虛置閘極堆疊和一第二虛置閘極堆疊於一凸出鰭片的一第一部分和一第二部分上；同時移除該第一虛置閘極堆疊的一第一閘極電極和該第二虛置閘極堆疊的一第二閘極電極以分別形成一第一溝槽和一第二溝槽；形成一蝕刻遮罩，其中該蝕刻遮罩填入該第一溝槽和該第二溝槽；圖案化該蝕刻遮罩以從該第一溝槽移除該蝕刻遮罩；移除該第一虛置閘極堆疊的一第一虛置閘極介電質，其中該蝕刻遮罩保護該第二虛置閘極堆疊的一第二虛置閘極介電質不被移除；以及形成一第一替換閘極堆疊和一第二替換閘極堆疊分別於該第一溝槽和該第二溝槽中。
  9. 如請求項8之半導體結構的形成方法，其中該第二虛置閘極堆疊延伸於該凸出鰭片的一第一側壁面、一第二側壁面、和一第三側壁面上，其中該第一側壁面和該第二側壁面係沿著該凸出鰭片的長度(lengthwise)方向，而該第三側壁面係沿著該凸出鰭片的寬度(widthwise)方向。
  10. 如請求項8之半導體結構的形成方法，其中該第一虛置閘極介電質包括具有一第一厚度的一第一氧化矽(silicon oxide)層，而形成該第一替換閘極堆疊包括形成具有一第二厚度的一第二氧化矽層，該第二厚度小於該第一厚度。
  11. 如請求項8~10中任一項之半導體結構的形成方法，包括：形成一源極區和一汲極區於該第一虛置閘極堆疊的兩側上；以及形成一額外源極/汲極區於該第二虛置閘極堆疊的一側上，其中該凸出鰭片終止於該第二虛置閘極堆疊正下方的位置。
  12. 一種半導體結構，包括：多個隔離區，延伸進入一半導體基底中；一凸出鰭片，於該些隔離區的多個部分之間，其中該凸出鰭片凸出高於該些隔離區；一第一閘極堆疊，包括：一第一閘極介電質，於該凸出鰭片的一第一部分的多個第一側壁和一第一頂面上，其中該第一閘極介電質具有一第一厚度，其中該第一閘極介電質包括一第一氧化物層和於該第一氧化物層上的一第一高介電常數(high-k)介電層；以及一第一閘極電極，於該第一閘極介電質上；以及一第二閘極堆疊，包括：一第二閘極介電質，於該凸出鰭片的一第二部分的多個第二側壁和一第二頂面上，其中該凸出鰭片終止於該第二閘極堆疊的正下方，且該第二閘極介電質具有一第二厚度，該第二厚度大於該第一厚度，其中該第二閘極介電質包括一第二氧化物層和於該第二氧化物層上的一第二高介電常數介電層，其中該第二氧化物層比該第一氧化物層更厚；以及一第二閘極電極，於該第二閘極介電質上。
  13. 如請求項12之半導體結構，更包括：一第一閘極間隔物，於該第一閘極堆疊的一側壁上；以及一第二閘極間隔物，於該第二閘極堆疊的一側壁上，其中該第一閘極間隔物比該第二閘極間隔物更薄。
  14. 如請求項12之半導體結構，其中該第二閘極介電質更延伸於該凸 出鰭片的該第二部分的一額外側壁上，且該額外側壁的延伸方向與該凸出鰭片的長度方向垂直。
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