CN112750771A - 鳍端部栅极结构及其形成方法 - Google Patents

鳍端部栅极结构及其形成方法 Download PDF

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CN112750771A
CN112750771A CN202011172342.3A CN202011172342A CN112750771A CN 112750771 A CN112750771 A CN 112750771A CN 202011172342 A CN202011172342 A CN 202011172342A CN 112750771 A CN112750771 A CN 112750771A
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gate
gate dielectric
dielectric
stack
forming
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林士尧
高魁佑
陈振平
林志翰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开涉及鳍端部栅极结构及其形成方法。一种方法包括：在突出鳍的第一部分和第二部分上同时形成第一虚设栅极堆叠和第二虚设栅极堆叠；同时去除第一虚设栅极堆叠的第一栅极电极和第二虚设栅极堆叠的第二栅极电极，以分别形成第一沟槽和第二沟槽；形成蚀刻掩模，其中，蚀刻掩模填充第一沟槽和第二沟槽；图案化蚀刻掩模以从第一沟槽去除蚀刻掩模；去除第一虚设栅极堆叠的第一虚设栅极电介质，其中，蚀刻掩模保护第一虚设栅极堆叠的第二栅极电介质不被去除；以及分别在第一沟槽和第二沟槽中形成第一替换栅极堆叠和第二替换栅极堆叠。

Description

鳍端部栅极结构及其形成方法
技术领域
本公开总体涉及鳍端部栅极结构及其形成方法。
背景技术
金属氧化物半导体(MOS)器件是集成电路中的基本构建元件。MOS 器件可以具有由掺杂有p型杂质或n型杂质的多晶硅形成的栅极电极，该 p型杂质或n型杂质是使用诸如离子注入或热扩散之类的掺杂工艺来掺杂的。可以将栅极电极的功函数调整为硅的带边缘(band-edge)。对于n型金属氧化物半导体(NMOS)器件，可以将功函数调整为接近硅的导带(conduction band)。对于P型金属氧化物半导体(PMOS)器件，可以将功函数调整为接近硅的价带(valence band)。可以通过选择适当的杂质来调节多晶硅栅极电极的功函数。
具有多晶硅栅极电极的MOS器件表现出载流子耗尽效应，这也被称为多晶硅耗尽效应。当所施加的电场从靠近栅极电介质的栅极区域清除载流子时发生多晶硅耗尽效应，形成耗尽层。在n掺杂多晶硅层中，耗尽层包括电离的非移动供体位点，其中，在p掺杂多晶硅层中，耗尽层包括电离的非移动受体点。耗尽效应导致有效栅极电介质厚度增加，使得更难在半导体表面上形成反型层。
可以通过形成金属栅极电极来解决多晶硅耗尽问题，其中，在NMOS 器件和PMOS器件中使用的金属栅极也可以具有带边缘功函数。因此，所得到的金属栅极包括多个层以满足NMOS器件和PMOS器件的要求。
金属栅极的形成通常涉及形成虚设栅极堆叠、去除虚设栅极堆叠以形成沟槽、形成包括延伸到沟槽中的金属栅极的替换栅极堆叠、以及然后执行化学机械抛光(CMP)工艺以去除金属栅极的多余部分。
发明内容
根据本公开的第一方面，提供了一种方法，包括：在第一突出鳍上沉积堆叠层；图案化所述堆叠层以形成下列项：第一栅极堆叠，包括：第一栅极电介质，在所述第一突出鳍的中间部分上；以及第一栅极电极，在所述第一栅极电介质上；以及第二栅极堆叠，包括：第二栅极电介质，在所述第一突出鳍的端部部分上；以及第二栅极电极，在所述第二栅极电介质上；去除所述第一栅极电极和所述第二栅极电极以分别露出所述第一栅极电介质和所述第二栅极电介质；去除所述第一栅极电介质，其中，所述第二栅极电介质在所述第一栅极电介质被去除之后保留；在所述第一突出鳍的所述中间部分上形成替换栅极电介质；以及分别在所述替换栅极电介质和所述第二栅极电介质上形成第一替换栅极电极和第二替换栅极电极。
根据本公开的第二方面，提供了一种方法，包括：在突出鳍的第一部分和第二部分上同时形成第一虚设栅极堆叠和第二虚设栅极堆叠；同时去除所述第一虚设栅极堆叠的第一栅极电极和所述第二虚设栅极堆叠的第二栅极电极，以分别形成第一沟槽和第二沟槽；形成蚀刻掩模，其中，所述蚀刻掩模填充所述第一沟槽和所述第二沟槽；图案化所述蚀刻掩模以从所述第一沟槽去除所述蚀刻掩模；去除所述第一虚设栅极堆叠的第一虚设栅极电介质，其中，所述蚀刻掩模保护所述第一虚设栅极堆叠的第二栅极电介质不被去除；以及分别在所述第一沟槽和所述第二沟槽中形成第一替换栅极堆叠和第二替换栅极堆叠。
根据本公开的第三方面，提供了一种结构，包括：隔离区域，延伸到半导体衬底中；突出鳍，在所述隔离区域的部分之间，其中，所述突出鳍突出高于所述隔离区域；第一栅极堆叠，包括：第一栅极电介质，在所述突出鳍的第一部分的第一侧壁和第一顶表面上，其中，所述第一栅极电介质具有第一厚度；以及第一栅极电极，在所述第一栅极电介质上；以及第二栅极堆叠，包括：第二栅极电介质，在所述突出鳍的第二部分的第二侧壁和第二顶表面上，其中，所述突出鳍在所述第二栅极堆叠的正下方终止，并且所述第二栅极电介质具有所述大于第一厚度的第二厚度；以及第二栅极电极，在所述第二栅极电介质上。
附图说明
在结合附图阅读下面的具体实施方式时，可以从下面的具体实施方式中最佳地理解本公开的各个方面。注意，根据行业的标准做法，各种特征不是按比例绘制的。事实上，为了讨论的清楚起见，各种特征的尺寸可能被任意增大或减小。
图1-3、图4A、图4B、图5A、图5B、图6A、图6B、图7A、图7B、图8A、图8B、图8C和图9-13示出了根据一些实施例的鳍式场效应晶体管(FinFET)和鳍端部栅极结构的形成中的中间阶段的透视图、顶视图和截面图。
图14-21、图22A和图22B示出了根据一些实施例的栅极环绕式(Gate All-Around，GAA)晶体管和鳍端部栅极结构的形成中的中间阶段的透视图、顶视图和截面图。
图23示出了根据一些实施例的用于形成FinFET和鳍端部栅极结构的工艺流程。
具体实施方式
下面的公开内容提供了用于实现本发明的不同特征的许多不同的实施例或示例。下文描述了组件和布置的具体示例以简化本公开。当然，这些仅仅是示例而不意图是限制性的。例如，在下面的说明中，在第二特征上方或之上形成第一特征可以包括以直接接触的方式形成第一特征和第二特征的实施例，并且还可以包括可以在第一特征和第二特征之间形成附加特征，使得第一特征和第二特征可以不直接接触的实施例。此外，本公开在各个示例中可能重复参考标号和/或字母。这种重复是为了简单性和清楚性的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，本文中可能使用了空间相关术语(例如，“下方”、“之下”、“低于”、“以上”、“上部”等)，以易于描述图中所示的一个要素或特征相对于另外(一个或多个)要素或(一个或多个)特征的关系。这些空间相关术语意在涵盖器件在使用或工作中除了图中所示朝向之外的不同朝向。装置可能以其他方式定向(旋转90度或处于其他朝向)，并且本文中所用的空间相关描述符同样可能被相应地解释。
根据一些实施例，提供了一种形成鳍式场效应晶体管(FinFET)、全栅极(GAA)晶体管和鳍端部栅极结构的方法，以及所得到的结构。根据一些实施例，示出了形成晶体管的中间阶段。讨论了一些实施例的一些变型。贯穿各种视图和说明性实施例，相同的参考标号用于指示相同的元件。诸如碳网络管(CNT)、多桥沟道FET(MBCFET)、纳米片FET (NSFET)、纳米结构晶体管、互补(CFET)、垂直FET(VFET)等之类的晶体管以及相应的鳍端部栅极结构的形成也可以采用本公开的实施例。本文讨论的实施例将提供得能够进行或使用本公开的主题的示例，并且本领域普通技术人员将容易理解可以进行的修改，同时保持在不同实施例的预期范围内。尽管方法实施例可以被讨论为以特定顺序执行，但是其他方法实施例可以以任何逻辑顺序执行。
根据本公开的一些实施例，可以包括虚设栅极电极的第一虚设栅极堆叠和第二虚设栅极堆叠分别形成在突出鳍的中间部分和端部部分上。突出鳍可以是突出半导体鳍，或者可以包括堆堆叠(例如，包括半导体层和牺牲层)。去除第一栅极堆叠和第二栅极堆叠的第一虚设栅极电极和第二虚设栅极电极，分别暴露下面的第一虚设栅极电介质和第二虚设栅极电介质。覆盖突出鳍的中间部分的第一虚设栅极电介质被去除，而覆盖突出鳍的端部部分的第二虚设栅极电介质未被去除。通过不去除第二虚设栅极电介质，保护了突出鳍的下面的端部部分免受后续工艺造成的损坏，并且保护了与突出鳍的端部部分相邻的最近的源极/漏极区域。
图1-3、图4A、图4B、图5A、图5B、图6A、图6B、图7A、图7B、图8A、图8B、图8C和图9-13示出了根据本公开的一些实施例的鳍式场效应晶体管(FinFET)和鳍端部结构的形成中的中间阶段的截面图和透视图。这些附图中所示的工艺还示意性地反映在图23所示的工艺流程400中。
在图1中，提供衬底20。衬底20可以是半导体衬底，例如，体半导体衬底、绝缘体上半导体(SOI)衬底等，其可以被掺杂(例如，用p型或n 型掺杂剂)或未掺杂。半导体衬底20可以是晶圆10的一部分。通常，SOI 衬底是在绝缘体层上形成的半导体材料层。绝缘体层可以是例如掩埋氧化物(BOX)层、氧化硅层等。绝缘层设置在通常为硅衬底或玻璃衬底的衬底上。还可以使用其他衬底，例如多层衬底或梯度衬底。在一些实施例中，半导体衬底20的半导体材料可以包括硅；锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括，SiGe、 GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或其组合。
进一步参考图1，在衬底20中形成阱区域22。相应工艺在图23所示的工艺流程400中被示为工艺402。根据本公开的一些实施例，阱区域22 是通过将p型杂质(可以是硼、铟等)注入到衬底20中而形成的p型阱区域。根据本公开的其他实施例，阱区域22是通过将n型杂质(可以是磷、砷、锑等)注入到衬底20中而形成的n型阱区域。所得的阱区域22可以延伸到衬底20的顶表面。n型或p型杂质浓度可以等于或小于1018cm-3，例如，在约1017cm-3和约1018cm-3之间的范围内。
参考图2，隔离区域24被形成为从衬底20的顶表面延伸到衬底20中。在下文中，隔离区域24替代地称为浅沟槽隔离(STI)区域。相应工艺在图23所示的工艺流程400中被示为工艺404。相邻的STI区域24之间的衬底20的部分被称为半导体条带26。为了形成STI区域24，可以在半导体衬底20上形成衬垫氧化物层28和硬掩模层30，并然后进行图案化。衬垫氧化物层28可以是由氧化硅形成的薄膜。根据本公开的一些实施例，在热氧化工艺中形成衬垫氧化物层28，其中，半导体衬底20的顶表面层被氧化。衬垫氧化物层28用作半导体衬底20与硬掩模层30之间的粘附层。衬垫氧化物层28还可以用作用于蚀刻硬掩模层30的蚀刻停止层。根据本公开的一些实施例，硬掩模层30是例如使用低压化学气相沉积(LPCVD) 由氮化硅形成的。根据本公开的其他实施例，硬掩模层30是通过硅的热氮化、或等离子体增强化学气相沉积(PECVD)形成的。在硬掩模层30上形成光致抗蚀剂(未示出)，然后对其进行图案化。然后，使用经图案化的光致抗蚀剂作为蚀刻掩模对硬掩模层30进行图案化，以形成如图2所示的硬掩模30。
接下来，将经图案化的硬掩模层30用作蚀刻掩模以蚀刻衬垫氧化物层28和衬底20，随后用(一种或多种)电介质材料填充衬底20中的所得沟槽。执行诸如化学机械抛光(CMP)工艺或机械研磨工艺之类的平坦化工艺以去除电介质材料的多余部分，并且(一种或多种)电介质材料的其余部分为STI区域24。STI区域24可以包括衬里电介质(未示出)，其可以是通过衬底20的表面层的热氧化而形成的热氧化物。衬里电介质也可以是使用例如原子层沉积(ALD)、高密度等离子体化学气相沉积 (HDPCVD)、化学气相沉积(CVD)等而沉积的氧化硅层、氮化硅层等。 STI区域24还包括在衬里氧化物之上的电介质材料，其中，该电介质材料可以使用可流动化学气相沉积(FCVD)、旋涂等形成。根据一些实施例，衬里电介质之上的电介质材料可以包括氧化硅。
硬掩模层30的顶表面和STI区域24的顶表面可以基本上彼此齐平。半导体条带26在相邻的STI区域24之间。根据本公开的一些实施例，半导体条带26是原始衬底20的部分，因此半导体条带26的材料与衬底20 的材料相同。根据本公开的替代实施例，半导体条带26是通过蚀刻STI区域24之间的衬底20的部分以形成凹槽，并且执行外延以在凹槽中再生长另一半导体材料而形成的替换条带。因此，半导体条带26由不同于衬底20 的半导体材料形成。根据一些实施例，半导体条带26由硅锗、硅碳、或 III-V族化合物半导体材料形成。
参考图3，STI区域24被凹陷，使得半导体条带26的顶部部分突出高于STI区域24的其余部分的顶表面24A，以形成突出鳍36。相应工艺在图 23所示的工艺流程400中被示为工艺406。可以使用干法蚀刻工艺来执行蚀刻，其中，例如将NF3和NH3用作蚀刻气体。在蚀刻工艺期间，可能产生等离子体。还可以包括氩。根据本公开的替代实施例，使用湿法蚀刻工艺执行STI区域24的凹陷。蚀刻化学品可以包括例如HF。
在上述实施例中，可以通过任意适当的方法对鳍进行图案化。例如，可以使用一个或多个光刻工艺来对鳍进行图案化，包括双图案化或多图案化工艺。通常，双图案化或多图案化工艺组合光刻和自对准工艺，允许创建具有例如比使用单个直接光刻工艺可获得的间距更小的间距的图案。例如，在一个实施例中，在衬底上方形成牺牲层并使用光刻工艺进行图案化。使用自对准工艺在经图案化的牺牲层旁边形成间隔件。然后去除牺牲层，然后可以使用剩余的间隔件或心轴来对鳍进行图案化。
参考图4A，虚设栅极堆叠38被形成为在(突出)鳍36的顶表面和侧壁上延伸。相应工艺在图23所示的工艺流程400中被示为工艺408。形成工艺可以包括沉积堆堆叠，并然后图案化堆堆叠以形成虚设栅极堆叠38。虚设栅极堆叠38可以包括虚设栅极电介质40以及虚设栅极电介质40上方的虚设栅极电极42。虚设栅极电极42可以例如使用多晶硅形成，也可以使用其他材料。虚设栅极堆叠38中的每一个还可以包括虚设栅极电极42 上方的一个(或多个)硬掩模层44。硬掩模层44可以由电介质层66形成，也可以由其他电介质材料形成或包括其他电介质材料，例如，SiN、SiON、 SiOCN、SiOC、SiO2、SiC等或其多层。虚设栅极堆叠38可以跨单个或多个突出鳍36和/或STI区域24。虚设栅极堆叠38还具有与突出鳍36的纵向方向垂直的纵向方向。
接下来，在虚设栅极堆叠38的侧壁上形成栅极间隔件46。相应工艺在图23所示的工艺流程400中也被示为工艺408。根据本公开的一些实施例，间隔件46由诸如氮化硅、碳氮化硅等之类的(一种或多种)电介质材料形成，并且可以具有单层结构、或包括多个电介质层的多层结构。
图4B示出了晶圆10的平面图，其包括突出鳍36、设栅极堆叠38和栅极间隔件46。虚设栅极堆叠38中的一些(表示为38A)在突出鳍36的中间部分36A上，并且一些其他虚设栅极堆叠38(表示为38B)在突出鳍 36的端部部分36B上。突出鳍36被STI区域24围绕。虚设栅极堆叠38B 中的每一个可以包括覆盖突出鳍36的端部部分的第一部分(例如，所示的左侧部分)，以及延伸超过突出鳍36的第二部分(例如，所示的右侧部分)。根据一些实施例，虚设栅极堆叠38B中的虚设栅极电极42被称为 OD边缘上的多晶硅(PODE)，其中，术语“OD”表示有源区域，例如，突出鳍36。类似地，在突出鳍36的左端(未示出)，也可以存在覆盖虚设栅极堆叠38B的左边缘部分的虚设栅极堆叠38B(未示出)。
然后，执行蚀刻工艺以蚀刻突出鳍36的未被虚设栅极堆叠38和栅极间隔件46覆盖的部分，从而得到图5A所示的结构。相应工艺在图23所示的工艺流程400中被示为工艺410。凹陷可以是各向异性的，因此鳍36的在虚设栅极堆叠38和栅极间隔件46正下方的部分被保护，并且未被蚀刻。根据一些实施例，经凹陷的半导体条带26的顶表面可以低于STI区域24的顶表面24A。相应地形成凹槽50。凹槽50包括位于虚设栅极堆叠38的相对侧的部分，以及在突出鳍36的其余部分之间的部分。
图5B示出了在形成凹槽50之后的晶圆10的平面图，其中，所示出的部分对应于如图4B所示的端部部分，并且对应于图5A所示的结构。
接下来，通过在凹槽50中(通过外延)选择性地生长半导体材料来形成外延区域(源极/漏极区域)54，得到图6A的结构。相应工艺在图23所示的工艺流程400中被示为工艺412。根据所得的FinFET是p型FinFET还是n型FinFET，可以在进行外延时原位掺杂p型杂质或n型杂质。例如，当所得的FinFET是p型FinFET时，可以生长硅锗硼(SiGeB)、硅硼 (SiB)等。相反，当所得的FinFET是n型FinFET时，可以生长硅磷 (SiP)、硅碳磷(SiCP)等。根据本公开的替代实施例，外延区域54包括III-V族化合物半导体，例如，GaAs、InP、GaN、InGaAs、InAlAs、 GaSb、AlSb、AlAs、AlP、GaP、其组合、或其多层。在凹槽50填充有外延区域54之后，外延区域54的进一步外延生长使得外延区域54水平扩展，并且可以形成小平面。外延区域54的进一步生长还可使得相邻的外延区域 54彼此融合。可能产生空隙(气隙)56。根据本公开的一些实施例，外延区域54的形成可以在外延区域54的顶表面仍然为波浪形、或者当合并的外延区域54的顶表面已经变得平坦时完成。
在外延工艺之后，外延区域54可以进一步注入p型杂质或n型杂质以形成源极区域和漏极区域，其也可以用参考标号54表示。根据本公开的替代实施例，当外延区域54在外延期间原位掺杂有p型杂质或n型杂质时，跳过注入步骤。
图6B示出了晶圆10的一部分的平面图，其中，所示出的部分对应于图6A所示的结构。
图7A示出了在形成接触蚀刻停止层(CESL)58和层间电介质层 (ILD)60之后的结构的透视图。相应工艺在图23所示的工艺流程400中被示为工艺414。CESL 58可以由氧化硅、氮化硅、碳氮化硅等形成，并且可以使用CVD、ALD等形成。ILD 60可以包括使用例如FCVD、旋涂、 CVD、或另一沉积方法形成的电介质材料。ILD 60可以由含氧电介质材料形成，该含氧电介质材料可以是基于氧化硅的材料，例如，氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂硼的磷硅酸盐玻璃 (BPSG)等。可以执行诸如CMP工艺或机械研磨工艺之类的平坦化工艺以使ILD 60、虚设栅极堆叠38和栅极间隔件46的顶表面彼此平齐。
图7B示出了三个器件区域100C、100FE和100IO的截面图。器件区域100C可以是用于形成第一FinFET(可以是核心(逻辑)FinFET)的核心(逻辑)器件区域。器件区域100C所示的截面图可以从图6B中的参考横截面100C-100C获得(除了CESL 58和ILD 60也在图7B中示出)。器件区域100FE是用于形成鳍端部栅极结构的器件区域。器件区域100FE中所示的截面图可以从图6B中的参考横截面100FE-100FE获得(除了添加 CESL 58和ILD 60之外)。器件区域100IO可以是用于形成第二FinFET (可以是输入/输出(IO)FinFET)的器件区域。可以理解，器件区域 100C和100IO中的晶体管可以具有不同的栅极长度。例如，根据一些实施例，栅极长度GL1可以小于栅极长度GL2。器件区域100IO中所示的结构的截面图可以从与所示的突出鳍36分开的另一突出鳍136(图8C，类似于鳍36)获得，并且该截面图是从突出鳍136的中间部分获得的。
应当理解，尽管以核心器件区域和IO器件区域为例，但是也可以考虑其他器件区域。在图7B中，器件区域100C、100FE和100IO中的栅极电介质40可形成为共享共同的形成工艺，并且因此具有相同的厚度。器件区域100C中的栅极电介质40在随后的工艺中被去除，因此是虚设栅极电介质。器件区域100IO中的栅极电介质40用作IO FinFET的功能栅极电介质，因此是有源栅极电介质而不是虚设栅极电介质。在图7B中，示出了STI区域24，并且突出半导体鳍36和136突出高于相应的相邻STI区域24的顶表面24A。
在形成图7A和图7B所示的结构之后，虚设栅极堆叠38被替换栅极代替，并且形成工艺在图8A、图8B、图8C和图9-13中示出。为了形成替换栅极，首先去除如图7A和图7B所示的硬掩模层44和虚设栅极电极 42，从而形成如图8A、图8B和图8C所示的沟槽62。图8A示出了在去除硬掩模层44和虚设栅极电极42之后的结构的透视图。因此，暴露虚设栅极电介质40(图8C)。相应工艺在图23所示的工艺流程400中被示为工艺416。图8B示出了晶圆10的平面图。
如图8B所示，栅极电介质40通过沟槽62露出。在该阶段，栅极电介质40覆盖突出鳍36。鳍端部部分36B上的每个栅极电介质40包括三个部分，其中两个部分位于相应的突出鳍端部部分36B的相对侧壁并沿着相应的突出鳍端部部分36B的纵向方向(X方向)延伸，并且第三部分沿着相应的鳍端部部分36B的横向方向(Y方向)延伸。
图8C示出了在去除虚设栅极电极之后的器件区域100C、100FE和 100IO的截面图。如图8C所示，在器件区域100FE中，露出鳍端部处的栅极电介质40，并且在所示横截面中，栅极电介质40还在突出鳍端部部分 36B的侧壁上延伸。根据一些实施例，在公共工艺中执行从器件区域100C、 100FE和100IO去除硬掩模层44，并且在公共工艺中执行从器件区域100C、 100FE和100IO去除虚设栅极电极42。
参考图9，形成并图案化蚀刻掩模64，其可以是光致抗蚀剂。经图案化的蚀刻掩模64留在器件区域100PE和100IO中，并且从器件区域100C 去除。相应工艺在图23所示的工艺流程400中被示为工艺418。通过蚀刻掩模64来填充器件区域100PE和100IO中的沟槽62。
接下来，参考图10，执行蚀刻工艺以去除器件区域100C中的虚设栅极电介质40。相应工艺在图23所示的工艺流程400中被示为工艺420。根据一些实施例，蚀刻是各向异性的。根据替代实施例，蚀刻是各向同性的。根据其中虚设栅极电介质40由氧化硅形成或包括氧化硅的一些实施例，可以使用NF3和NH3气体的混合物、或HF和NH3气体的混合物。根据其中使用湿法蚀刻工艺的其他实施例，可以使用HF溶液或类似蚀刻剂。当使用各向异性蚀刻时，虚设栅极电介质40可以留下一些残留部分并被栅极间隔件46重叠。在其他实施例中，虚设栅极电介质40完全从器件区域100C 中的沟槽62去除。在蚀刻工艺期间，器件区域100FE和100IO中的栅极电介质40被保护不受蚀刻。
在蚀刻工艺之后，去除蚀刻掩模64以再次露出器件区域100FE和 100IO中的栅极电介质40。所得的结构在图11中示出。相应工艺在图23 所示的工艺流程400中被示为工艺422。由于器件区域100C中的栅极间隔件46也暴露于用于蚀刻器件区域100C中的虚设栅极电介质40的蚀刻剂，因此器件区域100C中的栅极间隔件46(标记为46A)可被蚀刻剂变薄，并且可以分别比器件区域100FE和100IO中的栅极间隔件46B和46C更薄。根据一些实施例，厚度差(T2-T1)可以在约1nm与约2nm之间的范围内，其中，厚度T1是栅极间隔件46A的厚度，并且厚度T2是栅极间隔件 46B和46C的厚度。比率(T2-T1)/T2可以在约0.1与约0.3之间的范围内。
接下来，参考图12，形成栅极堆叠72A、72B和72C，其分别包括栅极电介质68A、68B和68C，以及栅极电极70A、70B和70C。由此分别形成FinFET 74A和FinFET 74C，它们可以是核心FinFET和IO FinFET。栅极电介质68A可以包括电介质层66和高k电介质层67A。电介质层66形成在突出鳍部分36A的暴露表面上，并且可以由氧化硅形成或可以包括氧化硅。相应工艺在图23所示的工艺流程400中被示为工艺424。根据一些实施例，电介质层66是界面层(IL)，其可以包括天然氧化物层，如图11 所示。由于半导体材料暴露于水分和氧气，天然氧化物层形成在突出鳍36 的暴露表面上。根据一些实施例，除了天然氧化之外，还可以通过化学氧化工艺或热氧化工艺来形成电介质层66。电介质层66还可以由其他电介质材料形成或可以包括其他电介质材料，例如，SiN、SiON、SiOCN、 SiOC、SiO2、SiC等。在器件区域100FE和100IO中，原始的电介质层40 保留。
在形成电介质层66之后，形成高k电介质层67A、67B和67C。相应工艺在图23所示的工艺流程400中被示为工艺426。高k电介质层67A、 67B和67C中的每一个可以由高k电介质材料形成，例如，氧化铪、氧化镧、氧化铝、氧化锆等、其组合、或其多个层。根据本公开的一些实施例，高k电介质层67A、67B和67C使用ALD、CVD等形成。高k电介质层67A、67B和67C可以是同一电介质层的部分，并且使用相同的材料同时形成并且具有相同的厚度，或者使用不同的材料分别形成和/或具有不同的厚度。电介质层(IL)66和上覆的高k电介质层67A被统称为栅极电介质层68A。器件区域100FE中的电介质层40和上覆的高k电介质层67B被统称为栅极电介质层68B。器件区域100IO中的电介质层40和上覆的高k电介质层67C被统称为栅极电介质层68C。高k电介质层67A、67B和67C 可以在相同的(一个或多个)沉积工艺形成，并且可以具有相同的厚度。
然后，形成栅极电极70A、70B和70C。相应工艺在图23所示的工艺流程400中被示为工艺428。根据本公开的一些实施例，栅极电极70A、 70B和70C中的每一个可以具有包括多个层的复合结构。根据一些实施例，栅极电极70A、70B和70C被同时形成并共享公共形成工艺，并因此具有相同的材料层和相同的厚度。根据替代实施例，栅极电极70A、70B和 70C可以在单独的工艺中形成，并且可以具有相同或不同的结构，并且具有相同或不同的材料，具有相同或不同的厚度。
根据一些实施例，栅极电极70A、70B和70C中的每一个可以具有扩散阻挡层、扩散阻挡层之上的功函数层、功函数层之上的帽盖层、以及帽盖层之上的填充金属区域。扩散阻挡层可以由TiN、TiSiN等形成、或可以包括TiN、TiSiN等。功函数层可以由根据在器件区域100C和100IO中形成的相应FinFET是n型FinFET还是p型FinFET而选择的材料形成、或可以包括这些选择的材料。例如，当FinFET是n型FinFET时，相应的功函数层可以包括基于铝的层(由例如TiAl、TiAlN、TiAlC、TaAlN或TaAlC 形成、或包括这些项)。当FinFET是p型FinFET时，相应的功函数层可以包括TiN层和TaN层。帽盖层(也称为阻挡层)可以由TiN、TaN等形成、或可以包括TiN、TaN等。可以使用ALD、CVD等来沉积扩散阻挡层、功函数层和帽盖层。填充金属区域可以由钨、钴等形成、或可以包括钨、钴等。
在图12中，在与器件区域100FE和100IO中的电介质层40不同的工艺中形成栅极电介质66。由于器件区域100IO中的电介质层40可以用于 IO器件，因此它们相对较厚，例如，其厚度T4在约
Figure RE-GDA0002935285420000121
与约
Figure RE-GDA0002935285420000122
之间的范围内。此外，器件区域100FE和100IO中的电介质层40的厚度可以彼此相等或基本上彼此相等，例如，差异小于约20％。另一方面，可以形成栅极电介质66以用于核心器件，并且厚度T3小于厚度T4。例如，厚度T3 可以在约
Figure RE-GDA0002935285420000131
与约
Figure RE-GDA0002935285420000132
之间的范围内。比率T4/T3与器件区域100C和 100IO中的器件的性能和可靠性要求有关。例如，器件区域100C中的器件的有效氧化物厚度(EOT)较低以实现较快速度，并且厚度T3较小，而较大的厚度T4可以提高IO器件的器件可靠性。因此，根据一些实施例，比率T4/T3可以在约4.0与约6.0之间的范围内。
图13示出FinFET 74A或74C的透视图。示出了栅极接触插塞114、源极/漏极硅化物区域110、源极/漏极接触插塞112和硬掩模116。
在以上形成工艺中，例如，如图10和图11所示的工艺，当从器件区域100C去除电介质层40时，未从鳍端部器件区域100FE去除电介质层40。由于鳍端部部分36B的长度LE(图12)随着集成电路的发展而变得越来越小，因此鳍端部部分36B可能例如在随后的清洁工艺中损坏。如果鳍端部部分36B被损坏，则相邻的源极/漏极区域54可能被损坏。因此，将电介质层40保留在器件区域100FE中具有保护突出鳍36的下面的端部部分 36B，并且保护相邻的源极/漏极区域的功能。
本公开的实施例可以应用于其他突出结构，并且可以用于形成其他类型的晶体管(例如，纳米片晶体管、纳米线晶体管、和/或全栅极(GAA) 晶体管)和相应的鳍端部栅极结构。图14-21、图22A和图22B示出了根据本公开的一些实施例的GAA晶体管(也可以是纳米片晶体管或纳米线晶体管)和相应的鳍端部栅极结构的形成中的中间阶段的截面图。除非另有说明，否则这些实施例中的组件的材料和形成工艺与在前述附图中所示的前述实施例中由相同的附图标记表示的相同的组件基本相同。因此，可以在前面的实施例的讨论中找到关于前面的图中所示的组件的形成工艺和材料的细节。
参考图14，形成突出鳍36’，并且在突出鳍36’的侧壁和顶表面上形成栅极堆叠38和栅极间隔件46。突出鳍36’可以包括堆叠层76，其包括沟道层78(详细信息请参见图15)和牺牲膜80。例如，沟道层78的总数和牺牲膜80的总数可以在1和10之间的范围内，并且包括1和10。可以理解，尽管在所示的示例实施例中牺牲膜80被示为堆叠层76的顶层，但是根据其他实施例，沟道层可以是堆叠层76的顶层。沟道层78和牺牲膜80的材料彼此不同。根据一些实施例，沟道层78由Si、SiGe等形成、或包括Si、 SiGe等。牺牲膜80可以由SiGe、SiP、SiOCN、SiC等形成、或可以包括 SiGe、SiP、SiOCN、SiC等。沟道层78和牺牲膜80中的每一个的厚度可以在约
Figure RE-GDA0002935285420000143
和约
Figure RE-GDA0002935285420000144
之间的范围内。堆叠层76与半导体条带26重叠。图14所示的结构的形成工艺类似于图1-3和图4A所示的工艺，不同之处在于在执行图1至图3所示的工艺之前，例如通过外延预先形成了堆叠层 76。
图15示出了图14中所示的结构的顶视图。该顶视图也与图4B中所示的顶视图相似，不同之处在于图14中的突出鳍36’替代了图4B中的突出鳍 36。
随后，执行图5A、图5B、图6A、图6B、图7A和图7B所示的工艺以形成源极/漏极区域54、CESL 58和ILD 60。所得的结构在图16中示出，其包括分别从同一突出鳍36’的中间部分和端部部分获得的截面图。图16 示出了器件区域100C和100FE中的结构的截面图，这些截面图是分别从如图15所示的参考横截面100C-100C和100FE-100FE获得的。在图16中，形成内部间隔件82。在内部间隔件82的示例形成工艺中，在图5A所示的鳍蚀刻工艺之后，牺牲膜80的侧壁被暴露。执行氧化工艺以氧化牺牲膜80 的端部部分，从而形成氧化物区域以用作内部间隔件82。内部间隔件82的材料可以取决于牺牲膜80的材料，并且可以包括SiGe、SiP、SiOCN、SiC 等的氧化物。内部间隔件82的宽度W1可以在约
Figure RE-GDA0002935285420000141
和约
Figure RE-GDA0002935285420000142
之间的范围内。
接下来，去除硬掩模44和虚设栅极电极42以形成沟槽62，并且所得的结构在图17中示出。栅极电介质40同时在器件区域100C和100FE中暴露。参考图18，形成经图案化的蚀刻掩模64以填充器件区域100FE中的沟槽62，同时从器件区域100C去除蚀刻掩模64。
接下来，从器件区域100C去除虚设栅极电介质层40，同时保护器件区域100FE中的栅极电介质层40不被去除。所得的结构在图19中示出。然后去除蚀刻掩模64，并且所得的结构在图20中示出。在随后的工艺中，从中间鳍部分36A’去除牺牲膜80，并且所得的结构在图21中示出。根据一些实施例，内部间隔件82未被去除，并且将保留在最终的GAA晶体管中。内间隔件82可以保护源极/漏极区域54在去除牺牲膜80时不受损坏，并且可以隔离随后形成的栅极堆叠而不与源极/漏极区域54短路。作为去除牺牲膜80的结果，在沟道层78之间形成空间。
在去除牺牲膜80时，沟槽62中剩余的电介质层40保护突出鳍的相应鳍端部部分36B’不被去除。因此，在最终结构中，突出鳍36’的鳍端部部分36B’保持未被去除。此外，当从中间鳍部分36A’去除牺牲膜80时，端部部分36B’中的牺牲膜80被保护不被去除，并且将保留在最终结构中。
在随后的工艺中，形成替换栅极堆叠72A和72B。因此形成GAA晶体管86。在形成期间，首先形成电介质层66以包围沟道层78，其可以包括天然氧化物，并且可能是通过沟道层78的表面部分的化学氧化或热氧化而形成的氧化物层。栅极堆叠72A包括电介质层66、高k电介质层67A和栅极电极70A。高k电介质层67A和栅极电极70A可以延伸到相邻的沟道层78之间的空间中。鳍端部栅极结构72B包括电介质层40、高k电介质层67B和栅极电极70B。
图22B示出了从图22A所示的参考横截面22B-22B获得的参考横截面，并且该参考横截面示出了GAA晶体管86的沟道和栅极部分。此外，还示出了器件区域100IO。
本公开的实施例具有一些有利特征。当从一些器件区域(例如，核心器件区域)去除虚设栅极电介质时，形成在突出鳍的鳍端部上的电介质层被保护不被去除。突出鳍的鳍端部上的剩余电介质层保护突出鳍的端部部分免于损坏，并且突出鳍的端部部分可以进一步保护相邻的源极/漏极区域。
根据本公开的一些实施例，一种方法包括：在第一突出鳍上沉积堆叠层；图案化堆叠层以形成下列项：第一栅极堆叠，包括：第一栅极电介质，在第一突出鳍的中间部分上；以及第一栅极电极，在第一栅极电介质上；以及第二栅极堆叠，包括：第二栅极电介质，在第一突出鳍的端部部分上；以及第二栅极电极，在第二栅极电介质上；去除第一栅极电极和第二栅极电极以分别露出第一栅极电介质和第二栅极电介质；去除第一栅极电介质，其中，第二栅极电介质在第一栅极电介质被去除之后保留；在第一突出鳍的中间部分上形成替换栅极电介质；以及分别在替换栅极电介质和第二栅极电介质上形成第一替换栅极电极和第二替换栅极电极。在一个实施例中，替换栅极电介质被形成为具有比第一栅极电介质更小的厚度。在一个实施例中，去除第一栅极电介质包括：形成蚀刻掩模以覆盖第二栅极电介质，其中，蚀刻掩模在第一栅极电介质被去除时保护第二栅极电介质；并去除蚀刻掩模。在一个实施例中，该方法还包括：在形成第一栅极堆叠时，形成第三栅极堆叠，包括：第三栅极电介质，在第二突出鳍的另外的中间部分上；以及第三栅极电极，在第三栅极电介质上；去除第三栅极电极以露出第三栅极电介质，其中，第三栅极电介质在第一栅极电介质被去除之后保留；以及在第三栅极电介质上形成第三替换栅极电极。在一个实施例中，该方法还包括：在形成堆叠层之前，形成延伸到半导体衬底中的隔离区域；以及形成突出高于隔离区域的第一突出鳍，其中，隔离区域包括位于第一突出鳍的相对侧的部分。在一个实施例中，整个第一突出鳍是半导体。在一个实施例中，第一突出鳍包括多个沟道层；以及多个牺牲膜，其中，该多个沟道层和该多个牺牲膜被交替地分配以形成另外的层堆叠。在一个实施例中，该方法还包括：从第一突出鳍的中间部分去除该多个牺牲膜。在一个实施例中，当从第一突出鳍的中间部分去除该多个牺牲膜时，第一突出鳍的端部部分中的多个牺牲膜被第二栅极电介质保护而不被去除。
根据本公开的一些实施例，一种方法包括：在突出鳍的第一部分和第二部分上同时形成第一虚设栅极堆叠和第二虚设栅极堆叠；同时去除第一虚设栅极堆叠的第一栅极电极和第二虚设栅极堆叠的第二栅极电极，以分别形成第一沟槽和第二沟槽；形成蚀刻掩模，其中，蚀刻掩模填充第一沟槽和第二沟槽；图案化蚀刻掩模以从第一沟槽去除蚀刻掩模；去除第一虚设栅极堆叠的第一虚设栅极电介质，其中，蚀刻掩模保护第一虚设栅极堆叠的第二栅极电介质不被去除；以及分别在第一沟槽和第二沟槽中形成第一替换栅极堆叠和第二替换栅极堆叠。在一个实施例中，第二虚设栅极堆叠在突出鳍的第一侧壁表面、第二侧壁表面和第三侧壁表面上延伸，其中，第一侧壁表面和第二侧壁表面沿着突出鳍的纵向方向，并且第三侧壁表面沿着突出鳍的横向方向。在一个实施例中，第一虚设栅极电介质包括具有第一厚度的第一氧化硅层，并且形成第一替换栅极堆叠包括：形成具有小于第一厚度的第二厚度的第二氧化硅层。在一个实施例中，该方法还包括：在第一虚设栅极堆叠的相对侧形成源极区域和漏极区域；以及在第二虚设栅极堆叠的一侧形成另外的源极/漏极区域，其中，突出鳍在第二虚设栅极堆叠正下方的位置处终止。在一个实施例中，形成蚀刻掩模包括：分配光致抗蚀剂。
根据本公开的一些实施例，一种结构包括：隔离区域，延伸到半导体衬底中；突出鳍，在隔离区域的部分之间，其中，突出鳍突出高于隔离区域；第一栅极堆叠，包括：第一栅极电介质，在突出鳍的第一部分的第一侧壁和第一顶表面上，其中，第一栅极电介质具有第一厚度；以及第一栅极电极，在第一栅极电介质上；以及第二栅极堆叠，包括：第二栅极电介质，在突出鳍的第二部分的第二侧壁和第二顶表面上，其中，突出鳍在第二栅极堆叠的正下方终止，并且第二栅极电介质具有大于第一厚度的第二厚度；以及第二栅极电极，在第二栅极电介质上。在一个实施例中，第一栅极电介质包括第一氧化物层以及第一氧化物层之上的第一高k电介质层，并且第二栅极电介质包括第二氧化物层以及第二氧化物层之上的第二高k 电介质层，并且第二氧化物层比第一氧化物层更厚。在一个实施例中，第一高k电介质层和第二高k电介质层由相同的材料形成。在一个实施例中，第二厚度与第一厚度的比率在约4与约6之间的范围内。在一个实施例中，该结构还包括：位于第一栅极堆叠的相对侧的源极区域和漏极区域；以及位于第二栅极堆叠的一侧的另外的源极/漏极区域。在一个实施例中，第二栅极电介质进一步在突出鳍的第二部分的另外的侧壁上延伸，并且该另外的侧壁沿着垂直于突出鳍的纵向方向的方向延伸。
以上概述了若干实施例的特征，使得本领域技术人员可以更好地理解本公开的各方面。本领域技术人员应当理解，他们可以容易地使用本公开作为设计或修改其他工艺和结构以实现本文介绍的实施例的相同目的和/或实现本文介绍的实施例的相同优点的基础。本领域技术人员还应该认识到，这样的等同构造不脱离本公开的精神和范围，并且他们可以在不脱离本公开的精神和范围的情况下在本文中进行各种改变、替换和变更。
示例1.一种方法，包括：在第一突出鳍上沉积堆叠层；图案化所述堆叠层以形成下列项：第一栅极堆叠，包括：第一栅极电介质，在所述第一突出鳍的中间部分上；以及第一栅极电极，在所述第一栅极电介质上；以及第二栅极堆叠，包括：第二栅极电介质，在所述第一突出鳍的端部部分上；以及第二栅极电极，在所述第二栅极电介质上；去除所述第一栅极电极和所述第二栅极电极以分别露出所述第一栅极电介质和所述第二栅极电介质；去除所述第一栅极电介质，其中，所述第二栅极电介质在所述第一栅极电介质被去除之后保留；在所述第一突出鳍的所述中间部分上形成替换栅极电介质；以及分别在所述替换栅极电介质和所述第二栅极电介质上形成第一替换栅极电极和第二替换栅极电极。
示例2.根据示例1所述的方法，其中，所述替换栅极电介质被形成为具有比所述第一栅极电介质更小的厚度。
示例3.根据示例1所述的方法，其中，去除所述第一栅极电介质包括：形成蚀刻掩模以覆盖所述第二栅极电介质，其中，所述蚀刻掩模在所述第一栅极电介质被去除时保护所述第二栅极电介质；以及去除所述蚀刻掩模。
示例4.根据示例1所述的方法，还包括：在形成所述第一栅极堆叠时，形成第三栅极堆叠，所述第三栅极堆叠包括：第三栅极电介质，在第二突出鳍的另外的中间部分上；以及第三栅极电极，在所述第三栅极电介质上；去除所述第三栅极电极以露出所述第三栅极电介质，其中，所述第三栅极电介质在所述第一栅极电介质被去除之后保留；以及在所述第三栅极电介质上形成第三替换栅极电极。
示例5.根据示例1所述的方法，还包括：在形成所述堆叠层之前：形成延伸到半导体衬底中的隔离区域；以及形成突出高于所述隔离区域的所述第一突出鳍，其中，所述隔离区域包括位于所述第一突出鳍的相对侧的部分。
示例6.根据示例1所述的方法，其中，整个所述第一突出鳍是半导体。
示例7.根据示例1所述的方法，其中，所述第一突出鳍包括：多个沟道层；以及多个牺牲膜，其中，所述多个沟道层和所述多个牺牲膜被交替地分配。
示例8.根据示例7所述的方法，还包括：从所述第一突出鳍的所述中间部分去除所述多个牺牲膜。
示例9.根据示例8所述的方法，其中，当从所述第一突出鳍的所述中间部分去除所述多个牺牲膜时，所述第一突出鳍的所述端部部分中的多个牺牲膜被所述第二栅极电介质保护而不被去除。
示例10.一种方法，包括：在突出鳍的第一部分和第二部分上同时形成第一虚设栅极堆叠和第二虚设栅极堆叠；同时去除所述第一虚设栅极堆叠的第一栅极电极和所述第二虚设栅极堆叠的第二栅极电极，以分别形成第一沟槽和第二沟槽；形成蚀刻掩模，其中，所述蚀刻掩模填充所述第一沟槽和所述第二沟槽；图案化所述蚀刻掩模以从所述第一沟槽去除所述蚀刻掩模；去除所述第一虚设栅极堆叠的第一虚设栅极电介质，其中，所述蚀刻掩模保护所述第一虚设栅极堆叠的第二栅极电介质不被去除；以及分别在所述第一沟槽和所述第二沟槽中形成第一替换栅极堆叠和第二替换栅极堆叠。
示例11.根据示例10所述的方法，其中，所述第二虚设栅极堆叠在所述突出鳍的第一侧壁表面、第二侧壁表面和第三侧壁表面上延伸，其中，所述第一侧壁表面和所述第二侧壁表面沿着所述突出鳍的纵向方向，并且所述第三侧壁表面沿着所述突出鳍的横向方向。
示例12.根据示例10所述的方法，其中，所述第一虚设栅极电介质包括具有第一厚度的第一氧化硅层，并且形成所述第一替换栅极堆叠包括：形成具有小于所述第一厚度的第二厚度的第二氧化硅层。
示例13.根据示例10所述的方法，还包括：在所述第一虚设栅极堆叠的相对侧形成源极区域和漏极区域；以及在所述第二虚设栅极堆叠的一侧形成另外的源极/漏极区域，其中，所述突出鳍在所述第二虚设栅极堆叠正下方的位置处终止。
示例14.根据示例10所述的方法，其中，形成所述蚀刻掩模包括：分配光致抗蚀剂。
示例15.一种结构，包括：隔离区域，延伸到半导体衬底中；突出鳍，在所述隔离区域的部分之间，其中，所述突出鳍突出高于所述隔离区域；第一栅极堆叠，包括：第一栅极电介质，在所述突出鳍的第一部分的第一侧壁和第一顶表面上，其中，所述第一栅极电介质具有第一厚度；以及第一栅极电极，在所述第一栅极电介质上；以及第二栅极堆叠，包括：第二栅极电介质，在所述突出鳍的第二部分的第二侧壁和第二顶表面上，其中，所述突出鳍在所述第二栅极堆叠的正下方终止，并且所述第二栅极电介质具有所述大于第一厚度的第二厚度；以及第二栅极电极，在所述第二栅极电介质上。
示例16.根据示例15所述的结构，其中，所述第一栅极电介质包括第一氧化物层以及位于所述第一氧化物层之上的第一高k电介质层，并且所述第二栅极电介质包括第二氧化物层以及位于所述第二氧化物层之上的第二高k电介质层，并且所述第二氧化物层比所述第一氧化物层更厚。
示例17.根据示例16所述的结构，其中，所述第一高k电介质层和所述第二高k电介质层由相同的材料形成。
示例18.根据示例16所述的结构，其中，所述第二厚度与所述第一厚度的比率在约4与约6之间的范围内。
示例19.根据示例15所述的结构，还包括：第一栅极间隔件，在所述第一栅极堆叠的侧壁上；以及第二栅极间隔件，在所述第二栅极堆叠的侧壁上，其中，所述第一栅极间隔件比所述第二栅极间隔件更薄。
示例20.根据示例15所述的结构，其中，所述第二栅极电介质进一步在所述突出鳍的所述第二部分的另外的侧壁上延伸，并且所述另外的侧壁沿着垂直于所述突出鳍的纵向方向的方向延伸。

Claims (10)

1.一种用于形成半导体器件的方法，包括：
在第一突出鳍上沉积堆叠层；
图案化所述堆叠层以形成下列项：
第一栅极堆叠，包括：
第一栅极电介质，在所述第一突出鳍的中间部分上；以及
第一栅极电极，在所述第一栅极电介质上；以及
第二栅极堆叠，包括：
第二栅极电介质，在所述第一突出鳍的端部部分上；以及
第二栅极电极，在所述第二栅极电介质上；
去除所述第一栅极电极和所述第二栅极电极以分别露出所述第一栅极电介质和所述第二栅极电介质；
去除所述第一栅极电介质，其中，所述第二栅极电介质在所述第一栅极电介质被去除之后保留；
在所述第一突出鳍的所述中间部分上形成替换栅极电介质；以及
分别在所述替换栅极电介质和所述第二栅极电介质上形成第一替换栅极电极和第二替换栅极电极。
2.根据权利要求1所述的方法，其中，所述替换栅极电介质被形成为具有比所述第一栅极电介质更小的厚度。
3.根据权利要求1所述的方法，其中，去除所述第一栅极电介质包括：
形成蚀刻掩模以覆盖所述第二栅极电介质，其中，所述蚀刻掩模在所述第一栅极电介质被去除时保护所述第二栅极电介质；以及
去除所述蚀刻掩模。
4.根据权利要求1所述的方法，还包括：在形成所述第一栅极堆叠时，形成第三栅极堆叠，所述第三栅极堆叠包括：
第三栅极电介质，在第二突出鳍的另外的中间部分上；以及
第三栅极电极，在所述第三栅极电介质上；
去除所述第三栅极电极以露出所述第三栅极电介质，其中，所述第三栅极电介质在所述第一栅极电介质被去除之后保留；以及
在所述第三栅极电介质上形成第三替换栅极电极。
5.根据权利要求1所述的方法，还包括：在形成所述堆叠层之前：
形成延伸到半导体衬底中的隔离区域；以及
形成突出高于所述隔离区域的所述第一突出鳍，其中，所述隔离区域包括位于所述第一突出鳍的相对侧的部分。
6.根据权利要求1所述的方法，其中，整个所述第一突出鳍是半导体。
7.根据权利要求1所述的方法，其中，所述第一突出鳍包括：
多个沟道层；以及
多个牺牲膜，其中，所述多个沟道层和所述多个牺牲膜被交替地分配。
8.根据权利要求7所述的方法，还包括：从所述第一突出鳍的所述中间部分去除所述多个牺牲膜。
9.一种用于形成半导体器件的方法，包括：
在突出鳍的第一部分和第二部分上同时形成第一虚设栅极堆叠和第二虚设栅极堆叠；
同时去除所述第一虚设栅极堆叠的第一栅极电极和所述第二虚设栅极堆叠的第二栅极电极，以分别形成第一沟槽和第二沟槽；
形成蚀刻掩模，其中，所述蚀刻掩模填充所述第一沟槽和所述第二沟槽；
图案化所述蚀刻掩模以从所述第一沟槽去除所述蚀刻掩模；
去除所述第一虚设栅极堆叠的第一虚设栅极电介质，其中，所述蚀刻掩模保护所述第一虚设栅极堆叠的第二栅极电介质不被去除；以及
分别在所述第一沟槽和所述第二沟槽中形成第一替换栅极堆叠和第二替换栅极堆叠。
10.一种半导体结构，包括：
隔离区域，延伸到半导体衬底中；
突出鳍，在所述隔离区域的部分之间，其中，所述突出鳍突出高于所述隔离区域；
第一栅极堆叠，包括：
第一栅极电介质，在所述突出鳍的第一部分的第一侧壁和第一顶表面上，其中，所述第一栅极电介质具有第一厚度；以及
第一栅极电极，在所述第一栅极电介质上；以及
第二栅极堆叠，包括：
第二栅极电介质，在所述突出鳍的第二部分的第二侧壁和第二顶表面上，其中，所述突出鳍在所述第二栅极堆叠的正下方终止，并且所述第二栅极电介质具有所述大于第一厚度的第二厚度；以及
第二栅极电极，在所述第二栅极电介质上。
CN202011172342.3A 2019-10-29 2020-10-28 鳍端部栅极结构及其形成方法 Pending CN112750771A (zh)

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