CN111200023A - 集成电路器件和形成集成电路结构的方法 - Google Patents

集成电路器件和形成集成电路结构的方法 Download PDF

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CN111200023A
CN111200023A CN201911128131.7A CN201911128131A CN111200023A CN 111200023 A CN111200023 A CN 111200023A CN 201911128131 A CN201911128131 A CN 201911128131A CN 111200023 A CN111200023 A CN 111200023A
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semiconductor
capping layer
layer
silicon
semiconductor fin
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CN111200023B (zh
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陈彦廷
赖柏宇
李健玮
宋学昌
李威养
杨丰诚
陈燕铭
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

形成集成电路结构的方法包括：形成突出高于隔离区域的顶面的半导体鳍。半导体鳍的顶部由第一半导体材料形成。在半导体鳍的顶面和侧壁上沉积半导体覆盖层。半导体覆盖层由与第一半导体材料不同的第二半导体材料形成。该方法还包括在半导体覆盖层上形成栅极堆叠件，在栅极堆叠件的侧壁上形成栅极间隔件，蚀刻栅极堆叠件的侧上的半导体鳍的部分，以形成延伸至半导体鳍中的第一凹槽，使半导体覆盖层凹进，以形成位于栅极间隔件的部分正下方的第二凹槽，以及实施外延以生长延伸至第一凹槽和第二凹槽中的外延区域。本发明的实施例还涉及集成电路器件。

Description

集成电路器件和形成集成电路结构的方法
技术领域
本发明的实施例涉及集成电路器件和形成集成电路结构的方法。
背景技术
晶体管是集成电路中的基建元件。在先前集成电路的开发中，形成鳍式场效应晶体管(FinFET)以代替平面晶体管。在FinFET的形成中，形成半导体鳍，并在该半导体鳍上形成伪栅极。在伪栅极堆叠件的侧壁上形成栅极间隔件。然后，去除该伪栅极堆叠件，以在栅极间隔件之间形成沟槽。随后，在该沟槽中形成替换栅极。
发明内容
本发明的实施例提供了一种形成集成电路结构的方法，所述方法包括：形成半导体鳍，所述半导体鳍突出高于所述半导体鳍的相对侧上的隔离区域的顶面，其中，所述半导体鳍的顶部由第一半导体材料形成；在所述半导体鳍的顶面和侧壁上沉积半导体覆盖层，其中，所述半导体覆盖层由与所述第一半导体材料不同的第二半导体材料形成；在所述半导体覆盖层上形成栅极堆叠件；在所述栅极堆叠件的侧壁上形成栅极间隔件；蚀刻所述半导体鳍的位于所述栅极堆叠件的侧上的部分，以形成延伸至所述半导体鳍中的第一凹槽；使所述半导体覆盖层凹进，以形成位于所述栅极间隔件的部分正下方的第二凹槽；以及实施外延以生长延伸至所述第一凹槽和所述第二凹槽中的外延区域。
本发明的另一实施例提供了一种形成集成电路结构的方法，包括：形成半导体鳍，其中，所述半导体鳍的顶部包括硅锗；在所述半导体鳍上沉积硅覆盖层；在所述硅覆盖层上形成伪栅极堆叠件；在所述栅极堆叠件的侧壁上形成栅极间隔件；实施第一蚀刻工艺以蚀刻所述硅覆盖层和部分所述半导体鳍，其中，在所述半导体鳍的侧上形成第一凹槽；实施第二蚀刻工艺以蚀刻所述硅覆盖层的位于所述栅极间隔件正下方的部分；以及实施外延以从所述半导体鳍和所述硅覆盖层生长外延区域。
本发明的又一实施例提供了一种集成电路器件，包括：隔离区域；半导体鳍，突出高于所述半导体鳍的相对侧上的所述隔离区域的部分，其中，所述半导体鳍的顶部由硅锗形成；硅覆盖层，位于所述半导体鳍上；栅极堆叠件，位于所述硅覆盖层上；栅极间隔件，位于所述栅极堆叠件的侧壁上，其中，所述栅极间隔件包括接触所述栅极堆叠件的内侧壁和与所述内侧壁相对的外侧壁，其中，所述硅覆盖层的位于所述栅极堆叠件的与所述栅极间隔件相同的侧上的边缘比所述栅极间隔件的外侧壁朝向所述栅极堆叠件凹进更多；以及源极/漏极区域，接触所述半导体鳍和所述硅覆盖层的边缘。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图8、图9A、图9B、图9C、图9D、图10A、图10B、图10C、图10D、图11、图12A、图12B、图12C、图12D和图13示出了根据一些实施例的鳍式场效应晶体管(FinFET)的形成中的中间阶段的截面图和立体图。
图14示出了根据一些实施例的用于形成FinFET的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据各个实施例，提供了晶体管及其形成方法。根据一些实施例而示出了晶体管形成中的中间阶段。还讨论了一些实施例的一些变型。贯穿各个视图和示例性实施例，相同的参考标号用于表示相同的元件。根据本发明的一些实施例，在半导体鳍上形成硅覆盖层，并在外延生长源极/漏极区域之前使硅覆盖层凹进，以增加外延源极/漏极区域和沟道区域之间的界面面积。因此，可减小电流拥挤现象。应该理解，尽管鳍式场效应晶体管(FinFET)用作讨论本发明的概念的示例性实施例，但本发明的概念也可容易地应用于其它类型的晶体管，诸如平面晶体管。
图1至图8、图9A、图9B、图9C、图10A、图10B、图10C、图10D、图11、图12A、图12B、图12C、图12D和图13示出了根据一些实施例的鳍式场效应晶体管(FinFET)的形成中的中间阶段的截面图和立体图。如图14所示的工艺流程200中也示意性地反映出了这些附图中所示的工艺。
在图1中，提供了作为晶圆10的一部分的衬底20。衬底20可以是半导体衬底，诸如块状半导体衬底、绝缘体上半导体(SOI)衬底等，其可以是掺杂(例如，掺杂有p型或n型掺杂剂)或未掺杂的。半导体衬底20可以是诸如硅晶圆的晶圆10的一部分。通常，SOI衬底是形成在绝缘层上的半导体材料层。例如，绝缘层可以是埋氧(BOX)层、氧化硅层等。绝缘层设置在衬底上，一般设置在硅或玻璃衬底上。还可使用其它衬底，诸如多层或梯度衬底。在一些实施例中，半导体衬底20的半导体材料可包括硅；锗；化合物半导体(包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟)；合金半导体(包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GalnP和/或GalnAsP)；或它们的组合。
进一步参考图1，在衬底20中形成阱区域22。相应的工艺示出为如图14所示的工艺流程200中的工艺202。根据本发明的一些实施例，阱区域22是通过将n型杂质(其可以是磷、砷、锑等)注入到衬底20中而形成的n型阱区域。根据本发明的其它实施例，阱区域22是通过将p型杂质(其可以是硼、铟等)注入到衬底20中而形成的p型阱区域。所得的阱区域22可延伸至衬底20的顶面中。n型或p型杂质浓度可等于或小于1018cm-3，诸如在约1017cm-3和约1018cm-3之间的范围内。
参考图2，凹槽29形成为从衬底20的顶面延伸至衬底20中。为了形成凹槽29，首先形成并且图案化衬垫氧化物层28和硬掩模层30。衬垫氧化物层28可以是由氧化硅形成的薄膜。根据本发明的一些实施例，在热氧化工艺中形成衬垫氧化物层28，其中将半导体衬底20的顶表面层氧化。衬垫氧化物层28用作半导体衬底20和硬掩模层30之间的粘合层。衬垫氧化物层28还可用作用于蚀刻硬掩模层30的蚀刻停止层。根据本发明的一些实施例，例如，使用低压化学气相沉积(LPCVD)来由氮化硅形成硬掩模层30。根据本发明的一些实施例，通过硅的热氮化或等离子体增强化学气相沉积(PECVD)形成硬掩模层30。在硬掩模层30上形成光刻胶(未示出)，然后图案化光刻胶。随后，使用图案化的光刻胶作为蚀刻掩模来图案化硬掩模层30，以形成如图2所示的图案。
接下来，将图案化的硬掩模层30用作蚀刻掩模，以蚀刻衬垫氧化物层28和半导体衬底20。因此，形成延伸至半导体衬底20中的凹槽29。相应的工艺示出为如图14所示的工艺流程200中的工艺204。根据本发明的一些实施例，凹槽29的底部高于阱区域22的底面。在下文中，将半导体衬底20中位于相邻凹槽26之间的部分称为半导体带26。将半导体衬底20中低于凹槽29的底部的部分成为半导体衬底20。
然后，在沟槽29中填充介电材料，如图3所示。实施诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺，以去除介电材料的过量的部分，并将介电材料的剩余部分称为STI区域24。相应的工艺示出为如图14所示的工艺流程200中的工艺206。STI区域24可包括衬垫电介质24A，该衬垫电介质可以是通过衬底20的表面层的热氧化所形成的热氧化物。衬垫电介质也可以是沉积的介电层，诸如氧化硅层、氮化硅层等。形成方法可包括原子层沉积(ALD)、高密度等离子体化学气相沉积(HDPCVD)、化学气相沉积(CVD)等。STI区域24还可包括位于衬垫电介质24A上方的介电材料24B，其中，可使用可流动化学气相沉积(FCVD)、旋涂等来形成介电材料24B。根据一些实施例，介电材料24B可包括氧化硅。
硬掩模30的顶面和STI区域24的顶面可基本彼此齐平。半导体带26位于相邻的STI区域24之间。根据本发明的一些实施例，用不同于半导体带26的材料的另一半导体材料来替换半导体带26的顶部，从而形成半导体带32，如图4所示。半导体带32的形成可包括蚀刻半导体带26的顶部以形成凹槽，以及实施外延工艺以在凹槽中再生长另一半导体材料。然后，实施诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺，以去除外延半导体材料中高于STI区域24的过量部分，并将半导体材料的剩余部分形成半导体带32。因此，半导体带32由不同于衬底20的材料的材料形成。根据一些实施例，半导体带32由硅锗、硅碳或III-V族化合物半导体材料形成。根据本发明的一些实施例，其中半导体带32由硅锗形成或包含硅锗，锗原子百分比可高于约30％，并可在约30％和约100％之间的范围内。
根据本发明的一些实施例，在外延期间，将半导体带32原位掺杂有与阱区域22的导电类型相同的杂质。此外，原位掺杂的杂质的浓度可与阱区域22处于相同的范围。例如，n型或p型杂质浓度可等于或小于1018cm-3，诸如在约1017cm-3和约1018cm-3之间的范围内。根据本发明的可选实施例，可以在形成半导体带32之后实施用于形成阱区域22的注入工艺，而不是在图1所示的工艺中实施该工艺。
根据本发明的其它实施例，未实施用另一材料替换半导体带26的顶部的替换工艺，且所示半导体带26是原衬底20的一部分，并且因此，半导体带26和32的材料与衬底20的材料相同。
参考图5，使STI区域24凹进，使得半导体带32的顶部突出高于STI区域24的剩余部分的顶面24A，以形成突出鳍36。相应的工艺示出为如图14所示的工艺流程200中的工艺208。可使用干蚀刻工艺来实施蚀刻，其中，例如使用HF3和NH3来作为蚀刻气体。在蚀刻工艺期间，可生成等离子体。还可包括氩气。根据本发明的可选实施例，使用湿蚀刻工艺来实施STI区域24的凹进。例如，蚀刻化学物质可包括稀释的HF。
根据本发明的一些实施例，凹进的STI区域24的顶面低于半导体带32与相应的下面的半导体带26之间的界面。根据本发明的可选实施例，凹进的STI区域24的顶面与半导体带32和相应的下面的半导体带26之间的界面齐平或高于半导体带32和相应的下面的半导体带26之间的界面。
在上面所示实施例中，可通过任何合适的方法图案化鳍。例如，可使用包括双图案化或多图案化工艺的一个或多个光刻工艺图案化鳍。通常，双图案化或多图案化工艺结合光刻和自对准工艺，从而允许产生具有例如小于使用单一直接光刻工艺可获得的间距的图案。例如，在一个实施例中，在衬底上方形成牺牲层，并使用光刻工艺图案化牺牲层。使用自对准工艺在图案化的牺牲层旁边形成间隔件。然后去除牺牲层，并且随后可使用剩余的间隔件或芯轴来图案化鳍。
图6示出了半导体覆盖层40的沉积。相应的工艺示出为如图14所示的工艺流程200中的工艺210。将半导体覆盖层40形成为共形层，其中水平部分的厚度等于或基本等于(例如，差值小于约10％)垂直部分的厚度。半导体覆盖层40的形成是选择性的，使得其可生长在诸如半导体带32的半导体材料上，而不生长在STI区域24上。例如，这可通过向诸如硅烷(SiH4)和/或二氯硅烷(DCS)的沉积气体中添加蚀刻气体来实现。可使用诸如CVD或ALD的共形沉积方法来实施沉积工艺。根据本发明的一些实施例，半导体覆盖层40由硅形成，其中可不含或基本上不含其它元素，诸如锗、碳等。例如，半导体覆盖层40中硅的原子百分比可大于约95％或99％。根据其它实施例，半导体覆盖层40由与半导体带32的材料不同的其它半导体材料形成。例如，半导体覆盖层40可由硅锗形成，其中锗浓度比半导体带32的锗浓度低。半导体覆盖层40可外延生长为晶体半导体层，或形成为多晶半导体层，例如，这可通过调节沉积工艺中的温度和生长速率来实现。半导体覆盖层40可具有大于约
Figure BDA0002277494550000071
的厚度，且其厚度可在约
Figure BDA0002277494550000072
和约
Figure BDA0002277494550000073
之间的范围内。
根据一些实施例，半导体覆盖层40是本征层，该层既未在沉积中原位掺杂有p型杂质，也未原位掺杂有n型杂质。根据可选实施例，半导体覆盖层40原位掺杂有p型杂质或n型杂质，且其中掺杂浓度低于阱区域22中的掺杂浓度。例如，掺杂浓度可低于约1017cm-3，或低于约1015cm-3。如果在沉积工艺期间进行原位掺杂，则半导体覆盖层40的导电类型与阱区域22的导电类型相同。
参考图7，形成了伪栅极介电层42、伪栅电极44和硬掩模46。相应的工艺示出为如图14所示的工艺流程200中的工艺212。伪栅极介电层42可由氧化硅或其它介电材料形成，并可通过沉积形成，使得其接触突出鳍36的侧壁和顶面。例如，可使用多晶硅形成伪栅电极44，并也可使用其它材料。在伪栅电极44上方形成一个(或多个)硬掩模层46。硬掩模层46可由氮化硅、氧化硅、碳氮化硅或其多层形成。在整个说明书中，硬掩模层46和伪栅电极44统称为伪栅极堆叠件48。伪栅极堆叠件48可横跨在单个或多个突出鳍36和/或STI区域24上方。伪栅极堆叠件48还具有垂直于突出鳍36的长度方向的长度方向。可通过在伪栅极介电层42上方沉积毯式伪栅电极层、在毯式伪栅电极层上方沉积毯式硬掩模层、以及然后对毯式硬掩模层和毯式伪栅电极层实施各向异性蚀刻工艺来形成伪栅极堆叠件48。根据本发明的一些实施例，蚀刻停止在用作蚀刻停止层的伪栅极介电层42上。根据本发明的一些实施例，还蚀刻伪栅极介电层42，且伪栅极堆叠件48还包括伪栅极介电层42的剩余部分。因此，暴露了STI区域24的顶面。
接下来，在伪栅极堆叠件48的侧壁和突出鳍36的侧壁上分别形成栅极间隔件50和鳍间隔件52。相应的工艺示出为如图14所示的工艺流程200中的工艺214。根据本发明的一些实施例，栅极间隔件50和鳍间隔件52由介电材料形成，诸如氮化硅、碳氮化硅等，并可具有单层结构或包括多个介电层的多层结构。形成工艺可包括沉积介电间隔件层、以及实施各向异性蚀刻工艺，以去除伪栅极堆叠件48和突出鳍36的顶面上的介电间隔件层的水平部分。该蚀刻也可实施为使用伪栅极介电层42作为蚀刻停止层。
图9A、图9B、图9C、图10A、图10B和图10C示出了伪栅极介电层42的蚀刻、半导体覆盖层40和突出鳍36的凹进以及半导体覆盖层40的进一步横向凹进的中间阶段的立体图和截面图。在图9A、图9B、图9C、图10A、图10B和图10C中，附图标号包括字符“A”、“B”和字符“C”。字符“A”表示示出立体图的相应的附图。字符“B”表示示出相应立体图的参考截面“B-B”的相应附图。字符“C”表示示出该结构的顶视图的相应附图，并且顶视图示出了包含线C-C的水平面处的截面图。
首先实施各向异性蚀刻工艺，以蚀刻如图8所示的伪栅极介电层42的水平部分。因此，暴露了半导体覆盖层40。接下来，蚀刻半导体覆盖层40和突出鳍36。图9A、图9B和图9C示出了所得的结构。根据本发明的一些实施例，使用NF3和NH3的混合气体或HF和NH3的混合气体来蚀刻伪栅极介电层42。可使用氟基和/或氯基气体(诸如C2F6、CF4、HBr、Cl2和O2的混合物、HBr、Cl2和O2的混合物或HBr、Cl2、O2和CF2的混合物等)来蚀刻半导体覆盖层40(其可以是其它材料形成硅覆盖层或半导体覆盖层)。可使用HBr和/或含氟蚀刻气体(诸如C2F6、CF4、CF2Cl2等)来蚀刻突出鳍36。相应的工艺示出为如图14所示的工艺流程200中的工艺216。在下文中将由突出鳍36中的去除部分留下的空间称为凹槽54(在图9B中标记)。根据本发明的一些实施例，凹槽54的底面高于STI区域24的顶面。此外，凹槽54的底面可以高于半导体带26与半导体带32之间的界面。因此，半导体带32的一些底部可留在凹槽54的正下方。根据本发明的一些实施例，凹槽54的底面低于鳍间隔件52。
如图9A所示，在凹槽54的底部处，半导体覆盖层40的顶面40TS可与半导体带32的顶面32TS齐平或比半导体带32的顶面32TS高。根据本发明的一些实施例，顶面40TS和32TS可以是倾斜的。例如，在凹槽54的底部处，整个倾斜的顶面40TS可以高于整个顶面32TS。根据可选实施例，顶面40TS可以包括比整个顶面32TS高的第一部分，以及与倾斜的顶面32TS的部分处于相同的层级的第二部分。
图9B示出了图9A中的参考截面B-B。图9B示出了相邻的伪栅极堆叠件48，而可存在更多并行分配的伪栅极堆叠件48。蚀刻半导体覆盖层40和半导体带32的位于伪栅极堆叠件48之间的部分，并将半导体覆盖层40和半导体带32的位于伪栅极堆叠件48正下方的部分保留为相应的FinFET的沟道区域。由于各向异性蚀刻，半导体覆盖层40的边缘与栅极间隔件50的相应边缘齐平。根据本发明的一些实施例，半导体带32的顶部具有与栅极间隔件50的相应边缘齐平的边缘，而半导体带32的底部可具有弯曲的顶面，该弯曲的顶面会聚到相邻的栅极间隔件50之间的中心线。
图9C示出了图9A中结构的一部分的顶视图，其中，顶视图在接近并略低于半导体带32的顶面水平的水平面处获得。例如，如图9B所示，可从水平面57获得顶视图，其中水平面57接近突出鳍36的顶面36’并比突出鳍36的顶面36’略低高度差△H，其中，高度差△H在例如约5nm和约10nm之间的范围内。图9B中的水平面57与线C-C的水平面相同。在该水平面处，如图9C所示，半导体带32的左边缘(突出鳍36的一部分)与半导体覆盖层40的左边缘和栅极间隔件50的左边缘齐平(对准)，半导体带32和突出鳍36的右边缘与半导体覆盖层40的右边缘和栅极间隔件50的右边缘齐平(对准)。
图9C示出了根据一些实施例的结构，其中，如图8所示，当未图案化介电层42时，形成栅极间隔件50，并且因此如图9C所示，栅极电介质42的左边缘和右边缘也分别与半导体覆盖层40的左边缘和右边缘齐平。图9D示出了根据可选实施例的结构，其中，当形成栅极间隔件50时，也将栅极介电层42图案化。因此，栅极电介质42的左边缘与左栅极间隔件50的左边缘齐平，并且栅极电介质42的右边缘与右间隔件50的右边缘齐平。
在蚀刻工艺之后，实施光刻胶去除工艺，该光刻胶用于覆盖相应晶圆的一些区域，同时使一些其它区域(诸如图示的FinFET区域)暴露。接下来，实施蚀刻后清洁工艺，以去除先前工艺中产生的副产物。根据本发明的一些实施例，蚀刻后清洁可包括湿蚀刻工艺，其可使用稀释的氟化氢(DHF)、包含NH4OH、H2O2和H2O的化学溶液(有时称为标准清洁1(SC1)溶液)和/或包含HCl、H2O2和H2O的化学溶液(有时称为标准清洁2(SC2)溶液)来实施该湿蚀刻工艺，并因此去除暴露的半导体区域表面上的残留物和颗粒。在蚀刻后清洁工艺中，基本上不蚀刻并不损坏半导体覆盖层40、栅极间隔件50和半导体带32。因此，蚀刻后清洁工艺之后所得的结构如图9A、图9B和图9C所示。
接下来，使半导体覆盖层40横向凹进，以形成凹槽56，并且图10A、图10B和图10C示出了所得结构。相应的工艺示出为如图14所示的工艺流程200中的工艺218。根据本发明的一些实施例，通过各向同性蚀刻工艺实施横向凹进工艺，该工艺可以是或包括干蚀刻工艺或湿蚀刻工艺。选择蚀刻化学物质(蚀刻气体或蚀刻溶液)，使得其蚀刻半导体覆盖层40，而不蚀刻半导体带32、栅极介电层42、栅极间隔件50和硬掩模46。根据本发明的一些实施例，蚀刻选择性，即半导体覆盖层40的蚀刻速率与半导体带32(突出鳍36的一部分)的蚀刻速率之间的比率，高于约10，并可高于约20、50或更高。根据本发明的一些实施例，采用干蚀刻工艺，并且蚀刻气体包括氢气(H2)和He气体。例如，晶圆的温度(和硅覆盖层40的温度)可高于约200度，并可在约200度和约400度之间的范围内。在高温下，H2气体与硅反应。由于GeH的键能高于SiH的键能，因此锗的损耗比小于硅，这使得SiGe的蚀刻速率高于硅的蚀刻速率。
图10B示出了图10A中的垂直参考截面B-B。图10B示出了从栅极间隔件50的相应外边缘和下面的半导体带32/鳍36的部分的相应边缘横向凹进半导体覆盖层40。可控制该凹进工艺，使得凹进距离D1不大于栅极间隔件50的厚度T1。凹进距离D1可大于约1nm并小于约2nm。此外，比率D1/T1大于0，并可等于或小于1.0。例如，比率D1/T1可在约0.2和约1.0之间的范围内。
图10C示出了图10A中结构的部分的顶视图，其中，顶视图在接近并略低于半导体带的顶面水平的水平面处获得。在图10B中，该水平面也被标记为水平面57。凹进的半导体覆盖层40的边缘的可能位置由如图10C所示的虚线53标记。在栅极间隔件50和半导体带32/突出鳍36之间形成凹槽56，半导体带32/突出鳍36形成相应FinFET的沟道区域。
图10D示出了根据可选实施例的图10A中的结构的部分的顶视图。该结构类似于图10C所示的结构，除了栅极电介质42的左边缘和右边缘不延伸至伪栅电极44的外边缘之外。相反地，栅极电介质42的左边缘与左栅极间隔件50的左边缘齐平，且栅极电介质42的右边缘与右间隔件50的右边缘齐平。左栅极间隔件50的左边缘和右栅极间隔件的右边缘也被称为栅极间隔件50的外边缘。
接下来，通过在凹槽56(图10B和10C)和凹槽54(图10B)中选择性地生长(通过外延)半导体材料来形成外延区域58(源极/漏极区域)，从而得到图11中的结构。相应的工艺示出为如图14所示的工艺流程200中的工艺220。取决于所得FinFET是p型FinFET还是n型FinFET，可在外延进行时进行p型杂质或n型杂质的原位掺杂。例如，当所得FinFET是p型FinFET时，可生长硅锗硼(SiGeB)或硅硼(SiB)。相反地，当所得FinFET是n型FinFET时，可生长硅磷(SiP)或硅碳磷(SiCP)。根据本发明的可选实施例，外延区域58包括III-V族化合物半导体，诸如，GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、它们的组合或它们的多层。在填充凹槽54和56之后，外延区域58的进一步外延生长使得外延区域58水平扩展，并可形成小平面。外延区域58的进一步生长也可使相邻的外延区域58彼此合并。根据本发明的一些实施例，外延区域58的形成可在外延区域58的顶面仍然是波状时完成，或可在合并的外延区域58的顶面变为平面时完成，这些通过在外延区域58上进一步生长来实现，如图11所示。
在外延工艺之后，外延区域58可进一步注入有p型和n型杂质，以形成源极和漏极区域，这些区域也使用参考标号58来表示。根据本发明的可选实施例，当外延区域58在外延期间原位掺杂有p型或n型杂质时，则跳过注入工艺。
图12A示出了在形成接触蚀刻停止层(CESL)60和层间电介质(ILD)62之后的结构的截面图。CESL 60可由氧化硅、氮化硅、碳氮化硅等形成，并可使用CVD、ALD等来形成。ILD62可包括使用例如FCVD、旋涂、CVD或其它沉积方法而形成的介电材料。ILD 62可由含氧介电材料形成，该材料可以是基于氧化硅的材料，诸如，正硅酸乙酯(TEOS)氧化物、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等。可实施诸如CMP工艺或机械研磨工艺的平坦化工艺，以使ILD 62、伪栅极堆叠件48和栅极间隔件50的顶面彼此齐平。如图12A所示，外延区域58延伸在栅极间隔件50的正下方，以接触半导体覆盖层40。
图12B示出了图12A中的结构的顶视图，其中，顶视图在接近并略低于突出鳍36的顶面水平的水平面处获得。在图12A中，该水平面也被标记为水平面57。另外，图12B示出了图11中的参考截面12B-12B。外延源极/漏极区域58与其接触的突出鳍36之间的界面长度等于L1+2D1。作为比较，如果未使半导体覆盖层40凹进，则外延区域58与其接触的突出鳍36之间的界面长度将等于L1。因此，使半导体覆盖层40凹进使得外延源极/漏极区域58与其接触的突出鳍36之间的接触面积增加。由于半导体覆盖层40未被掺杂或是轻掺杂的，因此其薄层电阻高，且其导通沟道电流的能力受到限制。因此，增加接触面积使得电流拥挤现象减少。图12C示出了类似于图12B所示的结构的结构的部分的顶视图，除了栅极电介质42的右边缘不延伸至伪栅电极44的外边缘之外。相反地，栅极电介质42的左边缘与左栅极间隔件50的左边缘齐平，且栅极电介质42的右边缘与右间隔件50的右边缘齐平。
图12D示出了类似于图12B所示结构的结构的部分的顶视图，除了从不同的水平面处获得图12B和图12D中的顶视图。例如，图12D所示的顶视图从图11和图12A所示的水平面57’处获得，该水平面57’低于水平面57。另外，图12D示出了图11中的参考截面12D-12D。如图12B和图12D所示，当水平面较低时，半导体带32中的未掺杂部分可更多地伸出超出栅极间隔件50的外边缘。此外，相应的半导体覆盖层40的边缘也可伸出超过栅极间隔件50的外边缘。在不同的水平面处，相应的半导体覆盖层40的边缘仍相对于半导体带32凹进。凹进的半导体覆盖层40的边缘的可能位置由虚线53’标记。
图13示出了后续工艺，该工艺包括用替换栅极堆叠件来替换伪栅极堆叠件48(图12A)、形成源极/漏极硅化物区域，以及形成源极/漏极接触插塞。如图13所示，形成替换栅极堆叠件80，该堆叠件包括栅极电介质64和栅电极70。相应的工艺示出为如图14所示的工艺流程200中的工艺222。栅极堆叠件80的形成包括形成/沉积多个层，以及然后实施诸如CMP工艺或机械研磨工艺的平坦化工艺。根据本发明的一些实施例，栅极电介质64包括作为其下部的界面层(IL)61。IL 61形成在突出鳍36的暴露表面上。IL 61可包括氧化物层，诸如氧化硅层，该氧化物层通过突出鳍36的热氧化、化学氧化工艺或沉积工艺来形成。栅极电介质64还可包括形成在IL 61上方的高k介电层63。高k介电层63可包括高k介电材料，诸如，HfO2、ZrO2、HfZrOx、HfSiOx、HfSiON、ZrSiOx、HfZrSiOx、A12O3、HfAlOx、HfAIN、ZrAlOx、La2O3、TiO2、Yb2O3、氮化硅等。高k介电材料的介电常数(k值)高于3.9，并可高于约7.0。高k介电层63形成为共形层，并在突出鳍36的侧壁和栅极间隔件50的侧壁上延伸。根据本发明的一些实施例，使用ALD或CVD形成高k介电层63。
栅电极70可包括多个子层，这些子层可包括粘合层72(例如，TiN)、功函层74，以及额外的导电材料和层76。
图13还示出了源极/漏极硅化物区域82和源极/漏极接触插塞84的形成。相应的工艺示出为如图14所示的工艺流程200中的工艺224。为了形成这些部件，首先通过蚀刻至ILD62和CESL 60中来形成接触开口，以露出源极/漏极区域58。然后形成延伸至ILD 62和CESL60中的硅化物区域82和源极/漏极接触插塞84。该形成工艺可包括将金属层沉积到接触插塞中，实施退火以使金属层和源极/漏极区域58反应来形成硅化物区域82，以及用诸如钨或钴的导电材料填充接触开口的剩余部分以形成接触插塞84。因此形成FinFET 86，该FinFET可以是根据一些实施例的p型FinFET。根据本发明的可选实施例，FinFET 86是n型FinFET。
本发明的实施例具有一些有利特征。通过使形成在半导体鳍上的半导体覆盖层(诸如，硅覆盖层)凹进，可增加外延源极/漏极区域与所得FinFET的沟道区域之间的界面面积。由于外延源极/漏极区域比半导体覆盖层更重地掺杂有p型或n型杂质，所以外延源极/漏极区域和半导体鳍之间的接触电阻低于半导体覆盖层和半导体鳍之间的接触电阻。减小了电流拥挤效应。
根据本发明的一些实施例，形成集成电路结构的方法，包括：形成突出高于半导体鳍的相对侧上的隔离区域的顶面的半导体鳍，其中，半导体鳍的顶部由第一半导体材料形成；在半导体鳍的顶面和侧壁上沉积半导体覆盖层，其中，半导体覆盖层由与第一半导体材料不同的第二半导体材料形成；在半导体覆盖层上形成栅极堆叠件；在栅极堆叠件的侧壁上形成栅极间隔件；蚀刻栅极堆叠件的侧上的半导体鳍的部分，以形成延伸至半导体鳍中的第一凹槽；使半导体覆盖层凹进，以形成位于栅极间隔件的部分正下方的第二凹槽；以及实施外延以生长延伸至第一凹槽和第二凹槽中的外延区域。在实施例中，第一半导体材料包括硅锗，并且沉积半导体覆盖层包括生长硅层。在实施例中，在使半导体覆盖层凹进的工艺中，未蚀刻半导体鳍和栅极间隔件。在实施例中，使半导体覆盖层凹进包括各向同性蚀刻工艺。在实施例中，各向同性蚀刻工艺包括干蚀刻工艺。在实施例中，该方法还包括在使半导体覆盖层凹进之前实施湿清洁工艺，其中，湿清洁工艺和使半导体覆盖层凹进是不同的工艺。在实施例中，该方法还包括蚀刻半导体带的位于隔离区域之间的部分；以及用第一半导体材料填充由半导体带的蚀刻部分留下的空间；以及使隔离区域凹进，其中，第一半导体材料突出高于隔离区域的剩余部分。在实施例中，半导体覆盖层形成为本征层。
根据本发明的一些实施例，形成集成电路结构的方法包括：形成半导体鳍，其中，半导体鳍的顶部包括硅锗；在半导体鳍上沉积硅覆盖层；在硅覆盖层上形成伪栅极堆叠件；在栅极堆叠件的侧壁上形成栅极间隔件；实施第一蚀刻工艺以蚀刻硅覆盖层和部分半导体鳍，其中，在半导体鳍的侧上形成第一凹槽；实施第二蚀刻工艺以蚀刻硅覆盖层的位于栅极间隔件正下方的部分；以及实施外延以从半导体鳍和硅覆盖层生长外延区域。在实施例中，硅覆盖层沉积为本征层。在实施例中，半导体鳍具有第一n型杂质浓度，并且硅覆盖层具有第二n型杂质浓度，第二n型杂质浓度低于第一n型杂质浓度，并且外延区域是p型。在实施例中，在第二蚀刻工艺之前，将硅覆盖层的边缘与半导体鳍的边缘齐平，并在第二蚀刻工艺之后，使硅覆盖层比半导体鳍的边缘凹进更多。在实施例中，在第二蚀刻工艺中，使硅覆盖层凹进大于约1nm的距离。在实施例中，第二蚀刻工艺包括各向同性干蚀刻工艺。
根据本发明的一些实施例，集成电路器件包括：隔离区域；半导体鳍，突出高于半导体鳍的相对侧上的隔离区域的部分，其中，半导体鳍的顶部由硅锗形成；硅覆盖层，位于半导体鳍上；栅极堆叠件，位于硅覆盖层上；栅极间隔件，位于栅极堆叠件的侧壁上，其中，栅极间隔件包括接触栅极堆叠件的内侧壁和相对于内侧壁的外侧壁，其中，硅覆盖层的位于栅极堆叠件的与栅极间隔件相同的侧上的边缘比栅极间隔件的外侧壁朝向栅极堆叠件凹进更多；以及源极/漏极区域，接触半导体鳍和硅覆盖层的边缘。在实施例中，半导体鳍是n型的，硅覆盖层的n型杂质浓度低于半导体鳍的n型杂质浓度。在实施例中，硅覆盖层比栅极间隔件的外侧壁朝向栅极堆叠件凹进多于大于约1nm的距离。在实施例中，硅覆盖层比半导体鳍与源极/漏极区域之间的界面朝向栅极堆叠件凹进更多，其中，该界面在接近和低于半导体鳍的顶面的水平面处测量。在实施例中，硅覆盖层的边缘与栅极间隔件的部分重叠，并且栅极间隔件的部分位于栅极间隔件的外边缘和内边缘之间。在实施例中，硅覆盖层的边缘比栅极间隔件的外侧壁朝向栅极堆叠件凹进多于凹进距离，并且该凹进距离与栅极间隔件的厚度的比率在约0.2和约1.0之间的范围内。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成集成电路结构的方法，所述方法包括：
形成半导体鳍，所述半导体鳍突出高于所述半导体鳍的相对侧上的隔离区域的顶面，其中，所述半导体鳍的顶部由第一半导体材料形成；
在所述半导体鳍的顶面和侧壁上沉积半导体覆盖层，其中，所述半导体覆盖层由与所述第一半导体材料不同的第二半导体材料形成；
在所述半导体覆盖层上形成栅极堆叠件；
在所述栅极堆叠件的侧壁上形成栅极间隔件；
蚀刻所述半导体鳍的位于所述栅极堆叠件的侧上的部分，以形成延伸至所述半导体鳍中的第一凹槽；
使所述半导体覆盖层凹进，以形成位于所述栅极间隔件的部分正下方的第二凹槽；以及
实施外延以生长延伸至所述第一凹槽和所述第二凹槽中的外延区域。
2.根据权利要求1所述的方法，其中，所述第一半导体材料包括硅锗，并且沉积所述半导体覆盖层包括生长硅层。
3.根据权利要求1所述的方法，其中，在使所述半导体覆盖层凹进中，未蚀刻所述半导体鳍和所述栅极间隔件。
4.根据权利要求1所述的方法，其中，使所述半导体覆盖层凹进包括各向同性蚀刻工艺。
5.根据权利要求4所述的方法，其中，所述各向同性蚀刻工艺包括干蚀刻工艺。
6.根据权利要求1所述的方法，还包括，在使所述半导体覆盖层凹进之前实施湿清洁工艺，其中，所述湿清洁工艺和使所述半导体覆盖层凹进是不同的工艺。
7.根据权利要求1所述的方法，还包括：
蚀刻所述半导体带的位于所述隔离区域之间的部分；以及
用所述第一半导体材料填充由所述半导体带的蚀刻部分留下的空间；以及
使所述隔离区域凹进，其中，所述第一半导体材料突出高于所述隔离区域的剩余部分。
8.根据权利要求1所述的方法，其中，所述半导体覆盖层形成为本征层。
9.一种形成集成电路结构的方法，包括：
形成半导体鳍，其中，所述半导体鳍的顶部包括硅锗；
在所述半导体鳍上沉积硅覆盖层；
在所述硅覆盖层上形成伪栅极堆叠件；
在所述栅极堆叠件的侧壁上形成栅极间隔件；
实施第一蚀刻工艺以蚀刻所述硅覆盖层和部分所述半导体鳍，其中，在所述半导体鳍的侧上形成第一凹槽；
实施第二蚀刻工艺以蚀刻所述硅覆盖层的位于所述栅极间隔件正下方的部分；以及
实施外延以从所述半导体鳍和所述硅覆盖层生长外延区域。
10.一种集成电路器件，包括：
隔离区域；
半导体鳍，突出高于所述半导体鳍的相对侧上的所述隔离区域的部分，其中，所述半导体鳍的顶部由硅锗形成；
硅覆盖层，位于所述半导体鳍上；
栅极堆叠件，位于所述硅覆盖层上；
栅极间隔件，位于所述栅极堆叠件的侧壁上，其中，所述栅极间隔件包括接触所述栅极堆叠件的内侧壁和与所述内侧壁相对的外侧壁，其中，所述硅覆盖层的位于所述栅极堆叠件的与所述栅极间隔件相同的侧上的边缘比所述栅极间隔件的外侧壁朝向所述栅极堆叠件凹进更多；以及
源极/漏极区域，接触所述半导体鳍和所述硅覆盖层的边缘。
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