TWI724611B - 積體電路裝置及其形成方法 - Google Patents

積體電路裝置及其形成方法 Download PDF

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TWI724611B
TWI724611B TW108140242A TW108140242A TWI724611B TW I724611 B TWI724611 B TW I724611B TW 108140242 A TW108140242 A TW 108140242A TW 108140242 A TW108140242 A TW 108140242A TW I724611 B TWI724611 B TW I724611B
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Taiwan
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semiconductor
cap layer
semiconductor fin
silicon
forming
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TW108140242A
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TW202038330A (zh
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陳彥廷
賴柏宇
李健瑋
宋學昌
李威養
楊豐誠
陳燕銘
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台灣積體電路製造股份有限公司
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    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate

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Abstract

一方法包含形成半導體鰭突出高於隔離區的頂表面，半導體鰭的頂部由第一半導體材料形成，在半導體鰭的頂表面和側壁上形成半導體蓋層，半導體蓋層由不同於第一半導體材料的第二半導體材料形成。此方法更包含在半導體蓋層上形成閘極堆疊物，在閘極堆疊物的側壁上形成閘極間隙壁，蝕刻在閘極堆疊物的一側上的半導體鰭的一部分，以形成第一凹口延伸至半導體鰭中，將半導體蓋層凹陷，以在閘極間隙壁正下方形成第二凹口，以及進行磊晶成長以形成磊晶區延伸至第一凹口和第二凹口中。

Description

積體電路裝置及其形成方法
本發明實施例係有關於半導體技術，且特別是有關於積體電路裝置及其形成方法。
電晶體為積體電路中的基礎建構元件。在積體電路的先前發展中，形成鰭式場效電晶體(Fin Field-Effect Transistors，FinFETs)以取代平面電晶體。在形成鰭式場效電晶體中，形成半導體鰭，且虛設閘極形成於半導體鰭上。閘極間隙壁形成於虛設閘極堆疊物的側壁上。接著，移除虛設閘極堆疊物以在閘極間隙壁之間形成溝槽。接著，在溝槽中形成取代閘極。
在一些實施例中，提供積體電路裝置的形成方法，此方法包含形成半導體鰭突出高於複數個隔離區的頂表面，複數個隔離區位於半導體鰭的兩側，其中半導體鰭的頂部由第一半導體材料形成；在半導體鰭的頂表面和側壁上沉積半導體蓋層，其中半導體蓋層由不同於第一半導體材料的第二半導體材料形成；在半導體蓋層上形成閘極堆疊物；在閘極堆疊物的側壁上形成閘極間隙壁；蝕刻在閘極堆疊物的一側上的半導體鰭的一部分，以形成第一凹口延伸至半導體鰭中；將半導體蓋層凹陷，以在閘極間隙壁正下方形成第二凹口；以 及進行磊晶成長以形成磊晶區延伸至第一凹口和第二凹口中。
在一些其他實施例中，提供積體電路裝置的形成方法，此方法包含形成半導體鰭，其中半導體鰭的頂部包含矽鍺；在半導體鰭上沉積矽蓋層；在矽蓋層上形成虛設閘極堆疊物；在虛設閘極堆疊物的側壁上形成閘極間隙壁；進行第一蝕刻製程以蝕刻矽蓋層和半導體鰭的一部分，其中第一凹口形成於半導體鰭的一側上；進行第二蝕刻製程以蝕刻在閘極間隙壁正下方的矽蓋層的一部分；以及進行磊晶成長以從半導體鰭和矽蓋層上形成磊晶區。
在另外一些實施例中，提供積體電路裝置，積體電路裝置包含複數個隔離區；半導體鰭，突出高於位於半導體鰭的兩側的隔離區的部分，其中半導體鰭的頂部由矽鍺形成；矽蓋層，位於半導體鰭上；閘極堆疊物，位於矽蓋層上；閘極間隙壁，位於閘極堆疊物的側壁上，其中閘極間隙壁包含接觸閘極堆疊物的內側壁以及相對於內側壁的外側壁，其中矽蓋層與閘極間隙壁位於閘極堆疊物的同一側的邊緣比閘極間隙壁的外側壁朝閘極堆疊物凹陷得更多；以及源極/汲極區，接觸半導體鰭和矽蓋層的邊緣。
10:晶圓
20:基底
22:井區
24:淺溝槽隔離區
24A:襯墊介電質
24B:介電材料
26、32:半導體條帶
28:墊氧化層
29、54、56:凹口
30:硬遮罩層
36:突出鰭
36’、32TS、40TS:頂表面
40:半導體蓋層
42:虛設閘極介電層
44:虛設閘極電極
46:硬遮罩
48:虛設閘極堆疊物
50:閘極間隙壁
52:鰭間隙壁
53、53’:虛線
57、57’:水平面
58:磊晶區
60:接觸蝕刻停止層
61:界面層
62:層間介電質
63:高介電常數介電層
64:閘極介電質
70:閘極電極
72:黏著層
74:功函數層
76:導電材料層
80:取代閘極堆疊物
82:源極/汲極矽化物區
84:源極/汲極接觸插塞
86:鰭式場效電晶體
200:製程流程
202、204、206、208、210、212、214、216、218、220、222、224:製程
D1:凹陷距離
T1:厚度
△H:高度差
根據以下的詳細說明並配合所附圖式可以更加理解本發明實施例。應注意的是，根據本產業的標準慣例，圖示中的各種部件(feature)並未必按照比例繪製。事實上，可能任意的放大或縮小各種部件的尺寸，以做清楚的說明。
第1-8、9A、9B、9C、9D、10A、10B、10C、10D、11、12A、12B、12C、12D和13圖顯示依據一些實施例之形成鰭式場效電晶體(FinFET)的中間階段的剖面示意圖和透視圖。
第14圖顯示依據一些實施例之形成鰭式場效電晶體的製程流程圖。
要瞭解的是以下的揭露內容提供許多不同的實施例或範例，以實施提供之主體的不同部件。以下敘述各個構件及其排列方式的特定範例，以求簡化揭露內容的說明。當然，這些僅為範例並非用以限定本發明。例如，以下的揭露內容敘述了將一第一部件形成於一第二部件之上或上方，即表示其包含了所形成的上述第一部件與上述第二部件是直接接觸的實施例，亦包含了尚可將附加的部件形成於上述第一部件與上述第二部件之間，而使上述第一部件與上述第二部件可能未直接接觸的實施例。此外，揭露內容中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或部件與另一(複數)元件或(複數)部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類似的用語。除了圖式所繪示的方位之外，空間相關用語也涵蓋裝置在使用或操作中的不同方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。
依據各種實施例提供電晶體及其形成方法。依據一些實施例顯示電晶體的形成的中間階段。討論一些實施例的一些變化。在各種視圖和顯示的實施例中，使用相似的參考符號標註相似元件。依據本發明一些實施例，矽蓋層形成於半導體鰭上，且在源極/汲極區的磊晶成長之前將矽蓋層凹陷，使得增加了磊晶源極/汲極區與通道區之間的界面區。因此，減少了電流擁擠(current crowding)。可以理解的是，雖然使用鰭式場效電晶體(FinFETs)作為範例實施例來討論本發明實施例的概念，但是本發明實施例的概念可應用於其他類型的電晶體，例如平面電晶體。
第1-8、9A、9B、9C、9D、10A、10B、10C、10D、11、12A、12B、12C、12D和13圖顯示依據一些實施例之形成鰭式場效電晶體(FinFET)的中間階段的剖面示意圖和透視圖。顯示於這些圖式中的製程也示意性地反映於第14圖所示的製程流程200中。
在第1圖中，提供基底20，基底20為晶圓10的一部分。基底20可為半導體基底，例如塊狀(bulk)半導體基底、絕緣層上覆半導體(Semiconductor-On-Insulator，SOI)基底或類似物，基底20可為摻雜(例如摻雜p型或n型摻雜物)或未摻雜。基底20可為晶圓的一部分，例如矽晶圓。一般來說，絕緣層上覆半導體基底為形成於絕緣層上的半導體材料層。絕緣層可例如為埋置氧化(Buried Oxide，BOX)層、氧化矽層或類似物。絕緣層提供於基底上，一般為矽基底或玻璃基底。也可使用其他基底，例如多層或漸變(gradient)基底。在一些實施例中，基底20的半導體材料可包含矽、鍺、化合物半導體(包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦)、合金半導體(包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP)或前述之組合。
請參照第1圖，井區22形成於基底20中。對應的製程以製程202顯示於第14圖中的製程流程200。依據本發明一些實施例，井區22為透過將n型雜質植入基底20中形成的n型井區，n型雜質可為磷、砷、銻或類似物。依據本發明其他實施例，井區22為透過將p型雜質植入基底20中形成的p型井區，p型雜質可為硼、銦或類似物。最終的井區22可延伸至基底20的頂表面。n型或p型雜質濃度可等於或小於1018cm-3，例如在約1017cm-3與約1018cm-3之間的範圍中。
請參照第2圖，形成凹口29(有時被稱為溝槽)從基底20的頂表面延伸至基底20中。為了形成凹口29，先形成墊氧化層28和硬遮罩層30，並將墊氧化層28和硬遮罩層30圖案化。依據本發明一些實施例，墊氧化層28由熱氧化製程形成，其中將基底20的頂表面層氧化。墊氧化層28作為基底20與硬遮罩層30 之間的黏著層。墊氧化層28也可作為用於蝕刻硬遮罩層30的蝕刻停止層。依據本發明一些實施例，硬遮罩層30由例如使用低壓化學氣相沉積(Low-Pressure Chemical Vapor Deposition，LPCVD)形成的氮化矽形成。依據本發明其他實施例，硬遮罩層30透過矽的熱氧化或電漿輔助化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition，PECVD)形成。光阻(未顯示)形成於硬遮罩層30上，且接著將光阻圖案化。接著，使用光阻作為蝕刻遮罩將硬遮罩層30圖案化，以形成第2圖的圖案。
接著，使用圖案化的硬遮罩層30作為蝕刻遮罩來蝕刻墊氧化層28和基底20。因此，凹口29形成延伸至基底20中。對應的製程以製程204顯示於第14圖中的製程流程200。依據本發明一些實施例，凹口29的底部高於井區22的底表面。基底20在相鄰凹口29之間的部分此後被稱為半導體條帶26。基底20低於凹口29的底部的部分被稱為基底20。
接著，以介電材料填充凹口29，如第3圖所示。進行平坦化製程(例如化學機械研磨(Chemical Mechanical Polish，CMP)製程或機械研磨製程)以移除介電材料的多餘部分，且介電材料的剩下部分被稱為淺溝槽隔離(Shallow Trench Isolation，STI)區24。對應的製程以製程206顯示於第14圖中的製程流程200。淺溝槽隔離區24可包含襯墊介電質24A，襯墊介電質24A可為透過將基底20的表面層熱氧化形成的熱氧化物。襯墊介電質24A也可為沉積的介電層，例如氧化矽層、氮化矽層或類似物。形成方法可包含原子層沉積(Atomic Layer Deposition，ALD)、高密度電漿化學氣相沉積(High-Density Plasma Chemical Vapor Deposition，HDPCVD)、化學氣相沉積(Chemical Vapor Deposition，CVD)或類似方法。淺溝槽隔離區24也可包含在襯墊介電質24A上方的介電材料24B，其中介電材料24B可透過使用可流動化學氣相沉積(Flowable Chemical Vapor Deposition，FCVD)、旋塗或類似方法形成。依據一些實施例，介電材料24B可 包含氧化矽。
硬遮罩層30的頂表面和淺溝槽隔離區24的頂表面可大致彼此齊平。半導體條帶26在相鄰的淺溝槽隔離區24之間。依據本發明一些實施例，半導體條帶26的頂部透過不同於半導體條帶26的半導體材料取代，使得形成半導體條帶32，如第4圖所示。半導體條帶32的形成可包含蝕刻半導體條帶26的頂部以形成凹口，以及進行磊晶製程以在凹口中再成長其他半導體材料。接著，進行平坦化製程(例如化學機械研磨(CMP)製程或機械研磨製程)以移除高於淺溝槽隔離區24的磊晶半導體材料的多餘部分，且半導體材料的剩下部分形成半導體條帶32。因此，半導體條帶32由不同於基底20的半導體材料形成。依據一些實施例，半導體條帶32由矽鍺、矽碳或第III-V族化合物半導體材料形成。依據本發明一些實施例，半導體條帶32由矽鍺形成或包括矽鍺，鍺原子百分比可高於約30%，且可在約30%與約100%之間的範圍中。
依據本發明一些實施例，半導體條帶32在磊晶期間原位摻雜與井區22相同導電類型的雜質。再者，原位摻雜的雜質可具有與井區22相同的濃度範圍。舉例來說，n型或p型雜質濃度可等於或小於1018cm-3，例如在約1017cm-3與約1018cm-3之間的範圍中。依據本發明其他實施例，用於形成井區22的佈植製程可在形成半導體條帶32之後進行，而非在第1圖所示的製程中進行。
依據本發明其他實施例，不進行取代製程來以其他材料取代半導體條帶26的頂部，且顯示的半導體條帶26為原基底20的一部分，且因此半導體條帶26和32的材料相同於基底20的材料。
請參照第5圖，將淺溝槽隔離區24凹陷，使得半導體條帶32的頂部突出高於淺溝槽隔離區24的剩下部分的頂表面以形成突出鰭36。對應的製程以製程208顯示於第14圖中的製程流程200。蝕刻可使用乾蝕刻製程進行，其中例如使用HF3和NH3作為蝕刻氣體。在蝕刻製程期間，可產生電漿。也可包含氬。 依據本發明其他實施例，淺溝槽隔離區24的凹陷透過使用濕蝕刻製程進行。舉例來說，蝕刻化學物可包含稀釋HF。
依據本發明一些實施例，凹陷的淺溝槽隔離區24的頂表面低於半導體條帶32與對應的下方半導體條帶26之間的界面。依據本發明其他實施例，凹陷的淺溝槽隔離區24的頂表面齊平於或高於半導體條帶32與對應的下方半導體條帶26之間的界面。
在以上顯示的實施例中，鰭可透過任何合適的方法圖案化。舉例來說，鰭可透過使用一個或多個光微影製程(包含雙重圖案化或多重圖案化製程)來圖案化。一般來說，雙重圖案化或多重圖案化製程結合了光微影和自對準製程，以創造具有較小間距的圖案，舉例來說，此圖案具有比使用單一直接光微影製程可獲得的間距更小的圖案。舉例來說，在一實施例中，犧牲層形成於基底上方並透過使用光微影製程圖案化。間隔物透過使用自對準製程形成於圖案化犧牲層旁邊。接著，移除犧牲層，且可接著使用剩下的間隔物或心軸(mandrel)將鰭圖案化。
第6圖顯示半導體蓋層40的沉積。對應的製程以製程210顯示於第14圖中的製程流程200。半導體蓋層40形成為順應層，有著水平部分的厚度等於或大致等於(例如有著差異小於約10%)垂直部分的厚度。半導體蓋層40的形成為選擇性的，使得半導體蓋層40成長於例如半導體條帶32的半導體材料上，且不成長於淺溝槽隔離區24上。此可透過在沉積氣體中添加蝕刻氣體來達成，沉積氣體例如矽烷(SiH4)及/或二氯矽烷(dichlorosilane，DCS)。沉積可透過使用順應性沉積方法進行，例如化學氣相沉積或原子層沉積。依據本發明一些實施例，半導體蓋層40由矽形成，其可不含或大致不含例如鍺、碳或類似物的其他元素。舉例來說，在半導體蓋層40中的矽的原子百分比可高於約95%或99%。依據其他實施例，半導體蓋層40由不同於半導體條帶32的其他半導體材料形成。舉例來 說，半導體蓋層40可由有著低於半導體條帶32的鍺濃度的矽鍺形成。可磊晶成長半導體蓋層40作為結晶半導體層或可形成為多晶半導體層，其可透過例如調整沉積製程中的溫度和成長速率來達成。半導體蓋層40可具有厚度大於約3Å，且厚度可在約3Å與約20Å之間的範圍中。
依據一些實施例，半導體蓋層40為不在沉積中原位摻雜p型或n型雜質的本質層。依據其他實施例，半導體蓋層40原位摻雜p型或n型雜質，且摻雜濃度低於井區22的摻雜濃度。舉例來說，摻雜濃度可低於約1017cm-3，或低於約1015cm-3。如果在沉積製程期間原位摻雜，半導體蓋層40的導電類型相同於井區22的導電類型。
請參照第7圖，形成虛設閘極介電層42、虛設閘極電極44和硬遮罩46。對應的製程以製程212顯示於第14圖中的製程流程200。虛設閘極介電層42可由氧化矽或其他介電材料形成，且可透過沉積形成，使得虛設閘極介電層42接觸突出鰭36的側壁和頂表面。虛設閘極電極44可例如使用多晶矽形成，且也可使用其他材料。一個(或複數個)硬遮罩46形成於虛設閘極電極44上方。硬遮罩46可由氮化矽、氧化矽、氮碳化矽或前述之多層形成。在本文的描述中，硬遮罩46和虛設閘極電極44被統稱為虛設閘極堆疊物48。虛設閘極堆疊物48可橫跨於單一個或複數個突出鰭36及/或淺溝槽隔離區24上方。虛設閘極堆疊物48也具有長度方向垂直於突出鰭36的長度方向。虛設閘極堆疊物48可透過在虛設閘極介電層42上方沉積毯覆性虛設閘極電極層，在毯覆性虛設閘極電極層上方沉積毯覆性硬遮罩層，且接著對毯覆性硬遮罩層和毯覆性虛設閘極電極層進行非等向性蝕刻製程來形成。依據本發明一些實施例，蝕刻停止於虛設閘極介電層42，虛設閘極介電層42用作蝕刻停止層。依據本發明一些實施例，也蝕刻虛設閘極介電層42，且虛設閘極堆疊物48也包含虛設閘極介電層42的剩下部分。因此，暴露出淺溝槽隔離區24的頂表面。
接著，閘極間隙壁50和鰭間隙壁52分別形成於虛設閘極堆疊物48的側壁和突出鰭36的側壁上。對應的製程以製程214顯示於第14圖中的製程流程200。依據本發明一些實施例，閘極間隙壁50和鰭間隙壁52由介電材料形成，例如氮化矽、氮碳化矽或類似物，且可具有單一層結構或包含複數個介電層的多層結構。形成製程可包含沉積介電間隔層，以及進行非等向性蝕刻製程以移除在虛設閘極堆疊物48和突出鰭36的頂表面上方的介電間隔層的水平部分。此蝕刻也可透過使用虛設閘極介電層42作為蝕刻停止層來進行。
第9A、9B、9C、10A、10B和10C圖顯示蝕刻虛設閘極介電層42，將半導體蓋層40和突出鰭36凹陷，以及將半導體蓋層40進一步橫向凹陷的中間階段的透視圖和剖面示意圖。在第9A、9B、9C、10A、10B和10C圖中，圖號包含字母“A”、“B”或“C”。字母“A”表示對應圖顯示透視圖。字母“B”表示對應圖顯示在對應透視圖中的參考剖面“B-B”。字母“C”表示對應圖顯示結構的上視圖，且上視圖顯示在含有線C-C的水平面的剖面。
先進行非等向性蝕刻製程以蝕刻如第8圖所示的虛設閘極介電層42的水平部分。因此，暴露出半導體蓋層40。接著，蝕刻半導體蓋層40和突出鰭36。形成的結構如第9A、9B和9C圖所示。依據本發明一些實施例，虛設閘極介電層42使用NF3和NH3的混合氣體或HF和NH3的混合氣體蝕刻。半導體蓋層40(其可為矽蓋或由其他材料形成的半導體蓋)可透過使用氟基及/或氯基氣體(例如C2F6、CF4，HBr、Cl2和O2的混合物或HBr、Cl2、O2和CF2等的混合物)蝕刻。突出鰭36可透過使用HBr及/或含氟蝕刻氣體(例如C2F6、CF4、CF2Cl2或類似物)蝕刻。對應的製程以製程216顯示於第14圖中的製程流程200。移除突出鰭36的一部分所留下的空間此後被稱為凹口54(標註於第9B圖)。依據一些實施例，凹口54的底表面高於淺溝槽隔離區24的頂表面。再者，凹口54的底表面可高於半導體條帶26與半導體條帶32之間的界面。因此，可在凹口54正下方留有半導體條 帶32的一些底部部分。依據本發明一些實施例，凹口54的底表面低於鰭側壁52。
如第9A圖所示，在凹口54的底部處，半導體蓋層40的頂表面40TS可齊平於或高於半導體條帶32的頂表面32TS。依據本發明一些實施例，頂表面40TS和32TS可為傾斜的。舉例來說，在凹口54的底部處，整個傾斜的頂表面40TS可高於整個頂表面32TS。依據其他實施例，頂表面40TS可包含高於整個頂表面32TS的第一部分以及與傾斜的頂表面32TS在相同水平面的第二部分。
第9B圖顯示第9A圖中的參考剖面C-C。第9B圖顯示兩相鄰的虛設閘極堆疊物48，但是可有更多的虛設閘極堆疊物48平行配置。蝕刻半導體蓋層40和半導體條帶32在相鄰的虛設閘極堆疊物48之間的部分，且保留半導體蓋層40和半導體條帶32在虛設閘極堆疊物48正下方的部分作為對應的鰭式場效電晶體的通道區。由於非等向性蝕刻的緣故，半導體蓋層40的邊緣與閘極間隙壁50的對應邊緣對齊。依據本發明一些實施例，半導體條帶32的頂部具有邊緣與閘極間隙壁50的對應邊緣齊平，而半導體條帶32的底部可具有彎曲頂表面，此彎曲頂表面收斂至相鄰閘極間隙壁50之間的中心線。
第9C圖顯示第9A圖的結構的一部分的上視圖，其中上視圖從接近且稍微低於半導體條帶32的頂表面水平面得到。舉例來說，上視圖可從第9B圖所示的水平面57得到，其中水平面57接近且以高度差△H稍微低於突出鰭36的頂表面36’，舉例來說，高度差△H在約5nm與約10nm之間的範圍中。水平面57相同於第9A圖的線C-C的水平面。在此水平面，如第9C圖所示，半導體條帶32的左邊緣與半導體蓋層40的左邊緣和閘極間隙壁50的左邊緣對齊(齊平)，且半導體條帶32和突出鰭36的右邊緣與半導體蓋層40的右邊緣和閘極間隙壁50的右邊緣對齊(齊平)。
第9C圖顯示依據一些實施例的結構，其中如第8圖所示，當未將虛設閘極介電層42圖案化時，形成閘極間隙壁50，且因此如第9C圖所示，虛設 閘極介電層42的左邊緣和右邊緣分別對齊半導體蓋層40的左邊緣和右邊緣。第9D圖顯示依據其他實施例的結構，其中當形成閘極間隙壁50時，也將虛設閘極介電層42圖案化。因此，虛設閘極介電層42的左邊緣對齊左邊閘極間隙壁50的右邊緣，且虛設閘極介電層42的右邊緣對齊右邊閘極間隙壁50的左邊緣。
在蝕刻製程之後，進行光阻移除製程，其中光阻用於覆蓋對應晶圓的一些區域，而暴露出一些其他區域(例如顯示的鰭式場效電晶體區域)。接著，進行蝕刻後清潔製程以移除先前製程產生的副產物。依據本發明一些實施例，蝕刻後清潔製程包含濕蝕刻製程，此濕蝕刻製程可使用稀釋氫氟酸(diluted hydrogen fluoride，DHF)、包括NH4OH、H2O2和H2O的化學溶液(有時被稱為標準清洗1(Standard Clean 1，SC1)溶液)及/或包括HCl、H2O2和H2O的化學溶液(有時被稱為標準清洗2(Standard Clean 2，SC2)溶液)來進行，且因此移除在暴露的半導體區域的表面上的殘留物和粒子。在蝕刻後清潔製程中，大致不蝕刻或不損壞半導體蓋層40、閘極間隙壁50和半導體條帶32。因此，在蝕刻後清潔製程之後所得的結構相同於第9A、9B和9C圖所示的結構。
接著，將半導體蓋層40橫向凹陷以形成凹口56，且第10A、10B和10C圖顯示所得到的結構。對應的製程以製程218顯示於第14圖中的製程流程200。依據本發明一些實施例，橫向凹陷製程透過等向性蝕刻製程進行，其可包含乾蝕刻製程或濕蝕刻製程。選擇蝕刻化學物(蝕刻氣體或蝕刻溶液)，使得蝕刻化學物蝕刻半導體蓋層40，而不蝕刻半導體條帶32、虛設閘極介電層42、閘極間隙壁50和硬遮罩46。依據一些實施例，蝕刻選擇性，其為半導體蓋層40的蝕刻速率與半導體條帶32(突出鰭36的一部分)的蝕刻速率的比值高於約10，且可高於約20、50或更高。依據本發明一些實施例，採用乾蝕刻製程，且蝕刻氣體包括氫(H2)和氦(He)氣體。舉例來說，晶圓的溫度(及半導體蓋層40的溫度)可高於約200℃，且可在約200℃與約400℃之間的範圍中。在高溫下，氫氣與矽反應。 由於GeH的鍵結能量高於SiH的鍵結能量，因此鍺比矽具有更小的損失比例，其導致矽的蝕刻速率高於矽鍺的蝕刻速率。
第10B圖顯示第10A圖的垂直參考剖面C-C。第10B圖顯示將半導體蓋層40從閘極間隙壁50的對應外側邊緣和下方半導體條帶32/突出鰭36的部分的對應邊緣橫向凹陷。可控制凹陷製程，使得凹陷距離D1不大於閘極間隙壁50的厚度T1。凹陷距離D1可大於約1nm且小於約2nm。再者，比例D1/T1大於0，且可等於或小於1.0。舉例來說，比例D1/T1可在約0.2與約1.0之間的範圍中。
第10C圖顯示第10A圖的結構的一部分的上視圖，其中上視圖從接近且稍微低於半導體條帶32的頂表面水平面得到。此水平面也以水平面57標註於第10B圖。凹陷的半導體蓋層40的邊緣的可能位置以虛線53標註於第10C圖。凹口56形成於閘極間隙壁50與半導體條帶32/突出鰭36之間，半導體條帶32/突出鰭36形成對應的鰭式場效電晶體的通道區。
第10D圖顯示依據其他實施例之第10A圖的結構的一部分的上視圖。此結構相似於第10C圖顯示的結構，除了第10C圖的虛設閘極介電層42的左邊緣和右邊緣不延伸至虛設閘極電極44的外側邊緣。反之，第10C圖的虛設閘極介電層42的左邊緣對齊左邊閘極間隙壁50的左邊緣，且虛設閘極介電層42的右邊緣對齊右邊閘極間隙壁50的右邊緣。左邊閘極間隙壁50的左邊緣和右邊閘極間隙壁50的右邊緣也被稱為閘極間隙壁50的外側邊緣。
接著，磊晶區58(源極/汲極區)透過在凹口56(第10B和10C圖)和凹口54(第10B圖)中(透過磊晶)選擇性成長半導體材料來形成，以形成第11圖中的結構。對應的製程以製程220顯示於第14圖中的製程流程200。取決於最終的鰭式場效電晶體為p型鰭式場效電晶體或n型鰭式場效電晶體，可在進行磊晶時原位摻雜p型雜質或n型雜質。舉例來說，當最終的鰭式場效電晶體為p型鰭式場效電晶體時，可成長矽鍺硼(SiGeB)或矽硼(SiB)。相對地，當最終的鰭式場效電晶 體為n型鰭式場效電晶體時，可成長矽磷(SiP)或矽碳磷(SiCP)。依據本發明其他實施例，磊晶區58包括第III-V族化合物半導體，例如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、前述之組合或前述之多層。在填充凹口54和56之後，磊晶區58的進一步磊晶成長導致磊晶區58水平地擴展，且可形成多面。磊晶區58的進一步成長也導致相鄰的磊晶區58彼此合併。依據本發明一些實施例，磊晶區58的形成可在當磊晶區58的頂表面仍為波浪狀時完成，或在當合併的磊晶區58的頂表面已變得平坦時完成，其可透過進一步在磊晶區58上成長來達成，如第11圖所示。
在磊晶製程之後，磊晶區58可進一步以p型或n型雜質佈植以形成源極和汲極區，源極和汲極區也使用參考符號58標註。依據本發明其他實施例，當磊晶區58為在磊晶期間原位摻雜p型或n型雜質時，省略佈植製程。
第12A圖顯示在形成接觸蝕刻停止層(Contact Etch Stop Layer，CESL)60和層間介電質(Inter-Layer Dielectric，ILD)62之後的結構的剖面示意圖。接觸蝕刻停止層60可由氧化矽、氮化矽、氮碳化矽或類似物形成，且可透過使用化學氣相沉積、原子層沉積或類似方法形成。層間介電質62可包含例如使用可流動化學氣相沉積、旋塗、化學氣相沉積或其他沉積方法形成的介電材料。層間介電質62可由含氧介電材料形成，含氧介電材料可為氧化矽基材料，例如四乙氧基矽烷(Tetra Ethyl Ortho Silicate，TEOS)氧化物、磷矽酸鹽玻璃(Phospho-Silicate Glass，PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass，BSG)、硼摻雜磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass，BPSG)或類似物。可進行平坦化製程(例如化學機械研磨製程或機械研磨製程)使層間介電質62、虛設閘極堆疊物48和閘極間隙壁50的頂表面彼此齊平。如第12A圖所示，磊晶區58延伸至閘極間隙壁50正下方，以接觸半導體蓋層40。
第12B圖顯示第12A圖的結構的一部分的上視圖，其中上視圖從接 近且稍微低於突出鰭36的頂表面水平面得到。此水平面也以水平面57標註於第12A圖。再者，第12B圖顯示第11圖中的參考剖面12B-12B。磊晶區58與磊晶區58接觸的突出鰭36之間的界面的長度等於L1+2D1。相較之下，如果未將半導體蓋層40凹陷，磊晶區58與磊晶區58接觸的突出鰭36之間的界面的長度將等於L1。因此，凹陷的半導體蓋層40導致磊晶區58與磊晶區58接觸的突出鰭36之間的接觸面積增加。由於半導體蓋層40為未摻雜或輕摻雜，因此半導體蓋層40為具有高的片電阻，且半導體蓋層40傳導通道電流的能力受限。增加接觸面積使得減少了電流擁擠。第12C圖顯示相似於第12B圖所示的結構的一部分的上視圖，除了第12B圖的虛設閘極介電層42的右邊緣不延伸至虛設閘極電極44的外側邊緣。反之，第12B圖的虛設閘極介電層42的左邊緣對齊左邊閘極間隙壁50的左邊緣，且虛設閘極介電層42的右邊緣對齊右邊閘極間隙壁50的右邊緣。
第12D圖顯示相似於第12B圖所示的結構的一部分的上視圖，除了第12B和12D圖的上視圖在不同水平面得到。舉例來說，第12D圖所示的上視圖從第11和12A圖水平面57’得到，其中水平面57’低於水平面57。再者，第12D圖顯示第11圖中的參考剖面12D-12D。如第12B和12D圖所示，當水平面較低，半導體條帶32的未蝕刻部分可突出更超過閘極間隙壁50的外側邊緣。再者，半導體蓋層40的對應邊緣也可突出超過閘極間隙壁50的外側邊緣。在不同水平面處，半導體蓋層40的對應邊緣仍相對於半導體條帶32凹陷。凹陷的半導體蓋層40的邊緣的可能位置以虛線53’標註。
第13圖顯示後續的製程，其包含以取代閘極堆疊物取代虛設閘極堆疊物48(第12A圖)，形成源極/汲極矽化物區，以及形成源極/汲極接觸插塞。如第13圖所示，形成取代閘極堆疊物80，取代閘極堆疊物80包含閘極介電質64和閘極電極70。對應的製程以製程222顯示於第14圖中的製程流程200。取代閘極堆疊物80的形成包含形成/沉積複數層，且接著進行平坦化製程，例如化學機 械研磨製程或機械研磨製程。依據本發明一些實施例，閘極介電質64包含界面層(Interfacial Layers，ILs)61作為閘極介電質64的下部。界面層61形成於突出鰭36的暴露表面上。界面層61可包含氧化層(例如氧化矽層)，氧化層透過將突出鰭36熱氧化、化學氧化製程或沉積製程形成。閘極介電質64也可包含形成於界面層61上方的高介電常數介電層63。高介電常數介電層63可包含高介電常數介電材料，例如HfO2、ZrO2、HfZrOx、HfSiOx、HfSiON、ZrSiOx、HfZrSiOx、Al2O3、HfAlOx、HfAlN、ZrAlOx、La2O3、TiO2、Yb2O3、氮化矽或類似物。高介電常數介電材料的介電常數(k值)高於3.9，且可高於約7.0。高介電常數介電層63由順應層形成，且延伸至突出鰭36的側壁和閘極間隙壁50的側壁上。依據本發明一些實施例，高介電常數介電層63透過使用原子層沉積或化學氣相沉積形成。
閘極電極70可包含複數個子層，子層可包含黏著層72(例如TiN)、功函數層74和額外的導電材料層76。
第13圖也顯示源極/汲極矽化物區82和源極/汲極接觸插塞84的形成。對應的製程以製程224顯示於第14圖中的製程流程200。為了形成這些部件，先透過蝕刻層間介電質62和接觸蝕刻停止層60以暴露出磊晶區58來形成接觸開口。接著，形成源極/汲極矽化物區82和源極/汲極接觸插塞84延伸至層間介電質62和接觸蝕刻停止層60中。形成製程可包含在接觸開口中沉積金屬層，進行退火以使金屬層與磊晶區58反應以形成源極/汲極矽化物區82，以及以導電材料(例如鎢或鈷)填充接觸開口的剩下部分以形成源極/汲極接觸插塞84。由此形成鰭式場效電晶體86，依據一些實施例，鰭式場效電晶體86可為p型鰭式場效電晶體。依據本發明其他實施例，鰭式場效電晶體86為n型鰭式場效電晶體。
本發明實施例具有一些優點特徵。透過將形成於半導體鰭上的半導體蓋層(例如矽蓋層)凹陷，增加了磊晶源極/汲極區與最終的鰭式場效電晶體的通道區之間界面區域。由於磊晶源極/汲極區比半導體蓋層更重摻雜p型或n型 雜質，因此磊晶源極/汲極區與半導體鰭之間的接觸電阻低於半導體蓋層與半導體鰭之間的接觸電阻。減少了電流擁擠效應。
依據本發明一些實施例，積體電路裝置的形成方法包含形成半導體鰭突出高於隔離區的頂表面，隔離區位於半導體鰭的兩側，其中半導體鰭的頂部由第一半導體材料形成；在半導體鰭的頂表面和側壁上沉積半導體蓋層，其中半導體蓋層由不同於第一半導體材料的第二半導體材料形成；在半導體蓋層上形成閘極堆疊物；在閘極堆疊物的側壁上形成閘極間隙壁；蝕刻在閘極堆疊物的一側上的半導體鰭的一部分，以形成第一凹口延伸至半導體鰭中；將半導體蓋層凹陷，以在閘極間隙壁正下方形成第二凹口；以及進行磊晶成長以形成磊晶區延伸至第一凹口和第二凹口中。在一實施例中，第一半導體材料包括矽鍺，且沉積半導體蓋層的步驟包括成長矽層。在一實施例中，在將半導體蓋層凹陷的步驟中，不蝕刻半導體鰭和閘極間隙壁。在一實施例中，將半導體蓋層凹陷的步驟包括等向性蝕刻製程。在一實施例中，等向性蝕刻製程包括乾蝕刻製程。在一實施例中，此方法更包含在將半導體蓋層凹陷之前進行濕清潔製程，其中濕清潔製程和將半導體蓋層凹陷的製程為不同的製程。在一實施例中，此方法更包含蝕刻隔離區之間的半導體條帶的一部分；以第一半導體材料填充由半導體條帶被蝕刻的部分留下的空間；以及將複數個隔離區凹陷，其中第一半導體材料突出高於隔離區的剩下部分。在一實施例中，半導體蓋層形成作為本質層。
依據本發明一些實施例，積體電路裝置的形成方法包含形成半導體鰭，其中半導體鰭的頂部包含矽鍺；在半導體鰭上沉積矽蓋層；在矽蓋層上形成虛設閘極堆疊物；在虛設閘極堆疊物的側壁上形成閘極間隙壁；進行第一蝕刻製程以蝕刻矽蓋層和半導體鰭的一部分，其中第一凹口形成於半導體鰭的一側上；進行第二蝕刻製程以蝕刻在閘極間隙壁正下方的矽蓋層的一部分；以 及進行磊晶成長以從半導體鰭和矽蓋層上形成磊晶區。在一實施例中，矽蓋層沉積作為本質層。在一實施例中，半導體鰭具有第一n型雜質濃度，且矽蓋層具有低於第一n型雜質濃度的第二n型雜質濃度，且磊晶區為p型。在一實施例中，在第二蝕刻製程之前，矽蓋層的邊緣對齊半導體鰭的邊緣，且在第二蝕刻製程之後，將矽蓋層比半導體鰭的邊緣凹陷得更多。在一實施例中，在第二蝕刻製程中，將矽蓋層凹陷的距離大於約1nm。在一實施例中，第二蝕刻製程包括等向性乾蝕刻製程。
依據本發明一些實施例，積體電路裝置包含隔離區；半導體鰭突出高於位於半導體鰭的兩側的隔離區的部分，其中半導體鰭的頂部由矽鍺形成；矽蓋層位於半導體鰭上；閘極堆疊物位於矽蓋層上；閘極間隙壁位於閘極堆疊物的側壁上，其中閘極間隙壁包含接觸閘極堆疊物的內側壁以及相對於內側壁的外側壁，其中矽蓋層與閘極間隙壁位於閘極堆疊物的同一側的邊緣比閘極間隙壁的外側壁朝閘極堆疊物凹陷得更多；以及源極/汲極區接觸半導體鰭和矽蓋層的邊緣。在一實施例中，半導體鰭為n型，且矽蓋層具有低於半導體鰭的n型雜質濃度。在一實施例中，矽蓋層比閘極間隙壁的外側壁朝閘極堆疊物凹陷更多距離大於約1nm。在一實施例中，矽蓋層比半導體鰭與源極/汲極區之間的界面朝閘極堆疊物凹陷得更多，其中測量界面在接近且低於半導體鰭的頂表面的水平面。在一實施例中，矽蓋層的邊緣與閘極間隙壁的一部分重疊，且閘極間隙壁的此部分在閘極件矽壁的外側壁與內側壁之間。在一實施例中，矽蓋層比閘極間隙壁的外側壁朝閘極堆疊物凹陷更多凹陷距離，且凹陷距離與閘極間隙壁的厚度的比值在約0.2與約1.0之間的範圍中。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更加了解本發明實施例。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並 以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明的發明精神與範圍。在不背離本發明的發明精神與範圍之前提下，可對本發明實施例進行各種改變、置換或修改。
200:製程流程
202、204、206、208、210、212、214、216、218、220、222、224:製程

Claims (14)

  1. 一種積體電路裝置的形成方法，包括：形成一半導體鰭突出高於複數個隔離區的頂表面，該複數個隔離區位於該半導體鰭的兩側，其中該半導體鰭的頂部由一第一半導體材料形成；在該半導體鰭的頂表面和側壁上沉積一半導體蓋層，其中該半導體蓋層由不同於該第一半導體材料的一第二半導體材料形成；在該半導體蓋層上形成一閘極堆疊物；在該閘極堆疊物的側壁上形成一閘極間隙壁；蝕刻在該閘極堆疊物的一側上的該半導體鰭的一部分，以形成一第一凹口延伸至該半導體鰭中；將該半導體蓋層凹陷，以在該閘極間隙壁正下方形成一第二凹口；以及進行一磊晶成長以形成一磊晶區延伸至該第一凹口和該第二凹口中。
  2. 如申請專利範圍第1項所述之積體電路裝置的形成方法，其中該第一半導體材料包括矽鍺，且沉積該半導體蓋層的步驟包括成長一矽層。
  3. 如申請專利範圍第1或2項所述之積體電路裝置的形成方法，其中在將該半導體蓋層凹陷的步驟中，不蝕刻該半導體鰭和該閘極間隙壁。
  4. 如申請專利範圍第1或2項所述之積體電路裝置的形成方法，其中將該半導體蓋層凹陷的步驟包括一等向性蝕刻製程。
  5. 如申請專利範圍第4項所述之積體電路裝置的形成方法，其中該等向性蝕刻製程包括一乾蝕刻製程。
  6. 如申請專利範圍第1或2項所述之積體電路裝置的形成方法，更包括在將該半導體蓋層凹陷之前進行一濕清潔製程，其中該濕清潔製程和將該半導體蓋層凹陷的製程為不同的製程。
  7. 如申請專利範圍第1或2項所述之積體電路裝置的形成方法，更包 括：蝕刻該複數個隔離區之間的一半導體條帶的一部分；以該第一半導體材料填充由該半導體條帶被蝕刻的該部分留下的一空間；以及將該複數個隔離區凹陷，其中該第一半導體材料突出高於該複數個隔離區的剩下部分。
  8. 如申請專利範圍第1或2項所述之積體電路裝置的形成方法，其中該半導體蓋層形成作為一本質層。
  9. 一種積體電路裝置的形成方法，包括：形成一半導體鰭，其中該半導體鰭的頂部包括矽鍺；在該半導體鰭上沉積一矽蓋層；在該矽蓋層上形成一虛設閘極堆疊物；在該虛設閘極堆疊物的側壁上形成一閘極間隙壁；進行一第一蝕刻製程以蝕刻該矽蓋層和該半導體鰭的一部分，其中一第一凹口形成於該半導體鰭的一側上；進行一第二蝕刻製程以蝕刻在該閘極間隙壁正下方的該矽蓋層的一部分；以及進行一磊晶成長以從該半導體鰭和該矽蓋層上形成一磊晶區。
  10. 如申請專利範圍第9項所述之積體電路裝置的形成方法，其中該半導體鰭具有一第一n型雜質濃度，且該矽蓋層具有低於該第一n型雜質濃度的一第二n型雜質濃度，且該磊晶區為p型。
  11. 如申請專利範圍第9或10項所述之積體電路裝置的形成方法，其中在該第二蝕刻製程之前，該矽蓋層的邊緣對齊該半導體鰭的邊緣，且在該第二蝕刻製程之後，將該矽蓋層比該半導體鰭的邊緣凹陷得更多。
  12. 一種積體電路裝置，包括：複數個隔離區；一半導體鰭，突出高於位於該半導體鰭的兩側的該複數個隔離區的部分，其中該半導體鰭的頂部由矽鍺形成；一矽蓋層，位於該半導體鰭上；一閘極堆疊物，位於該矽蓋層上；一閘極間隙壁，位於該閘極堆疊物的側壁上，其中該閘極間隙壁包括接觸該閘極堆疊物的內側壁以及相對於該內側壁的一外側壁，其中該矽蓋層與該閘極間隙壁位於該閘極堆疊物的同一側的一邊緣比該閘極間隙壁的該外側壁朝該閘極堆疊物凹陷得更多；以及一源極/汲極區，接觸該半導體鰭和該矽蓋層的該邊緣。
  13. 如申請專利範圍第12項所述之積體電路裝置，其中該矽蓋層比該半導體鰭與該源極/汲極區之間的一界面朝該閘極堆疊物凹陷得更多，其中測量該界面在接近且低於該半導體鰭的頂表面的一水平面。
  14. 如申請專利範圍第12或13項所述之積體電路裝置，其中該矽蓋層的該邊緣與該閘極間隙壁的一部分重疊，且該閘極間隙壁的該部分在該閘極件矽壁的該外側壁與該內側壁之間。
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