TWI721605B - 積體電路結構及其形成方法 - Google Patents

積體電路結構及其形成方法 Download PDF

Info

Publication number
TWI721605B
TWI721605B TW108137415A TW108137415A TWI721605B TW I721605 B TWI721605 B TW I721605B TW 108137415 A TW108137415 A TW 108137415A TW 108137415 A TW108137415 A TW 108137415A TW I721605 B TWI721605 B TW I721605B
Authority
TW
Taiwan
Prior art keywords
hard mask
dielectric hard
dielectric
forming
gate
Prior art date
Application number
TW108137415A
Other languages
English (en)
Other versions
TW202025237A (zh
Inventor
黃麟淯
游力蓁
王聖璁
游家權
張家豪
林天祿
林佑明
王志豪
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202025237A publication Critical patent/TW202025237A/zh
Application granted granted Critical
Publication of TWI721605B publication Critical patent/TWI721605B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L2029/7858—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一種積體電路結構之形成方法，包括：形成第一源極/汲極接觸插塞於電晶體的源極/汲極區上且與其電性耦合、形成一第一介電硬遮罩，與一閘極堆疊重疊、凹入此第一源極/汲極接觸插塞，以形成一第一凹槽、形成一第二介電硬遮罩於此第一凹槽中、凹入一層間介電層以形成一第二凹槽、以及形成一第三介電硬遮罩於此第二凹槽中。此第三介電硬遮罩接觸此第一介電硬遮罩及此第二介電硬遮罩。

Description

積體電路結構及其形成方法
本發明實施例是關於半導體技術，特別是關於一種包含接觸插塞之半導體結構及其形成方法。
在電晶體生產技術的近期發展中，金屬被用來形成接觸插塞及金屬閘極。接觸插塞是用於連接電晶體的源極和汲極區、以及閘極。源極/汲極接觸插塞通常連接至源極/汲極矽化物區，其形成是透過沉積金屬層，然後執行退火使此金屬層與源極/汲極區中的矽起反應。閘極接觸插塞是用於連接金屬閘極。
金屬閘極之形成可包含形成虛設閘極堆疊、移除虛設閘極堆疊以形成開口、將金屬材料填入開口、以及執行平坦化將過量的金屬材料移除以形成金屬閘極。然後凹入金屬閘極以形成凹槽，且將介電硬遮罩填入凹槽。當閘極接觸插塞形成時，移除硬遮罩，使閘極接觸插塞可接觸金屬閘極。
同時形成源極/汲極接觸插塞與源極/汲極區電性耦合。源極/汲極接觸插塞之形成包含蝕刻層間介電質以形成接觸開口，且形成源極/汲極矽化物區和接觸插塞於接觸開口。
本發明實施例提供一種積體電路結構之形成方法，包括：形成第一源極/汲極接觸插塞於電晶體的源極/汲極區上且與其電性耦合；形成一第一介電硬遮罩，與一閘極堆疊重疊；凹入此第一源極/汲極接觸插塞，以形成一第一凹槽；形成一第二介電硬遮罩於此第一凹槽中；凹入一層間介電層以形成一第二凹槽；以及形成一第三介電硬遮罩於此第二凹槽中，其中此第三介電硬遮罩接觸此第一介電硬遮罩及此第二介電硬遮罩。
本發明實施例提供一種積體電路結構之形成方法，包括：凹入一層間介電質以形成一第一凹槽；以一第一介電硬遮罩填充此第一凹槽；形成一硬遮罩於此第一介電硬遮罩及二個第二介電硬遮罩上，其中所述二個第二介電硬遮罩位於此第一介電硬遮罩之相對兩側上，且與其接觸；形成一狹縫開口於此硬遮罩，以露出此第一介電硬遮罩及所述二個第二介電硬遮罩；使用蝕刻移除所述二個第二介電硬遮罩，以形成多個狹縫開口延伸區，其中下方導電部件暴露於此些狹縫開口延伸區，且此下方導電部件包括閘極堆疊或源極/汲極接觸插塞，其中此第一介電硬遮罩在此蝕刻中是露出的，且在此蝕刻後仍存在；填充一導電材料，其中此導電材料包括此狹縫開口中的一第一部分及此些狹縫開口延伸區中的多個第二部分；以及移除此導電材料之此第一部分，其中留下此導電材料之此些第二部分，以形成彼此實體上分隔的二個接觸插塞。
本發明實施例提供一種積體電路結構，包括：一第一閘極堆疊及一第二閘極堆疊；一層間介電質，位於此第一閘極堆疊及此第二閘極堆疊之間；一介電硬遮罩，與此層間介電質重疊且接觸，其中此介電質硬遮罩及此層間介電質是由不同材料形成；一第一閘極接觸件，位於此第一閘極堆疊上且與其接 觸；以及一第二閘極接觸件，位於此第二閘極堆疊上且與其接觸，其中此第一閘極接觸件與此第二閘極接觸件彼此被此介電硬遮罩分隔，且此第一閘極接觸件及此第二閘極接觸件之側壁接觸此介電硬遮罩之側壁，形成實質上垂直的多個界面。
10:晶圓
20:基底
22:井區
24:隔離區
24A:頂部表面
26:半導體條
28:墊氧化層
30:硬遮罩層
36:鰭片
38:虛設閘極堆疊
40:虛設閘極介電質
42:虛設閘極電極
44:硬遮罩層
46:閘極間隔物
50:凹槽
54:磊晶區(源極/汲極區)
58:接觸蝕刻停止層
60:層間介電質
62:溝槽
64:界面層
66:高介電常數介電層
68:閘極介電質
70:閘極電極
72:閘極堆疊
74:含金屬層
76:金屬填充區
80:硬遮罩
82、116:源極/汲極接觸插塞
84:矽化區
86:鰭式場效電晶體
88:介電硬遮罩
90:開口
91A,94A,94B:區域
92:介電材料
94:氣隙
96:孔洞
102:蝕刻停止層
104:硬遮罩
112:狹縫開口
114:閘極接觸插塞
202,204,206,208,210,212,214,216,218,220,222,224,228,230,232,234,236:製程
D1:垂直距離
H1,H2,H3:高度
W1,W2,W3:寬度
由以下的詳細敘述配合所附圖式，可最好地理解本發明實施例。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製。事實上，可任意地放大或縮小各種元件的尺寸，以清楚地表現出本發明實施例之特徵。
第1-6、7A、7B、8、9A、9B、10、11、12A、12B、12C、12D、13A、13B、13C、13D、14A、14B、14C、14D、15A、15B、15C、15D、16A、16B、16C、16D、17A、17B、17C、17D、18A、18B、18C、18D、19A、19B、19C、19D、20A、20B、20C、20D、21A、21B、21C、及21D圖是根據一些實施例，繪示出形成狹縫源極/汲極接觸插塞及狹縫閘極接觸插塞之中間階段的透視及剖面示意圖。
第22圖是根據一些實施例，繪示出部分狹縫源極/汲極接觸插塞的放大視圖。
第23圖是根據一些實施例，繪示出形成狹縫源極/汲極接觸插塞及狹縫閘極接觸插塞的流程圖。
以下揭露提供了許多的實施例或範例，用於實施所提供的標的物之不同元件。各元件和其配置的具體範例描述如下，以簡化本發明實施例之說 明。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例而言，敘述中若提及第一元件形成在第二元件之上，可能包含第一和第二元件直接接觸的實施例，也可能包含額外的元件形成在第一和第二元件之間，使得它們不直接接觸的實施例。此外，本發明實施例可能在各種範例中重複參考數值以及/或字母。如此重複是為了簡明和清楚之目的，而非用以表示所討論的不同實施例及/或配置之間的關係。
再者，其中可能用到與空間相對用詞，例如「在......之下」、「下方」、「較低的」、「上方」、「較高的」等類似用詞，是為了便於描述圖式中一個(些)部件或特徵與另一個(些)部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位)，其中所使用的空間相對形容詞也將依轉向後的方位來解釋。
根據一些實施例，提供具有狹縫源極/汲極接觸插塞和狹縫閘極接觸插塞的電晶體以及其形成方法。根據一些實施例，繪示出形成狹縫源極/汲極接觸插塞及狹縫閘極接觸插塞之中間階段。討論部分實施例的一些變化。遍及各種視圖及圖示的實施例中，使用相似的參考數字以標出相似的元件。一些圖示的實施例中，使用鰭式場效電晶體(FinFET)作為範例以說明本發明實施例之概念。平面式電晶體也可採用本發明實施例之概念。
第1-6、7A、7B、8、9A、9B、10、11、12A、12B、12C、12D、13A、13B、13C、13D、14A、14B、14C、14D、15A、15B、15C、15D、16A、16B、16C、16D、17A、17B、17C、17D、18A、18B、18C、18D、19A、19B、19C、19D、20A、20B、20C、20D、21A、21B、21C、及21D圖是根據本發明 的一些實施例，繪示出形成鰭式場效電晶體和相應的狹縫源極/汲極接觸插塞及狹縫閘極接觸插塞之中間階段的透視及剖面示意圖。在全文中，接觸插塞也可稱作接觸件，且其俯視形狀可包括狹縫(長條)型、矩形、圓形、或任何其他可用的形狀。圖示之製程也反映在第23圖的製程流程200中。
第1圖中提供基底20。基底20可為半導體基底，例如塊體半導體基底、絕緣體上覆半導體(SOI)基底、或其他類似的基底，其可為摻雜的(例如以p型或n型摻質)或未摻雜的。半導體基底20可為一部分的晶圓10，例如矽晶圓。一般而言，絕緣體上半導體基底是形成於絕緣層上的半導體材料層。舉例而言，絕緣層可為埋入式氧化物(buried oxide,BOX)層、氧化矽層、或其他類似的層。提供絕緣層於基底上，其通常為矽或玻璃基底。亦可使用其他基底，例如多層或漸變(gradient)基底。一些實施例中，半導體基底20的半導體材料可包括矽；鍺；化合物半導體包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦；合金半導體包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、及/或GaInAsP；或前述之組合。
參照第1圖，形成井區22於基底20。此製程在第23圖所示的製程流程200中繪示為製程202。根據本發明的一些實施例，井區22是n型井區，其形成是經由佈植n型雜質至基底20，其可為磷、砷、銻、或其他類似雜質。根據本發明的其他實施例，井區22是p型井區，其形成是經由佈植p型雜質至基底20，其可為硼、銦、或其他類似雜質。由此產生的井區22可延伸至基底20之頂部表面。此n型或p型雜質濃度可等於或低於1018cm-3，例如1017-1018cm-3。
參照第2圖，形成隔離區24，從基底20的頂部表面延伸至基底20。此後隔離區24可替代地稱為淺溝槽隔離(STI)區。此製程在第23圖所示的製程流 程200中繪示為製程204。基底20位於相鄰淺溝槽隔離區24間的部分稱為半導體條(semiconductor strip)26。為形成淺溝槽隔離區24，形成墊氧化層28及硬遮罩層30於半導體基底20上，然後將其圖案化。墊氧化層28可為由氧化矽形成的薄膜。根據本發明的一些實施例，墊氧化層28形成於熱氧化製程，其中半導體基底20的一頂部表面層被氧化。墊氧化層28作為半導體基底20及硬遮罩層30間的黏合層(adhesion layer)。墊氧化層28也可作為蝕刻硬遮罩層30的蝕刻停止層。根據本發明的一些實施例，硬遮罩層30由氮化矽形成，例如使用低壓化學氣相沉積(LPCVD)。根據本發明的其他實施例，硬遮罩層30之形成可透過矽的熱氮化、或電漿輔助化學氣相沉積(PECVD)。形成光阻(未繪示)於硬遮罩層30上然後將其圖案化。接著使用圖案化光阻作為蝕刻遮罩，將硬遮罩層30圖案化，以形成如第2圖所示的硬遮罩30。
然後使用硬遮罩層30作為蝕刻遮罩，蝕刻墊氧化層28及基底20，接著以介電材料填充基底20中所產生的溝槽。執行平坦化製程，例如化學機械研磨(CMP)製程或機械磨光法(mechanical grinding process)，以移除介電材料的過量部分，且介電材料的剩餘部分為淺溝槽隔離區24。淺溝槽隔離區24可包含襯層(liner)介電質(未繪示)，其可為以基底20表面層之熱氧化所形成的熱氧化物。襯層介電質也可是沉積的氧化矽層、氮化矽層、或其他類似的層，其使用例如原子層沉積(ALD)、高密度電漿化學氣相沉積(HDPCVD)、或化學氣相沉積而形成。淺溝槽隔離區24也可包括襯層氧化物上的介電材料，其中介電材料可使用流動化學氣相沉積(FCVD)、旋轉(spin-on)塗佈、或其他類似的製程而形成。根據一些實施例，襯層介電質上的介電材料可包含氧化矽。
硬遮罩30的頂部表面與淺溝槽隔離區24的頂部表面彼此可實質 上同高度。半導體條26位於相鄰淺溝槽隔離區24間。根據本發明的一些實施例，半導體條26為部分的基底20，因此半導體條26的材料與基底20的材料相同。根據本發明的替代實施例，半導體條26是置換條(replacement strip)，其形成是藉由蝕刻基底20位於淺溝槽隔離區24之間的部分以形成凹槽，並執行磊晶以再成長(regrow)另一半導體材料於凹槽中。因此半導體條26是由與基底20不同的材料形成。根據一些實施例，半導體條26是由矽鍺(silicon germanium)、矽碳(silicon carbon)、或三-五族化合物半導體材料形成。
參照第3圖，將淺溝槽隔離區24凹入，使半導體條26的頂部部分突出並高於淺溝槽隔離區24剩餘部分的頂部表面24A，以形成突出鰭片36。此製程在第23圖所示的製程流程200中繪示為製程206。執行蝕刻可使用乾蝕刻製程，其中使用例如HF3及NH3作為蝕刻氣體。在蝕刻製程期間，可能產生電漿。也可能包含氬。根據本發明的替代實施例，執行淺溝槽隔離區24的凹入是使用濕蝕刻製程。舉例而言，蝕刻化學品可包括HF。
上述的實施例中，可用任何適合的方法將鰭片圖案化。舉例而言，可使用一或多道光微影(photolithography)製程將鰭片圖案化，包括雙重圖案化(double-patterning)或多重圖案化(multi-patterning)製程。一般而言，相較於單一的(single)、直接的(direct)光微影製程，雙重圖案化或多重圖案化製程結合光微影及自對準(self-aligned)製程，舉例而言，可使將產生的圖案具有較小的節距(pitch)。例如在一實施例中，形成犧牲層於基底上且使用光微影製程將其圖案化。使用自對準製程，沿圖案化犧牲層之側壁形成間隔物。然後移除犧牲層，且剩餘的間隔物，或心軸(mandrels)，可接著用於將鰭片圖案化。
參照第4圖，形成虛設閘極堆疊38，延伸至(突出)鰭片36的頂部表 面及側壁上。此製程在第23圖所示的製程流程200中繪示為製程208。虛設閘極堆疊38可包含虛設閘極介電質40及位於虛設閘極介電質40上的虛設閘極電極42。舉例而言，形成虛設閘極電極42可使用多晶矽(polysilicon)，且也可使用其他材料。每一個虛設閘極堆疊38也可包含虛設閘極電極42上的一(或複數)硬遮罩層44。可由氮化矽、氧化矽、碳氮化矽(silicon carbo-nitride)、或前述的多層形成硬遮罩層44。虛設閘極堆疊38可跨過單一或複數個突出鰭片36及/或淺溝槽隔離區24。此外，虛設閘極堆疊38之縱長方向(lengthwise direction)與突出鰭片36之縱長方向垂直。
然後形成閘極間隔物46於虛設閘極堆疊38之側壁上。此製程也在第23圖所示的製程流程200中繪示為製程208。根據本發明的一些實施例，由介電材料，例如氮化矽、碳氮化矽、或其他類似的介電材料形成閘極間隔物46，且其可具有單層結構或包含複數介電層的多層結構。
接著執行蝕刻製程，蝕刻突出鰭片36未被虛設閘極堆疊38及閘極間隔物46覆蓋的部分，產生如第5圖所示的結構。此製程在第23圖所示的製程流程200中繪示為製程210。此凹蝕可為非等向性(anisotropic)，因此鰭片36在虛設閘極堆疊38及閘極間隔物46的正下方部分受到保護而未被蝕刻。根據一些實施例，凹入的半導體條26之頂部表面可低於淺溝槽隔離區24之頂部表面24A。由此形成凹槽50。凹槽50包含位於虛設閘極堆疊38兩側的部分、以及在突出鰭片36剩餘部分之間的部分。
然後藉由選擇性地(selectively)成長(透過磊晶)半導體材料於凹槽50中，形成磊晶區(源極/汲極區)54，產生如第6圖所示的結構。此製程在第23圖所示的製程流程200中繪示為製程212。依產生的鰭式場效電晶體是p型鰭式場效 電晶體或n型鰭式場效電晶體而定，磊晶時可原位(in-situ)摻雜p型或n型雜質。舉例而言，當產生的鰭式場效電晶體是p型鰭式場效電晶體，可成長SiGeB或SiB。反之，當產生的鰭式場效電晶體是n型鰭式場效電晶體，可成長SiP或SiCP。根據本發明的替代實施例，磊晶區54包含三-五族化合物半導體，例如GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、前述之組合、前述之多層、或其他類似的化合物半導體。以磊晶區54填充凹槽50後，磊晶區54的進一步磊晶成長使磊晶區54水平延伸，並可形成刻面。磊晶區54的進一步成長也可使相鄰的磊晶區54彼此合併(merge)。可產生孔洞(void)(氣隙(air gap))56。根據本發明的一些實施例，結束磊晶區54的形成可在磊晶區54的頂部表面仍是波狀(wavy)時、或合併的磊晶區54之頂部表面已變得實質上平坦時，其可透過在磊晶區54上進一步成長達到，如第6圖所示。
在磊晶製程後，磊晶區54可進一步以p型或n型雜質佈植，以形成源極/汲極區，其也使用54表示。根據本發明的替代實施例，在磊晶期間，當磊晶區54以p型或n型雜質原位摻雜時，將佈植步驟略過。
第7A圖繪示出形成接觸蝕刻停止層(CESL)58及層間介電質(ILD)60後的結構示意圖。此製程在第23圖所示的製程流程200中繪示為製程214。接觸蝕刻停止層58可由氧化矽、氮化矽、碳氮化矽、或其他類似的材料形成，且可使用化學氣相沉積、原子層沉積、或其他類似的製程形成。層間介電質60可包括介電材料，舉例來說，使用流動化學氣相沉積、旋轉塗佈、化學氣相沉積、或另一沉積方法而形成的介電材料。層間介電質60可由含氧介電材料形成，其可為氧化矽為主的材料，例如四乙氧基矽烷(Tetra Ethyl Ortho Silicate,TEOS)氧化物、磷矽酸鹽玻璃(Phospho-Silicate Glass,PSG)、硼矽酸鹽玻璃 (Boro-Silicate Glass,BSG)、摻硼磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass,BPSG)、或其他類似的材料。可執行平坦化製程如化學機械研磨製程或機械磨光法，使層間介電質60、虛設閘極堆疊38、及閘極間隔物46之頂部表面彼此等高。
第7B圖繪示出第7A圖中的參考剖面7B-7B，其中繪示了虛設閘極堆疊38。接著將虛設閘極堆疊38蝕刻，其包括硬遮罩層44、虛設閘極電極42及虛設閘極介電質40，以形成閘極間隔物46之間的溝槽62，如第8圖所示。此製程在第23圖所示的製程流程200中繪示為製程216。突出鰭片36的頂部表面及側壁暴露於溝槽62。
然後如第9A及9B圖所示，形成置換閘極堆疊72於溝槽62(第8圖)中。第9B圖繪示出第9A圖中的參考剖面9B-9B。此製程在第23圖所示的製程流程200中繪示為製程218。置換閘極堆疊72包括閘極介電質68及相應的閘極電極70。
根據本發明的一些實施例，閘極介電質68包含界面層(IL)64作為其較低的部分。界面層64形成於突出鰭片36所露出的表面上。界面層64可包括氧化物層，例如氧化矽層，其形成是透過突出鰭片36的熱氧化、化學氧化製程、或沉積製程。閘極介電質68也可包括形成於界面層64上的高介電常數介電層66。高介電常數介電層66包含高介電常數介電材料，例如氧化鉿、氧化鑭、氧化鋁、氧化鋯、或其他類似的材料。高介電常數介電材料的常數介電(k值)高於3.9，且可高於約7.0，有時可高至21.0或更高。高介電常數介電層66覆在界面層64上且可與其接觸。將高介電常數介電層66形成為順應層(conformal layer)，且延伸至突出鰭片36之側壁及閘極間隔物46之頂部表面和側壁上。根據本發明的 一些實施例，形成高介電常數介電層66是使用原子層沉積、化學氣相沉積、電漿輔助化學氣相沉積、分子束沉積、或其他類似的製程。
進一步參照第9B圖，形成閘極電極70於閘極介電質68上。閘極電極70可包含複數個含金屬層74，可將其形成為順應層，且金屬填充區76填充其餘未被此複數個含金屬層74填充的溝槽。含金屬層74可包括阻障層、阻障層上的功函數層、以及功函數層上的一或複數個金屬蓋層。
第10圖是根據一些實施例，繪示出介電硬遮罩80之形成。此製程在第23圖所示的製程流程200中繪示為製程220。形成介電硬遮罩80可包括執行蝕刻製程以凹入閘極堆疊72，使凹槽形成，以介電材料填充此凹槽，然後執行平坦化製程如化學機械研磨製程或機械磨光法，以移除此介電材料的多餘部分。蝕刻製程中，也可能凹入閘極間隔物46，且介電硬遮罩80可突出並高於閘極間隔物46的頂部表面。可由氮化矽、氮氧化矽、氮碳氧化矽(silicon oxy-carbo-nitride)、或其他類似的材料形成介電硬遮罩80。
第11圖繪示出源極/汲極接觸插塞82之形成。此製程在第23圖所示的製程流程200中繪示為製程222。形成源極/汲極接觸插塞82包括蝕刻層間介電質60以暴露接觸蝕刻停止層58的下方部分，然後蝕刻接觸蝕刻停止層58的暴露部分，以露出源極/汲極區54。後續的製程中，沉積金屬層(例如Ti層)且延伸至接觸開口中。可形成金屬氮化物蓋層。然後執行退火製程使金屬層與源極/汲極區54的頂部表面起反應，以形成矽化區84。之後，將先前形成的金屬氮化物層留下，或者將先前形成的金屬氮化物層移除，然後沉積新的金屬氮化物層(例如氮化鈦層)。然後對接觸開口填入金屬填充材料，例如鎢、鈷、或其他類似的材料，接著透過平坦化移除多餘的材料，以產生源極/汲極接觸插塞82。接觸插塞82可延伸至接觸蝕刻停止層58的側壁部分且可與其接觸，或是藉由層間介電質60的 一些部分與接觸蝕刻停止層58的側壁部分隔開。因此形成多個鰭式場效電晶體86，可將其並聯為一個鰭式場效電晶體。
然後形成接觸插塞於源極/汲極接觸插塞82及閘極堆疊72中的閘極電極70上且與其電性連接。後續圖中的標示數字(例如12A、12B、12C、及12D)可包括相同數字後接續字母「A」、「B」、「C」、或「D」。字母「A」表示俯視圖。字母「B」表示在俯視圖中的參考剖面「B-B」之示意圖。字母「C」表示在俯視圖中的參考剖面「C-C」之示意圖。字母「D」表示在俯視圖中的參考剖面「D-D」之示意圖。
第12A圖繪示出第11圖所示的結構之俯視圖，且第12B、12C、及12D分別繪示出第12A圖中的參考剖面「B-B」、「C-C」、及「D-D」。結構的部分細節未繪示於第12A、12B、12C、12D、及後續的圖中。舉例而言，在第12B圖中，未繪示閘極堆疊72之細節，且在第12B、12C、及12D圖中，未繪示源極/汲極區、源極/汲極矽化區(source/drain silicide region)、半導體鰭片、淺溝槽隔離區、及其他類似的部分。舉例而言，參照第9B及11圖可找到未繪示的細節。
如第12A圖所示，可將源極/汲極接觸插塞82及層間介電質60分配(allocated)為複數欄(column)，且可將其交替地分配。可理解的是，所繪示的布局為範例，其中的源極/汲極接觸插塞82是依電路設計而形成。將介電硬遮罩80形成為條狀，具有在硬遮罩80下方的閘極堆疊72(未見於第12A圖，參照第12B圖)。可理解的是，由於閘極堆疊可分割為較短的部分以將同一欄中的閘極電極分隔為較小段(piece)，同一欄中的介電硬遮罩80可(或可不)分隔為較小的部分。
第12B圖繪示出第12A圖中的參考剖面B-B，且繪示了交替地分配複數個閘極堆疊72及複數個部分層間介電質60及下方的接觸蝕刻停止層58。第12C圖繪示出第12A圖中的參考剖面C-C，且繪示了交替地分配複數個閘極堆疊 72及複數個源極/汲極接觸插塞82。第12D圖繪示出第12A圖中的參考剖面D-D，且繪示了二個相鄰的源極/汲極接觸插塞82彼此被位於其間的層間介電質60及接觸蝕刻停止層58分隔。在全文中，將介電硬遮罩80替代地稱作自對準介電質-1(Self-Aligned Dielectric-1,SAD-1)。由於介電硬遮罩80的尺寸及位置是自對準於閘極堆疊及閘極間隔物的尺寸及位置。自對準介電質-1之材料可由以下材料中選擇且不限於：SiC、LaO、AlO、AlON、ZrO、HfO、SiN、ZnO、ZrN、ZrAlO、TiO、TaO、YO、TaCN、ZrSi、SiOCN、SiOC、SiCN、HfSi、SiO、以及其他類似的材料。
參照第13A、13C、及13D圖，形成介電硬遮罩88。此製程在第23圖所示的製程流程200中繪示為製程224。由於介電硬遮罩88是自對準於源極/汲極接觸插塞82且位於介電硬遮罩80之間，將其稱作自對準介電質-2(SAD-2)。介電硬遮罩88的材料與層間介電質60的材料不同，可由以下材料中選擇且不限於此：SiC、LaO、AlO、AlON、ZrO、HfO、SiN、ZnO、ZrN、ZrAlO、TiO、TaO、YO、TaCN、ZrSi、SiOCN、SiOC、SiCN、HfSi、SiO、以及其他類似的材料。此外，介電硬遮罩88的材料可與介電硬遮罩80的材料相同或相異。介電硬遮罩88的形成可包括：蝕刻第12A、12C及12D圖所示的源極/汲極接觸插塞82，以形成凹槽，將介電材料填入凹槽中，且執行平坦化製程，例如化學機械研磨製程或機械磨光法。介電硬遮罩88的底部可低於、或高於閘極間隔物46的頂部表面、或與其等高。介電硬遮罩88可不延伸至第13B圖的參考剖面，因此未繪示於其中。
第14A、14B、14C、14D、15A、15B、15C、15D、16A、16B、16C、及16D圖繪示出介電硬遮罩92之形成，其可替代地稱為自對準介電質-3(SAD-3)。此製程在第23圖所示的製程流程200中繪示為製程228。參照第14B 及14D圖，在蝕刻製程中將層間介電質60凹入，形成開口90。如第14A圖所示，凹槽90的位置和尺寸分別與層間介電質60及接觸蝕刻停止層58的位置和尺寸相同。凹蝕後，部分層間介電質60及接觸蝕刻停止層58留在各自的開口90下，其中接觸蝕刻停止層58具有U型剖面圖(參照第11圖)。開口90的底部可低於、或高於源極/汲極接觸插塞82及介電硬遮罩88間的界面(第14C及14D圖所示)、或與其等高。使用相對於介電硬遮罩80及88具高蝕刻選擇性的蝕刻氣體進行蝕刻，使介電硬遮罩80及88不被蝕刻。此外，閘極間隔物46未被損壞。
第15A、15B、15C、及15D圖繪示出介電材料92之形成。介電材料92可從具高崩潰電壓(breakdown voltage)的材料中選擇，例如高介電常數介電材料。介電材料92可包含以下材料且不限於此：SiC、LaO、AlO、AlON、ZrO、HfO、SiN、Si、ZnO、ZrN、ZrAlO、TiO、TaO、YO、TaCN、ZrSi、SiOCN、SiOC、SiCN、HfSi、或其他類似的材料。此外，雖然介電材料92可與介電硬遮罩80及88具有共通的候選材料，但介電材料92的材料與介電硬遮罩80及88的材料都不同，使後續的蝕刻製程有高蝕刻選擇值(etching selectivity value)。介電材料92的形成方法包括原子層沉積、旋轉塗佈、電漿輔助化學氣相沉積、或其他類似的方法。
根據本發明的一些實施例，若介電材料92的頂部表面是不平坦的，則將其平坦化。否則可略過平坦化製程。然後執行回蝕刻(etch-back)製程，直到剩餘介電材料92的頂部表面與介電硬遮罩80(第16B圖)及介電硬遮罩88(第16C圖)的頂部表面共平面。根據本發明的一些實施例，執行平坦化製程直到介電硬遮罩80及88都露出。介電材料92的剩餘部分也可稱作介電硬遮罩92或自對準介電質-3 92。第16A及16D圖分別繪示出俯視圖及剖面圖。此時介電硬遮罩 80、88、及92的頂部表面皆露出，且可共平面。
如第16D圖所示，形成氣隙94，其被封入相應的介電硬遮罩92。並由於介電硬遮罩92的頂部寬度小於底部寬度，孔洞96可能形成於底角，其為角落區(corner region)，是由源極/汲極接觸插塞82、接觸蝕刻停止層/層間介電質58/60、及介電硬遮罩92所定義。若在俯視視角，氣隙94及孔洞96可形成細長條(elongated strip)，其縱長方向平行於硬遮罩92的縱長方向。根據一些替代實施例，氣隙94及孔洞96的其中之一未形成，或者是兩者皆未形成。
第17A、17B、17C、及17D圖繪示出蝕刻停止層102及硬遮罩104的形成，其用於形成及保護狹縫閘極接觸開口和狹縫源極/汲極接觸開口的圖案。此製程在第23圖所示的製程流程200中繪示為製程230。可由氧化物、氮化物、碳化物、氧碳化物(oxycarbide)、或其他類似的材料形成蝕刻停止層102。可由氮化鈦、氮化硼、氧化物、氮化物、或其他類似的材料形成硬遮罩104。
接著如第18A、18B、18C、及18D圖所示，形成狹縫源極/汲極接觸開口。此製程在第23圖所示的製程流程200中繪示為製程232。蝕刻部分硬遮罩104及蝕刻停止層102，使開口106(第18A、18C、及18D圖所示)形成於硬遮罩104及蝕刻停止層102中。第18A圖繪示一範例，其中形成狹縫型(細長的)開口106，由此露出下方的介電硬遮罩88及92。根據本發明的一些實施例，為形成開口106，先形成光阻108且將其圖案化，然後使用圖案化光阻108作為蝕刻遮罩，蝕刻硬遮罩104及蝕刻停止層102。
接著如第18C及18D圖所示，蝕刻介電硬遮罩88露出的部分以延伸狹縫開口106至介電硬遮罩80之間。此製程在第23圖所示的製程流程200中繪示為製程232。部分狹縫開口106因此向下延伸至低於第三介電硬遮罩92的頂部表 面(第18D圖)，以下將此些部分稱為狹縫開口延伸區。一些源極/汲極接觸插塞82是暴露的，如第18C及18D圖所示。且如第18D圖所示，留下介電硬遮罩92。用蝕刻劑執行介電硬遮罩88之蝕刻，使蝕刻具高蝕刻選擇值(介電硬遮罩88之蝕刻速率對介電硬遮罩92之蝕刻速率的比值)，舉例而言，高於約20、30，或更高。因此如第18D圖所示，介電硬遮罩92未被蝕刻而留下，以將相鄰狹縫開口延伸區彼此分隔。此外，舉例而言，蝕刻中的蝕刻選擇性(介電硬遮罩88之蝕刻速率對比介電硬遮罩80之蝕刻速率)可為約1.0至約50。然後將光阻108移除。
第19A、19B、19C、及19D圖與第20A、20B、20C、及20D圖繪示出狹縫閘極接觸開口之形成。此製程在第23圖所示的製程流程200中繪示為製程234。第19A、19B、19C、及19D圖繪示出此形成及光阻110的圖案化，其中如第19A及19B圖所示，形成狹縫開口112。接著使用光阻110作為蝕刻遮罩，將下方的硬遮罩104及蝕刻停止層102進行蝕刻，使狹縫開口112延伸至硬遮罩104及蝕刻停止層102，如第20B圖所示。
在硬遮罩104及蝕刻停止層102的蝕刻後，蝕刻暴露的硬遮罩80，露出下方的閘極堆疊72，如第20A及20B圖所示。此製程也在第23圖所示的製程流程200中繪示為製程234。部分狹縫開口112因此向下延伸至低於第三介電硬遮罩92的頂部表面，以下將此些部分稱為狹縫開口延伸區。用蝕刻劑執行介電硬遮罩80之蝕刻，使蝕刻具高蝕刻選擇值(介電硬遮罩80之蝕刻速率對介電硬遮罩92之蝕刻速率的比值)，舉例而言，高於約20、30，或更高。因此如第20B圖所示，介電硬遮罩92未被蝕刻而留下，以將相鄰狹縫開口延伸區彼此分隔。此外，舉例而言，蝕刻中的蝕刻選擇性(介電硬遮罩80之蝕刻速率對比介電硬遮罩88之蝕刻速率)可為約1.0至約50。然後將光阻110移除。
由於形成介電硬遮罩92所選擇的材料不同於介電硬遮罩80及88的材料，蝕刻介電硬遮罩80及88時可具有高蝕刻選擇性，因此在狹縫源極/汲極接觸開口106及狹縫閘極接觸開口112的形成期間，介電硬遮罩92未被凹入。除此之外，若未形成介電硬遮罩92以置換層間介電質60，在形成狹縫開口時，區域91A(第20B圖)及區域94B(第20D圖)中的層間介電質60之頂部部分將被凹入。
以上所討論的製程中，是將二個源極/汲極接觸插塞82暴露於狹縫源極/汲極接觸開口106作為範例，且將二個閘極堆疊72暴露於狹縫閘極接觸開口112作為範例。根據本發明的一些實施例，可將狹縫源極/汲極接觸開口106及狹縫閘極接觸開口112形成為更細長，使三個或更多個源極/汲極接觸插塞82可暴露於相同的狹縫源極/汲極接觸開口106，且使三個或更多個閘極堆疊72可暴露於相同的狹縫閘極接觸開口112。
如第20B及20D圖所示，狹縫開口106和112都保留在硬遮罩104和蝕刻停止層102中。二個(或更多個)源極/汲極接觸插塞82位於下方且暴露於相同的狹縫源極/汲極接觸開口106，且二個(或更多個)閘極堆疊72位於下方且暴露於相同的狹縫閘極接觸開口112。
然後形成源極/汲極接觸插塞及閘極接觸插塞於開口106及112中。此製程在第23圖所示的製程流程200中繪示為製程236。此形成製程可包括將一種(或多種)導電材料填入開口106及112中，並且執行平坦化製程，例如化學機械研磨製程或機械磨光法，以移除導電材料的過量部分。由此產生的閘極接觸插塞114及源極/汲極接觸插塞116，繪示於第21A、21B、21C、及21D圖。所繪示的閘極接觸插塞114可屬於不同的鰭式場效電晶體。所繪示的源極/汲極接觸插塞116也可屬於不同的鰭式場效電晶體。根據本發明的一些實施例，填充的導 電材料包含擴散阻障層及填充材料，其中擴散阻障層可由氮化鈦、氮化鉭、鈦、或鉭形成，且填充材料的範例為銅、鎢、鈷、釕、或其他類似的材料。
如第21A及21B圖所示，二個相鄰的閘極接觸插塞114被位於其間的介電硬遮罩92彼此分隔。如前所提及，介電硬遮罩92的材料選擇是為了在形成閘極接觸插塞114將填入的開口時，可不被凹入。不過若未形成介電硬遮罩92，則層間介電質60可佔據介電硬遮罩92的空間，並且當狹縫接觸開口106(第18D圖)形成時，層間介電質60可能被凹入，導致在形成閘極接觸開口時，區域94A(第21B圖)可能變成凹槽。如此將造成相鄰的閘極接觸插塞114電性短路。因此，透過形成介電硬遮罩92，將相鄰閘極接觸插塞114的電性短路消除。同樣地，形成介電硬遮罩92於區域94B中(第21D圖)，使其在形成源極/汲極接觸開口時更能抵抗損害。因此將相鄰源極/汲極接觸接觸插塞116的電性短路消除。
第22圖繪示出放大的第21D圖。根據本發明的一些實施例，氣隙94的高度H1約0nm至約50nm，其寬度W1約0nm至約30nm。孔洞96的高度H2約0nm至約50nm，其寬度W2約0nm至約30nm。氣隙94的底部至下方層間介電質60的頂部之垂直距離D1約0nm至約60nm。剩餘介電硬遮罩88的寬度W3約0nm至約30nm。在繪示的介電硬遮罩92之側壁上未有剩餘的介電硬遮罩88，且源極/汲極接觸插塞116時與介電硬遮罩92實體接觸，第21D圖中每個剩餘介電硬遮罩88的存在與否，取決於狹縫源極/汲極接觸開口之尺寸。介電硬遮罩92的高度H3(第21B圖)約1nm至約40nm。此外，高度H3對層間介電質60及接觸蝕刻停止層58位於介電硬遮罩92的正下方部分之總高度的比例約0.2至12。
本發明之實施例具有一些有利的特徵。隨著積體電路中部件尺寸的縮小，源極/汲極接觸插塞和閘極接觸插塞的尺寸也縮小。舉例來說，由於光微影製程(photo lithography)的限制，形成小尺寸的接觸插塞變得更困難。於是形成狹縫接觸插塞以克服此限制，透過相同的狹縫源極/汲極接觸開口，使複數個 源極/汲極接觸插塞得以形成，且透過相同的狹縫閘極接觸開口，形成複數個閘極接觸插塞。但由於層間介電質的損壞，透過相同的狹縫開口所形成的源極/汲極接觸插塞遭受電性短路的問題，且透過相同的狹縫源開口所形成的閘極接觸插塞也因層間介電質的損壞而遭受電性短路。藉由形成介電硬遮罩92可解決此問題。此外，由於相鄰閘極接觸插塞(或源極/汲極接觸插塞)之間的距離很小，介電質崩潰的可能性也增加。根據本發明的實施例，可因此使用比層間介電質具更高崩潰電壓的材料形成介電硬遮罩92。
根據本發明的一些實施例，積體電路結構之形成方法包括：形成第一源極/汲極接觸插塞於電晶體的源極/汲極區上且與其電性耦合；形成一第一介電硬遮罩，與一閘極堆疊重疊；凹入此第一源極/汲極接觸插塞，以形成一第一凹槽；形成一第二介電硬遮罩於此第一凹槽中；凹入一層間介電層以形成一第二凹槽；以及形成一第三介電硬遮罩於此第二凹槽中，其中此第三介電硬遮罩接觸此第一介電硬遮罩及此第二介電硬遮罩。在一實施例中，形成第三介電硬遮罩包括一平坦化製程，以平坦化第一介電硬遮罩、第二介電硬遮罩、及第三介電硬遮罩彼此的頂部表面。在一實施例中，此方法更包括在形成第三介電硬遮罩後，移除第二介電硬遮罩以形成一第三凹槽。在一實施例中，此方法更包括將一導電材料填入第三凹槽，以形成一第二源極/汲極接觸插塞於第一源極/汲極接觸插塞上且與其接觸，其中第二源極/汲極接觸插塞的一側壁接觸第一介電硬遮罩的一側壁，形成實質上垂直的一界面。在一實施例中，使用一蝕刻劑移除第二介電硬遮罩，且暴露於此蝕刻劑的第三介電硬遮罩並未被蝕刻。在一實施例中，此方法更包括在形成第三介電硬遮罩後，移除第一介電硬遮罩以形成一第四凹槽。在一實施例中，此方法更包括將一導電材料填入第四凹槽，以形成一閘極接觸插塞於閘極堆疊上且與其接觸，其中此閘極接觸插塞的一側壁接觸第三介電硬遮罩的一側壁，形成實質上垂直的一界面。在一實施例中， 使用一蝕刻劑移除第一介電硬遮罩，且暴露於此蝕刻劑的第三介電硬遮罩並未被蝕刻。在一實施例中，形成第三介電硬遮罩包括形成一高介電常數介電區。在一實施例中，一氣隙被封入第三介電硬遮罩。
根據本發明的一些實施例，積體電路結構之形成方法包括：凹入一層間介電質以形成一第一凹槽；以一第一介電硬遮罩填充此第一凹槽；形成一硬遮罩於此第一介電硬遮罩及二個第二介電硬遮罩上，其中所述二個第二介電硬遮罩位於此第一介電硬遮罩之相對兩側上，且與其接觸；形成一狹縫開口於此硬遮罩，以露出此第一介電硬遮罩及所述二個第二介電硬遮罩；使用蝕刻移除所述二個第二介電硬遮罩，以形成多個狹縫開口延伸區，其中下方導電部件暴露於此些狹縫開口延伸區，且此下方導電部件包括閘極堆疊或源極/汲極接觸插塞，其中此第一介電硬遮罩在此蝕刻中是露出的，且在此蝕刻後仍存在；填充一導電材料，其中此導電材料包括此狹縫開口中的一第一部分及此些狹縫開口延伸區中的多個第二部分；以及移除此導電材料之此第一部分，其中留下此導電材料之此些第二部分，以形成彼此實體上分隔的二個接觸插塞。在一實施例中，下方導電部件包括源極/汲極接觸插塞，且所述二個接觸插塞包括二個額外的源極/汲極接觸插塞。在一實施例中，下方導電部件包括閘極堆疊，且所述二個接觸插塞包括二個閘極接觸插塞。在一實施例中，在移除所述二個第二介電硬遮罩時，所述二個第二介電硬遮罩及第一介電硬遮罩具有一高於約20的蝕刻選擇性。在一實施例中，移除導電材料之第一部分包括一平坦化製程，且其中在此平坦化製程後露出第一介電硬遮罩。
根據本發明的一些實施例，積體電路結構包括：一第一閘極堆疊及一第二閘極堆疊；一層間介電質，位於此第一閘極堆疊及此第二閘極堆疊之間；一介電硬遮罩，與此層間介電質重疊且接觸，其中此介電質硬遮罩及此層間介電質是由不同材料形成；一第一閘極接觸插塞，位於此第一閘極堆疊上且 與其接觸；以及一第二閘極接觸插塞，位於此第二閘極堆疊上且與其接觸，其中此第一閘極接觸插塞與此第二閘極接觸插塞彼此被此介電硬遮罩分隔，且此第一閘極接觸插塞及此第二閘極接觸插塞之側壁接觸此介電硬遮罩之側壁，形成實質上垂直的多個界面。在一實施例中，第一閘極接觸插塞、第二閘極接觸插塞、及介電硬遮罩之頂部表面共平面。在一實施例中，介電硬遮罩是由高介電常數介電材料形成。在一實施例中，積體電路結構更包括多個閘極間隔物，位於第一閘極堆疊及第二閘極堆疊之兩側上，其中介電硬遮罩之一底部表面低於此些閘極間隔物之頂部表面。在一實施例中，介電硬遮罩之一頂部表面高於閘極間隔物之頂部表面。
以上概述數個實施例之部件，以便在本發明所屬技術領域中具有通常知識者可更易理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解，他們能以本發明實施例為基礎，設計或修改其他製程和結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解到，此類等效的製程和結構並無悖離本發明的精神與範圍，且他們能在不違背本發明之精神和範圍之下，做各式各樣的改變、取代和替換。
58:接觸蝕刻停止層
60:層間介電質
82,116:源極/汲極接觸插塞
88:介電硬遮罩
92:介電材料
94:氣隙
96:孔洞
D1:垂直距離
H1,H2,H3:高度
W1,W2,W3:寬度

Claims (15)

  1. 一種積體電路結構之形成方法，包括：形成一第一源極/汲極接觸插塞於一電晶體的源極/汲極區上且與其電性耦合；形成一第一介電硬遮罩，與該電晶體的一閘極堆疊重疊，其中該第一介電硬遮罩具有一側壁；凹入該第一源極/汲極接觸插塞，以形成一第一凹槽；形成一第二介電硬遮罩於該第一凹槽中；凹入一層間介電層以形成一第二凹槽；以及形成一第三介電硬遮罩於該第二凹槽中，其中該第一介電硬遮罩的該側壁接觸該第三介電硬遮罩及該第二介電硬遮罩。
  2. 如請求項1所述的積體電路結構之形成方法，其中形成該第三介電硬遮罩包括一平坦化製程，以平坦化該第一介電硬遮罩、該第二介電硬遮罩、及該第三介電硬遮罩彼此的頂部表面。
  3. 如請求項1或2所述的積體電路結構之形成方法，更包括在形成該第三介電硬遮罩後，移除該第二介電硬遮罩以形成一第三凹槽，其中使用一蝕刻劑移除該第二介電硬遮罩，且暴露於該蝕刻劑的該第三介電硬遮罩並未被蝕刻。
  4. 如請求項3所述的積體電路結構之形成方法，更包括將一導電材料填入該第三凹槽，以形成一第二源極/汲極接觸插塞於該第一源極/汲極接觸插塞上且與其接觸，其中該第二源極/汲極接觸插塞的一側壁接觸該第一介電硬遮罩的該側壁，形成實質上垂直的一界面。
  5. 如請求項1或2所述的積體電路結構之形成方法，更包括在形成該第三介電硬遮罩後，移除該第一介電硬遮罩以形成一第四凹槽，其中使用一蝕刻劑移除該第一介電硬遮罩，且暴露於該蝕刻劑的該第三介電硬遮罩並未被蝕刻。
  6. 如請求項5所述的積體電路結構之形成方法，更包括將一導電材料填入該第四凹槽，以形成一閘極接觸插塞於該閘極堆疊上且與其接觸，其中該閘極接觸插塞的一側壁接觸該第三介電硬遮罩的一側壁，形成實質上垂直的一界面。
  7. 如請求項1或2所述的積體電路結構之形成方法，其中形成該第三介電硬遮罩包括形成一高介電常數介電區。
  8. 如請求項1或2所述的積體電路結構之形成方法，其中一氣隙被封入該第三介電硬遮罩。
  9. 一種積體電路結構之形成方法，包括：凹入一層間介電質以形成一第一凹槽；以一第一介電硬遮罩填充該第一凹槽；形成一硬遮罩於該第一介電硬遮罩及二個第二介電硬遮罩上，其中所述二個第二介電硬遮罩位於該第一介電硬遮罩之兩側上，且與其接觸；形成一狹縫開口於該硬遮罩，以露出該第一介電硬遮罩及所述二個第二介電硬遮罩；使用蝕刻移除所述二個第二介電硬遮罩，以形成多個狹縫開口延伸區，其中下方導電部件暴露於該些狹縫開口延伸區，且該下方導電部件包括閘極堆疊或源極/汲極接觸插塞，其中該第一介電硬遮罩在該蝕刻中是露出 的，且在該蝕刻後仍存在；填充一導電材料，其中該導電材料包括該狹縫開口中的一第一部分及該些狹縫開口延伸區中的多個第二部分；以及移除該導電材料之該第一部分，其中留下該導電材料之該些第二部分，以形成彼此實體上分隔的二個接觸插塞。
  10. 如請求項9所述的積體電路結構之形成方法，其中該下方導電部件包括源極/汲極接觸插塞或閘極堆疊，且所述二個接觸插塞包括二個額外的源極/汲極接觸插塞或二個閘極接觸插塞。
  11. 如請求項9所述的積體電路結構之形成方法，其中在移除所述二個第二介電硬遮罩時，所述二個第二介電硬遮罩及該第一介電硬遮罩具有一高於約20的蝕刻選擇性。
  12. 如請求項9所述的積體電路結構之形成方法，其中移除該導電材料之該第一部分包括一平坦化製程，且其中在該平坦化製程後露出該第一介電硬遮罩。
  13. 一種積體電路結構，包括：一第一閘極堆疊及一第二閘極堆疊；一層間介電質，位於該第一閘極堆疊及該第二閘極堆疊之間；一介電硬遮罩，與該層間介電質重疊且接觸，其中該介電質硬遮罩及該層間介電質是由不同材料形成；一第一閘極接觸件，位於該第一閘極堆疊上且與其接觸；以及一第二閘極接觸件，位於該第二閘極堆疊上且與其接觸，其中該第一閘極接觸件與該第二閘極接觸件彼此被該介電硬遮罩分隔，且該第一閘極接觸件及該 第二閘極接觸件之側壁接觸該介電硬遮罩之側壁，形成實質上垂直的多個界面。
  14. 如請求項13所述的積體電路結構，其中該第一閘極接觸件、該第二閘極接觸件、及該介電硬遮罩之頂部表面共平面。
  15. 如請求項13所述的積體電路結構，更包括多個閘極間隔物，位於該第一閘極堆疊及該第二閘極堆疊之兩側上，其中該介電硬遮罩之一底部表面低於該些閘極間隔物之頂部表面或該介電硬遮罩之一頂部表面高於該些閘極間隔物之頂部表面。
TW108137415A 2018-10-23 2019-10-17 積體電路結構及其形成方法 TWI721605B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862749207P 2018-10-23 2018-10-23
US62/749,207 2018-10-23
US16/373,215 2019-04-02
US16/373,215 US10943829B2 (en) 2018-10-23 2019-04-02 Slot contacts and method forming same

Publications (2)

Publication Number Publication Date
TW202025237A TW202025237A (zh) 2020-07-01
TWI721605B true TWI721605B (zh) 2021-03-11

Family

ID=70279760

Family Applications (1)

Application Number Title Priority Date Filing Date
TW108137415A TWI721605B (zh) 2018-10-23 2019-10-17 積體電路結構及其形成方法

Country Status (5)

Country Link
US (3) US10943829B2 (zh)
KR (1) KR102269804B1 (zh)
CN (1) CN111092053B (zh)
DE (1) DE102019110004A1 (zh)
TW (1) TWI721605B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11476196B2 (en) * 2018-11-27 2022-10-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with multi-layer dielectric
US11721580B2 (en) * 2019-06-10 2023-08-08 Intel Corporation 1D vertical edge blocking (VEB) via and plug
US11355637B2 (en) 2020-06-30 2022-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160149036A1 (en) * 2014-11-25 2016-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain structure and manufacturing the same
TW201712866A (zh) * 2015-09-18 2017-04-01 台灣積體電路製造股份有限公司 半導體結構及其製造方法
US20170117406A1 (en) * 2013-08-01 2017-04-27 Samsung Electronics Co., Ltd. Semiconductor device with adjacent source/drain regions connected by a semiconductor bridge, and method for fabricating the same
US20170256613A1 (en) * 2016-03-03 2017-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US20170256456A1 (en) * 2016-03-04 2017-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100414220B1 (ko) * 2001-06-22 2004-01-07 삼성전자주식회사 공유 콘택을 가지는 반도체 장치 및 그 제조 방법
KR100503519B1 (ko) * 2003-01-22 2005-07-22 삼성전자주식회사 반도체 장치 및 그 제조방법
KR100569523B1 (ko) 2003-06-30 2006-04-07 주식회사 하이닉스반도체 반도체소자의 비트라인 형성방법
CN100514596C (zh) * 2006-01-13 2009-07-15 联华电子股份有限公司 金属内连线的制作方法与结构
CN103915372B (zh) * 2013-01-08 2016-08-31 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
CN103915384B (zh) * 2013-01-08 2016-08-10 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN104900593B (zh) * 2014-03-04 2018-02-16 中芯国际集成电路制造(上海)有限公司 存储器及其形成方法
US10163704B2 (en) 2015-12-29 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
US9793372B1 (en) 2016-05-25 2017-10-17 Globalfoundries Inc. Integrated circuit including a dummy gate structure and method for the formation thereof
US10164111B2 (en) * 2016-08-03 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and methods of manufacture
US10062784B1 (en) * 2017-04-20 2018-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned gate hard mask and method forming same
US10475654B2 (en) * 2017-08-31 2019-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap-around contact plug and method manufacturing same
US11587791B2 (en) * 2018-10-23 2023-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon intermixing layer for blocking diffusion

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170117406A1 (en) * 2013-08-01 2017-04-27 Samsung Electronics Co., Ltd. Semiconductor device with adjacent source/drain regions connected by a semiconductor bridge, and method for fabricating the same
US20160149036A1 (en) * 2014-11-25 2016-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain structure and manufacturing the same
TW201712866A (zh) * 2015-09-18 2017-04-01 台灣積體電路製造股份有限公司 半導體結構及其製造方法
US20170256613A1 (en) * 2016-03-03 2017-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US20170256456A1 (en) * 2016-03-04 2017-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
CN111092053A (zh) 2020-05-01
US20210175125A1 (en) 2021-06-10
DE102019110004A1 (de) 2020-04-23
US11532518B2 (en) 2022-12-20
US10943829B2 (en) 2021-03-09
KR20200047292A (ko) 2020-05-07
CN111092053B (zh) 2023-12-29
US20200126865A1 (en) 2020-04-23
US20230119732A1 (en) 2023-04-20
TW202025237A (zh) 2020-07-01
KR102269804B1 (ko) 2021-06-29

Similar Documents

Publication Publication Date Title
TWI723288B (zh) 半導體裝置及其製造方法
US10186511B2 (en) Metal gate isolation structure and method forming same
TWI662601B (zh) 半導體元件及其製造方法
TWI619178B (zh) 半導體裝置及其製造方法
US11791393B2 (en) Semiconductor device and method of forming the same
TW202109629A (zh) 半導體裝置及其形成方法
TWI643252B (zh) 半導體裝置的形成方法
TWI724611B (zh) 積體電路裝置及其形成方法
TWI721605B (zh) 積體電路結構及其形成方法
US11177361B2 (en) FinFET and gate-all-around FET with selective high-k oxide deposition
US20230246089A1 (en) Reducing Pattern Loading in the Etch-Back of Metal Gate
US20220336449A1 (en) Semiconductor device structure and methods of forming the same
TW202113974A (zh) 半導體裝置
TW202131389A (zh) 半導體結構及其形成方法
TW202139264A (zh) 半導體裝置的製造方法
TW202123472A (zh) 半導體裝置及其形成方法
US11658244B2 (en) Semiconductor device structure
US11145728B2 (en) Semiconductor device and method of forming same
TW202240899A (zh) 半導體裝置結構
KR102379097B1 (ko) 저비저항 전도성층을 통한 게이트 저항 감소
TW202143300A (zh) 半導體裝置及其製造方法
US11942478B2 (en) Semiconductor device structure and methods of forming the same
US20230369127A1 (en) Semiconductor structure and method for forming the same
TW202240698A (zh) 半導體裝置的形成方法
TW202236682A (zh) 半導體裝置結構