CN105489513A - 用于永久连接两个金属表面的方法 - Google Patents

用于永久连接两个金属表面的方法 Download PDF

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CN105489513A
CN105489513A CN201510912162.7A CN201510912162A CN105489513A CN 105489513 A CN105489513 A CN 105489513A CN 201510912162 A CN201510912162 A CN 201510912162A CN 105489513 A CN105489513 A CN 105489513A
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metal
diffusion
bonding
contact
atom
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CN105489513B (zh
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M.温普林格
V.德拉戈伊
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EV Group E Thallner GmbH
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EV Group E Thallner GmbH
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Abstract

本发明涉及用于永久连接两个金属表面的方法。本发明涉及用于在第一衬底的第一金属表面和第二衬底的第二金属表面之间制造永久的导电连接的方法，具有如下方法步骤：定向和键合第一和第二金属表面，其中在两个金属表面紧密接触期间进行温度步骤，使得在第一和第二金属表面之间的空洞通过塑性变形被封闭。

Description

用于永久连接两个金属表面的方法
技术领域
本申请是申请日为2011年2月23日、申请号为201180016870.2、发明名称为“用于永久连接两个金属表面的方法”的发明专利申请的分案申请。
本发明涉及按照权利要求1的用于在两个金属表面之间制造永久连接的方法。
背景技术
在两个金属表面之间制造永久的导电金属连接在半导体工业中越来越重要。特别是对于在所谓的“3D集成器件或IC（3DIC）”的领域中新式的封装技术，在两个功能层面之间的金属键合（Bond）连接起决定性作用。在此，首先在两个独立的衬底上制成有源或无源的电路，并且在键合步骤将它们永久地相互连接，以及建立电接触。该连接步骤可以或者借助两个晶片（晶片到晶片-W2W）的连接、一个或多个芯片与晶片（芯片到晶片-C2W）的连接、或者一个或多个芯片与芯片（芯片到芯片-C2C）的连接方法来进行。在这些连接方法中对在两个连接面之间的直接连接有大的兴趣，其中两个面很大程度上由相同的材料（金属）组成。在此如下方法是完全尤其有利的，所述方法在所述连接层面中很大程度上无附加的材料也行。通常在此情况下使用铜（Cu）或铝（Al）或金（Au）作为金属化结构。但是，应当澄清的是，本发明原则上也与其它金属相互作用地起作用，并且金属选择主要基于芯片结构的要求和预加工步骤。因此其他金属也应当是被认为是本发明的所需要的。此外，该方法也可以被应用到所谓的“混合键合界面（HybridBondInterface）”上。这些混合界面由被非金属区域包围的金属接触面的合适组合组成。这些非金属区域在此被设计为使得可以在单个结合步骤中不仅制造金属接触、而且制造在非金属区域之间的接触。当前这些没有异质材料、尤其是异质金属的连接是通过所谓的扩散键合方法来制造的。在此，接触面相对彼此定向并且接触。接触面借助合适的方法（例如“化学机械抛光（ChemicalMechanicalPolishing）”或者简写为“CMP”）这样被预处理，使得它们是非常平的，并且具有小的表面粗糙度。接触面于是在合适的设备（例如晶片键合机）中被压在一起并且同时被加热到可自由选择的过程温度。这里也可以证实为有利的是，这发生在优化的气氛中、例如真空（例如<1mbar,优选<1e-3mbar）或者在还原性气氛中、尤其是具有氢（H2）高含量（>1％，优选>3％，更好地>5％并且理想地>9％）的气氛。在这些过程条件下现在形成在两个金属表面之间的所谓的扩散键合。在此，金属原子或分子在低共熔金属复合物的情况下在两个表面之间来回扩散并且由此建立永久的、金属传导的并且机械上非常稳定的在表面之间的连接。通常，该连接在此具有使得在金属组织中对原始接触面的探测不可能的性质。更确切地说，该连接表现为均质的金属结构，其现在延伸超出原始的接触面。当今强烈限制该技术的使用的因素是大多相对高的温度，该温度是制造连接和实现尤其是扩散所必需的。在许多情况下，该温度高于300℃，在许多情况下高于350℃，典型地380至400℃并且在确定的情况下也直至450或500℃高于由部件可以容忍的温度（典型地<260℃，经常<230℃，对于确定的部件<200℃，并且在确定情况下<180或甚至150<℃）并且因此防止或者限制了该方法的使用。现在本发明回避了该问题，因为其能够实现如下方法，其中所需要的过程温度被显著地降低。
这些金属连接在下面在该文献中现在应当被称为“真实的（sortenreine）键合连接”。在此，总是提到键合连接，在键合连接中在两个由金属A制成的金属接触面之间产生连接，而不借助永久地置入该连接中的异质材料、尤其是异质金属B，其具有不同的基本成分。
如上面已经描述地，当前存在的方法通过实现扩散过程需要的过程温度限制。原则上，可以理解，扩散过程是与大量因素相关的过程。但是使得该过程在较低的温度情况下较缓慢地进行。但是这在实践中是有问题的，因为这会限制这种过程的经济性或者使得非常费时的（>1h）过程是不经济的。因此，扩散键合过程不应用在同类的接触面之间。代替地，在该情况下，使用焊接连接或者低共熔连接和所谓的金属间复合连接的最不同的表现。作为例子，这里列举了基于铅/锡焊接、铜-银-锡焊接的焊接连接、基于铟的焊接或者还有金-锡或金-硅或者铝-锗以及铜-锡（金属间复合Cu3Sn）。这些方法的缺点不仅存在于制造物流问题中而且也存在于技术问题中。经常应该在制造的仅仅建立并且合格化确定的金属化结构（例如铜）的范围中制造这些键合连接。在该情况下，除了该金属化结构外构建和也合格化用于另外的金属化结构的基础设施是巨大的额外耗费。从技术的角度，低共熔连接在长期稳定性方面被考虑为是关键性的。确定的连接是极其易碎并且因此可以尤其是出现机械的疲劳现象。此外，对于确定的金属化结构要遵循在混合比方面的非常窄的容差，以便保证低共熔连接的所希望的特性（例如融化温度，机械和电特性）。此外，可能引起与低共熔连接问题关联的扩散效应。这样，当来自两个铜接触面之间的界面的锡会扩散穿过整个铜接触并且到达位于其下的、在铜接触和位于其下的层之间的界限层时，这例如是严重的问题。由于变化的金属复合物，这会导致在该界面中的铜的机械分层，并且由此导致部件的机械故障，所述机械故障只有在现场中在多年之后才可能出现。这是以该形式仅仅在微结构情况下可能出现的效应，因为这里使用非常薄的层，其中这种效应才能够起作用。
发明内容
因此本发明的任务是，说明一种方法，利用所述方法能够实现在金属键合连接情况下的减小的过程温度和/或减少的过程时间。
该任务借助权利要求1的特征来解决。本发明的有利的改进在从属权利要求中被说明。由至少两个在说明书、权利要求书和/或图中说明的特征的全部组合也落入本发明的范畴中。在所说明的值范围情况下，处于所提到的界限内部的值也作为界限值被公开并且可以以任意组合被要求保护。
具体实施方式
本发明现在呈现方法和过程，借助其可以使用于真实的键合连接的键合温度显著下降，并且其由此可以实现将无异质金属也行的连接使用于广泛的使用范围。本发明的附加利用也是过程的加速，该加速在理想选择的过程参数的情况下可以被实现，并且其提高过程的经济性。
扩散一般可以被划分为置换式和填隙式扩散。
在置换扩散情况下，沿着晶格中的其它原子可能所处的点进行各个原子的扩散跳跃。但是，为了根本上可以进行这种扩散跳跃，不允许在原子想跳跃到其上的位置处存在其它原子（存在例外：直接原子交换机制，其在科学上被讨论但是还没有被证实，如果所述直接原子交换机制存在，则其与其它原子交换机制相比稀少地出现，使得其可被忽视）。在其处不存在原子的位置被称为空穴。空穴在进一步的专利描述中将占据根本上重要的方面。
在填隙式扩散情况下，较小的原子在晶体的晶格间隙内部扩散。因为我们在本专利中主要研究同原子扩散，因此不进一步考虑填隙式扩散。
用于填隙式扩散的例子是氢，其扩散到Si晶体晶格的晶格间隙中。氢与Si相比是如此“小”，使得其在晶格间隙中有空间。
按照本发明，对于相同金属种类的同原子扩散的情况仅仅置换扩散是合适的。
此外，可以在表面扩散、晶界扩散和体积扩散之间进行区别。原子最好在其由尽可能少的其它原子限制的地方扩散。该状态尤其是存在于表面处，由此也表明原子在表面上的高移动性。即使在晶界中，原子通常也具有比在晶体晶格本身中多的空间。扩散种类的速度因此处于表面扩散的速度和体积扩散的速度之间。晶界扩散的前提当然是晶界的存在。
对于多晶的金属表面的当前情况，在直接键合情况下出现下面的问题。
第一，多晶的材料由多个晶粒组成，这些晶粒相对于待键合的表面不同地取向。这导致表面由不同的结晶表面组成。各个晶粒表面的不同的物理特性一般具有不同的氧化特性、扩散特性、粘附特性等等。
第二，这些晶粒具有所谓的晶界，也即在埃至纳米范围中的无原子范围，它们将晶粒彼此分离，在其中原子具有比在晶粒体积中高的扩散性。
第三，待键合的表面在最罕见情况下无氧化产品。
多晶表面在具有氧化产品和非零的表面粗糙度的最坏情况下存在的事实使得不能实现直接焊接。在接触时，表面不是整面地平放、而是在界面中形成细孔。不将这种“微观孔”与上面描述的空穴混淆，这些空穴对于扩散具有基本意义，而“微观孔”在界面中防止原子“向其他侧”的跳跃。
总而言之可以说，按照本发明两个表面的修改这样进行，使得在尽可能低的温度情况下必须尽可能简单地进行原子交错的扩散。
扩散例如可以被促进，其方式是，将待连接的金属表面设计为使得提供近表面层或理想情况下从表面开始、伸到该材料中确定的深度“d”（层厚）的层，该层具有在待连接的表面之间引起扩散、尤其是主要是置换扩散的构造。接着，现在描述方法，所述方法能够实现产生该近表面的层。尤其是可以被证实是有益的是，提供近表面的层，该层较少稠密地被封装。由此认为，空穴浓度是相应地高的。现在，这些晶格缺陷具有优点，即在热处理时发生构造的再组织，这最后导致较稠密的封装（和晶格缺陷的排除）。当现在进行该温度步骤，同时两个金属接触面紧密接触时，所述金属接触面可以塑性变形并且由此也封闭在界面中的空洞，由此能够实现更好的接触，并且有利于在这两个表面之间的扩散键合的形成。现在存在一系列用于处理表面的变型方案，借助其可以产生这些层：
晶格缺陷的后来产生：
在这些方法中，借助由现有技术已知的方法来制造金属接触面。对此常见的方法步骤是所谓的“晶种层（SeedLayer）”的沉积，该晶种层用于实现金属（例如铜）的电化学沉积。该金属化结构在此借助光刻、和所谓的电镀掩模（PlatingMaske）的定义（在接触区域和非金属的、围绕接触区域的相邻区域中）获得所需的结构化。在金属的该电化学沉积之后，所述金属大多借助化学机械抛光（CMP）来抛光，以便保证平坦的表面和非常小的表面粗糙度（<2nm,理想地<1nm，更优选地<0.5nm均方根[rms]，借助2x2μmAFM扫描来测量）。这些方法在工业中是充分地已知的。根据键合界面的构型，围绕金属焊盘的非金属区域可以由二氧化硅或者由有机绝缘体材料或其它合适材料制成。在此，在金属区域和围绕区域之间的形貌或者可以被选择为使得不仅金属区域而且非金属区域同时接触，使得因此不存在形貌，或者代替地，非金属区域相对于金属区域轻微地往后移（例如大约100A优选1000A或2000A），使得仅仅金属区域相互接触。
代替金属的电化学沉积，也可以考虑其它方法如溅射等等。
由以很大程度上与传统的扩散键合方法相应的表面质量制造的金属接触面出发，经历这些现在合适的方法来后来装入晶格缺陷。
在该实施方式中，这些晶格缺陷通过注入气体离子来产生。优选地，对此选择具有足够质量的离子，以便在构造中通过相应的金属原子或金属分子的“位错（Dislocation）”产生晶格缺陷。对此特别合适的是考虑与金属不发生反应的气体，尤其是惰性气体例如氩。但是对于确定的应用情况也可以考虑氮气或其它具有足够质量的气体。这里，决定性的问题是，气体离子质量与金属原子质量相比的比例。该注入过程原则上可以在每个设备中实现，其允许用气体离子轰击金属表面。但是，这优选地用基于等离子体的系统引起。在该类别中优选的是所谓的电感耦合等离子体系统（ICP）或者所谓的电容耦合等离子体系统（CCP）。在两个系统并且尤其是在ICP系统情况下，决定性的是，正确地选择针对离子的加速能量，以便实现近表面金属层的所希望的特性。在ICP系统情况下，可以借助可变的场强调整该加速能量。在CCP系统情况下可以借助一系列变型来优化该加速能量。对此，按照本发明可以在晶片容纳物上设置自偏置电压，并且优选也有针对性地调整它，以便影响离子的加速能量。但是更理想的是，使用所谓的双频等离子体（“dualfrequencyplasma”）设置。由此能够实现，以两个频率之一控制等离子体密度和温度，而可以以第二个频率（在晶片容纳物上所施加的频率）影响加速能量。如果在晶片处施加的频率被选择地比较低（与工业上常见的具有13.56Mhz运行频率的等离子体系统相比），则该设置更理想地起作用。该频率优选小于1Mhz，以<500kHz的频率实现更好的结果，以<200kHz的频率实现最佳的结果，并且以<50kHz的频率实现最好的结果。
在优选的实施方式中，借助尤其是附加的直流电压引起在界限层（鞘（Sheath））中较强的电场，由此离子被更强地加速到衬底表面上。
当所选择的用于产生等离子体的气体不仅由用于产生晶格缺陷的离子组成、而且包含附加的有益地影响该过程的分量时，实现特别好的结果。这里特别合适的例如是氢的混合，因为氢还原性地作用，并且这样防止金属表面的氧化，或者甚至可以去除已经存在的氧化层。尤其是被注入到金属表面中的氢离子可以具有持久的防氧化作用，其在少数直多个分钟上持续（例如至少1分钟、3分钟或5到10分钟）。由此，提供足够的时间窗口，以便例如能够将晶片相互定向，并且接着能够将这些晶片引入键合室用于键合。在此，为了实现理想前提，可以并行地进行用不同离子的注入，其方式是，如上所描述地使用相应选择的气体混合物，或者也通过在使用不同过程气体的情况下执行相继的注入步骤而顺序地进行。这可以或者发生在相同的过程室或者发生在不同的过程室中。
接着所述晶格缺陷的产生，如迄今常见的那样，进行面的接触和键合。有利地，仅仅可以匹配过程参数。尤其是，现在可以在明显减少的过程温度情况下进行键合。这里，已经在<300℃的温度时实现出色的结果。在优化的近表面层情况下，温度能够减少到<260℃，理想地到<230℃，在许多情况下<200℃，并且在个别情况下也到<180或<160℃。代替地，也可以这样选择过程窗口，使得可以在稍微较高的过程温度情况下减少过程时间。
产生具有缺陷的近表面层：
在相应地选择金属沉积过程情况下可以产生具有较低的质量的金属层。大多数情况下，这是不希望的，因为这些层的导电性仅仅是有限的。这应归因于金属构造的次优构成。这种效应根据本发明被利用。在此，首先以工业中常见的方法制造金属面。这里，参考上述的实施。构建于这些层上地，现在施加极其薄的金属层，该金属层是质量较低的。典型地，该层的具有<3nm,更好地具有<2nm，但是还更理想地具有<1nm或者<0.5nm的厚度被选择。该层可以或者被施加到两个接触面上或者也可代替地仅仅施加到面之一上。于是在此，厚度相应地被优化。接着，如迄今常见的那样使接触面接触并且加热。在此，现在剔除晶格缺陷，并且在接触面处在两个表面之间形成扩散键合。具有较低值质量的金属层在此有利于形成该扩散键合。该（多个）层的制造可以通过在这种沉积过程处的已知过程参数来控制。在此影响层质量的参数在工业中是已知的并且在专业有关文献中是清楚的。多数情况下在此涉及沉积温度、在沉积系统的过程室中的环境压力以及气体的选择和存在于沉积系统的沉积室中的环境条件。适于此的方法例如是溅射过程，该溅射过程在通常被看作次优的过程条件（例如太低的过程温度）下被执行。
代替地，该层也可以借助电镀来制造。在此可以设想，首先平面地制造表面（如上所描述的），并且接着借助电镀制造薄层（层厚参见上面）。基于电镀过程的优化选择（化学成分、电流值、温度等等），可以由此产生具有所希望的特性的层。
针对球形或等效形状的空穴，在本发明意义上的晶格缺陷具有理想情况下具有一个或多个原子大小的大小，尤其是<10nm,优选<5nm，更优选<3nm，更优选<1nm，更优选<0.5nm。
施加金属的纳米颗粒：
已经由科学文献已知，具有<100nm、理想地<70nm、更好地<50至30nm并且优选地<20或<10nm的大小的金属颗粒（例如金，但是还有铜）具有如下特性：即在热处理时在温度低于根据颗粒大小的熔点、但是也远低于该熔点的情况下连接成均质的、连续的金属构造。这种特性现在可以被使用于键合过程，其方式是，将这种颗粒以薄层的形式施加到一个或两个金属接触面上。接触面接着处于接触，并且经历热处理。在该热处理期间，这些纳米颗粒能够实现相互键合和与金属接触面的键合并且作为最后结果实现两个金属接触面相互的完全键合。这通过以下方式可以实现，即纳米颗粒本身是非常有活性的，并且具有理想地与尤其是由相同的金属制成的金属表面连接的特性。在使用小的颗粒情况下，该连接已经可以在<250℃、理想地<200℃、更优选地<150℃并且在以非常小的颗粒的情况下甚至<120℃的温度下进行。
表面粗糙度的优化：
扩散键合的类似加速和尤其是在温度强烈减少情况下的键合也是在表面粗糙度方面相应地优化表面的另外的可能性。基本原理在于，表面波动性和微粗糙度的平面化。均方根（RMS）粗糙度应当处于纳米范围中。调整的粗糙度必须是均质的。这意味着，借助原子力显微镜（AFM）测量的平均波长以及山-谷轮廓的平均幅度在整个表面处必须是相同的。对于表面在接触时能够如此彼此搭接，使得一个表面的山填充另一表面的谷并且反之亦然，这是必要的前提。基于这些最佳的接触，强烈地有利于扩散键合的形成并且已经在较低的温度时也能够实现。
为此所需的表面粗糙度可以通过有针对性地选择的CMP过程来实现。一方面，CMP过程能够实现产生非常平坦的表面，而借助合适地选择粘合液（Slurries）也可以影响表面粗糙度。所希望的表面性质的产生在此可以或者在单个CMP步骤中进行，或者在两个相继的步骤中进行。在该情况下，第一步骤用于，保证表面的平面性，而第二步骤用于制造所希望的局部的表面粗糙度。可选地，也可以借助特定的蚀刻步骤来产生表面粗糙度。此外可以设想，所要求的粗糙度借助在电镀和CMP之间的相互作用或作为有针对性地执行的电镀步骤的结果来产生。在此，可以设想，首先平面地制造表面，接着借助电镀来制造薄层（层厚参见具有缺陷的近表面层的产生变型）。基于电镀过程（化学成分、电流值、温度等等）的优化选择由此可以产生具有所希望的特性的层。
表面粗糙度（针对2x2μm面用AFM测量）应当<20nm、尤其是<10nm、优选<5nm、更优选<3nm、更优选<1nm，更优选<0.5nm。
为了能够实现特别优化的过程结果，也可以将上述的变型相互任意地组合。尤其是作为用于避免氧化的措施的氢注入与所描述的其它方法的相互作用可以提供特别优化的结果。
这里又一次提到，该方法也可以被用于所谓的“混合键合界面（HybridBondInterfaces）”。该混合界面由被非金属区域围绕的金属接触面的合适的组合组成。非金属区域在此被设计为使得在单个键合步骤中不仅能够制造金属接触、而且能够制造在非金属区域之间的接触。
这里，可以特别有利的是，这样设计等离子体注入步骤，使得不仅在低温情况下可以产生金属连接，而且可以在与金属区域邻接的非金属区域之间产生连接。这些非金属区域在此可以由二氧化硅组成，其同样可以借助等离子体处理这样被修改，使得键合可以在非常低的温度下进行。
本发明尤其是在于用于在第一衬底的第一金属表面和第二衬底的第二金属表面之间制造永久的导电连接的过程流，具有如下方法步骤，尤其是方法流程：
－这样处理第一和第二金属表面，使得在连接金属表面时、尤其是在处理之后的几分钟的时间段中可以制造至少主要由于在两个金属表面的尤其是同类的、优选相同的金属离子和/或金属原子之间的置换扩散产生的永久的导电连接，
－定向和连接第一和第二金属表面，其中在处理、定向和连接期间不超过最大300℃、尤其最大260℃、优选230℃、更优选200℃、特别优选最大180℃、理想地最大160℃的过程温度。

Claims (2)

1.用于在第一衬底的第一金属表面和第二衬底的第二金属表面之间制造永久的导电连接的方法，具有如下方法步骤：
－定向和键合第一和第二金属表面，其中在两个金属表面紧密接触期间进行温度步骤，使得在第一和第二金属表面之间的空洞通过塑性变形被封闭。
2.根据上述权利要求之一所述的方法，其中，在处理第一和第二金属表面期间，附加地进行氢的注入。
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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2372755B1 (de) * 2010-03-31 2013-03-20 EV Group E. Thallner GmbH Verfahren zum permanenten Verbinden zweier Metalloberflächen
SG186759A1 (en) * 2012-01-23 2013-02-28 Ev Group E Thallner Gmbh Method and device for permanent bonding of wafers, as well as cutting tool
SG11201600043RA (en) 2013-07-05 2016-02-26 Ev Group E Thallner Gmbh Method for bonding of contact surfaces
EP3057123B1 (en) 2013-10-07 2021-12-08 Furukawa Electric Co., Ltd. Joining structure comprising layers with different average crystal grain sizes for a semiconductor chip
DE102014106231A1 (de) * 2014-05-05 2015-11-05 Ev Group E. Thallner Gmbh Verfahren und Vorrichtung zum permanenten Bonden
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
CN108369893B (zh) 2015-11-24 2022-07-19 住友电气工业株式会社 碳化硅单晶衬底、碳化硅外延衬底及制造碳化硅半导体器件的方法
TWI822659B (zh) 2016-10-27 2023-11-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
CN106876607B (zh) 2017-03-21 2019-07-26 京东方科技集团股份有限公司 一种薄膜封装结构、薄膜封装方法及显示装置
CN109545766B (zh) * 2018-11-14 2020-08-21 长江存储科技有限责任公司 三维存储器及其制造方法
CN110773859A (zh) * 2019-11-04 2020-02-11 深圳市汇城精密科技有限公司 金属材料焊接方法
US11495557B2 (en) 2020-03-20 2022-11-08 Advanced Semiconductor Engineering, Inc. Semiconductor device and method of manufacturing the same
CN114080146B (zh) * 2021-11-02 2023-12-05 中国电子科技集团公司第三十八研究所 一种低温无压的传感器金属外壳密封方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004025196A (ja) * 2002-06-21 2004-01-29 Okutekku:Kk 固体接合方法
US20040235266A1 (en) * 2003-05-19 2004-11-25 Ziptronix, Inc. Method of room temperature covalent bonding
US20050048758A1 (en) * 2002-02-28 2005-03-03 Khalil Hosseini Diffusion solder position, and process for producing it
CN101295753A (zh) * 2007-04-24 2008-10-29 中国科学院上海微系统与信息技术研究所 用于III-V族化合物器件的低温Au-In-Au键合方法
US20090134501A1 (en) * 2007-11-26 2009-05-28 Infineon Technologies Ag Device and method including a soldering process
JP2009177078A (ja) * 2008-01-28 2009-08-06 Olympus Corp 実装構造

Family Cites Families (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4452389A (en) 1982-04-05 1984-06-05 The Bendix Corporation Method for welding with the help of ion implantation
US4706870A (en) 1984-12-18 1987-11-17 Motorola Inc. Controlled chemical reduction of surface film
US4774196A (en) * 1987-08-25 1988-09-27 Siliconix Incorporated Method of bonding semiconductor wafers
US4849247A (en) * 1987-12-14 1989-07-18 Sundstrand Corporation Enhanced adhesion of substrate materials using ion-beam implantation
US5611140A (en) * 1989-12-18 1997-03-18 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
JPH04111982A (ja) 1990-08-29 1992-04-13 Ishikawajima Harima Heavy Ind Co Ltd 拡散接合方法
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
US5503704A (en) * 1993-01-06 1996-04-02 The Regents Of The University Of California Nitrogen based low temperature direct bonding
JPH07506773A (ja) * 1993-01-19 1995-07-27 ヒューズ・エアクラフト・カンパニー 中間温度拡散接合
GB2300375B (en) * 1994-08-01 1998-02-25 Nippon Denso Co Bonding method for electric element
JP3215008B2 (ja) 1995-04-21 2001-10-02 株式会社日立製作所 電子回路の製造方法
JP3368140B2 (ja) * 1996-03-22 2003-01-20 太陽誘電株式会社 電子部品の実装方法及びその構造
US6326241B1 (en) * 1997-12-29 2001-12-04 Visteon Global Technologies, Inc. Solderless flip-chip assembly and method and material for same
US6108210A (en) * 1998-04-24 2000-08-22 Amerasia International Technology, Inc. Flip chip devices with flexible conductive adhesive
DE19929278A1 (de) * 1998-06-26 2000-02-17 Nissin Electric Co Ltd Verfahren zum Implantieren negativer Wasserstoffionen und Implantierungseinrichtung
US6342442B1 (en) * 1998-11-20 2002-01-29 Agere Systems Guardian Corp. Kinetically controlled solder bonding
KR100316029B1 (ko) 1998-12-30 2002-01-12 박종섭 반도체 소자의 제조방법
US6555414B1 (en) * 2000-02-09 2003-04-29 Interuniversitair Microelektronica Centrum, Vzw Flip-chip assembly of semiconductor devices using adhesives
JP2001274368A (ja) * 2000-03-27 2001-10-05 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法およびこの方法で製造された貼り合わせウエーハ
US6563133B1 (en) * 2000-08-09 2003-05-13 Ziptronix, Inc. Method of epitaxial-like wafer bonding at low temperature and bonded structure
FR2817395B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
JP4656275B2 (ja) * 2001-01-15 2011-03-23 日本電気株式会社 半導体装置の製造方法
JP2002222832A (ja) 2001-01-29 2002-08-09 Nec Corp 半導体装置及び半導体素子の実装方法
US6537846B2 (en) * 2001-03-30 2003-03-25 Hewlett-Packard Development Company, L.P. Substrate bonding using a selenidation reaction
US6887769B2 (en) * 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6727587B2 (en) * 2002-04-30 2004-04-27 Infineon Technologies Ag Connection device and method for producing the same
US6979630B2 (en) * 2002-08-08 2005-12-27 Isonics Corporation Method and apparatus for transferring a thin layer of semiconductor material
EP1578559B1 (en) 2002-09-18 2009-03-18 Ebara Corporation Bonding method
FR2845523B1 (fr) * 2002-10-07 2005-10-28 Procede pour realiser un substrat par transfert d'une plaquette donneuse comportant des especes etrangeres, et plaquette donneuse associee
US6962835B2 (en) * 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
US6821878B2 (en) * 2003-02-27 2004-11-23 Freescale Semiconductor, Inc. Area-array device assembly with pre-applied underfill layers on printed wiring board
TW584934B (en) * 2003-03-05 2004-04-21 Au Optronics Corp Method of forming a contact and structure thereof
JP4283567B2 (ja) * 2003-03-07 2009-06-24 株式会社オクテック 金属薄膜の接合方法
US20050003652A1 (en) 2003-07-02 2005-01-06 Shriram Ramanathan Method and apparatus for low temperature copper to copper bonding
US7420083B2 (en) 2003-09-25 2008-09-02 Wyeth Substituted aryloximes
CN100564726C (zh) * 2003-10-01 2009-12-02 邱则有 一种模壳构件
GB0329460D0 (en) 2003-12-19 2004-01-28 Oxford Instr Plasma Technology Apparatus and method for plasma processing
JP3790995B2 (ja) 2004-01-22 2006-06-28 有限会社ボンドテック 接合方法及びこの方法により作成されるデバイス並びに接合装置
WO2005104192A2 (en) * 2004-04-21 2005-11-03 California Institute Of Technology A METHOD FOR THE FABRICATION OF GaAs/Si AND RELATED WAFER BONDED VIRTUAL SUBSTRATES
US7442992B2 (en) * 2004-05-19 2008-10-28 Sumco Corporation Bonded SOI substrate, and method for manufacturing the same
US7750487B2 (en) * 2004-08-11 2010-07-06 Intel Corporation Metal-metal bonding of compliant interconnect
US20060270192A1 (en) * 2005-05-24 2006-11-30 International Business Machines Corporation Semiconductor substrate and device with deuterated buried layer
EP1732116B1 (en) * 2005-06-08 2017-02-01 Imec Methods for bonding and micro-electronic devices produced according to such methods
DE602005015103D1 (de) * 2005-07-28 2009-08-06 Infineon Technologies Ag Verbindungsstruktur zur Befestigung eines Halbleiterchips auf einem Metallsubstrat, Halbleiterchip und elektronisches Bauelement mit der Verbindungsstruktur, und Verfahren zur Herstellung der Verbindungsstruktur
JP4728755B2 (ja) 2005-09-22 2011-07-20 ハリマ化成株式会社 導電性接合の形成方法
JP2007090394A (ja) * 2005-09-29 2007-04-12 Tokyo Institute Of Technology 金属の接合方法
DE102005052563B4 (de) * 2005-11-02 2016-01-14 Infineon Technologies Ag Halbleiterchip, Halbleiterbauteil und Verfahren zu deren Herstellung
JP2007149723A (ja) * 2005-11-24 2007-06-14 Sumco Corp 貼り合わせウェーハの製造方法
DE102005058654B4 (de) * 2005-12-07 2015-06-11 Infineon Technologies Ag Verfahren zum flächigen Fügen von Komponenten von Halbleiterbauelementen
EP1798764A1 (en) * 2005-12-14 2007-06-20 STMicroelectronics S.r.l. Process for manufacturing wafers usable in the semiconductor industry
US20070148917A1 (en) * 2005-12-22 2007-06-28 Sumco Corporation Process for Regeneration of a Layer Transferred Wafer and Regenerated Layer Transferred Wafer
JP2007184408A (ja) 2006-01-06 2007-07-19 Nec Corp 電極接合方法
DE102006017115B4 (de) * 2006-04-10 2008-08-28 Infineon Technologies Ag Halbleiterbauteil mit einem Kunststoffgehäuse und Verfahren zu seiner Herstellung
JP5028845B2 (ja) * 2006-04-14 2012-09-19 株式会社Ｓｕｍｃｏ 貼り合わせウェーハ及びその製造方法
US8013342B2 (en) * 2007-11-14 2011-09-06 International Business Machines Corporation Double-sided integrated circuit chips
US7385283B2 (en) * 2006-06-27 2008-06-10 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuit and method of making the same
US7750488B2 (en) * 2006-07-10 2010-07-06 Tezzaron Semiconductor, Inc. Method for bonding wafers to produce stacked integrated circuits
TWI302372B (en) * 2006-08-30 2008-10-21 Polytronics Technology Corp Heat dissipation substrate for electronic device
JP2008066500A (ja) * 2006-09-07 2008-03-21 Sumco Corp 貼り合わせウェーハおよびその製造方法
US7811900B2 (en) 2006-09-08 2010-10-12 Silicon Genesis Corporation Method and structure for fabricating solar cells using a thick layer transfer process
JP2008066603A (ja) * 2006-09-08 2008-03-21 Toshiba Corp 半導体記憶装置及びその製造方法
US8241995B2 (en) * 2006-09-18 2012-08-14 International Business Machines Corporation Bonding of substrates including metal-dielectric patterns with metal raised above dielectric
JP2008294098A (ja) * 2007-05-23 2008-12-04 Nikon Corp 表面清浄活性化装置および電極接合装置
US20090278233A1 (en) * 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
JP4992604B2 (ja) 2007-08-15 2012-08-08 株式会社ニコン 接合装置、接合方法
DE102007043360A1 (de) * 2007-09-12 2009-03-19 Forschungszentrum Karlsruhe Gmbh Elektronisches Bauelement, Verfahren zu seiner Herstellung und seine Verwendung
US7888782B2 (en) * 2007-10-26 2011-02-15 Infineon Technologies Ag Apparatus and method configured to lower thermal stresses
EP2067532A1 (en) * 2007-12-04 2009-06-10 Sony Corporation A method of producing a nanoparticle film on a substrate
EP2067525A1 (en) * 2007-12-04 2009-06-10 Sony Corporation A method of preparing a nanoparticle film having metal ions incorporated
KR100855404B1 (ko) * 2007-12-21 2008-08-29 주식회사 동부하이텍 이미지센서 및 그 제조방법
JP2008098683A (ja) * 2008-01-10 2008-04-24 Ebara Corp 電極配設基体の電極接合方法
JP4471002B2 (ja) 2008-01-23 2010-06-02 セイコーエプソン株式会社 接合体の形成方法
US7872357B2 (en) * 2008-03-05 2011-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Protection for bonding pads and methods of formation
JP2009260818A (ja) 2008-04-18 2009-11-05 Nec Corp サーバ装置とコンテンツ配信方法とプログラム
US8304324B2 (en) * 2008-05-16 2012-11-06 Corporation For National Research Initiatives Low-temperature wafer bonding of semiconductors to metals
KR101458213B1 (ko) * 2008-07-09 2014-11-04 삼성전자주식회사 나노구조 박막 및 나노 구조 박막의 표면특성 제어방법
JP5401661B2 (ja) * 2008-08-22 2014-01-29 株式会社ムサシノエンジニアリング 原子拡散接合方法及び前記方法により接合された構造体
WO2010031845A1 (en) * 2008-09-18 2010-03-25 Imec Methods and systems for material bonding
US8159060B2 (en) * 2009-10-29 2012-04-17 International Business Machines Corporation Hybrid bonding interface for 3-dimensional chip integration
US8748288B2 (en) 2010-02-05 2014-06-10 International Business Machines Corporation Bonded structure with enhanced adhesion strength
EP2372755B1 (de) * 2010-03-31 2013-03-20 EV Group E. Thallner GmbH Verfahren zum permanenten Verbinden zweier Metalloberflächen
US9048283B2 (en) * 2012-06-05 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding systems and methods for semiconductor wafers
US8916448B2 (en) * 2013-01-09 2014-12-23 International Business Machines Corporation Metal to metal bonding for stacked (3D) integrated circuits
US9953941B2 (en) * 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
CN109285825B (zh) * 2017-07-21 2021-02-05 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050048758A1 (en) * 2002-02-28 2005-03-03 Khalil Hosseini Diffusion solder position, and process for producing it
JP2004025196A (ja) * 2002-06-21 2004-01-29 Okutekku:Kk 固体接合方法
US20040235266A1 (en) * 2003-05-19 2004-11-25 Ziptronix, Inc. Method of room temperature covalent bonding
CN101295753A (zh) * 2007-04-24 2008-10-29 中国科学院上海微系统与信息技术研究所 用于III-V族化合物器件的低温Au-In-Au键合方法
US20090134501A1 (en) * 2007-11-26 2009-05-28 Infineon Technologies Ag Device and method including a soldering process
JP2009177078A (ja) * 2008-01-28 2009-08-06 Olympus Corp 実装構造

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