TWI587417B - 使兩種金屬表面持久性連接之方法 - Google Patents

使兩種金屬表面持久性連接之方法 Download PDF

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TWI587417B
TWI587417B TW104144076A TW104144076A TWI587417B TW I587417 B TWI587417 B TW I587417B TW 104144076 A TW104144076 A TW 104144076A TW 104144076 A TW104144076 A TW 104144076A TW I587417 B TWI587417 B TW I587417B
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metal
substrate
diffusion
creating
metal surface
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TW104144076A
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TW201612999A (en
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馬克斯 威普林格
維爾 達戈
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Ｅｖ集團Ｅ塔那有限公司
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Description

使兩種金屬表面持久性連接之方法
本發明係關於一種如請求項1之在兩種金屬表面之間產生持久性連接之方法。
在半導體工業中，在兩種金屬表面之間產生持久性導電金屬連接係日益重要。主要對於所謂之「3D積體裝置或IC(3D IC)」領域中之新穎類型封裝技術而言，兩個功能性平面之間的金屬鍵合連接起決定性作用。在此情況下，第一主動或被動電路係於兩塊獨立的基板上製造，且該兩塊基板係於鍵合步驟中彼此持久性連接，並建立電接觸。此連接步驟可藉由連接兩個晶圓(晶圓對晶圓-W2W)、藉由連接一或多個晶片與晶圓(晶片對晶圓-C2W)、或藉由連接一或多個晶片與晶片(晶片對晶片-C2C)之方法實現。在此等連接方法中，兩個連接表面之間的直接連接受到高度關注，其中兩個表面在很大程度上係由相同材料(金屬)組成。此處，以在此連接平面中大部分情況下無需其他材料之方法特別佳。在此連接中，銅(Cu)或鋁(Al)或金(Au)通常係用於金屬化。然而，應明瞭，本發明基本上亦以與其他金屬之相互作用操作，且金屬選擇主要係基於晶片結構及預處理步驟之要求。因此，不同的金屬亦被視為本發明所主張。此外，該方法亦可用於所謂之「雜化鍵合界面」。該等雜化界面係由經非金屬區域包圍之金屬接觸 表面之適宜組合所組成。在此情況下，該等非金屬區域係以使得於個別連接步驟中，可同時形成金屬接觸及該等非金屬區域間之接觸之方式經組態。此時，不含外源材料(尤其係外源金屬)之此等連接係藉由所謂之擴散鍵合法產生。此處，將該等接觸表面定向成彼此相對，且使其接觸。該等接觸表面係藉由適宜方法(例如，「化學機械拋光」，或簡稱「CMP」)，以使其非常平整且具有細微的表面粗糙度之方式進行預處理。隨後，以適宜的裝置(例如，晶圓鍵合器)將該等接觸表面壓縮在一起，且同時加熱至可自由選擇之製程溫度。此處，如果此操作係於優化氣氛中，例如，在真空(例如，<1mbar，較佳係<1至3mbar)或還原氣氛中，尤其係具有高氫氣(H2)含量(>1%，較佳係>3%，甚至更佳係>5%，且理想係>9%)之氣氛中進行，則亦可顯示有利。在此等製程條件下，現在於兩個金屬表面之間產生所謂之擴散鍵合。此處，在低共熔金屬組合物之情況下，金屬原子或分子在兩個表面之間來回擴散，且由此在該等表面之間建立持久性金屬導電且機械上極安定之連接。在此情況下，該連接經常具有不可能產生原始接觸表面之金屬結構缺陷之品質。相反地，該連接係顯示為均質金屬結構，其現在優於原始接觸表面。如今極大地限制此技術之使用之一因素係在大多數情況下溫度相對較高，其係產生該連接及尤其係實現可能的擴散所必需。在諸多情況下，該溫度係高於300℃，在諸多情況下高於350℃，通常係380至400℃，且在特定情況下，甚至高達450℃或500℃，此高於該等組件之可耐受溫度(通常係<260℃，在諸多情況能下<230℃，對於特定組件而言<200℃，且在特定情況下<180℃或甚至<150℃)，且因此阻止或限制此方法之使用。本發明現在解決此問題，因為其使一種大幅降低所需製程溫度之方法成為可能。
現該等金屬連接在下文中將被稱為「可靠鍵合連接」。在此情況下，鍵合連接通常係意指在由金屬A所組成之兩個金屬接觸表面之間 產生連接，而無需使用持久安裝於該連接中之外源金屬，尤其係具有不同元素組成之外源金屬B。
如上已述，目前存在之方法係受到可進行擴散過程之所需製程溫度限制。原則上，可斷言擴散過程係取決於多種因素之作用。然而，其使得該製程在較低溫度下進行得更慢。然而，實際上，由於此將限制該等製程之經濟效率，或將使極冗長(>1h)之製程變得不經濟，此點係問題。因此，擴散鍵合製程不應用於相同接觸表面之間。或者，在此情況下，使用焊料接點或最廣泛變化表現之低共熔連接及所謂金屬間化合物連接應用。此處可引述以鉛/錫焊料、銅-銀-錫焊料、銦基焊料或其他金-錫或金-矽或鋁-鎵、及銅-錫(金屬間化合物Cu3Sn)為主之焊料接點。此等方法之缺點在於：製造邏輯及技術之問題。在諸多情況下，此等鍵合連接將於僅建立某些金屬化(例如，Cu)並使其符合要求之製造領域中產生。在此情況下，除此金屬化以外，建立另一金屬化之基礎結構並使其符合要求將需要極高的額外費用。從技術方面而言，低共熔連接之長期安定性被視為係關鍵。缺少此安定性，某些連接係極脆弱，且可導致機械疲勞現象。此外，對於某些金屬化而言，觀測到有關混合比之極窄容限以確保低共熔連接之所需特性(例如，熔化溫度、機械特性及電性質)。此外，與低共熔連接相關之擴散效應可造成問題。因此，例如，如果錫自兩個銅接觸表面間之一界面擴散至整個銅觸點中且到達銅觸點與下層之間的下層障壁層，則其將係嚴重問題。由於改變的金屬組成，故此將導致此界面處中之銅機械分層，且因此造成組件之機械缺陷，此僅在數年後實地發生。此等係可以此僅具微結構之形式發生之效應，因為本文中使用該等效應僅可在其中發揮作用之極薄層。
因此，本發明之目標係指示一種可在金屬鍵合連接中實現降低 製程溫度及/或減少製程時間之方法。
利用請求項1之特徵實現此目標。
本發明之其他優點係示於子請求項中。此外，由至少兩種在實施方式、申請專利範圍及/或圖表中所示之特徵所組成之所有組合係在本發明之範圍內。在數值之所示範圍內，亦揭示位於上述範圍內之數值作為界限值且可主張任何組合。
本發明現提供可大幅降低可靠鍵合連接之鍵合溫度之方法及製程，且由此可使無需外源金屬之連接用於寬廣的應用領域中。本發明之另一用途亦係加快該製程，其可在理想的選定製程參數之情況下實現，且其提高該製程之經濟效率。
擴散大體上可分為替位及間隙擴散。
在替位擴散中，個別原子之擴散跳躍係沿著網格中之各點發生，在各點上可定位其他原子。因此，若需要，該擴散跳躍實際上可在某原子可跳躍但不可定位其他原子之位置處發生(存在例外：直接原子交換機制，其經科學論述但尚未經檢驗；如果其存在，其較之其他原子交換機制極少發生，因此可將其忽略)。無原子定位之位置係稱為空隙。該空隙作為將本發明之其他描述之基礎重要態樣。
在間隙擴散中，較小的原子在結晶之晶格孔內擴散。由於本專利案中，吾人主要處理同原子擴撒，所以不進一步考慮間隙擴散。
在Si結晶網格之晶格孔中擴散之氫可係間隙擴散之一實例。相比於Si，氫係「較小」，因此其在晶格孔中具有空間。
根據本發明，僅替位擴散適用於相同金屬種類之同原子擴散之情況。
此外，表面、晶界及體積擴散可係不同。原子在其受到儘可能少的其他原子限制的地方擴散最佳。此狀態主要存在於表面上，藉此亦闡明該表面上原子之高遷移性。甚至於在晶界中，原子一般具有比 在該晶體柵格本身中更多的空間。因此，擴散種類之速度係介於在該等表面擴散速度與體積擴散速度之間。針對晶界擴散之要求當然係存在晶界。
對於此多晶金屬表面而言，隨直接鍵出現以下問題。
首先，多晶材料係由數種相對於待鍵合之表面經不同定向之晶粒組成。此導致該表面由不同的晶體表面組成。該等個別晶粒表面之不同物理性質一般具有不同的氧化、擴散、及黏附特性等等。
其次，該等晶粒具有所謂之晶界，即：將晶粒彼此分開之在埃米至奈米範圍之無原子區域，其中原子具有高於在晶粒體積中之擴散性。
第三，待鍵合之表面在極少的情況下係不含氧化產物。
多晶表面在最壞情況下存在氧化產物及非零表面粗糙度之事實使得不可直接焊接。該等表面並非完全平坦地位於觸點上，而是在界面中形成孔隙。此等「微觀孔」不應與上述對於擴散具有基本重要性之空隙混淆，同時界面中之「微觀孔」阻止原子跳躍至「另一側」。
總言之，可根據本發明，以如下方式實施兩個表面之改質：在可能的最低溫度下，必須儘可能簡單地實施原子之彼此擴散。
可藉由(例如)使待連接之金屬表面以如下方式經配置來促進擴散：可獲得接近該表面之層或理想係始自該表面且在材料中達到一定深度「d」(層厚度)之層，且該層具有在待結合之表面之間產生擴散(特定言之主要係替位擴散)之結構。下文中，現描述可產生接近該表面之此層之方法。主要地，獲得接近該表面且填充較不緊密之層可顯示有利。因此，其意味著空隙濃度較高。該等表面缺陷現具有以下優點：在溫度處理中，發生結構重組，其最終導致更緊密之填充(並消除該等表面缺陷)。當此溫度步驟發生時，在兩個金屬接觸表面緊密 接觸時，後者可塑性變形且因此亦封閉該界面中之真空；因此，其使甚至更佳的接觸成為可能並促進該兩個表面之間的擴散鍵合之發展。現提供一系列處理表面之變化項，利用該等變化項可產生此等層：
隨後產生表面缺陷：
在此方法中，利用先前技術已知之方法，製備該等金屬接觸表面。
就此而言，常用方法步驟係所謂之「晶種層」沉積，其係用於使金屬(例如銅)之電化學沉積可進行。在此情況下，金屬化係藉由微影法並界定所謂之鍍層遮罩獲得所需之結構化(在接觸區域及位於接觸區域周圍之非金屬鄰近區域)。在電化學沉積該金屬之後，該後者在大多數情況下係藉由化學機械拋光(CMP)拋光以確保表面平整及極低的表面粗糙度(<2nm，理想地<1nm，甚至更佳<0.5nm均方根[rms]，藉由2×2μm之AFM掃描測得)。該等方法在工業中係熟知。取決於該鍵合界面之組態，位於金屬墊周圍之非金屬區域可由二氧化矽或有機絕緣材料或其他適宜材料組成。在此情況下，在金屬區域及周圍區域之間的形態可以如下方式選擇：金屬區域及非金屬區域同時接觸以使得無形態存在，或者，非金屬區域相較於金屬區域稍微凹陷(例如約100A，較佳1,000A或2,000A)，以使得僅金屬區域彼此接觸。
除金屬之電化學沉積法以外，其他方法(如，濺射或類似者)亦適宜。
自所製得表面品質極大程度上相當於習知擴散鍵合方法之金屬接觸表面開始，使現在適宜之此等方法係併入隨後之表面缺陷。
在一實施例中，藉由植入氣體離子產生此等表面缺陷。就此而言，更佳地，離子係選自具有足夠質量以藉由相應金屬原子或金屬分子之「位錯」以在結構中產生表面缺陷者。就此而言，不與該金屬反 應之氣體，尤其係稀有氣體(如氬氣)被視為尤其適宜。然而，對於某些應用而言，氮氣或其他具有足夠質量之氣體亦適宜。此處，決定性問題係氣體離子質量相對於金屬原子質量之比例。原則上，此植入過程可於任何允許以氣體離子轟擊金屬表面之裝置中實現。然而，據發現，較佳係使用基於電漿之系統進行。在此類別中，以所謂之感應耦合電漿系統(ICP)或所謂之電容耦合電漿系統(CCP)為較佳。在兩種系統且尤其係ICP系統中，重要的是正確選擇離子之加速能以獲得接近表面之金屬層的所需特性。在ICP系統中，可藉由可變場強度設定此加速能。在CCP系統中，可藉由一系列變數優化此加速能。根據本發明，為此目的，可在晶圓接收器上提供一自偏電壓，且較佳地，後者亦可經特定設定以影響離子之加速能。然而，甚至更理想係使用所謂之「雙頻率電漿」裝置。因此，可利用該兩種頻率中之一者控制電漿密度及溫度，同時可利用另一者(施加至晶圓接收器之頻率)影響加速能。當選擇施加至晶圓之頻率較低(相較於工業中常見之操作頻率為13.56MHz之電漿系統)時，甚至更理想地操作該裝置。更佳地，此頻率係低於1MHz；利用<500kHz之頻率獲得更佳結果，利用<200kHz之頻率獲得優化結果，且利用<50kHz之頻率獲得最佳結果。
在一較佳實施例中，利用(特定言之)額外DC電壓在邊界層(護套)中產生較強電場，藉此在基板表面上更強地加速離子。
當用於電漿製備之選定氣體不僅係由用於產生表面缺陷之離子組成，而且亦含有有利地影響該製程之其他部分時，獲得極佳結果。例如，此處由於氫氣具有還原作用且因此避免金屬表面之氧化，或甚至可移除已存在之氧化層，所以添加氫氣尤其適宜。特定言之，植入金屬表面之氫離子可具有持久性避免氧化之作用，其持續幾分鐘至數分鐘(例如，至少1分鐘、3分鐘、或5至10分鐘)。因此，可獲得足夠的時間窗口，以(例如)使晶圓彼此定向且可隨後使後者在鍵合室中鍵 合。在此情況下，不同離子之植入可平行進行，以藉由(如上所述)所使用之對應的選定氣體混合物實現更理想的要求；或藉由使用不同製程氣體進行之連續植入步驟依序進行。此可在相同或不同處理室中進行。
迄今為止，在產生表面缺陷之後，如常進行該等表面之接觸及鍵合。僅可有利地匹配製程參數。特定言之，現可進行製程溫度顯著降低之鍵合。此處，已可在溫度<300℃下獲得極佳的結果。利用接近該表面之優化層，可將溫度降低至<260℃，理想至<230℃，在諸多情況下至<200℃，且在個別情況下甚至降低至<180℃或<160℃。或者，甚至可以在稍高製程溫度下可減少製程時間之方式選擇該製程窗口。
產生接近表面之具有缺陷之層
在對應的金屬沉積方法之選擇中，可產生品質較差之金屬層。在大多數情況下，此係非所需，因為該等層之導電性只會受到限制。此可歸因於金屬結構之次優組態。根據本發明使用此效應。在此情況下，首先利用工業中常用之方法產生金屬表面。此處，可參考以上實施例。建立於該等層之上，現施加品質較差之極薄金屬層。一般而言，選擇該層之厚度<3nm，更佳係<2nm，且然而甚至更理想係<1nm或<0.5nm。可將該層施加至兩個接觸表面或者甚至僅施加至該等表面中之一者。在此情況下，隨後使該厚度相應最優化。隨後，使該等接觸表面接觸並如通常操作般進行加熱。在此情況下，現消除該等表面缺陷，並在該兩個表面之間的接觸表面上產生擴散鍵合。在此情況下，具有較差品質之金屬層促進此擴散鍵合之發展。可藉由該等沉積製程中之已知製程參數控制此(等)層之產生。在此情況下，影響該層品質之參數係工業中已知且可參見相關文獻資料。此處，在大多數情況下，該等參數係沉積溫度、沉積系統之處理室中之周圍壓力、及 沉積系統之沉積室中之氣體與環境條件之選擇。就此而言，適宜的方法可係(例如)濺射法，其係在通常被視為次優之製程條件(例如，過低的製程溫度)下進行。
或者，亦可藉由電鍍法產生該層。在此情況下，首先可形成呈平面形式之表面(如上所述)，且隨後藉由電鍍法產生薄層(層厚度參見上文)。基於電鍍法之最佳選擇(化學組成、電流值、溫度等)，由此可產生具有所需特性之層。
就本發明而言，表面缺陷具有在理想情況下具有一或多個原子之尺寸，特定言之相對於球形或相當形狀中之空隙係<10nm，較佳係<5nm，甚至更佳係<3nm，甚至更佳係<1nm，且甚至更佳係<0.5nm。
施用金屬奈米顆粒
自科學文獻資料中已知，尺寸為<100nm，理想係<70nm，甚至更佳係<50至30nm，且較佳係<20或<10nm之金屬顆粒(例如金及銅)在於低於熔點之溫度(該溫度視該等顆粒之尺寸而定，且遠低於該熔點)下之熱處理中具有連接成均質連續金屬結構之特性。現可藉由以薄層形式施加至一或兩個金屬接觸表面上之此等顆粒，將此特性用於鍵合製程中。隨後，使該等接觸表面接觸，並接受熱處理。於此熱處理期間，該等奈米顆粒可在彼此之下層鍵合且與該等金屬接觸表面鍵合，且最終使兩個金屬接觸表面彼此完全鍵合。此係由於該等奈米顆粒本身極具反應性且具有與尤其係由相同金屬所組成之金屬表面理想連接之特性而可能進行。利用較小顆粒，此連接甚至可在<250℃，理想<200℃，甚至更佳<150℃，及在利用極小顆粒之情況下甚至<250℃之溫度下進行。
表面粗糙度之最優化
擴散鍵合及尤其在大幅降低溫度下之鍵合之類似加速亦係使表 面之表面粗糙度相應最優化之另一可能方法。基本原理在於表面波紋及微粗糙結構之平坦化。均方根(RMS)粗糙度係在奈米範圍內。所設定之粗糙度必須均勻。此意味著利用原子力顯微鏡(AFM)所測得之平均波長、及脊谷分佈之平均振幅在整個表面上必須相同。此係必需要求，以使得該等表面在接觸時可以使一表面之脊填滿另一表面之谷且反之亦然之方式彼此接合。基於此最佳接觸，極大地促進擴散鍵合之發展且使其甚至於較低溫度下亦可進行。
就此而言所需之表面粗糙度可藉由特定選擇之CMP製程實現。在一方面，CMP製程可產生極平整之表面，同時亦可利用適宜選擇之漿液影響表面粗糙度。在此情況下，所需表面組成之產生可於個別CMP步驟中或於彼此銜接之兩個步驟中進行。在此情況下，第一步驟係用於確保該等表面之平坦性，而第二步驟係用於產生所需之局部表面粗糙度。亦可視情況藉由特定的蝕刻步驟產生表面粗糙度。此外，可利用電鍍及CMP之間的相互作用，或特定進行之電鍍步驟產生所需粗糙度。在此情況下，首先可形成呈平面形式之表面且隨後藉由電鍍法產生薄層(層厚度參見變化項「產生接近表面之具有缺陷之層」)。基於電鍍法之最佳選擇(化學組成，電流值、溫度等)，由此可產生具有所需特性之層。
表面粗糙度(利用AFM針對2*2μm表面測得)應<20nm，特定言之<10nm，較佳係<5nm，甚至更佳係<3nm，甚至更佳係<1nm，且甚至更佳係<0.5nm。
為實現特別佳之製程結果，亦可視需要將上述變化項彼此組合。主要地，植入氫氣作為避免在與其他所述方法之相互作用中之氧化的措施可產生特別佳的結果。
本文可再次提及該方法亦可應用於所謂之「雜化鍵合界面」。該等雜化界面係由經非金屬區域包圍之金屬接觸表面之適宜組合所組 成。在此情況下，該等非金屬區域係以使得於個別鍵合步驟中可產生金屬接觸及非金屬區域之間的接觸之方式經組態。
在本文中，以如下方式配置電漿植入步驟可尤其有利：使得可產生低溫下之金屬連接及鄰接該等金屬區域之非金屬區域之間的連接。在此情況下，該等非金屬區域可由二氧化矽組成，其亦可藉由電漿處理以使鍵合可於極低溫度下進行之方式進行改質。
特定言之，本發明係關於一種在第一基板之第一金屬表面與第二基板之第二金屬表面之間產生持久性導電連接之方法流程，其具有以下方法步驟，特定言之係該方法之過程：以如下方式處理該第一及第二金屬表面：使得在該等金屬表面之連接中，尤其係在處理後數分鐘之時間內，可產生持久性導電連接，其至少主要藉由該兩種金屬表面之特定言之類似(較佳係相同)的金屬離子及/或金屬原子之間的替位擴散而產生；使該第一及第二金屬表面定向及連接，進行的方式為：於該處理、定向及連接期間，不超過至多300℃，特定言之至多260℃，較佳230℃，甚至更佳200℃，特別佳至多180℃，且理想至多160℃之製程溫度。

Claims (5)

  1. 一種在第一基板之第一金屬表面與第二基板之第二金屬表面之間產生持久性導電連接之方法，其具有以下方法步驟，以如下藉由產生表面缺陷之方式，處理該第一及第二金屬表面：在連接該等金屬表面時，產生持久性導電鍵合(bond)，其至少主要藉由該等二金屬表面之金屬離子及/或金屬原子之間的替位擴散產生；使該第一及第二金屬表面對準及鍵合(bonding)，進行的方式為，施以溫度處理，使該第一及第二金屬表面之接近表面之層，發生結構重組以消除表面缺陷。
  2. 如請求項1之在第一基板之第一金屬表面與第二基板之第二金屬表面之間產生持久性導電連接之方法，其特徵在於，該溫度處理係在<300℃下進行。
  3. 如請求項1或2之在第一基板之第一金屬表面與第二基板之第二金屬表面之間產生持久性導電連接之方法，其中該第一及第二金屬表面之金屬區域的處理，係藉由氣體離子轟擊(implanting)及/或施用金屬奈米顆粒所產生之接近表面之具有表面缺陷之層所實施。
  4. 如請求項1或2之在第一基板之第一金屬表面與第二基板之第二金屬表面之間產生持久性導電連接之方法，其中在處理該第一及第二金屬表面時，額外地植入氫。
  5. 如請求項1或2之在第一基板之第一金屬表面與第二基板之第二金屬表面之間產生持久性導電連接之方法，其中該處理包括使該等金屬表面之至少一者之表面粗糙度最優化。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG186759A1 (en) * 2012-01-23 2013-02-28 Ev Group E Thallner Gmbh Method and device for permanent bonding of wafers, as well as cutting tool
CN110310896B (zh) 2013-07-05 2023-08-15 Ev 集团 E·索尔纳有限责任公司 用于接合基板的接触表面的方法
EP3057123B1 (en) 2013-10-07 2021-12-08 Furukawa Electric Co., Ltd. Joining structure comprising layers with different average crystal grain sizes for a semiconductor chip
DE102014106231A1 (de) * 2014-05-05 2015-11-05 Ev Group E. Thallner Gmbh Verfahren und Vorrichtung zum permanenten Bonden
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
WO2017090279A1 (ja) 2015-11-24 2017-06-01 住友電気工業株式会社 炭化珪素単結晶基板、炭化珪素エピタキシャル基板および炭化珪素半導体装置の製造方法
CN108470755B (zh) 2017-03-21 2020-07-24 京东方科技集团股份有限公司 一种薄膜封装结构、薄膜封装方法及显示装置
CN109545766B (zh) * 2018-11-14 2020-08-21 长江存储科技有限责任公司 三维存储器及其制造方法
CN110773859A (zh) * 2019-11-04 2020-02-11 深圳市汇城精密科技有限公司 金属材料焊接方法
US11495557B2 (en) 2020-03-20 2022-11-08 Advanced Semiconductor Engineering, Inc. Semiconductor device and method of manufacturing the same
CN114080146B (zh) * 2021-11-02 2023-12-05 中国电子科技集团公司第三十八研究所 一种低温无压的传感器金属外壳密封方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030201532A1 (en) * 2002-04-30 2003-10-30 Edmund Riedl Connection device and method for producing the same
US20090134501A1 (en) * 2007-11-26 2009-05-28 Infineon Technologies Ag Device and method including a soldering process

Family Cites Families (88)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4452389A (en) 1982-04-05 1984-06-05 The Bendix Corporation Method for welding with the help of ion implantation
US4706870A (en) 1984-12-18 1987-11-17 Motorola Inc. Controlled chemical reduction of surface film
US4774196A (en) * 1987-08-25 1988-09-27 Siliconix Incorporated Method of bonding semiconductor wafers
US4849247A (en) * 1987-12-14 1989-07-18 Sundstrand Corporation Enhanced adhesion of substrate materials using ion-beam implantation
US5611140A (en) * 1989-12-18 1997-03-18 Epoxy Technology, Inc. Method of forming electrically conductive polymer interconnects on electrical substrates
JPH04111982A (ja) 1990-08-29 1992-04-13 Ishikawajima Harima Heavy Ind Co Ltd 拡散接合方法
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
US5503704A (en) * 1993-01-06 1996-04-02 The Regents Of The University Of California Nitrogen based low temperature direct bonding
WO1994017551A1 (en) * 1993-01-19 1994-08-04 Hughes Aircraft Company Intermediate-temperature diffusion welding
GB2300375B (en) * 1994-08-01 1998-02-25 Nippon Denso Co Bonding method for electric element
JP3215008B2 (ja) 1995-04-21 2001-10-02 株式会社日立製作所 電子回路の製造方法
JP3368140B2 (ja) * 1996-03-22 2003-01-20 太陽誘電株式会社 電子部品の実装方法及びその構造
US6326241B1 (en) * 1997-12-29 2001-12-04 Visteon Global Technologies, Inc. Solderless flip-chip assembly and method and material for same
US6108210A (en) * 1998-04-24 2000-08-22 Amerasia International Technology, Inc. Flip chip devices with flexible conductive adhesive
US6335535B1 (en) * 1998-06-26 2002-01-01 Nissin Electric Co., Ltd Method for implanting negative hydrogen ion and implanting apparatus
US6342442B1 (en) * 1998-11-20 2002-01-29 Agere Systems Guardian Corp. Kinetically controlled solder bonding
KR100316029B1 (ko) 1998-12-30 2002-01-12 박종섭 반도체 소자의 제조방법
EP1126517B1 (en) * 2000-02-09 2007-01-17 Interuniversitair Micro-Elektronica Centrum Method for flip-chip assembly of semiconductor devices using adhesives
JP2001274368A (ja) * 2000-03-27 2001-10-05 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法およびこの方法で製造された貼り合わせウエーハ
US6563133B1 (en) * 2000-08-09 2003-05-13 Ziptronix, Inc. Method of epitaxial-like wafer bonding at low temperature and bonded structure
FR2817395B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
JP4656275B2 (ja) 2001-01-15 2011-03-23 日本電気株式会社 半導体装置の製造方法
JP2002222832A (ja) 2001-01-29 2002-08-09 Nec Corp 半導体装置及び半導体素子の実装方法
US6537846B2 (en) * 2001-03-30 2003-03-25 Hewlett-Packard Development Company, L.P. Substrate bonding using a selenidation reaction
US6887769B2 (en) * 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
DE10208635B4 (de) * 2002-02-28 2010-09-16 Infineon Technologies Ag Diffusionslotstelle, Verbund aus zwei über eine Diffusionslotstelle verbundenen Teilen und Verfahren zur Herstellung der Diffusionslotstelle
JP4255652B2 (ja) * 2002-06-21 2009-04-15 株式会社オクテック 固体接合方法
US6979630B2 (en) * 2002-08-08 2005-12-27 Isonics Corporation Method and apparatus for transferring a thin layer of semiconductor material
KR20050040812A (ko) 2002-09-18 2005-05-03 가부시키가이샤 에바라 세이사꾸쇼 본딩물질 및 본딩방법
FR2845523B1 (fr) * 2002-10-07 2005-10-28 Procede pour realiser un substrat par transfert d'une plaquette donneuse comportant des especes etrangeres, et plaquette donneuse associee
US6962835B2 (en) 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
US6821878B2 (en) * 2003-02-27 2004-11-23 Freescale Semiconductor, Inc. Area-array device assembly with pre-applied underfill layers on printed wiring board
TW584934B (en) * 2003-03-05 2004-04-21 Au Optronics Corp Method of forming a contact and structure thereof
JP4283567B2 (ja) * 2003-03-07 2009-06-24 株式会社オクテック 金属薄膜の接合方法
US7109092B2 (en) * 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US20050003652A1 (en) 2003-07-02 2005-01-06 Shriram Ramanathan Method and apparatus for low temperature copper to copper bonding
US7420083B2 (en) 2003-09-25 2008-09-02 Wyeth Substituted aryloximes
CN100564726C (zh) * 2003-10-01 2009-12-02 邱则有 一种模壳构件
GB0329460D0 (en) 2003-12-19 2004-01-28 Oxford Instr Plasma Technology Apparatus and method for plasma processing
US7784670B2 (en) 2004-01-22 2010-08-31 Bondtech Inc. Joining method and device produced by this method and joining unit
US20080211061A1 (en) * 2004-04-21 2008-09-04 California Institute Of Technology Method For the Fabrication of GaAs/Si and Related Wafer Bonded Virtual Substrates
US7442992B2 (en) * 2004-05-19 2008-10-28 Sumco Corporation Bonded SOI substrate, and method for manufacturing the same
US7750487B2 (en) * 2004-08-11 2010-07-06 Intel Corporation Metal-metal bonding of compliant interconnect
US20060270192A1 (en) * 2005-05-24 2006-11-30 International Business Machines Corporation Semiconductor substrate and device with deuterated buried layer
EP1732116B1 (en) * 2005-06-08 2017-02-01 Imec Methods for bonding and micro-electronic devices produced according to such methods
DE602005015103D1 (de) * 2005-07-28 2009-08-06 Infineon Technologies Ag Verbindungsstruktur zur Befestigung eines Halbleiterchips auf einem Metallsubstrat, Halbleiterchip und elektronisches Bauelement mit der Verbindungsstruktur, und Verfahren zur Herstellung der Verbindungsstruktur
JP4728755B2 (ja) 2005-09-22 2011-07-20 ハリマ化成株式会社 導電性接合の形成方法
JP2007090394A (ja) * 2005-09-29 2007-04-12 Tokyo Institute Of Technology 金属の接合方法
DE102005052563B4 (de) * 2005-11-02 2016-01-14 Infineon Technologies Ag Halbleiterchip, Halbleiterbauteil und Verfahren zu deren Herstellung
JP2007149723A (ja) * 2005-11-24 2007-06-14 Sumco Corp 貼り合わせウェーハの製造方法
DE102005058654B4 (de) * 2005-12-07 2015-06-11 Infineon Technologies Ag Verfahren zum flächigen Fügen von Komponenten von Halbleiterbauelementen
EP1798764A1 (en) * 2005-12-14 2007-06-20 STMicroelectronics S.r.l. Process for manufacturing wafers usable in the semiconductor industry
US20070148917A1 (en) * 2005-12-22 2007-06-28 Sumco Corporation Process for Regeneration of a Layer Transferred Wafer and Regenerated Layer Transferred Wafer
JP2007184408A (ja) 2006-01-06 2007-07-19 Nec Corp 電極接合方法
DE102006017115B4 (de) * 2006-04-10 2008-08-28 Infineon Technologies Ag Halbleiterbauteil mit einem Kunststoffgehäuse und Verfahren zu seiner Herstellung
JP5028845B2 (ja) * 2006-04-14 2012-09-19 株式会社Ｓｕｍｃｏ 貼り合わせウェーハ及びその製造方法
US8013342B2 (en) * 2007-11-14 2011-09-06 International Business Machines Corporation Double-sided integrated circuit chips
US7385283B2 (en) * 2006-06-27 2008-06-10 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuit and method of making the same
US7750488B2 (en) * 2006-07-10 2010-07-06 Tezzaron Semiconductor, Inc. Method for bonding wafers to produce stacked integrated circuits
TWI302372B (en) * 2006-08-30 2008-10-21 Polytronics Technology Corp Heat dissipation substrate for electronic device
JP2008066500A (ja) * 2006-09-07 2008-03-21 Sumco Corp 貼り合わせウェーハおよびその製造方法
US7811900B2 (en) 2006-09-08 2010-10-12 Silicon Genesis Corporation Method and structure for fabricating solar cells using a thick layer transfer process
JP2008066603A (ja) * 2006-09-08 2008-03-21 Toshiba Corp 半導体記憶装置及びその製造方法
US8241995B2 (en) * 2006-09-18 2012-08-14 International Business Machines Corporation Bonding of substrates including metal-dielectric patterns with metal raised above dielectric
CN101295753B (zh) * 2007-04-24 2011-04-20 中国科学院上海微系统与信息技术研究所 用于Ⅲ-V族化合物器件的低温Au-In-Au键合方法
JP2008294098A (ja) * 2007-05-23 2008-12-04 Nikon Corp 表面清浄活性化装置および電極接合装置
US20090278233A1 (en) * 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
JP4992604B2 (ja) * 2007-08-15 2012-08-08 株式会社ニコン 接合装置、接合方法
DE102007043360A1 (de) * 2007-09-12 2009-03-19 Forschungszentrum Karlsruhe Gmbh Elektronisches Bauelement, Verfahren zu seiner Herstellung und seine Verwendung
US7888782B2 (en) * 2007-10-26 2011-02-15 Infineon Technologies Ag Apparatus and method configured to lower thermal stresses
EP2067525A1 (en) * 2007-12-04 2009-06-10 Sony Corporation A method of preparing a nanoparticle film having metal ions incorporated
EP2067532A1 (en) * 2007-12-04 2009-06-10 Sony Corporation A method of producing a nanoparticle film on a substrate
KR100855404B1 (ko) * 2007-12-21 2008-08-29 주식회사 동부하이텍 이미지센서 및 그 제조방법
JP2008098683A (ja) * 2008-01-10 2008-04-24 Ebara Corp 電極配設基体の電極接合方法
JP4471002B2 (ja) 2008-01-23 2010-06-02 セイコーエプソン株式会社 接合体の形成方法
JP2009177078A (ja) * 2008-01-28 2009-08-06 Olympus Corp 実装構造
US7872357B2 (en) * 2008-03-05 2011-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Protection for bonding pads and methods of formation
JP2009260818A (ja) 2008-04-18 2009-11-05 Nec Corp サーバ装置とコンテンツ配信方法とプログラム
US8304324B2 (en) * 2008-05-16 2012-11-06 Corporation For National Research Initiatives Low-temperature wafer bonding of semiconductors to metals
KR101458213B1 (ko) * 2008-07-09 2014-11-04 삼성전자주식회사 나노구조 박막 및 나노 구조 박막의 표면특성 제어방법
JP5401661B2 (ja) * 2008-08-22 2014-01-29 株式会社ムサシノエンジニアリング 原子拡散接合方法及び前記方法により接合された構造体
WO2010031845A1 (en) * 2008-09-18 2010-03-25 Imec Methods and systems for material bonding
US8159060B2 (en) * 2009-10-29 2012-04-17 International Business Machines Corporation Hybrid bonding interface for 3-dimensional chip integration
US8748288B2 (en) 2010-02-05 2014-06-10 International Business Machines Corporation Bonded structure with enhanced adhesion strength
US9048283B2 (en) * 2012-06-05 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding systems and methods for semiconductor wafers
US8916448B2 (en) * 2013-01-09 2014-12-23 International Business Machines Corporation Metal to metal bonding for stacked (3D) integrated circuits
US9953941B2 (en) * 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
CN112164688B (zh) * 2017-07-21 2023-06-13 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030201532A1 (en) * 2002-04-30 2003-10-30 Edmund Riedl Connection device and method for producing the same
US20090134501A1 (en) * 2007-11-26 2009-05-28 Infineon Technologies Ag Device and method including a soldering process

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