CN105097567B - 堆叠器件的方法 - Google Patents

堆叠器件的方法 Download PDF

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Publication number
CN105097567B
CN105097567B CN201510427008.0A CN201510427008A CN105097567B CN 105097567 B CN105097567 B CN 105097567B CN 201510427008 A CN201510427008 A CN 201510427008A CN 105097567 B CN105097567 B CN 105097567B
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coating material
silicon
circuit
semiconductor devices
manufacture
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CN105097567A (zh
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王宗鼎
李建勋
陈承先
赵智杰
李明机
郭祖宽
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开一种制造半导体器件的方法，提供第一器件，所述第一器件包括第一穿透硅通孔(TSV)结构；在所述第一器件上方形成第一涂层材料，其中，所述第一涂层材料在所述第一器件上方连续地延伸并且覆盖所述第一穿透硅通孔结构；将第二器件设置在所述第一器件上方以及所述第一涂层材料内，其中，所述第二器件包括第二穿透硅通孔结构和多个导电凸点，设置所述第二器件包括所述多个导电凸点位于所述第一涂层材料内；在所述第二器件上方形成第二涂层材料；将第三器件设置在所述第二涂层材料上方；对所述第一涂层材料和所述第二涂层材料进行预处理；以及此后，同一处理中对所述第一涂层材料和所述第二涂层材料进行固化。

Description

堆叠器件的方法
该申请为分案申请，其原案申请的申请号为200910150015.5、申请日为2009年06月18日、发明名称为“堆叠器件的方法”。
技术领域
本发明一般地涉及一种半导体制造工艺，特别地涉及一种制造堆叠半导体器件的方法。
背景技术
通孔通常被广泛地用于半导体制造以在半导体器件和一个或多个导体材料层之间提供电耦合。传统的引线键合有局限性，例如，随着性能和密度需求的提高使得进行传统的引线键合不再合适，最近，穿透硅通孔(TSV)技术成为了克服这种传统的引线键合局限性的方法。TSV允许在z轴形成互连线实现更短的互连。从衬底前表面延伸到后表面而形成的通孔可以穿透衬底(例如晶片)建立互连。TSV在3D封装技术中的堆叠晶片、堆叠芯片和/或其组合形成互连是非常有用的。
在制造堆叠半导体器件中，包括焊剂的液体无流式底部填充(NFU)技术通常被用于堆叠和耦合两个器件。NFU层经过热处理(例如，固化/回流循环)，其中NFU层被固化并把相关的结构封装在器件之间的区域内。同样，两个器件之一的焊料凸点回流并形成与其它器件的TSV结构的焊料接合点，这样各器件能够被电耦合。对于每个需要堆叠和耦合的附加器件，需要提供附加NFU层并且重复进行热处理。虽然这一方法对于其所意欲达到的目标而言是满意的，但是在其它方面是不满意的。其中一个缺陷就是，在堆叠半导体器件的制造过程中低NFU层经过多次固化/回流循环。这将增加NFU层的热应力，并且引入例如NFU层中的气泡、焊料凸点褶皱或破碎、NFU层的脱落等各种缺陷，从而导致较差的器件性能和可靠性。
因此，需要一种制造堆叠半导体器件的方法以减少器件之间的涂层材料的热应力。
发明内容
因此，本发明的一些实施例提供了制造半导体器件的方法，包括提供第一器件、第二器件和第三器件；提供在第一器件和第二器件之间的第一涂层材料；提供在第二器件和第三器件之间的第二涂层材料；以及此后，在同一处理中对第一和第二涂层材料进行固化。在一些实施例中，每个所述第一、第二和第三器件包括电路；每个所述第一和第二器件包括穿透硅通孔(TSV)结构；所述方法还包括，响应于所述固化，利用所述第一和第二器件的TSV结构对第一、第二和第三器件的电路进行电耦合；其中，所述第一和第二涂层材料均包括利于耦合的焊料成分。在另一些实施例中，所述第一、第二和第三器件是管芯和晶片中的一种。
在另一些实施例中，所述第三器件包括形成于其上的第三涂层材料，并且所述方法包括在固化之前在所述第三涂层材料和所述第三器件上覆盖第四器件，所述第四器件是管芯和晶片中的一种；其中所述固化包括对第三涂层材料进行固化以使第三涂层材料与第一和第二涂层材料基本相同地从第一态转化为第二态。在其它实施例中，所述方法还包括在固化前对所述第一和第二涂层材料进行预处理。在一些实施例中，所述预处理包括将第一和第二涂层材料加热到低于第一和第二涂层材料的固化温度的温度。在一些实施例中，所述方法还包括在固化后对所述第一和第二涂层材料进行后处理。
在一些实施例中，所述提供第一涂层材料的步骤包括在所述第一器件上形成所述第一涂层材料，以及在所述第一涂层材料和第一器件上覆盖所述第二器件；以及所述提供第二涂层材料的步骤包括在所述第二器件上形成所述第二涂层材料，以及在所述第二涂层材料和第二器件上覆盖所述第三器件。在另外一些实施例中，所述提供第一涂层材料的步骤包括在所述第二器件上形成所述第一涂层材料，以及在所述第一器件上覆盖具有所述第一涂层材料的所述第二器件；以及所述提供第二涂层材料的步骤包括在所述第三器件上形成所述第二涂层材料，以及在所述第二器件上覆盖具有所述第二涂层材料的所述第三器件。
本发明的一些实施例还提供一种半导体器件，包括第一器件；第二器件，覆盖在所述第一器件上并且电耦合到所述第一器件；第三器件，覆盖在所述第二器件上并且电耦合到所述第二器件；第一涂层材料，置于所述第一和第二器件之间；以及第二涂层材料，置于所述第二和第三器件之间；其中所述第一和第二涂层材料被设定了基本相同的热处理历史。在一些实施例中，所述第一和第二涂层材料具有基本相同的固化循环。在另一些实施例中，所述第一、第二和第三器件是管芯和晶片中的一种。在另一些实施例中，所述的半导体器件，还包括第四器件，所述第四器件是管芯和晶片中的一种；以及第三涂层材料，置于所述第三和第四器件之间，所述第三涂层材料具有与第一和第二涂层材料的固化循环基本相同的固化循环。
在另一些实施例中，每个所述第一、第二和第三器件包括多个穿透硅通孔(TSV)结构。在一些实施例中，所述第一器件的一个TSV结构电耦合到所述第二器件的一个TSV结构；以及其中所述第二器件的一个TSV结构电耦合到所述第三器件的一个TSV结构。在另一些实施例中，所述第一器件包括用于连接另一半导体器件的多个导电凸点。在另一些实施例中，所述半导体器件进一步包括用于支撑结构的承载衬底；以及所述第一器件覆盖在所述承载衬底上并且固定到所述承载衬底上。
此外，本发明的一些实施例还提供了一种制造堆叠半导体器件的方法，包括：提供具有电路和形成于其上的第一涂层材料的第一器件；在所述第一涂层材料和所述第一器件上堆叠第二器件，所述第二器件具有电路和形成于其上的第二涂层材料；在所述第二涂层材料和所述第二器件上堆叠第三器件，所述第三器件具有电路；以及执行一个热处理用于电耦合所述第一、第二和第三器件的电路从而形成堆叠半导体器件的电路。在一些实施例中所述方法包括在执行所述热处理之前对所述第一和第二涂层材料进行预处理，其中预处理的温度从大约80℃至大约150℃。在另一些实施例中，所述方法包括在执行所述热处理之后对所述第一和第二涂层材料进行后处理，其中所述后处理的温度从大约100℃至大约200℃。
在另一些实施例中，所述热处理的温度从大约200℃至大约300℃。在其它实施例中，第四器件包括在其上形成的第三涂层材料，所述第三涂层材料与第一和第二涂层材料基本相同，所述方法还包括在第三涂层材料和第四器件上堆叠的第五器件，所述第五器件是具有电路的芯片，并且响应于热处理，所述第五器件的电路电耦合到所述第四器件的电路。在另一些实施例中，所述方法还包括选择第一和第二涂层材料为B阶聚合物和固体膜之一。
根据本发明的一方面，提供了一种制造半导体器件的方法，包括：提供第一器件，所述第一器件包括第一穿透硅通孔(TSV)结构；在所述第一器件上方形成第一涂层材料，其中，所述第一涂层材料在所述第一器件上方连续地延伸并且覆盖所述第一穿透硅通孔结构；将第二器件设置在所述第一器件上方以及所述第一涂层材料内，其中，所述第二器件包括第二穿透硅通孔结构和多个导电凸点，设置所述第二器件包括所述多个导电凸点位于所述第一涂层材料内；在所述第二器件上方形成第二涂层材料，其中，所述第二涂层材料在所述第二器件上方连续地延伸并且覆盖所述第二穿透硅通孔结构；将第三器件设置在所述第二涂层材料上方，其中，所述第三器件包括第三穿透硅通孔结构；对所述第一涂层材料和所述第二涂层材料进行预处理；以及此后，同一处理中对所述第一涂层材料和所述第二涂层材料进行固化。
在该方法中，每个所述第一器件、所述第二器件和所述第三器件均包括电路；其中，所述第一涂层材料和所述第二涂层材料均包括焊剂成分；以及其中，响应于所述固化，利用所述第一穿透硅通孔结构、所述第二穿透硅通孔结构和所述第三穿透硅通孔结构将所述第一器件、所述第二器件和所述第三器件的电路电耦合。
在该方法中，每个所述第一器件、所述第二器件和所述第三器件均是管芯。
该方法包括：将第四器件设置在第三涂层材料上方，其中，所述第四器件包括第四穿透硅通孔结构；以及其中，所述固化包括在与所述第一涂层材料和所述第二涂层材料相同的同一处理中对所述第三涂层材料进行固化。
在该方法中，所述预处理的温度从大约80℃至大约150℃。
在该方法中，所述预处理包括将所述第一涂层材料和所述第二涂层材料加热至比所述第一涂层材料和所述第二涂层材料的固化温度低的温度。
该方法还包括：在所述固化之后对所述第一涂层材料和所述第二涂层材料进行后处理。
在该方法中，所述后处理的温度从大约100℃至大约200℃。
在该方法中，所述固化包括温度在大约200℃至大约300℃的热处理。
根据本发明的另一方面，提供了一种制造堆叠半导体器件的方法，所述方法包括：
提供具有第一电路和第一穿透硅通孔(TSV)结构的第一器件；
在所述第一器件上方形成第一涂层材料，所述第一涂层材料在所述第一器件上方连续地延伸并且覆盖所述第一穿透硅通孔结构；在所述第一涂层材料上堆叠第二器件，所述第二器件具有第二电路、第二穿透硅通孔结构和第一多个导电凸点，其中，堆叠所述第二器件促使所述第一多个导电凸点进入所述第一涂层材料；在所述第二器件上方形成形成第二涂层材料，所述第二涂层材料在所述第二器件上方连续地延伸并且覆盖所述第二穿透硅通孔结构；在所述第二涂层材料上堆叠第三器件，所述第三器件具有第三电路和第二多个导电凸点，其中，堆叠所述第三器件促使所述第二多个导电凸点进入所述第二涂层材料；对所述第一涂层材料和所述第二涂层材料进行预处理；以及此后，执行热处理，所述热处理电耦合所述第一电路、所述第二电路和所述第三电路以形成所述堆叠半导体器件的电路，并且将所述第一涂层材料和所述第二涂层材料固化。
在该方法中，所述预处理的温度从大约80℃至大约150℃。
该方法还包括：在所述热处理之后对所述第一涂层材料和所述第二涂层材料进行后处理，其中，所述后处理的温度从大约100℃至大约200℃。
在该方法中，所述热处理的温度从大约200℃至大约300℃。
在该方法中，所述第一涂层材料和所述第二涂层材料包括B阶聚合物。
附图说明
本发明的很多方面能够通过结合附图进行的详细说明变得更加易于理解。应该注意，根据行业中标准的做法，各种特征并非依比例绘制。实际上，为便于清楚地讨论，各种特征的尺寸可以任意放大或缩小。
图1A至1G示出了堆叠半导体器件各种制造阶段的横截面视图；
图2示出了具有在制造过程中可能引入的各种缺陷的堆叠半导体器件的横截面视图；
图3示出了根据本发明的很多方面的制造堆叠半导体器件的方法的流程图；
图4A至4E示出了根据图3所示的方法的各种制造阶段的堆叠半导体器件的横截面视图；
图5示出了根据本发明的很多方面的制造堆叠半导体器件的可选方法的流程图；
图6A至6F示出了根据图5所示的方法的各种制造阶段的堆叠半导体器件的横截面视图；
图7示出了利用形成涂层材料可选方法制造的图4所示的堆叠半导体器件的横截面视图；
图8A和8B示出了利用形成涂层材料的可选方法制造的图6所示的堆叠半导体器件的横截面视图。
具体实施方式
本发明通常涉及一种半导体制造工艺，特别地涉及一种制造堆叠半导体器件的方法。然而应该知道，所提供的特定实施例仅仅作为实例来教导更广泛的发明概念，本领域的普通技术人员可以容易地将本发明的教导应用到其它方法或器件上。此外，应该知道，本发明中讨论的方法和装置包括一些传统的结构和/或工序。由于这些结构和工序是本领域所公知的，因此本发明仅进行概要的讨论。
此外，为了方便和起到示例作用，在整个附图中重复使用了一些附图标记，这种重复并不表示整个附图中的任何必须的特征或步骤的组合。而且，在下文中，第一特征在第二特征之上、相邻、或者相耦合的构造可以包括第一和第二特征直接接触的实施例，也可以包括附加特征形成在第一特征和第二特征之间的实施例，也就是说第一和第二特征可以不直接接触。而且，在衬底上的特征的形成，包括例如蚀刻衬底，可以包括在衬底表面之上形成特征，直接在衬底表面上形成特征的实施例，和/或延伸到衬底表面下形成特征到实施例。
参考图1A至1G，它们示出了堆叠半导体器件100在各种制造阶段的横截面视图。在图1A中，半导体器件100包括具有电路的第一层器件102。相应地，器件102可以包括衬底104，所述衬底包括一个或多个在衬底上形成的特征。这些特征没有示出，但是存在于衬底104之上，并且包括，例如栅结构，源/漏区域，其它掺杂区域，绝缘结构，对一个或多个栅、源或者漏区域的接触孔，存储元件(例如，存储单元)，和/或其它本领域公知的特征。器件102还可以包括形成于衬底104的前表面106上的一个或多个金属层和层间电介质(统称为互连结构)。器件102还可以包括提供对互连结构的电接触的一个或多个触点。
器件102还包括形成于衬底104之上和其中的多个穿透硅通孔(TSV)结构108。TSV结构108可以是穿过衬底104的垂直导电结构。同样，TSV结构108也可以电耦合到各触点，以及电耦合到互连结构。正如下面将要讨论的，TSV结构108可以暴露于衬底104的后表面110以便进行3-D封装，例如堆叠和耦合到其它器件。器件102还可以包括电耦合到互连结构的多个键合点112，并且可以支持导电特征例如焊料凸点(或球)用于倒装芯片封装技术和其它适当的封装技术。
器件102可以固定到真空板120上，所述真空板能够提供真空吸取力122、124。真空板120也可以提供稳定的基础支持以便堆叠多个器件来形成堆叠半导体器件100。真空板120可以包括形成于其上的具有缓冲层的支撑板126以支撑器件102的前表面106中包括的各种结构例如键合点112的区域。因此，在器件102的前表面106上的各种结构在堆叠处理中能够不被破坏。器件102的前表面106中不包含外部结构的区域基本上为平面，通过吸取力122，124可以适于固定到真空板120上。可选地，器件102也可以通过粘合材料固定到承载衬底上。
液体无流式底部填充(NFU)层130可以形成在器件102的后表面110上。NFU可以充当封装用低粘性液体环氧材料，以及充当回流用焊剂成分(flux component)。NFU层130(称为NFU印刷)可以通过分布器132应用于后表面110。应该知道，在这里提到的“前”和“后”例如衬底的前表面和衬底的后表面是任意的，衬底的表面可以根据适当的习惯来标记。
图1B示出的半导体器件100可以包括具有电路的第二器件140。相应地，器件140可以包括具有起电路作用的各种特征(类似于器件102的特征)的衬底142，形成于前表面145的、电耦合到所述电路的多个键合点143和小凸点144，以及延伸通过衬底并且可能暴露于后表面147的多个TSV结构146。器件140可以置于层130和器件102之上以便小凸点144可以接触到并和器件102中适当的TSV结构108对齐。
在图1C中，包括器件102和器件140的半导体器件100可以移至加温室150例如烤炉中，并且半导体器件100可以在一段时间内(例如固化/回流循环)加热(155)到期望的温度或温度范围。例如，温度范围可以是从200至300℃。如前所述，层130包括封装用环氧材料和回流用焊剂。相应地，响应于所述加热，环氧材料全固化并封装器件102和140之间的各种结构。这为将器件102堆叠和键合到器件140上提供了所需的机械强度和稳定性。同时，焊剂回流器件140的小凸点144，并且形成与器件102的TSV结构108的焊接点。这样，器件102的电路可以被电耦合到器件140的电路上。
在图1D中，液体NFU层160可以通过分布器132形成在器件140的后表面147上。如前所述，NFU可以充当填充或封装用低粘性液体环氧材料，以及充当回流或焊接用焊剂。在图1E中，半导体器件100可以包括具有电路的第三层器件170。相应地，器件170可以包括具有起电路作用的各种特征(类似于器件102的特征)的衬底172，形成于前表面175的、电耦合到所述电路的多个键合点173和小凸点174，以及延伸通过衬底并且可能暴露于后表面177的多个TSV结构176。器件170可以置于层160和器件140之上以便小凸点174可以接触到并和器件140的中适当的TSV结构146对齐。
在图1F中，包括器件102，器件140和器件170的半导体器件100可以置于加温室150中，并且类似于图1C的热处理，半导体器件100可以在一段时间内(例如，循环)加热到期望的温度或温度范围。层160全固化并封装器件140和器件170之间的结构，同时焊剂回流小凸点174形成与器件140的TSV结构146的焊接点。然而，全固化层130经过另一热循环，并且层130的热应力可以得到提高。在图1G中，上述处理重复应用到将要堆叠的每一个附加器件上，器件的数量可以取决于应用和/或设计需要。在最后的器件被堆叠并且最后的NFU层被全固化后，真空吸取力122，124将被关闭，半导体器件100可以从真空板120上移除以便进一步处理。
参考图2，图2示出了在堆叠半导体200的制造过程中可能引入的各种缺陷。堆叠半导体200可以用与图1所述的堆叠半导体100相似的方法制造。堆叠半导体200可以包括第一器件201、第二器件202、第三器件203、第四器件204、第五器件205和第n器件206(其中n是被堆叠的器件的总数)。器件201可以包括每个均形成于键合点208上的多个焊料凸点(或球)207用于倒装芯片封装技术或其它适当的封装技术。器件201还进一步包括多个再分布层(RDL)结构209用于将键合点重新排布到器件201的各种区域。器件201还可以包括多个TSV结构210用于在3－D器件封装和/或器件堆叠配置中耦合到另一器件上。
正如上文所述的，NFU层211(类似于图1的层130)可以分布于(也称为NFU印刷)器件201之上，并且器件202可以放置于NFU层211和器件201之上。器件202可以包括多个小凸点(或球)216，每一个所述小凸点均形成于键合点218上以便耦合到器件201的一个或多个TSV结构210上。而后NFU层211经过热处理以便固化NFU层211并且回流所述小凸点以便电耦合所述器件201和202。器件202还包括一个或多个TSV结构219用于在3－D器件封装和/或器件堆叠配置中耦合到另一器件上。上述处理重复应用到每一个附加器件203、204、205、206上以形成堆叠半导体器件200。相应地，NFU层211经过(n－1)次固化/回流循环，NFU层212经过(n－2)次固化/回流循环，NFU层213经过(n－3)次固化/回流循环，NFU层214经过(n－4)次固化/回流循环，NFU层215经过(n－5)次固化/回流循环，等等。由此，每个NFU层211－215具有与其它层不同的热处理历史或循环，NFU层211具有最长的热循环并且NFU层215具有最短的热循环(如果n＝6，即总共6个器件)。
可以看到，随着NFU层的热处理历史或循环的不断增加将会引入各种缺陷。也就是，NFU层经过越长越多次的热处理(例如，固化/回流循环)，热应力将会更可能在NFU层中引入缺陷。例如，NFU层211可能具有最长的热循环，那么可能引入的缺陷包括焊点褶皱或可能导致微小焊点与键合点分离的断裂，在NFU层211中的气泡220、224、226、228和在NFU层211和小凸点216的交界面发生的脱层或脱落229。NFU层212具有第二长的热循环，这样类似的缺陷也会被引入，例如在NFU层212中的分层或脱落230，和气泡234、236、238。NFU层213具有第三长的热循环，这样可能在NFU层213中引入例如气泡240，242这样的缺陷。NFU层215具有最短的热循环，仅仅包括一个固化/回流循环，这样热应力基本上不会或很少会引入缺陷。然而，NFU层215在被全固化之前是低粘性液体，因此例如气泡这样的一些缺陷甚至可以在一个固化/回流循环之后被改进。各种各样的缺陷将导致器件的低性能和低可靠性。
为了举例说明，下面将示出在一系列处理操作中一个示例器件的各种实施例。应该知道，很多处理步骤都被简化描述了，这些步骤对于本领域的普通技术人员而言是公知的。此外，也可以添加额外的处理步骤，并且处理步骤流程中的某些步骤可以被去除和/或修改而仍然实现本发明。下面的描述仅用于理解本实施例，并不意在教导一个或多个步骤是必需的。还应该知道，在这里提到的“前”和“后”例如衬底的前表面和衬底的后表面是任意的，衬底的表面可以根据适当的习惯来标记。
参考图3，图3示出了利用了一个固化/回流循环制造堆叠半导体器件的方法300。参考图4A至4E，它们示出了根据图3的方法300制造的堆叠半导体器件400的横截面视图。在图4A中，方法300从方框302开始，在方框302提供在其上形成有第一涂层材料404的第一层器件402。
涂层材料404可以通过使用具有聚合物成分和焊剂成分的层压结构或卷带装置406来形成。涂层材料404可以包括被用作高粘性固体膜的环氧聚合物。相应地，涂层材料404具有足够的机械强度和稳定性以在稍后材料被全固化时能够将器件保持在适当的位置。可选地，涂层材料404可以替代地通过旋涂处理来形成。例如，涂层材料404包括应用于器件402的具有焊剂成分的液体环氧聚合物，并且涂层材料404可以经过预处理。在预处理过程中，涂层材料404可以加热到低于涂层材料404的固化温度的温度。例如，涂层材料404可以加热到80℃至150℃。加热可以包括热源，例如闪光灯，紫外线照射，或者其它适当的加热机制。相应地，涂层材料404可以从液态变为B阶聚合物(例如，在液态和全固化之间的中间阶)，以使涂层材料的粘性得到提升。这样，涂层材料404能够具有足够的机械强度和稳定性以在稍候材料被全固化时能够保持器件在适当的位置。此外，涂层材料404可以包括用于提升涂层材料404的粘着性的助聚剂，以及其它用于提高涂层材料404的固化的添加剂。
器件402包括形成于半导体衬底410中的电路，例如结晶硅。可选地，衬底410可以具有在块状半导体上的外延层。此外，衬底410可以变性以提升性能。例如，外延层可以包括不同于块状半导体的半导体材料，例如在块状硅之上的锗硅层，或者在通过包括选择性外延生长(SEG)的处理而形成的块状锗硅之上的硅层。此外，衬底410可以包括绝缘层上覆半导体(SOI)结构。例如，衬底410可以包括通过例如注氧隔离法(SIMOX)的处理形成的埋氧(BOX)层。衬底410可以包括各种掺杂阱，掺杂特征和半导体层，被配置用于形成各种微电子器件例如包括互补金属氧化物半导体(CMOS)的金属氧化物半导体场效应晶体管(MOSFET)，包括CMOS图像传感器(CIS)的图像传感器，微电子机械系统(MEMS)，存储单元，和/或其它适当的有源和无源器件。衬底410可以包括各种绝缘特征，被配置用于隔离在衬底上形成的不同器件。所述绝缘特征包括各种结构并且可以使用不同的处理技术来形成。例如，绝缘特征可以包括电介质隔离特征，例如浅沟槽隔离(STI)。掺杂阱和掺杂特征包括由例如离子注入的掺杂处理形成的p型掺杂区域和/或n型掺杂区域。
器件402进一步包括具有一个或多个金属层的互连结构，所述金属层被配置用于连接在半导体衬底410中的各种掺杂区域和/或特征，以获得实用电路。互连结构包括导体材料，例如铜、铜合金、钛、氮化钛、钽、氮化钽、钨、多晶硅、金属硅或其组合。铜互连结构可以通过例如CVD、溅射法、镀覆法或其它适合的处理技术形成。可选地或额外地，也可以使用铝互连结构并且它可以包括铝、铝/硅/铜合金、钛、氮化钛、钨、多晶硅、金属硅或其组合。铝互连结构可以通过包括物理气相沉积(或溅射法)、化学气相沉积(CVD)或其组合等处理来形成。形成铝互连结构的其它制造技术还可以包括光刻处理和蚀刻来构图导电材料为垂直(通过和触点)和水平连接(导电线)。
互连结构可以包括具有低电介质常数，例如低于大约3.5的层间电介质。电介质包括氧化硅、氮化硅、氧氮化硅、聚酰亚胺、旋制氧化硅(SOG)、氟掺杂硅玻璃(FSG)、碳掺杂氧化硅、Black(加利福尼亚州圣克拉拉的美国应用材料公司)，干凝胶、气凝胶、非晶氟化碳、聚对二甲苯、BCB(苯并环丁烯)、SiLK(Dow Chemical，密西根州米德兰)和/或其它适当的材料。电介质可以通过包括旋制、CVD、溅射、或其它适当的处理技术形成。金属层和层间电介质可以通过例如镶嵌处理或者光刻/等离子体蚀刻处理等集成处理来形成。
器件402可以包括用于支撑焊料凸点(或球)的多个键合点412，以及用于倒装晶片封装技术的其它外部键合机构或者其它适当的封装技术。器件402可以进一步包括多个再分布层(RDL)结构(未示出)，用于将键合点重新分布到器件402的各种区域。键合点412可以在衬底410的前表面413上的顶层金属层之上的钝化层中形成，并且可以电耦合到互连结构。器件402可以进一步包括多个穿透硅通孔(TSV)结构414。TSV结构414可以是穿过衬底410的垂直导电结构，也可以被电耦合到互连结构和/或键合点412。如下面将要讨论的，TSV结构414可以暴露于衬底410的后表面415以便进行3-D封装，例如堆叠和耦合到其它器件。这种3-D封装穿过衬底体建立垂直连接，避免了额外的连线并且构建了更平整和紧凑的结构。
器件402可以固定到真空板420上，所述真空板能够提供真空吸取力422、424。真空板420也可以提供稳定的基础支持以便堆叠多个器件来形成堆叠半导体器件400。真空板420可以包括具有形成于其上的缓冲层的支撑板426，以支撑器件402的前表面413中包括的各种结构例如键合点112的区域。因此，在器件402的前表面413上的各种结构在堆叠处理中能够不被破坏。器件402的前表面413中不包含外部结构的区域基本上为平面，并且可以适于通过吸取力422、424来固定到真空板420上。可选地，器件402也可以通过粘合材料固定到承载衬底上。
在图4B中，所述方法300从方框304处继续，其中在第一涂层材料404和第一层器件402上放置第二器件430。所述器件430包括形成于其上的第二涂层材料431。涂层材料431可以类似于涂层材料404，并且可以与上面讨论的方法相似的方法形成。同样地，涂层材料431可以在放置在器件402之前预层压到器件430上，以便缩减处理时间。器件430可以进一步包括具有起电路作用的各种特征(类似于上面讨论的器件402的特征)的衬底432，形成于前表面435的、通过互连结构电耦合到所述电路的多个键合点433和小凸点434，以及延伸通过衬底432并且可能暴露于后表面437的多个TSV结构436。TSV结构436可以电耦合到所述互连结构和/或键合点433。需要对器件430施加足够的力以使前表面435与涂层材料404接触并粘附。此外，器件430的小凸点434可以与器件402中适当的TSV结构414对齐，并且置于接近或者与TSV结构414接触的位置以便回流小凸点434。
可选地，参考图7，涂层材料404可选地可以在堆叠之前不在器件402的后表面415上形成，而在器件430的前表面435上形成。相应地，具有涂层材料404的器件430可以被翻转702并且堆叠到器件402之上。需要对器件430施加足够的力以使器件402的前表面415与涂层材料404接触并粘附。此外，器件430的小凸点434可以与器件402中适当的TSV结构414对齐，并且置于接近或者与TSV结构414接触的位置以便回流小凸点434。
在图4C中，方法300从方框306处继续，其中在第二涂层材料431和第二层器件430上放置第三层器件440。器件440可以包括形成于其上用于堆叠另一器件的第三涂层材料(未示出)。器件440可以进一步包括具有起电路作用的各种特征(类似于上面讨论的器件402的特征)的衬底442，形成于前表面445的、通过互连结构电耦合到所述电路的多个键合点443和小凸点444，以及延伸通过衬底442并且可能暴露于后表面447的多个TSV结构446。TSV结构446可以电耦合到所述互连结构和/或键合点443。需要对器件440施加足够的力以使前表面445与涂层材料431接触并粘附。此外，器件440的小凸点434可以与器件430中适当的TSV结构436对齐，并且置于接近或者与TSV结构436接触的位置以便回流小凸点444。
应该注意，类似于上文对图7的讨论，涂层材料431可以在堆叠之前不在器件430的后表面437上形成，而在器件440的前表面445上形成。相应地，后续的涂层材料可以以相似的方法形成以便堆叠附加器件从而形成堆叠半导体器件400。
可以对每一个需要堆叠的附加器件重复上面讨论的处理，器件的数量可以根据堆叠半导体器件400的设计需求变化。应该知道，为了清楚和便于理解本发明的实施例，这里仅描述了三个器件的例子。在图4D中，在最后一个器件被堆叠后，方法300从方框308处继续，其中在同一热处理中对涂层材料404、431进行固化。半导体器件400可以移至加温室450例如烤炉中，并且半导体器件400可以在一段时间内(例如固化/回流循环)加热455到期望的温度或温度范围。例如，温度范围可以是从200至300℃。加温室450可以包括热源，例如闪光灯，紫外线照射，或者其它适当的加热机制。如前面所说明的，涂层材料404、431均包括封装用环氧材料和回流用焊剂。相应地，响应于所述加热，环氧材料全固化并封装在器件402、430和440之间的各种结构，这为将为堆叠和键合所述器件提供所需的机械强度和稳定性。同时，焊剂回流小凸点434、444，并且形成与相应的TSV结构414、436的焊接点。
这样，器件402、430和440的电路可以相互电耦合以形成堆叠半导体器件400的电路。相应地，涂层材料404、431被全固化并且在同一固化/回流循环中回流小凸点434、444，从而使得涂层材料404、431具有基本上相同的热处理历史。这将大大减少涂层材料404、431的热应力，即使被堆叠的器件的数量增加，因为所有的涂层材料都将经过同一固化/回流循环。图2所讨论的热应力所引入的各种缺陷也将被最小化，从而提升了半导体器件400的性能和稳定性。此外，由于涂层材料404、431可以被用作用于器件堆叠的高粘性固体膜或B阶聚合物，与图2所讨论的使用低粘性液体NFU相比，在涂层材料404、431中形成的气泡将会减少。
此外，半导体器件400可选地在加温室中进行后处理以便使涂层材料404和431的环氧聚合物进行充分交联。在后处理中，半导体器件400可以加热到100至200℃的温度范围。加温室可以包括热源，例如闪光灯，紫外线照射，或者其它适当的加热机制。
在图4E中，在固化/回流处理之后，就可以通过关闭真空吸取力422、424来将堆叠半导体器件400从真空板420上移除。半导体器件400可以进一步包括多个焊料凸点(或球)460用于倒装芯片封装技术或其它适当的封装技术。每个器件402、430、440均包括芯片(或管芯)，这样图3的方法300就可以实现芯片到芯片的堆叠和键合。可选地，每个器件402、430、440均包括晶片，这样图3的方法300就可以实现晶片到晶片的堆叠和键合。
现在参考图5，图5所示出的是用于制造堆叠半导体器件的方法500。一同参考图6A至6F，它们示出了根据图5所示的方法500制造的堆叠半导体器件600的横截面视图。堆叠半导体器件600类似于图4所示的堆叠半导体器件400，区别在于器件600包括管芯到晶片的堆叠和键合。为了简便和清楚地描述，图4和图6中相似的特征使用了相同的附图标记。
在图6A中，方法500从方框502开始，其中提供其上形成有涂层材料404的晶片602，例如半导体晶片。所述晶片602可以包括起电路作用的各种半导体特征(类似于对器件402的讨论中提到的特征)，形成于前表面609的、通过互连结构(未示出)电耦合到所述电路的多个键合点607和导电凸点608(例如，金、铜或其它适当的导电材料)。导电凸点608可以用于倒装芯片封装技术或其它适当的封装技术。晶片602还进一步包括多个再分布层(RDL)结构(未示出)用于将键合点重新排布到晶片602的各种区域。晶片602还包括延伸通过晶片602并且可能暴露于后表面613的多个穿透硅通孔(TSV)结构610、611、612。如下面将要讨论的，每个TSV结构610、611、612可以形成于晶片602的一个部分中以便耦合到多个芯片。TSV结构610、611、612可以通过互连结构电耦合到所述电路，并且可以电耦合到键合点和/或其它导电特征。可选地，TSV结构610、611、612可以是互连结构的一部分。
晶片602可以固定到真空板420上，所述真空板能够提供真空吸取力422、424。真空板420也可以提供稳定的基础支持以便堆叠多个器件来形成堆叠半导体器件600。真空板420可以包括具有形成于其上的缓冲层的支撑板426以支撑晶片602的前表面609中包括的各种结构例如导电凸点608。因此，在晶片602的前表面609上的各种结构在堆叠处理中能够不被破坏。晶片602的前表面609中不包含外部结构的区域基本上为平面，并且可以适于通过吸取力422，424来固定到真空板420上。
在图6B中，方法500从方框504处继续，其中在涂层材料404和晶片602上堆叠多个第一层芯片621、622、623。应该知道，第一层芯片的数量可以变化，并且为了清楚和便于理解本发明的实施例，这里仅描述了三个芯片的例子。每个芯片621、622和623可以包括例如存储单元的电路，以及用于电耦合到晶片602的相应的TSV结构610、611、612上的凸点层630(包括键合点)。相应地，芯片621、622和623的电路可以电耦合到晶片602的电路。凸点层630可以包括焊料凸点、金凸点、铜凸点或者其它本领域公知的适当的导电凸点。如下所述，每个芯片621、622和623可以进一步包括用于耦合到其它芯片的多个TSV结构632。芯片621、622和623可以通过机器人臂640或者其它适当的机构堆叠到晶片602之上，以便凸点层630能够准确地与相应的TSV结构610、611、612对齐，并且凸点层630接近或者与相应的TSV结构接触以便回流。此外，芯片621、622和623可以由涂层材料404进行固定。芯片621、622和623可以进一步包括形成于其上的涂层材料645，涂层材料645可以基本上与涂层材料404相同并且可以用相似的方法形成。
可选地，参考图8A，涂层材料802(类似于图6A的涂层材料404)可以在将第一层芯片堆叠到晶片之前不在晶片602的后表面613(图6A)上形成，而在第一层芯片621、622和623上形成。
在图6C中，方法500从方框506处继续，其中在涂层材料645和第一层芯片621、622和623上分别堆叠多个第二层芯片651、652、653。每个芯片651、652、653可以包括例如存储单元的电路，以及用于电耦合到相应的第一层芯片621、622和623的TSV结构632上的凸点层654(包括键合点)。相应地，芯片651、652和653的电路可以分别电耦合到芯片621、622和623的电路。凸点层654可以包括焊料凸点、金凸点、铜凸点或者其它本领域公知的适当的导电凸点。如下所述，每个芯片651、652和653可以进一步包括用于耦合到其它芯片的多个TSV结构656。芯片651、652和653可以通过机器人臂640堆叠到芯片621、622和623，以便凸点层654能够准确地与相应的芯片621、622和623的TSV结构632对齐，并且凸点层654接近或者与TSV结构接触以便回流。此外，芯片651、652、653可以由涂层材料645进行固定。芯片651、652、653可以进一步包括形成于其上的涂层材料658，涂层材料658可以基本上与涂层材料404相同并且可以用相似的方法形成。
可选地，参考图8B，如上文图6C所述，涂层材料645可以在将第二层芯片堆叠到相应的第一层芯片之前不在第一层芯片621、622和623(图6B)上形成，而在第二层芯片651、652、653上形成。
在图6D中，方法500从方框508处继续，其中在涂层材料658和芯片651、652、653上分别堆叠多个顶层芯片661、662、663。应该知道，层数可以根据堆叠半导体器件600的设计需要变化，并且为了清楚和便于理解本发明的实施例，这里仅描述了三层的例子。每个芯片661、662、663可以包括例如存储单元的电路，以及用于电耦合到相应的芯片651、652、653的TSV结构656上的凸点层664。相应地，芯片661、662、663的电路可以分别电耦合到芯片651、652、653的电路。凸点层664可以包括焊料凸点、金凸点、铜凸点。芯片661、662、663可以不包括TSV结构和涂层材料，因为它们是顶层芯片而且没有其它的芯片会堆叠在其上。芯片661、662、663可以通过机器人臂640进行堆叠，以便凸点层664能够准确地与相应的芯片651、652、653的TSV结构656对齐，并且凸点层664接近或者与TSV结构接触以便回流。
可选地，参考图8B，如上文图6D所述，涂层材料658可以在将顶层芯片堆叠到相应的第二层芯片之前不在第二层芯片651、652、653(图6C)上形成，而在顶层芯片661、662、663上形成。
在图6E中方法500从方框510处继续，其中涂层材料404、645、658可以在同一热处理中进行固化。半导体器件600可以移至加温室450例如烤炉中，并且半导体器件600可以在一段时间内(例如固化/回流循环)加热455到期望的温度或温度范围。例如，温度范围可以是从200至300℃。如前所述，每个涂层材料404、645、658包括封装用环氧材料和回流用焊剂。相应地，响应于所述加热，环氧材料全固化并封装在芯片621-623、651-653、661-663之间以及在芯片621-623和晶片602之间的各种结构，这为芯片和晶片的堆叠和键合提供了所需的机械强度和稳定性。同时，焊剂成分回流凸点层630、654、664，并且形成与相应的TSV结构610-612、632、656的电接合点。
相应地，涂层材料404、645、658被全固化并且在同一固化/回流循环中回流凸点层630、654、664，从而使得涂层材料404、645、658具有基本上相同的热处理历史。这将大大减少涂层材料404、645、658的热应力，即使被堆叠的器件的数量增加，因为所有的涂层材料都将经过同一固化/回流循环。图2所讨论的热应力所引入的各种缺陷也将被最小化，从而提升了半导体器件600的性能和稳定性。此外，由于涂层材料404、645、658可以被用作用于器件堆叠的高粘性固体膜或B阶聚合物，与图2所讨论的使用低粘性液体NFU相比，在涂层材料404、645、658中形成的气泡将会减少。
此外，半导体器件600可选地在加温室中进行后处理以便使涂层材料404、645、658的环氧聚合物进行充分交联。在后处理中，半导体器件600可以加热到100至200℃的温度范围。加温室可以包括热源，例如闪光灯，紫外线照射，或者其它适当的加热机制。
在图6F中方法500从方框512处继续，其中半导体器件600经过晶片成型处理。成型化合物670、NFU或其它适当的材料可以部分包裹半导体器件600而形成以起到保护和保证机械强度的作用。半导体器件600可以从真空板420上移除并且可以进行进一步的半导体处理。
虽然已经详细地描述了本发明的具体实施例，本领域的技术人员应该知道在不背离本发明的精神和范围的前提下可以对本发明做出各种改变、置换和替代。例如，虽然实施例中芯片和晶片封装使用了TSV结构，应该知道所述方法可以在不使用TSV结构的其它传统封装技术中实现。因此，所有变化、置换和替代都包含在由附随的权利要求所限定的本发明的保护范围中。
一些不同的有益效果存在于这些或另一些实施例中。在此公开的方法和堆叠半导体器件提供了一种简单经济的技术，从而最小化在堆叠半导体器件中由热应力引入的各种缺陷。这样，堆叠半导体器件的性能和可靠性将会提升。堆叠半导体器件的涂层的固化/回流在一个热处理中进行。因此，堆叠半导体器件的制造将会花费更少的处理事件，更少的设备来完成一个完整的多层处理，从而减少了成本。在此公开的涂层材料可以由层压结构或卷带装置来形成，这样就能够在它们被叠加并键合形成堆叠半导体器件前容易地施加到器件上。此外，在此公开的所述方法和堆叠半导体器件可以用于芯片到芯片堆叠、晶片到晶片堆叠以及芯片到晶片堆叠。

Claims (14)

1.一种制造半导体器件的方法，包括：
提供第一器件，所述第一器件包括第一穿透硅通孔(TSV)结构；
在所述第一器件上方形成第一涂层材料，其中，所述第一涂层材料在所述第一器件上方连续地延伸并且覆盖所述第一穿透硅通孔结构；
将第二器件设置在所述第一器件上方以及所述第一涂层材料内，其中，所述第二器件包括暴露于后表面的第二穿透硅通孔结构和形成于前表面的多个导电凸点，设置所述第二器件包括所述多个导电凸点位于所述第一涂层材料内；
在所述第二器件上方形成第二涂层材料，其中，所述第二涂层材料在所述第二器件上方连续地延伸并且覆盖所述第二穿透硅通孔结构；
将第三器件设置在所述第二涂层材料上方，其中，所述第三器件包括第三穿透硅通孔结构；
对所述第一涂层材料和所述第二涂层材料进行预处理；以及
此后，同一处理中对所述第一涂层材料和所述第二涂层材料进行固化。
2.根据权利要求1所述的制造半导体器件的方法，
其中，每个所述第一器件、所述第二器件和所述第三器件均包括电路；
其中，所述第一涂层材料和所述第二涂层材料均包括焊剂成分；以及
其中，响应于所述固化，利用所述第一穿透硅通孔结构、所述第二穿透硅通孔结构和所述第三穿透硅通孔结构将所述第一器件、所述第二器件和所述第三器件的电路电耦合。
3.根据权利要求1所述的制造半导体器件的方法，其中，每个所述第一器件、所述第二器件和所述第三器件均是管芯。
4.根据权利要求3所述的制造半导体器件的方法，包括：
将第四器件设置在第三涂层材料上方，其中，所述第四器件包括第四穿透硅通孔结构；以及
其中，所述固化包括在与所述第一涂层材料和所述第二涂层材料相同的同一处理中对所述第三涂层材料进行固化。
5.根据权利要求1所述的制造半导体器件的方法，其中，所述预处理的温度从80℃至150℃。
6.根据权利要求1所述的制造半导体器件的方法，其中，所述预处理包括将所述第一涂层材料和所述第二涂层材料加热至比所述第一涂层材料和所述第二涂层材料的固化温度低的温度。
7.根据权利要求1所述的制造半导体器件的方法，还包括：
在所述固化之后对所述第一涂层材料和所述第二涂层材料进行后处理。
8.根据权利要求7所述的制造半导体器件的方法，其中，所述后处理的温度从100℃至200℃。
9.根据权利要求1所述的制造半导体器件的方法，其中，所述固化包括温度在200℃至300℃的热处理。
10.一种制造堆叠半导体器件的方法，所述方法包括：
提供具有第一电路和第一穿透硅通孔(TSV)结构的第一器件；
在所述第一器件上方形成第一涂层材料，所述第一涂层材料在所述第一器件上方连续地延伸并且覆盖所述第一穿透硅通孔结构；
在所述第一涂层材料上堆叠第二器件，所述第二器件具有第二电路、暴露于后表面的第二穿透硅通孔结构和形成于前表面的第一多个导电凸点，其中，堆叠所述第二器件促使所述第一多个导电凸点进入所述第一涂层材料；
在所述第二器件上方形成第二涂层材料，所述第二涂层材料在所述第二器件上方连续地延伸并且覆盖所述第二穿透硅通孔结构；
在所述第二涂层材料上堆叠第三器件，所述第三器件具有第三电路和第二多个导电凸点，其中，堆叠所述第三器件促使所述第二多个导电凸点进入所述第二涂层材料；
对所述第一涂层材料和所述第二涂层材料进行预处理；以及
此后，执行热处理，所述热处理电耦合所述第一电路、所述第二电路和所述第三电路以形成所述堆叠半导体器件的电路，并且将所述第一涂层材料和所述第二涂层材料固化。
11.根据权利要求10所述的制造堆叠半导体器件的方法，其中，所述预处理的温度从80℃至150℃。
12.根据权利要求10所述的制造堆叠半导体器件的方法，还包括：
在所述热处理之后对所述第一涂层材料和所述第二涂层材料进行后处理，其中，所述后处理的温度从100℃至200℃。
13.根据权利要求10所述的制造堆叠半导体器件的方法，其中，所述热处理的温度从200℃至300℃。
14.根据权利要求10所述的制造堆叠半导体器件的方法，其中，所述第一涂层材料和所述第二涂层材料包括B阶聚合物。
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