TWI797461B - 封裝裝置 - Google Patents

封裝裝置 Download PDF

Info

Publication number
TWI797461B
TWI797461B TW109122946A TW109122946A TWI797461B TW I797461 B TWI797461 B TW I797461B TW 109122946 A TW109122946 A TW 109122946A TW 109122946 A TW109122946 A TW 109122946A TW I797461 B TWI797461 B TW I797461B
Authority
TW
Taiwan
Prior art keywords
wafer
bonding
station
substrate
substrate wafer
Prior art date
Application number
TW109122946A
Other languages
English (en)
Other versions
TW202109715A (zh
Inventor
林聖
歌野哲弥
瀬山耕平
Original Assignee
日商新川股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商新川股份有限公司 filed Critical 日商新川股份有限公司
Publication of TW202109715A publication Critical patent/TW202109715A/zh
Application granted granted Critical
Publication of TWI797461B publication Critical patent/TWI797461B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67126—Apparatus for sealing, encapsulating, glassing, decapsulating or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrates to be conveyed not being semiconductor wafers or large planar substrates, e.g. chips, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67742—Mechanical parts of transfer devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
    • H01L21/67766—Mechanical parts of transfer devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
    • H01L21/67778—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading involving loading and unloading of wafers
    • H01L21/67781—Batch transfer of wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16147—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/751—Means for controlling the bonding environment, e.g. valves, vacuum pumps
    • H01L2224/75101—Chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7565—Means for transporting the components to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75701—Means for aligning in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75753—Means for optical alignment, e.g. sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/758—Means for moving parts
    • H01L2224/75801—Lower part of the bonding apparatus, e.g. XY table
    • H01L2224/75802—Rotational mechanism
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/759—Means for monitoring the connection process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H01L2224/81204—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding with a graded temperature profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81905—Combinations of bonding methods provided for in at least two different groups from H01L2224/818 - H01L2224/81904
    • H01L2224/81907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92143—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies

Abstract

本發明提供一種可提高晶圓上晶片方式的半導體裝置的生產能力且亦可抑制空間、費用的增加的封裝裝置。封裝裝置包括多個接合站14、以及單個晶圓搬運裝置12，所述多個接合站14分別具有將半導體晶片102接合至基板晶圓100的接合裝置16、以及向所述接合裝置16供給半導體晶片102的晶片供給裝置18，所述單個晶圓搬運裝置12為了對所述多個接合站14各自供給所述基板晶圓100並自所述多個接合站14各自回收所述基板晶圓100，而搬運所述基板晶圓100。

Description

封裝裝置
本說明書中，揭示了一種將半導體晶片接合並封裝於基板晶圓的封裝裝置。
自先前以來，已知有將半導體晶片接合至基板上來製造半導體裝置的封裝裝置。近年來，提出了使用晶圓作為基板的晶圓上晶片方式的半導體裝置。於製造晶圓上晶片方式的半導體裝置的封裝裝置中，設置有將半導體晶片接合至晶圓的接合裝置、以及向接合裝置供給並自接合裝置回收作為基板發揮功能的晶圓(以下稱為「基板晶圓」)的晶圓搬運裝置。晶圓搬運裝置設置有用以於不與基板晶圓的表面接觸的情況下搬運晶圓的搬運機器人、或者修正基板晶圓的旋轉角度的預對準器等。而且，晶圓搬運裝置於自載入埠(load port)取出基板晶圓後，修正所述基板晶圓的旋轉角度，然後將所述基板晶圓供給至接合裝置。於接合裝置中，若接合處理結束，則晶圓搬運裝置自接合裝置回收處理後的基板晶圓，且視需要於進行檢查等之後，將所述基板晶圓搬運至載入埠。
此處，為了提高半導體裝置的生產能力，提出了設置多個所述封裝裝置。藉由使多個封裝裝置並行運行，可提高生產能力。於設置多個封裝裝置的情況下，當然，不僅設置接合裝置或晶片供給裝置，而且亦設置多個晶圓搬運裝置。但是，通常基板晶圓的搬運或檢查所需要的時間與接合處理所需要的時間相比，大幅度地變短。因此，晶圓搬運裝置與接合裝置相比，不運行的待機時間多，浪費多。設置多個所述晶圓搬運裝置浪費了空間、費用。
因此，本說明書中，揭示了一種可提高晶圓上晶片方式的半導體裝置的生產能力且亦可抑制空間、費用的增加的封裝裝置。
本說明書中揭示的封裝裝置的特徵在於包括多個接合站、以及單個晶圓搬運裝置，所述多個接合站分別具有將半導體晶片接合至基板晶圓的接合裝置、以及向所述接合裝置供給半導體晶片的晶片供給裝置，所述單個晶圓搬運裝置為了對所述多個接合站各自供給所述基板晶圓並自所述多個接合站各自回收所述基板晶圓，而搬運所述基板晶圓。
藉由設為所述結構，可於多個接合站中共用一個晶圓搬運裝置，因此可提高生產能力且亦可抑制空間、費用的增加。
另外，所述多個接合站各自的所述接合裝置可與所述晶 圓搬運裝置相鄰配置，所述多個接合站各自的所述晶片供給裝置隔著所述接合裝置而配置於所述晶圓搬運裝置的相反側。
藉由設為所述結構，可於不橫貫晶片供給裝置的情況下供給、回收基板晶圓。
另外，所述晶圓搬運裝置及所述多個接合站可彼此協作而形成一個腔室，所述晶圓搬運裝置可於不使所述基板晶圓露出至所述腔室的外部的情況下自一個接合站搬運至其他接合站。
藉由設為所述結構，可防止基板晶圓的污染，且於使基板晶圓不收容於搬運用容器中的情況下於多個接合站之間簡易地移動。
另外，所述多個接合站可包括第一接合站以及第二接合站，所述第二接合站隔著所述晶圓搬運裝置而配置於第一接合站的相反側，所述第一接合站、所述晶圓搬運裝置及所述第二接合站排成一行配置。
藉由設為所述結構，可減少死空間(dead space)，因此可更有效地利用空間。
另外，封裝裝置可進而包括對處理後的基板晶圓進行檢查的單個所述檢查裝置，所述多個接合站共用所述單個檢查裝置。
藉由設為所述結構，可防止檢查裝置的設置所需要的費用、空間的增加。
另外，所述晶圓搬運裝置可包括搬運所述基板晶圓的單個搬運機器人、以及修正所述基板晶圓的旋轉角度的單個預對準 器，於多個接合站中共用單個所述搬運機器人及單個所述預對準器。
另外，所述晶圓搬運裝置可具有能夠同時保持兩個所述基板晶圓的搬運機器人，所述搬運機器人於在一個接合站中回收處理後的基板晶圓後，可於不移動的情況下立即供給新的基板晶圓。
藉由設為所述結構，可進一步縮短基板晶圓的供給、回收所需要的時間。
另外，所述多個接合站可包含第一接合站以及第二接合站，所述晶圓搬運裝置將自所述第一接合站回收的處理後的所述基板晶圓供給至所述第二接合站。
藉由設為所述結構，可對一個基板晶圓串列實施不同的兩種接合處理。
該情況下，於所述第一接合站中，可執行將所述半導體晶片臨時壓接於所述基板晶圓的臨時壓接處理，於所述第二接合站中，執行對所述臨時壓接的半導體晶片進行正式壓接的正式壓接處理。另外，於所述第一接合站中，可執行將第一半導體晶片接合至所述基板晶圓的處理，於所述第二接合站中，執行於所述第一半導體晶片上接合與所述第一半導體晶片不同的第二半導體晶片的處理。
根據本說明書中揭示的封裝裝置，可於多個接合站中共用一 個晶圓搬運裝置，因此可提高生產能力且亦可抑制空間、費用的增加。
10:封裝裝置
12:晶圓搬運裝置
14:接合站
14f:第一接合站
14s:第二接合站
16:接合裝置
16f:第一接合裝置
16s:第二接合裝置
18:晶片供給裝置
18f:第一晶片供給裝置
18s:第二晶片供給裝置
20:檢查裝置
22:接合台
22f:第一接合台
22s:第二接合台
24:晶片供給源
26:載入埠
28:搬運機器人
30:預對準器
30a:旋轉桌
30b:照相機
32:待機台
32f:第一待機台
32s:第二待機台
34:臂
34a:基本臂
34b:中間臂
36:保持手
36a:吸附孔
36f:第一保持手
36s:第二保持手
38、38f、38s:接合頭
100:基板晶圓
102:半導體晶片
102f:第一半導體晶片
102s:第二半導體晶片
104:金屬凸塊
106:接著層
E:區域
tb1、tb2:接合處理時間
td:時間差
tc:更換時間
tw:待機時間
tt:檢查時間設
T1:低溫
T2:高溫
圖1是封裝裝置的概略平面圖。
圖2是表示晶圓搬運裝置的結構的概略剖面圖。
圖3是搬運機器人的概略立體圖。
圖4是表示封裝裝置的另一佈局例的圖。
圖5是表示封裝裝置的運作時序的一例的圖。
圖6是表示封裝裝置的運作時序的一例的圖。
圖7是表示封裝裝置的運作時序的一例的圖。
圖8是表示封裝裝置的運作時序的一例的圖。
圖9是表示封裝裝置的另一佈局例的圖。
圖10是表示封裝裝置的運作時序的一例的圖。
圖11是表示封裝裝置的運作時序的一例的圖。
圖12是表示封裝裝置的運作時序的一例的圖。
圖13是表示第一接合站中的接合狀況的圖。
圖14是表示第二接合站中的接合狀況的圖。
圖15是表示第一接合站中的接合狀況的圖。
圖16是表示第二接合站中的接合狀況的圖。
圖17是表示封裝裝置的運作時序的一例的圖。
圖18是表示封裝裝置的運作時序的一例的圖。
圖19是表示封裝裝置的運作時序的一例的圖。
圖20是另一例的搬運機器人的概略立體圖。
圖21是表示封裝裝置的運作時序的一例的圖。
以下，參照圖示說明封裝裝置10的結構。圖1是封裝裝置10的概略平面圖。另外，圖2是表示晶圓搬運裝置12的結構的概略剖面圖，圖3是搬運機器人28的概略立體圖。
所述封裝裝置10製造將半導體晶片102封裝於基板晶圓100的半導體裝置、所謂的「COW」(晶圓上晶片(Chip On Wafer))方式的半導體裝置。
封裝裝置10包括一個晶圓搬運裝置12、第一接合站14f及第二接合站14s。再者，於以下的說明中，於不區別第一、第二的情況下，省略標注f、s，簡稱為「接合站14」。其他要素亦相同。第一接合站14f、第二接合站14s彼此具有相同的結構。另外，晶圓搬運裝置12與兩個接合站14f、接合站14s彼此協作而形成一個腔室。因此，晶圓搬運裝置12可於不使基板晶圓100露出至所述腔室的外部的情況下自一個接合站14搬運至其他接合站14。
各接合站14包括接合裝置16、以及晶片供給裝置18，所述晶片供給裝置18於X方向與所述接合裝置16相鄰配置。接合裝置16是將半導體晶片102接合至基板晶圓100的裝置，且具有載置有基板晶圓100的接合台22。於所述接合台22的上方設置 有吸附並搬運半導體晶片102的接合頭(圖1中未圖示)。接合頭38藉由將吸附保持的半導體晶片102按壓至基板晶圓100表面且進行加熱，而電氣及機械地固定於基板晶圓100上。
晶片供給裝置18是向接合裝置16供給半導體晶片102的裝置，且具有晶片供給源24。晶片選擇器(picker)(未圖示)拾取位於晶片供給源24中的半導體晶片102並進行搬運，供給至接合頭38。作為所述晶片供給裝置18的結構，可利用公知的現有技術，因此此處省略詳細說明。
晶圓搬運裝置12是向兩個接合站14兩者供給基板晶圓100且自兩個接合站14回收處理後的基板晶圓100的裝置。於本例中，晶圓搬運裝置12設置於兩個接合站14之間。更具體而言，第一晶片供給裝置18f、第一接合裝置16f、晶圓搬運裝置12、第二接合裝置16s及第二晶片供給裝置18s按照該順序於X方向排成一行配置。就另一個角度而言，兩個接合站14以晶圓搬運裝置12為中心對稱配置或者鏡像配置。另外，兩個接合站14各自的接合裝置16與晶圓搬運裝置12相鄰配置，多個接合站14各自的晶片供給裝置18隔著接合裝置16而配置於晶圓搬運裝置12的相反側。
晶圓搬運裝置12是搬運基板晶圓100的裝置，但要求基板晶圓100的上表面保持正常且不能接觸。因此，於晶圓搬運裝置12中設置有吸附保持基板晶圓100的底面且進行搬運的搬運機器人28。如圖3所示，所述搬運機器人28是具有多個臂34的 多關節機器人。所述多關節機器人的結構並無特別限定，於本例中，搬運機器人28包括：於Z軸方向可伸縮的基本臂34a、於水平面內可旋轉的多個中間臂34b、以及設置於多關節機器人的前端的保持手36。於保持手36的表面形成有多個用以吸附保持基板晶圓100的吸附孔36a。所述搬運機器人28具有可接近第一接合台22f及第二接合台22s兩者的程度的可移動範圍。
於晶圓搬運裝置12的前端部分設置有用以搬入、搬出基板晶圓100的載入埠26。於本例中，設置兩個所述載入埠26，但載入埠26的個數可為一個，亦可為三個以上。另外，多個載入埠26亦可分為處理前的基板晶圓100待機的搬入用埠、以及實施了封裝處理的處理後的基板晶圓100待機的搬出用埠。另外，多個載入埠26亦可分為收容在第一接合站14f中處理的基板晶圓100的埠、以及收容在第二接合站14s中處理的基板晶圓100的埠。
進而，於晶圓搬運裝置12中亦設置有修正基板晶圓100的旋轉角度的預對準器30。即，於基板晶圓100中通常設置有被稱為定向平面的直線部或凹口作為用以規定所述基板晶圓100的旋轉角度的標記。於向接合台22供給基板晶圓100並載置時，必須以所述基板晶圓100的標記成為預先規定的朝向(旋轉角度)的方式載置。因此，設置有預對準器30，所述預對準器30於將基板晶圓100供給至接合台22之前，確認所述基板晶圓100的旋轉角度並進行修正。預對準器30例如具有載置有基板晶圓100的旋轉桌30a、以及拍攝基板晶圓100的照相機30b。
於預對準器30的下側設置有第一待機台32f、第二待機台32s。所述待機台32是載置有進行了接合處理的基板晶圓100的台。所述待機台32例如用於在接合處理後使高溫狀態的基板晶圓100冷卻。
於以上的結構的封裝裝置10中，使用單個搬運機器人28及預對準器30，進行於多個接合站14中處理的基板晶圓100的供給、回收、或旋轉角度的修正。換言之，於本例中，於多個接合站14中共用單個晶圓搬運裝置12。藉由設為所述結構，可更有效率地製造COW方式的半導體裝置。
即，先前的封裝裝置10大多相對於一個接合站14設置一個晶圓搬運裝置12。因此，為了提高製造能力，於設置兩個接合站14的情況下，亦設置兩個晶圓搬運裝置12。然而，通常大多是將多個半導體晶片102接合至一個基板晶圓100，由接合裝置16執行的接合處理時間與基板晶圓100的搬運或旋轉角度修正所需要的時間相比，大幅度地變長。因此，晶圓搬運裝置12與接合裝置16相比，未驅動的待機時間多，浪費多。另一方面，如上所述，晶圓搬運裝置12具有搬運機器人28等。因此，於設置多個晶圓搬運裝置12的情況下，空間上及成本上的負擔大。
因此，於本例中，構成為設置多個接合站14，且於所述多個接合站14中共用單個晶圓搬運裝置12。藉由設置多個接合站14，可提高半導體裝置的生產能力。另一方面，晶圓搬運裝置12僅一個便足夠，因此可抑制晶圓搬運裝置12所花費的費用、空間 的增加。
另外，如上所述，於本例中，以晶圓搬運裝置12為中心，鏡像配置兩個接合站14。藉由設為所述配置，可減少死空間。即，兩個接合站14的配置態樣不限於如圖1所示的鏡像配置，亦考慮其他配置。例如，亦考慮設為如圖4所示，自晶圓搬運裝置12觀察時，第一接合站14f位於X方向、第二接合站14s位於Y方向的L字狀配置。然而，於所述配置的情況下，由L字包圍的區域E容易成為死空間，工廠內的佈局容易變得困難。另一方面，若設為如圖1所示的鏡像配置(或一行配置)，則難以產生死空間，工廠內的佈局變得容易。其中，當然，若不產生空間上的問題，則亦可設為如圖4所示的L字狀配置。另外，即使為任意配置，多個接合站14各自的接合裝置16亦理想的是與晶圓搬運裝置12相鄰配置。藉由設為所述配置，搬運機器人28可在不橫貫晶片供給裝置18的情況下到達接合裝置16。其結果，由於不需要增大搬運機器人28的可移動範圍，因此可防止搬運機器人28的大型化。另外，由於搬運機器人28不橫貫晶片供給裝置18，因此亦可有效地抑制搬運機器人28與其他構件的干涉。
其次，對所述封裝裝置10中的封裝處理的流程進行說明。圖5至圖8是表示搬運機器人28的運作時序與基板晶圓100的滯留部位的時序圖。圖5至圖8中，第一段表示搬運機器人28搬運基板晶圓100的時序。另外，第二段以後表示基板晶圓100的滯留部位。更具體而言，於在第一接合站14f中被處理的基板 晶圓100中，第奇數片的基板晶圓100(以下稱為「第一奇數晶圓W1O」)表示為淡墨的帶，第偶數片的基板晶圓100(以下稱為「第一偶數晶圓W1E」)表示為濃墨的帶。另外，於在第二接合站14s中被處理的基板晶圓100中，第奇數片的基板晶圓100(以下稱為「第二奇數晶圓W2O」)表示為傾斜陰影線的帶，第偶數片的基板晶圓100(以下稱為「第二偶數晶圓W2E」)表示為交叉陰影線的帶。
圖5是最基本的時序圖。如圖5所示，搬運機器人28最初將第一奇數晶圓W1O(淡墨)自晶圓搬運裝置12搬運至第一接合站14f(t1)。於第一接合站14f中，對所述第一奇數晶圓W1O執行接合處理。如圖5所示，所述接合處理所需要的時間與搬運所需要的時間相比，大幅度地變長。因此，搬運機器人28於對第一奇數晶圓W1O執行接合處理的期間中，將第二奇數晶圓W2O(傾斜陰影線)自晶圓搬運裝置12搬運至第二接合站14s(t2)。
若第一接合站14f中的接合裝置16結束(t3)，則搬運機器人28於將第一奇數晶圓W1O回收至晶圓搬運裝置12之後，將第一偶數晶圓W1E(濃墨)搬運至第一接合站14f。於第一接合站14f中，對所述第一偶數晶圓W1E執行接合處理。於對第一偶數晶圓W1E執行接合處理的期間中，第二奇數晶圓W2O的接合處理結束(t4)。若為所述狀態，則搬運機器人28於將第二奇數晶圓W2O回收至晶圓搬運裝置12之後，將第二偶數晶圓W2E(交叉陰影線)搬運至第二接合站14s。以後，重覆相同的處理。
如上所述，於在一個接合站14中執行接合處理的期間中，向其他接合站14供給或回收基板晶圓100。藉由設為所述結構，於第一接合站14f、第二接合站14s中，基板晶圓100的供給、回收的時序錯開，因此可於多個接合站14中共用單個晶圓搬運裝置12。再者，當然，預先使兩個接合站14f、接合站14s中的基板晶圓100的搬運時序錯開，以便於第一接合站14f與第二接合站14s中基板晶圓100的交換時序不重覆。具體而言，於將第一接合站14f、第二接合站14s各自中的接合處理時間設為tb1、tb2，將基板晶圓100的交換所需要的時間設為tc，且將兩個接合站14f、接合站14s中的基板晶圓100的搬運時序的時間差設為td的情況下，需要滿足tb1+tc<tb2+td的條件。因此，於第一接合站14f、第二接合站14s中製造相同種類的半導體裝置，於tb1=tb2的情況下，只要使時間差td比基板晶圓100的交換時間tc大(即tc<td)即可。
其次，參照圖6說明更具體的運作時序。於圖6的例子中，各基板晶圓100被收容於載入埠26中，自所述載入埠26經由預對準器30被供給至接合站14。若具體說明，則搬運機器人28將第一奇數晶圓W1O(淡墨)自載入埠26搬運至預對準器30(t1)。於預對準器30中，確認第一奇數晶圓W1O的旋轉角度，視需要進行修正。若旋轉角度的修正結束，則搬運機器人28將第一奇數晶圓W1O自預對準器30供給至第一接合站14f(t2)。於第一接合站14f中，對所述第一奇數晶圓W1O執行接合處理。
若對第一奇數晶圓W1O的接合處理開始，則搬運機器人28將第二奇數晶圓W2O(傾斜陰影線)自載入埠26搬運至預對準器30(t3)。然後，若於預對準器30中結束旋轉角度的修正，則搬運機器人28將第二奇數晶圓W2O自預對準器30供給至第二接合站14s(t4)。
若第一奇數晶圓W1O的接合處理結束，則搬運機器人28於將第一奇數晶圓W1O自第一接合站14f回收至載入埠26之後，將第一偶數晶圓W1E(濃墨)自載入埠26搬運至預對準器30(t5)。然後，若預對準器30中的處理結束，則將所述第一偶數晶圓W1E自預對準器30供給至第一接合站14f(t6)。
同樣地，若第二奇數晶圓W2O的接合處理結束，則搬運機器人28於將第二奇數晶圓W2O自第二接合站14s回收至載入埠26之後，將第二偶數晶圓W2E(交叉陰影線)自載入埠26搬運至預對準器30(t7)。然後，若預對準器30中的處理結束，則將所述第二偶數晶圓W2E自預對準器30供給至第二接合站14s(t8)。以後，重覆相同的處理。
如上所述，於圖6的例子中，亦於在一個接合站14中執行接合處理的期間中，進行於其他接合站14中處理的基板晶圓100的搬運及旋轉角度修正。藉由設為所述結構，可於多個接合站14中共用單個搬運機器人28及預對準器30。
其次，參照圖7、圖8說明處理後的基板晶圓100為高溫時的運作時序。於將半導體晶片102接合至基板晶圓100時， 存在半導體晶片102及基板晶圓100於高溫下受到加熱的情況。因此，接合處理剛結束後的基板晶圓100為高溫，因此存在無法直接收容於載入埠26中的情況。該情況下，處理後的基板晶圓100於在待機台32被臨時保管並冷卻之後，被搬運至載入埠26。圖7、圖8表示該情況下的運作時序的一例。
首先，說明圖7的例子。於圖7的例子中，於使在第一接合站14f中處理的基板晶圓100在第一待機台32f待機的期間中，進行第二接合站14s中的基板晶圓100的更換。具體而言，搬運機器人28首先將第一奇數晶圓W1O(淡墨)經由預對準器30搬運至第一接合站14f(t1，t2)。進而，搬運機器人28於對第一奇數晶圓W1O進行接合的期間中，將第二奇數晶圓W2O(傾斜陰影線)經由預對準器30搬運至第二接合站14s(t3，t4)。
若第一奇數晶圓W1O的接合處理結束，則搬運機器人28將第一奇數晶圓W1O搬運至第一待機台32f，而並非搬運至載入埠26(t5)。若所述搬運結束，則搬運機器人28接下來將第一偶數晶圓W1E(濃墨)經由預對準器30搬運至第一接合站14f(t6)。進而，於本例中，於第一奇數晶圓W1O的待機期間中，第二奇數晶圓W2O的接合處理結束(t7)。因此，於本例中，於第一奇數晶圓W1O的待機期間中，進行第一接合站14f中的基板晶圓100的交換(t7，t8)。
之後，於第一偶數晶圓W1E及第二偶數晶圓W2E的接合處理的執行過程中，經過第一奇數晶圓W1O及第二奇數晶圓 W2O的待機時間，兩個晶圓被充分地冷卻。若為所述狀態，則搬運機器人28自各待機台32回收基板晶圓100，並將其搬運至載入埠26(t9，t10)。以後，重覆相同的順序。
如上所述，於圖7的例子中，亦可於多個接合站14中共用單個搬運機器人28及預對準器30。再者，於在第一待機台32f中使基板晶圓100待機的期間中，為了進行第二接合站14s中的基板晶圓100的交換，當然，於將第一接合站14f、第二接合站14s各自中的接合處理時間設為tb1、tb2，將兩個接合站14f、接合站14s中的基板晶圓100的搬運時序的時間差設為td，且將第一待機台32f中的基板晶圓100的待機時間設為tw的情況下，必須為tb1+tw>td+tb2，於tb1=tb2的情況下，必須為待機時間比時間差大(即tw>td)。換言之，於在其中一個接合站14中處理的基板晶圓100的待機期間中，藉由在另一個接合站14中進行基板晶圓100的交換，可縮短兩個接合站14f、接合站14s中的基板晶圓100的搬運時序的時間差td，可縮短整體的處理時間。
其次，參照圖8說明使於其中一個接合台22中被處理的基板晶圓100的待機與另一個接合台22中的基板晶圓100的交換不重覆的例子。於圖8的例子中，亦與圖7同樣地，若對第一奇數晶圓W1O的接合處理結束，則搬運機器人28於將第一奇數晶圓W1O自第一接合站14f搬運至第一待機台32f之後，將第二偶數晶圓W2E搬運至第一接合站14f(t5，t6)。於圖8的例子中，於第二奇數晶圓W2O的接合處理結束之前，第一奇數晶圓W1O 的待機時間到期(t7)。因此，搬運機器人28於第二接合站14s中的基板晶圓100的交換(t8，t9)之前，將第一奇數晶圓W1O自第一待機台32f搬運至載入埠26。之後，若第二偶數晶圓W2E的接合處理結束，則於將第二奇數晶圓W2O搬運至第二待機台32s之後，將第二偶數晶圓W2E搬運至第二接合站14s(t8，t9)。
如上所述，於圖8的例子中，亦可於多個接合站14中共用單個搬運機器人28及預對準器30。另外，根據圖8的例子，第一待機台32f中的待機時間與第二待機台32s中的待機時間不重覆。因此，根據所述結構，不需要設置兩個待機台32，可於兩個接合站14f、接合站14s中共用一個待機台32。再者，該情況下，需要滿足tb1+tw<td+tb2，若為tb1=tb2，則需要滿足tw<td。
其次，對其他例子進行說明。圖9是表示封裝裝置10的其他配置例的影像圖。於圖9的例子中，與圖1的例子相同，兩個接合站14f、接合站14s隔著一個晶圓搬運裝置12而被鏡像配置。於圖9的例子中，進而於晶圓搬運裝置12的Y方向(與兩個接合站14的排列方向正交的方向)裏側設置有檢查裝置20。所述檢查裝置20檢查進行了接合處理的處理後的基板晶圓100(即、半導體裝置)並判斷製品的好壞。所述檢查裝置20例如具有照相機或紅外線感測器等。所述檢查裝置20的結構可使用公知的現有技術，因此此處省略詳細說明。
與晶圓搬運裝置12同樣地，僅設置一個所述檢查裝置20，且可於多個接合站14中共用。藉由設為所述結構，可減少檢 查裝置20的設置所需要的空間、費用。再者，於圖9的例子中，將檢查裝置20配置於晶圓搬運裝置12的外側，但檢查裝置20亦可組裝於晶圓搬運裝置12的內部。
其次，參照圖10至圖12說明檢查處理後的基板晶圓100時的運作時序的例子。圖10表示最基本的運作時序。於圖10的例子中，於第一奇數晶圓W1O(淡墨)被搬運至第一接合站14f之後(t1)，於經過時間差td之後，第二奇數晶圓W2O(傾斜陰影線)被搬運至第二接合站14s(t2)。之後，於第一奇數晶圓W1O的接合處理結束時，搬運機器人28於將第一奇數晶圓W1O搬運至檢查裝置20之後，將第一偶數晶圓W1E(濃墨)搬運至第一接合站14f(t3)。然後，若第一奇數晶圓W1O的檢查結束，則搬運機器人28將第一奇數晶圓W1O搬運至晶圓搬運裝置12的載入埠26(t4)。於第一奇數晶圓W1O的檢查結束之後，第二奇數晶圓W2O的接合處理結束(t5)。若為所述狀態，則搬運機器人28於將第二奇數晶圓W2O搬運至檢查裝置20之後，將第二偶數晶圓W2E搬運至第二接合站14s。以後，重覆相同的順序。
根據以上的說明可明確，於所述例子中，除了晶圓搬運裝置12以外，檢查裝置20亦可於多個接合站14中共用。其結果，可減少檢查裝置20的設置所需要的空間、費用。再者，為了於兩個接合站14中共用一個檢查裝置20，需要使於第一接合站14f中處理的基板晶圓100的檢查期間與第二接合站14s中處理的基板晶圓100的檢查期間不重覆。為此，於將檢查時間設為tt的情況 下，需要滿足tb1+tt<td+tb2，於tb1=tb2的情況下，需要設置比檢查時間tt大的時間差td(即，td>tt)。
圖11是表示更詳細的運作時序的例子的圖。於圖11的例子中，藉由接合處理而獲得的處理後的基板晶圓100於在待機台32中待機一次之後，經由預對準器30被發送至檢查裝置20(t5~t7，t8~t10)。該情況下，可知於將待機及預對準(prealign)所需要的時間設為tw的情況下，需要滿足tb1+tw+tt<td+tb2+tw，於tb1=tb2的情況下，只要滿足tt<td即可。另外，於圖11的例子中，為了縮小時間差td，於在第一接合站14f中處理的基板晶圓100的檢查時間中，進行第二接合站14s中的基板晶圓100的交換。於設為所述結構的情況下，只要設為tb1+tw+tt>td+tb2即可，於tb1=tb2的情況下，可使時間差td小於tw+tt。其結果，可減少整體的處理時間。
圖12表示檢查處理後的基板晶圓100且使於其中一個接合台22中被處理的基板晶圓100的檢查與另一個接合台22中的基板晶圓100的交換不重覆的例子。具體而言，於圖12的例子中，以於第一奇數晶圓W1O(淡墨)的接合處理、待機、預對準、檢查(t5~t8)結束之後第二奇數晶圓W2O(傾斜陰影線)的接合處理結束(t9)的方式設定時間差td。具體而言，設為tb1+tw+tt<td+tb2(於tb1=tb2的情況下，tw+tt<td)。藉由設為所述結構，避免了檢查時間的重覆，因此可將待機台32的個數設為一個。
其次，參照圖13至圖19說明其他例子。於至今為止的 說明中，說明了對一個基板晶圓100的接合處理於一個接合站14中結束的情況。然而，根據半導體裝置的種類，存在有於兩個接合站14中進行串列處理更有效率的情況。例如，半導體裝置中有將彼此不同的兩種半導體晶片102積層而成者。於製造所述半導體晶片102時，若如圖13所示利用第一接合站14f的接合頭38f接合具有接著層106的第一半導體晶片102f，之後，如圖14所示利用第二接合站14s的接合頭38f於第一半導體晶片102f上接合第二半導體晶片102s，則效率良好。
另外，於接合半導體晶片102時，存在分開進行臨時壓接與正式壓接較佳的情況。臨時壓接是臨時放置半導體晶片102的步驟，通常於附著於半導體晶片102的底面的熱硬化性樹脂硬化但金屬凸塊104不熔融的程度的低溫T1下對半導體晶片102進行加熱加壓。另外，正式壓接是用於最終封裝經臨時壓接的半導體晶片102的步驟，通常於金屬凸塊104熔融的程度的高溫T2下對半導體晶片102進行加熱加壓。此處，於在一個接合站14中進行臨時壓接與正式壓接此兩者的情況下，需要切換接合頭38或接合台22的溫度，相應地，花費多餘的時間，而導致生產效率的惡化。因此，該情況下，若如圖15所示利用第一接合站14f的接合頭38f進行半導體晶片102的臨時壓接，之後，如圖16所示利用第二接合站14s的接合頭38s對經臨時壓接的半導體晶片102進行正式壓接，則效率良好。
此處，於本例的封裝裝置10中，兩個接合站14經由晶 圓搬運裝置12連結，兩個接合站14及晶圓搬運裝置12彼此協作而形成自外部隔絕的一個腔室。因此，於將基板晶圓100自第一接合站14f搬運至第二接合站14s時，不需要將所述基板晶圓100取出至腔室的外部。因此，於搬運基板晶圓100時，不需要將基板晶圓100收容於用於防止污染的搬運容器(例如前端開啟式晶圓傳送盒(Front Opening Unified Pod，FOUP))中，可容易地搬運。
圖17至圖19表示於兩個接合站14中對一個基板晶圓100進行串列處理時的運作時序。於圖17至圖19中，於封裝裝置10中處理的基板晶圓100中，淡墨、濃墨、傾斜陰影線、交叉陰影線的帶分別表示第一片、第二片、第三片、第四片基板晶圓100。
圖17表示最基本的運作時序。於圖17的例子中，首先，將第一片基板晶圓100自晶圓搬運裝置12搬運至第一接合站14f(t1)，執行對第一片基板晶圓100的接合處理。若對第一片基板晶圓100的接合處理結束，則搬運機器人28將第一片基板晶圓100自第一接合站14f搬運至第二接合站14s(t2)。
於所述時間點，第一接合站14f空閒，因此搬運機器人28將第二片基板晶圓100重新搬運至第一接合站14f。藉此，於第一接合站14f及第二接合站14s並行地執行接合處理。然後，若對第二接合站14s中的第一片基板晶圓100的接合處理結束，則搬運機器人28將所述第一片基板晶圓100搬運至晶圓搬運裝置12(t3)。藉此，可獲得對一個基板晶圓100實施了利用第一接合站 進行的接合處理及利用第二接合站14s進行的接合處理的處理後的基板晶圓100(半導體裝置)。
若第二接合站14s空閒，則搬運機器人28將位於第一接合站14f的第二片基板晶圓100搬運至第二接合站14s。而且，以後重覆相同的處理。
根據以上的說明可明確，藉由設為自第一接合站14f向第二接合站14s搬運基板晶圓100的結構，可有效率地對一個基板晶圓100進行不同的兩種接合處理。
其次，參考圖18說明運作時序的更具體的例子。圖18的例子是如參照圖15、圖16所說明般於第一接合站14f對一片基板晶圓100進行臨時壓接處理且於第二接合站14s進行正式壓接處理時的運作時序的一例。於臨時壓接處理中，由於在一個地方積層多個半導體晶片102，因此臨時壓接處理所需要的時間與正式壓接處理所需要的時間相比變長。另外，於臨時壓接中，於較低的溫度下加熱半導體晶片102，因此不需要處理後的冷卻(待機)，另一方面，於正式壓接中，於高溫下加熱半導體晶片102，因此於處理後需要冷卻(待機)。另外，每當臨時壓接及正式壓接結束時，利用檢查裝置20進行檢查，但於進行所述檢查時，基板晶圓100由預對準器30進行角度修正。
若具體說明，則第一片基板晶圓100(淡墨)經由預對準器30被搬運至第一接合站14f(t1，t2)。於第一接合站14f中，對基板晶圓100實施臨時壓接處理。若所述臨時壓接處理結束， 則搬運機器人28將臨時壓接處理後的基板晶圓100經由預對準器30搬運至檢查裝置20(t3，t4)。另外，若為所述狀態，則由於第一接合站14f空閒，因此搬運機器人28向所述第一接合站14f搬運第二片基板晶圓100(濃墨)(t4，t5)。
若對第一片基板晶圓100的檢查結束，則搬運機器人28將所述第一片基板晶圓100經由預對準器30搬運至第二接合站14s(t6，t7)。於第二接合站14s中，對第一片基板晶圓100實施正式壓接處理。若所述正式壓接處理結束，則再次利用檢查裝置20進行檢查，但正式壓接處理後的基板晶圓100由於為高溫，因此事先被搬運至待機台32並進行冷卻(t11)。若可充分地冷卻，則第一片基板晶圓100經由預對準器30被搬運至檢查裝置20(t13，t14)。然後，若所述檢查結束，則將第一片基板晶圓100輸出至載入埠26(t15)。第二片基板晶圓100亦以與第一片基板晶圓100相同的順序實施處理。另外，第三片以後的基板晶圓100亦同樣地依次被追加。
此處，雖然存在一些時間差，但第一片基板晶圓100(淡墨)的第一次檢查(t4~)與第二片基板晶圓100(濃墨)的臨時壓接處理(t5~)大致同時開始。而且，為了避免第二片基板晶圓100的第一次檢查(t9~)與第一片基板晶圓100的第二次檢查(t14~)的重覆，於將臨時壓接處理時間設為tb1，將正式壓接處理時間設為tb2，將檢查時間設為tt，且將待機時間設為tw的情況下，只要設為tb1+tt<tt+tb2+tw、即tb1<tb2+tw即可。
根據以上的說明可明確，根據圖18的例子，可有效率地執行對一個基板晶圓100串列實施臨時壓接處理與正式壓接處理的步驟。另外，若tb2<tb1<tb2+tw，則於臨時壓接處理及正式壓接處理之後可利用一個檢查裝置20檢查基板晶圓100。
其次，參照圖19說明運作時序的另一例。圖19的例子是如參照圖13、圖14所說明般於第一接合站14f將第一半導體晶片102f接合至一片基板晶圓100且於第二接合站14s將第二半導體晶片102s接合至一片基板晶圓100時的運作時序的一例。該情況下，由於第一接合站14f、第二接合站14s均於高溫下加熱半導體晶片102，因此每當於第一接合站14f、第二接合站14s中的接合處理結束時，需要使基板晶圓100在待機台32冷卻。
若具體說明，則第一片基板晶圓100(淡墨)經由預對準器30被搬運至第一接合站14f(t1，t2)。於第一接合站14f中，將第一半導體晶片102f接合至基板晶圓100。若所述接合處理結束，則搬運機器人28將第一片基板晶圓100搬運至待機台32並使其冷卻(t3)。若為所述狀態，則由於第一接合站14f空閒，因此搬運機器人28將第二片基板晶圓100(濃墨)搬運至所述第一接合站14f(t3，t4)。若第一片基板晶圓100可充分地冷卻，則搬運機器人28將第一片基板晶圓100經由預對準器30搬運至檢查裝置20(t5，t6)。
若對第一片基板晶圓100的檢查結束，則搬運機器人28將所述第一片基板晶圓100經由預對準器30搬運至第二接合站 14s(t7，t8)。於第二接合站14s中，將第二半導體晶片102s接合至第一片基板晶圓100。若所述接合處理結束，則第一片基板晶圓100經由待機台32、預對準器30被搬運至檢查裝置20(t13~t16)。然後，若第二次檢查結束，則第一片基板晶圓100被輸出至載入埠26(t17)。第二片基板晶圓100亦以與第一片基板晶圓100相同的順序實施處理。另外，第三片以後的基板晶圓100亦同樣地依次被追加。
根據以上的說明可明確，根據所述圖19的例子，可有效率地執行對一個基板晶圓100串列接合第一半導體晶片102f與第二半導體晶片102s的步驟。
其次，參照圖20、圖21說明其他例子。於至今為止的說明中，一個搬運機器人28僅具有一個吸附保持基板晶圓100的保持手36。該情況下，為了於自一個接合站14回收基板晶圓100之後供給新的基板晶圓100，搬運機器人28需要於載入埠26與接合站14之間往返兩次。因此，為了減少所述往返次數，如圖20所示，亦可於一個搬運機器人28中設置兩個保持手36。藉由設為所述結構，搬運機器人28於自一個接合站14回收基板晶圓100之後，於不移動的情況下立即向所述接合站14供給新的基板晶圓100。其結果，可藉由一次往返動作實現基板晶圓100的回收與供給，可進一步縮短處理時間。
圖21是表示該情況下的運作時序的一例的圖。圖21的例子中，彼此獨立地驅動第一接合站14f與第二接合站14s，且於 兩個接合站14之間不存在基板往來。但是，圖20所示的具有兩個保持手36的搬運機器人28亦可於在第一接合站14f、第二接合站14s中對一個基板晶圓100串列處理的情況下利用。
圖21的例子中，首先，第一奇數晶圓W1O經由預對準器30被搬運至第一接合站14f(t1，t2)。另外，於對所述第一奇數晶圓W1O的接合處理的執行期間中，第二奇數晶圓W2O經由預對準器30被搬運至第二接合站14s(t3，t4)。
若第一接合站14f中的接合處理結束，則進行第一奇數晶圓W1O與第一偶數晶圓W1E的更換。為了進行所述更換，於接合處理結束前，第一偶數晶圓W1E由搬運機器人28搬運至預對準器30，並修正其旋轉角度(t5)。之後，搬運機器人28於第一保持手36f吸附第一偶數晶圓W1E的狀態下移動至第一接合站14f。然後，於第一接合站14f中，搬運機器人28於利用第二保持手36s吸附並回收第一奇數晶圓W1O之後，將第一偶數晶圓W1E載置於第一接合站14f(t6)。然後，搬運機器人28於吸附第一奇數晶圓W1O的狀態下向載入埠26移動，將第一奇數晶圓W1O輸出至載入埠26。以後，於第一接合站14f、第二接合站14s各自中重覆相同的處理。
根據以上的說明可明確，根據本例，由於在一個搬運機器人28中設置兩個保持手36，因此可藉由一次往返動作來實現基板晶圓100的回收與供給，可進一步縮短處理時間。
再者，至今為止說明的結構為一例，若為於多個接合站 14中共用至少一個晶圓搬運裝置12，則其他結構亦可適宜變更。
10:封裝裝置
12:晶圓搬運裝置
14f:第一接合站
14s:第二接合站
16f:第一接合裝置
16s:第二接合裝置
18f:第一晶片供給裝置
18s:第二晶片供給裝置
22f:第一接合台
22s:第二接合台
24:晶片供給源24
26:載入埠
28:搬運機器人
30:預對準器
32:待機台
100:基板晶圓

Claims (9)

  1. 一種封裝裝置，其特徵在於包括多個接合站、以及單個晶圓搬運裝置，所述多個接合站分別具有將半導體晶片接合至基板晶圓的接合裝置、以及向所述接合裝置供給半導體晶片的晶片供給裝置，所述單個晶圓搬運裝置為了對所述多個接合站各自供給所述基板晶圓並自所述多個接合站各自回收所述基板晶圓，而搬運所述基板晶圓，其中所述多個接合站各自的所述接合裝置與所述晶圓搬運裝置相鄰配置，所述多個接合站各自的所述晶片供給裝置隔著所述接合裝置而配置於所述晶圓搬運裝置的相反側。
  2. 如請求項1所述的封裝裝置，其中所述晶圓搬運裝置及所述多個接合站彼此協作而形成一個腔室，所述晶圓搬運裝置可於不使所述基板晶圓露出至所述腔室的外部的情況下自一個接合站搬運至其他接合站。
  3. 如請求項1所述的封裝裝置，其中所述多個接合站包括第一接合站以及第二接合站，所述第二接合站隔著所述晶圓搬運裝置而配置於第一接合站的相反側，所述第一接合站、所述晶圓搬運裝置及所述第二接合站排成一行配置。
  4. 如請求項1所述的封裝裝置，進而包括對處理後的所述基板晶圓進行檢查的單個檢查裝置，所述多個接合站共用所述單個檢查裝置。
  5. 如請求項1所述的封裝裝置，其中所述晶圓搬運裝置包括搬運所述基板晶圓的單個搬運機器人、以及修正所述基板晶圓的旋轉角度的單個預對準器，於多個接合站中共用單個所述搬運機器人及單個所述預對準器。
  6. 如請求項1所述的封裝裝置，其中所述晶圓搬運裝置具有可同時保持兩個所述基板晶圓的搬運機器人，所述搬運機器人於在一個接合站中回收處理後的基板晶圓後，可於不移動的情況下立即供給新的基板晶圓。
  7. 如請求項1所述的封裝裝置，其中所述多個接合站包含第一接合站以及第二接合站，所述晶圓搬運裝置將自所述第一接合站回收的處理後的所述基板晶圓供給至所述第二接合站。
  8. 如請求項7所述的封裝裝置，其中於所述第一接合站中，執行將所述半導體晶片臨時壓接於所述基板晶圓的臨時壓接處理，於所述第二接合站中，執行對所述臨時壓接的半導體晶片進行正式壓接的正式壓接處理。
  9. 如請求項7所述的封裝裝置，其中於所述第一接合站中，執行將第一半導體晶片接合至所述基板晶圓的處理，於所述第二接合站中，執行於所述第一半導體晶片上接合與所述第一半導體晶片不同的第二半導體晶片的處理。
TW109122946A 2019-07-26 2020-07-08 封裝裝置 TWI797461B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019137696 2019-07-26
JP2019-137696 2019-07-26

Publications (2)

Publication Number Publication Date
TW202109715A TW202109715A (zh) 2021-03-01
TWI797461B true TWI797461B (zh) 2023-04-01

Family

ID=74229835

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109122946A TWI797461B (zh) 2019-07-26 2020-07-08 封裝裝置

Country Status (7)

Country Link
US (1) US20220320034A1 (zh)
JP (1) JP7165445B2 (zh)
KR (1) KR102642166B1 (zh)
CN (1) CN113632212A (zh)
SG (1) SG11202110483XA (zh)
TW (1) TWI797461B (zh)
WO (1) WO2021020124A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013161891A1 (ja) * 2012-04-24 2013-10-31 ボンドテック株式会社 チップオンウエハ接合方法及び接合装置並びにチップとウエハとを含む構造体
WO2018075262A1 (en) * 2016-10-18 2018-04-26 Mattson Technology, Inc. Systems and methods for workpiece processing
WO2019028254A1 (en) * 2017-08-03 2019-02-07 Applied Materials Israel Ltd. METHOD AND SYSTEM FOR MOVING A SUBSTRATE

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003203963A (ja) * 2002-01-08 2003-07-18 Tokyo Electron Ltd 搬送機構、処理システム及び搬送方法
US9226407B2 (en) * 2002-07-01 2015-12-29 Semigear Inc Reflow treating unit and substrate treating apparatus
US10086511B2 (en) * 2003-11-10 2018-10-02 Brooks Automation, Inc. Semiconductor manufacturing systems
KR100583727B1 (ko) * 2004-01-07 2006-05-25 삼성전자주식회사 기판 제조 장치 및 이에 사용되는 기판 이송 모듈
JP5120017B2 (ja) * 2007-05-15 2013-01-16 東京エレクトロン株式会社 プローブ装置
US8334170B2 (en) * 2008-06-27 2012-12-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for stacking devices
CN102598897B (zh) * 2010-09-10 2017-02-15 松下知识产权经营株式会社 基板衬垫装置以及基板的热压接装置
JP5478565B2 (ja) * 2011-07-15 2014-04-23 東京エレクトロン株式会社 接合システム
JP5815345B2 (ja) * 2011-09-16 2015-11-17 ファスフォードテクノロジ株式会社 ダイボンダ及びボンディング方法
WO2013088733A1 (ja) * 2011-12-14 2013-06-20 株式会社ニコン 基板ホルダ及び一対の基板ホルダ
JP2015525468A (ja) * 2012-05-30 2015-09-03 エーファウ・グループ・エー・タルナー・ゲーエムベーハー 基板同士をボンディングする装置および方法
CN104823272B (zh) * 2012-11-30 2017-07-14 应用材料公司 具有非等长前臂的多轴机械手设备、电子装置制造系统、及用于在电子装置制造中传送基板的方法
JP6703937B2 (ja) * 2013-03-15 2020-06-03 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ 基板堆積システム、ロボット移送装置、及び電子デバイス製造のための方法
JP6190645B2 (ja) * 2013-07-09 2017-08-30 東京エレクトロン株式会社 基板搬送方法
JP6046007B2 (ja) * 2013-08-29 2016-12-14 東京エレクトロン株式会社 接合システム
US9724834B2 (en) * 2014-01-05 2017-08-08 Applied Materials, Inc. Robot apparatus, drive assemblies, and methods for transporting substrates in electronic device manufacturing
US10381257B2 (en) * 2015-08-31 2019-08-13 Kawasaki Jukogyo Kabushiki Kaisha Substrate conveying robot and substrate processing system with pair of blade members arranged in position out of vertical direction
US10910248B2 (en) * 2016-01-06 2021-02-02 Shinkawa Ltd. Electronic component mounting apparatus
JP6670713B2 (ja) * 2016-09-20 2020-03-25 東京エレクトロン株式会社 基板処理装置及び基板搬送方法
TWI668789B (zh) 2017-02-03 2019-08-11 日商新川股份有限公司 接合裝置
KR102000079B1 (ko) * 2017-07-19 2019-07-18 세메스 주식회사 다이 본딩 장치
KR102047035B1 (ko) * 2017-09-25 2019-11-20 세메스 주식회사 다이 본딩 장치
JP7129793B2 (ja) * 2018-03-06 2022-09-02 シャープ株式会社 接合装置
KR102630226B1 (ko) * 2021-09-23 2024-01-29 한화정밀기계 주식회사 하이브리드 본딩 장치 및 이를 이용하는 하이브리드 본딩 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013161891A1 (ja) * 2012-04-24 2013-10-31 ボンドテック株式会社 チップオンウエハ接合方法及び接合装置並びにチップとウエハとを含む構造体
WO2018075262A1 (en) * 2016-10-18 2018-04-26 Mattson Technology, Inc. Systems and methods for workpiece processing
WO2019028254A1 (en) * 2017-08-03 2019-02-07 Applied Materials Israel Ltd. METHOD AND SYSTEM FOR MOVING A SUBSTRATE

Also Published As

Publication number Publication date
SG11202110483XA (en) 2021-10-28
JP7165445B2 (ja) 2022-11-04
KR102642166B1 (ko) 2024-03-04
TW202109715A (zh) 2021-03-01
CN113632212A (zh) 2021-11-09
KR20210138070A (ko) 2021-11-18
JPWO2021020124A1 (ja) 2021-11-11
WO2021020124A1 (ja) 2021-02-04
US20220320034A1 (en) 2022-10-06

Similar Documents

Publication Publication Date Title
US7568606B2 (en) Electronic device handler for a bonding apparatus
TWI541967B (zh) Cutting device and cutting method
JP2009130269A (ja) 半導体製造装置および半導体装置の製造方法
US7677431B2 (en) Electronic device handler for a bonding apparatus
CN212694244U (zh) 涂敷、显影装置
WO2008097012A1 (en) Vision system of sawing and placement equipment
TWI797461B (zh) 封裝裝置
TWI246736B (en) Intermediate product manufacturing apparatus, and intermediate product manufacturing method
KR101460626B1 (ko) 반도체 자재 공급장치
JP2011181936A (ja) 半導体装置の製造方法
US20170025378A1 (en) Method of bonding a bump of a semiconductor package and apparatus for performing the same
JP3621908B2 (ja) ベアチップ実装方法および実装システム
KR20210102460A (ko) 반도체 소자를 기판에 본딩하는 방법 및 관련된 본딩 시스템
JP2001250834A (ja) 半導体装置の製造方法
KR102548907B1 (ko) 플립 칩 본딩을 위한 기판 로딩 장치
CN112596351B (zh) 涂布显影装置和涂布显影方法
CN219873412U (zh) 一种晶圆键合设备
KR102590869B1 (ko) 플립 칩 본딩을 위한 웨이퍼 로딩 장치
JP2001196528A (ja) 半導体装置の製造方法
US20230107043A1 (en) Equipment front end module and destructive analysis automation apparatus including the same
CN117855082A (zh) 裸片键合装置
TW202305960A (zh) 晶粒接合方法以及晶粒接合裝置
US6412680B1 (en) Dual-in-line BGA ball mounter
KR101794978B1 (ko) 반도체 제조 장치의 플립퍼
JP2001274179A (ja) チップマウンタおよび半導体装置の製造方法