WO2013161891A1 - チップオンウエハ接合方法及び接合装置並びにチップとウエハとを含む構造体 - Google Patents
チップオンウエハ接合方法及び接合装置並びにチップとウエハとを含む構造体 Download PDFInfo
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- WO2013161891A1 WO2013161891A1 PCT/JP2013/062100 JP2013062100W WO2013161891A1 WO 2013161891 A1 WO2013161891 A1 WO 2013161891A1 JP 2013062100 W JP2013062100 W JP 2013062100W WO 2013161891 A1 WO2013161891 A1 WO 2013161891A1
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Definitions
- the present invention relates to a chip-on-wafer (COW, Chip-On-Wafer) bonding method and a bonding apparatus for mounting a chip on a wafer, and a structure including a wafer and a plurality of chips bonded on the wafer.
- COW chip-on-wafer
- Chip-On-Wafer Chip-On-Wafer
- a technique for bonding a semiconductor integrated circuit (chip) that has already been packaged onto a wafer (substrate) by a flip chip mounting technique has attracted attention.
- the chip has a bump-shaped or flat metal region, and the chip is stacked between the chip and the wafer or when the chip is three-dimensionally stacked through the metal region. Electrical connections between multiple chips can be established.
- the chip may have a part for bonding with a wafer or another chip in order to increase mechanical strength, and this part may be configured as a metal region.
- NCP Non Conductive Paste
- the chip is pushed into the NCP layer applied to the surface of the substrate to which the chip is bonded, and the metal region of the chip is brought into contact with a predetermined region such as a metal region on the substrate to perform temporary bonding. Thereafter, main bonding is performed by applying a predetermined heat treatment to establish electrical connection between the chip and the wafer (substrate) and increase the mechanical strength.
- NCP is a material that is generally used for lead-free bonding for chip-on-wafer bonding, and has a function of adhering or temporarily fixing the chip to the substrate, and between the bonded chip and the wafer. It is used as an underfill material that fills the gaps between them to increase the mechanical strength between the chip and the wafer and protects the bonding surface from the environment.
- a chip having a bump tip formed of a solder material is joined to a predetermined part on a substrate.
- flux is used to improve the wettability of the solder. Therefore, a process of removing residual flux is performed after joining is completed.
- it tends to be difficult to remove the flux.
- a method of bonding a chip to a wafer (substrate) using a solder material for the bump has a problem that the resin remains at the bonding interface between the solder bump of the chip and the substrate. Even if the chip is pressed against the substrate with a predetermined force or heat treatment is performed after temporary bonding, there is a problem that the resin used for temporary bonding, such as NCP, can remain at the bonding interface. Since this residue is taken into the joining interface after joining, it cannot act directly or physically from the outside. That is, it is difficult to remove the residue after the joining is completed. And the resin which is taken in and remains in the bonding interface has a problem in that the conductivity and mechanical strength between the chip and the substrate are lowered, and the reliability of the bonded portion is lowered.
- the present invention does not leave an undesirable residue such as a resin at the bonding interface, and establishes an electrical connection between the chip and the wafer or between a plurality of stacked chips to increase the mechanical strength.
- An object of the present invention is to provide a technique for efficiently bonding chips on a wafer.
- a wafer (hereinafter referred to as a substrate) includes a plate-like semiconductor, but is not limited thereto, and other than a semiconductor, a material such as glass, ceramics, metal, plastic, or a composite material thereof. It may be formed and is formed in various shapes such as a circle and a rectangle.
- the term “chip” is given as a broad concept term indicating a molded semiconductor plate-like component including a semiconductor component, an electronic component such as a packaged semiconductor integrated circuit (IC), and the like.
- the “chip” includes a component generally called a “die”, a component having a size smaller than that of the substrate, and a size that allows a plurality of components to be bonded to the substrate, or a small substrate.
- electronic components optical components, optoelectronic components, and mechanical components are also included.
- a method of bonding a plurality of chips having a chip side bonding surface having one or a plurality of metal regions to a substrate having a plurality of bonding portions is a chip. At least the metal region of the side bonding surface is subjected to surface activation treatment by colliding particles having a predetermined kinetic energy and hydrophilization treatment by adhering water, and the bonding portion of the substrate is subjected to predetermined movement.
- a step of surface activation treatment by colliding particles having energy and a hydrophilic treatment treatment by adhering water, and a plurality of chips subjected to the surface activation treatment and the hydrophilic treatment treatment are each made of a metal of the chip.
- a clean bonding interface is formed between a chip and a substrate, and a structure including a chip and a substrate having good conductivity and high mechanical strength can be manufactured.
- the present invention is configured such that after all the chips are mounted on the substrate, the heat treatment for the main bonding is performed only once, thereby bonding a plurality of chips on the substrate with high production efficiency. There is an effect that can be.
- the step of mounting the plurality of chips on the corresponding bonding portion of the substrate takes 0.1 to 10 seconds when the metal region of the chip contacts the bonding portion of the substrate.
- the metal region and the substrate junction may be heated to a temperature of 100 degrees Celsius to 350 degrees Celsius.
- the bonding strength of the structure including the chip and the substrate after the temporary bonding and the main bonding can be improved. Since the substantial contact area is increased when the flatness of the bonding surface is increased (for example, when the surface roughness is several nanometers), the bonding by the original hydroxyl group (OH group) becomes a strong bonding, It is possible to obtain sufficient bonding strength even at low pressure bonding.
- the metal region is substantially crushed by pressing (tens of M to several hundreds of MPa).
- the substantial junction area can be increased by enlarging the contact area or promoting diffusion by heating (for example, 150 ° C. or more) at about several hundred degrees Celsius to promote the movement of atoms at the junction interface.
- the adhesion of water to the chip-side bonding surface and the adhesion of water to the bonding portion of the substrate are 10% relative humidity in the atmosphere around the chip-side bonding surface and the bonding portion of the substrate, respectively. It may be performed by being controlled so as to be 100%. Thereby, water can be made to adhere uniformly and densely onto the new surface formed after the surface activation treatment.
- a method of forcibly adding water to the bonding surface by making the atmosphere of the bonding surface and the humidity in the chamber in which the bonding surface is disposed higher than the humidity of the atmosphere is preferable.
- the humidity of the atmosphere is often about 30 to 50%, so it is preferable to set the humidity in the chamber to 50% to 100%, for example.
- the adhesion of water to the chip-side bonding surface and the adhesion of water to the bonding portion of the substrate are exposed to the air after the surface activation treatment, respectively. It may be performed in the chamber without this. As a result, it is possible to suppress the adhesion of organic substances and impurities and allow only water to adhere, so that it is possible to efficiently generate hydroxyl groups (OH groups) on the bonding surface.
- the humidity in the chamber is preferably higher than the atmospheric humidity.
- the bonding method according to the present invention after the step of hydrophilizing the chip-side bonding surface, before attaching the plurality of chips on the corresponding bonding portion of the substrate, water adhesion is performed so that water adheres to the chip-side bonding surface.
- a step may be further provided. Thereby, water adheres on the bonding surface subjected to the surface activation treatment, and the bonding strength of the structure including the chip and the substrate after temporary bonding can be increased.
- the deposits on the bonding surface are removed and activated by argon ion bombardment, but impurities are reattached to the bonding surface that has been surface activated when exposed to the atmosphere.
- the joining method according to the present invention by attaching water to the joint surface subjected to the surface activation treatment, a hydroxyl group (OH group) is formed on the joint surface, so that the water molecule is in a hydrophilic state in which water molecules are easily bonded. . Therefore, even if the bonding surface subjected to the hydrophilic treatment is exposed to the atmosphere, the bonding surface is protected from the atmosphere by adhesion of water molecules. After temporarily bonding a plurality of chips with water intervening, it is possible to form a bonded interface without leaving impurities by removing water from the bonded interface of multiple chips at once by heating in the main bonding Become.
- the water adhesion step may be performed by spraying water on the metal region of the chip-side bonding surface.
- the water adhesion step may be performed by immersing the metal region of the chip-side bonding surface in liquid water. Thereby, a large amount of water can be more reliably adhered on the joint surface subjected to the surface activation treatment.
- the particles may be neutral atoms, ions or radicals of an element selected from the group consisting of Ne, Ar, Kr, and Xe, or a mixture thereof. Since these noble gases have a relatively large mass, they can efficiently cause a sputtering phenomenon and disturb the crystal structure of the nascent surface.
- the kinetic energy of the particles may be 1 eV to 2 keV.
- a plasma containing particles is generated around the chip-side bonding surface or the bonding portion of the substrate, and the particles in the plasma are converted into voltages.
- a predetermined kinetic energy may be imparted to the particles.
- plasma can be generated in an atmosphere with a low degree of vacuum of about several Pascals (Pa), so that the vacuum system can be simplified and the steps such as evacuation can be shortened.
- particles having a predetermined kinetic energy may be radiated from a position separated from the chip-side bonding surface or the bonding portion of the substrate toward the chip-side bonding surface or the bonding portion of the substrate.
- high kinetic energy can be imparted to the particles using a particle beam source or the like, so that the surface layer can be efficiently removed and the new surface can be made amorphous. Since the amorphized nascent surface does not have a strong crystal structure, water adheres along the atomic structure of the amorphized nascent surface to form hydroxyl groups (OH groups), so hydroxyl groups (OH groups) are efficiently formed. Can be formed on the joint surface.
- the chip-side bonding surface has a non-metal region in a region other than the metal region, the non-metal region is formed of a resin, and the chip-side bonding surface is separated from the chip-side bonding surface or the bonding portion of the substrate.
- the surface activation treatment may be performed by emitting particles having a predetermined kinetic energy toward the chip-side bonding surface or the bonding portion of the substrate.
- a plasma generator such as reactive ion etching (RIE) or the like
- RIE reactive ion etching
- an alternating voltage is applied to the bonding surface to generate a plasma containing particles around the bonding surface.
- the surface activation treatment is performed by accelerating the ionized particles toward the bonding surface by the above voltage
- the following contamination of the bonding surface may occur. That is, the resin components and impurities that are blown off by the sputtering phenomenon of the surface activation treatment and exist in the atmosphere around the joint surface can be accelerated and collide so as to be attracted to the joint surface by the voltage.
- resin components and impurities adhere to the surface of the metal region subjected to the surface activation treatment, and the joint surface is contaminated.
- high bonding strength may not be obtained.
- the surface activation treatment is performed using a neutral atom beam source such as an ion beam source or a fast atom beam source (FAB, Fast Atom Beam), so that the ion beam source or the neutral atom beam source is used.
- a neutral atom beam source such as an ion beam source or a fast atom beam source (FAB, Fast Atom Beam)
- FAB Fast Atom Beam
- the problem of contamination of the joint surface due to the reattachment of the resin to the metal region is reduced, and a structure including a chip and a substrate having higher joint strength can be manufactured.
- the step of attaching the plurality of chips on the corresponding bonding portions of the substrate includes a step of pressing the chip and the substrate in a direction close to each other, and the pressing step is performed on the metal region. It may be performed at a pressure of 0.3 to 600 MPa. Thereby, the joint strength of the structure of the chip
- the pressurizing step may be performed by applying a force of 100 N or more per chip or a pressure of 150 MPa or more to the metal region.
- the step of heating the structure including the substrate and the plurality of chips attached on the substrate starts from 10 minutes at a temperature of 100 degrees Celsius or more and less than the melting point of the metal forming the metal region. It may be performed over 100 hours. Thereby, the final bonding strength of the structure including the chip and the substrate can be increased.
- the step of heating the structure including the substrate and the plurality of chips attached on the substrate pressurizes the substrate and the plurality of chips bonded to the substrate in directions close to each other. Steps may be included. Thereby, the substantial bonding area between the metal region of the chip and the substrate can be increased, and the final bonding strength of the structure composed of the chip and the substrate can be further increased.
- the step of heating the structure including the substrate and the plurality of chips attached on the substrate may be performed in a reducing atmosphere.
- the oxide film, OH group, etc. of a joint surface are removed by reduction
- the chip in order to perform the bump reduction process, the chip must be individually reduced before being mounted on the substrate, or the chip can be temporarily fixed with an adhesive. Therefore, when the reduction treatment is performed before mounting the chip, the reduction treatment surface is re-oxidized while being handled in the atmosphere until it moves to bonding, or the reduction treatment is performed with the adhesive temporarily fixed.
- the bump material itself can be temporarily bonded without using other materials such as an adhesive, and it is possible to bond only with the bump material without impurities by applying pressure afterwards without reoxidation after the reduction treatment. .
- the atmosphere around the structure may be evacuated and a gas containing hydrogen may be introduced as a reducing atmosphere.
- a gas containing hydrogen such as hydrogen radicals, tends to enter and diffuse into the bonding interface. Further, by evacuating before introducing the gas containing hydrogen, the gas containing hydrogen is more likely to enter the minute gap at the temporarily joined joint interface. Accordingly, it is possible to increase the speed of the reduction treatment of the bonding surface to form a new surface, and to more efficiently increase the conductivity between the chip and the substrate.
- the step of pressing the substrate and the plurality of chips bonded to the substrate in directions close to each other may be performed after the reduction processing step.
- the gap can be crushed by pressurization to increase the bonding area.
- the metal region may be formed of a material selected from the group consisting of copper (Cu), solder material, gold (Au), and alloys thereof.
- the chip-side bonding surface may have a non-metal region in a region other than the metal region, and the surface of the metal region and the non-metal region may be substantially on the same plane.
- the gap between the chip and the substrate can be eliminated, and the bonding area between the chip substrates can be increased by bonding not only the metal region but also the non-metal region. Therefore, the bonding strength can be increased, the thickness of the final product can be reduced, and the density of the device can be increased. Further, since the bonding interface is protected from the external atmosphere to prevent oxidation and contamination particles from entering, the reliability of the final product can be improved and the life can be extended.
- the non-metal region of the chip-side bonding surface has a hydrophobic side of the chip-side hydrophobized region, and the bonding portion of the substrate is bonded to the bonding region corresponding to the metal region of the chip,
- the chip can be accurately positioned and attached at a predetermined position on the bonding portion of the substrate.
- the metal region may be formed so as to protrude from a region other than the metal region on the chip-side bonding surface.
- the metal region has one or more first metal regions and a closed annular second metal region formed so as to surround the first metal region. May be.
- the bonding method according to the present invention may further include a step of performing a predetermined inspection on the chip and supplying only the chip determined to be good. Thereby, only the chip judged to be good by inspection is bonded to the substrate and mounted, whereby the yield of the final product produced by the bonding method of the present invention can be increased.
- the bonding method according to the present invention may further include a step of removing the attached water molecules from the chip-side bonding surface while leaving the OH group generated by the hydrophilic treatment step after the hydrophilic treatment step.
- a metal region of the first bonding surface of the chip is subjected to a surface activation treatment by colliding particles having a predetermined kinetic energy
- Each of the predetermined number of chips subjected to the surface activation treatment and the hydrophilic treatment is subjected to the surface activation treatment and the hydrophilic treatment so that the metal region of the chip is in contact with the bonding portion of the substrate.
- Mounting on a corresponding joint of the prepared substrate, and at least a metal region of the first joint surface of a predetermined number of chips to be mounted next is surface-activated by colliding particles having a predetermined kinetic energy. And a step of hydrophilizing by adhering water, and particles having a predetermined kinetic energy collide with the second bonding surfaces of a predetermined number of chips in the uppermost layer among the chips stacked on the substrate.
- a clean bonding interface is formed between a chip and a substrate and between the chips, and a structure including a multi-layer chip and a substrate having good conductivity and high mechanical strength is manufactured.
- the present invention is configured to perform the heat treatment for the main bonding only once after attaching all the chips over a plurality of layers, thereby bonding the chips of the plurality of layers onto the substrate with high production efficiency. There is an effect that can be.
- an apparatus for bonding a plurality of chips having a chip-side bonding surface having one or a plurality of metal regions to a substrate having a plurality of bonding portions activates at least the metal region of the chip-side bonding surface.
- the surface activation processing means for the chip that collides particles having a predetermined kinetic energy against the chip-side bonding surface, and the surface activation processing for the surface activation processing of the bonding portion of the substrate,
- water is attached to the metal area of the chip.
- the heat treatment for the main bonding is performed only once, it is possible to bond a plurality of chips on the substrate with high production efficiency. Play.
- the bonding apparatus further includes a water adhering means for further adhering water to the chip-side bonding surface that has been surface activated by the chip surface activation processing means and hydrophilized by the chip hydrophilizing means. It may be configured as follows. As a result, water adheres to the bonding surface that has been subjected to the surface activation treatment and the hydrophilization treatment, promotes the generation of OH groups, and increases the bonding strength of the structure including the chip and the substrate after temporary bonding. it can.
- the chip attachment means includes a chip conveyance means for conveying the chip toward the substrate, and a chip placement means for receiving the chip conveyed by the chip conveyance means and placing the chip on the substrate. It may be configured so that the water adhering means is provided in the chip transporting means, and the chip mounting means sprays water on the chip-side joining surface after receiving the chip. Thereby, an efficient process synchronized with the conveyance of the chip can be performed.
- the water adhering means may be configured to have a hole formed in the chip conveying means, and water may be sprayed to the chip-side bonding surface through the hole.
- a water adhesion means can be comprised by simple structure and an apparatus can be reduced in size.
- the bonding apparatus according to the present invention may be configured such that the hole is also used to vacuum-suck the chip. Thereby, the apparatus can be further miniaturized by sharing the part that performs vacuum suction and water adhesion of the chip in the hole.
- the water adhering means is arranged on a path along which the chip is moved by the chip attaching means, and sprays water toward the chip-side bonding surface when the chip passes through the water adhering means. May be configured. Thereby, water adhesion can be performed by a small number, for example, one water adhesion means.
- the joining apparatus according to the present invention may be configured such that the water adhering means is disposed on a path along which the chip is moved by the chip attaching means and includes a water tank that stores liquid water. As a result, a large amount of water can be more reliably adhered to the bonding surface that has been surface activated.
- the chip surface activation processing unit and the substrate surface activation processing unit apply alternating voltages to the plurality of chips and the substrate, respectively, A plasma containing particles is generated around the junction of the substrate, and the particles in the plasma are accelerated toward the chip-side junction surface and the junction of the substrate by a voltage to give the particles predetermined kinetic energy.
- the plasma generator may be included.
- plasma can be generated in an atmosphere with a low degree of vacuum of about several Pascals (Pa), so that the vacuum system can be simplified and the steps such as evacuation can be shortened.
- the chip surface activation processing means and the substrate surface activation processing means are arranged separately from the chip side bonding surface and the bonding portion of the substrate, respectively.
- a particle beam source that emits particles having a predetermined kinetic energy toward the bonding portion of the substrate may be used. As a result, high kinetic energy can be imparted to the particles, so that the surface layer can be efficiently removed and the nascent surface can be made amorphous.
- the bonding apparatus according to the present invention may be configured such that the hydrophilic treatment means for chips and the hydrophilic treatment means for substrates are realized by a single hydrophilic treatment means. Thereby, the joining apparatus can be further simplified and reduced in size, and the production efficiency of the structure including the chip and the substrate can be increased.
- the bonding apparatus may be configured such that the chip surface activation processing means and the chip hydrophilization processing means have a common particle beam source.
- a particle beam source is used as the surface activation means and the hydrophilization treatment means, and in the surface activation treatment, a rare gas such as argon is introduced to generate an atom or ion beam on the bonding surface.
- argon is introduced to generate an atom or ion beam on the bonding surface.
- water gas or the like is introduced to generate a molecular beam of water and radiate it toward the bonding surface. Therefore, since at least two processing means can be integrated to form, for example, one processing means, the joining apparatus can be further miniaturized and the production efficiency of a structure including a chip and a substrate can be increased. Can do.
- the chip mounting means has a head configured to move the chip in the vertical direction with respect to the surface of the substrate, and the apparatus has the substrate in a plane direction perpendicular to the moving direction of the chip.
- a stage that movably supports the stage, and a frame that fixes the stage with respect to the direction of movement of the chip and supports the chip mounting means so as to be fixed with respect to a surface direction perpendicular to the direction of movement of the chip. It may be configured such that a force of 100 N or more against the chip or a pressure of 150 MPa or more against the metal region of the chip can be applied to the chip and the substrate that are in contact with each other.
- the chip attaching means can be fixed with high rigidity to the substrate or stage (substrate moving means) in the apparatus, so that a high force can be applied to the bonding surface between the chip and the substrate. Therefore, even in the case of solid-phase bonding performed at a temperature lower than the melting point of the metal region, the substantial bonding area can be increased and a bonding interface having good conductivity and mechanical strength can be formed.
- the joining apparatus according to the present invention includes a chip transfer means for supplying the chip to the fixed chip mounting means and a stage for moving the chip mounting position on the substrate. It is configured. However, in the case of a small-scale production apparatus, it is possible to transfer a chip to the head by moving the substrate stage by arranging a plurality of chips arranged on the tray on the substrate stage. And the stage can also be used.
- the bonding apparatus further includes means for pressing the chip and the substrate in directions close to each other when the chip mounting means mounts the chip on the corresponding bonding portion of the substrate.
- a pressure of 0.3 to 600 MPa may be applied to the metal region of the chip.
- the bonding apparatus may further include a heating means for heating a structure including a plurality of chips and a substrate.
- a heating means for heating a structure including a plurality of chips and a substrate.
- the bonding apparatus may further include a reduction processing means for introducing a reducing gas into the atmosphere of the structure when the structure including a plurality of chips and the substrate is heated.
- a reduction processing means for introducing a reducing gas into the atmosphere of the structure when the structure including a plurality of chips and the substrate is heated.
- the joining apparatus is configured such that the reduction treatment means introduces a gas containing hydrogen as a reducing gas into the atmosphere of the structure, and further includes a vacuum drawing means for evacuating the atmosphere of the structure. May be configured. This makes it easy for hydrogen to enter and diffuse into the bonding interface. In addition, hydrogen is introduced into the bonding interface after being in a vacuum state, thereby allowing it to enter and diffuse into the bonding interface very efficiently. The speed can be increased to form a new surface, and the conductivity between the chip and the substrate can be increased more efficiently.
- An apparatus for laminating a chip layer composed of a plurality of chips having a first bonding surface having one or a plurality of metal regions on a substrate having a plurality of bonding portions over a plurality of layers.
- surface activation treatment means for the first bonding surface that collides particles having a predetermined kinetic energy against the first bonding surface of the chip, Surface activation for chip second bonding surface in which particles having predetermined kinetic energy collide with the second bonding surface of the chip in order to surface-activate the second bonding surface located on the back side of the first bonding surface Processing means, surface activation processing means for a substrate for causing particles having a predetermined kinetic energy to collide with the bonding portion of the substrate, and a chip subjected to the surface activation processing in order to surface-activate the bonding portion of the substrate First joint of In order to hydrophilize the chip, the chip first joint surface hydrophilization treatment means for adhering water to the first joint
- the chip second bonding surface hydrophilization treatment means for adhering water to the second bonding surface of the chip, and the substrate bonding portion to hydrophilize the bonding portion of the substrate
- the substrate is hydrophilized and the chip is mounted on the corresponding joint of the substrate so that the metal region of the chip is in contact with the joint of the substrate.
- Chip attachment means for attaching the chip onto the chip attached on the substrate so that the first joint surface of the chip to be attached next contacts the two joint surfaces.
- the present invention it is possible to manufacture a structure including a multi-layer chip and a substrate that form a clean bonding interface between the chip and the substrate and provide good conductivity and high mechanical strength.
- the present invention is configured such that after all the chips are mounted on the substrate, the heat treatment for the main bonding is performed only once, so that a plurality of chips are bonded on the substrate with high production efficiency. There is an effect that can be.
- the bonding apparatus is configured to further include a heating means for heating a structure including a substrate and a plurality of chips laminated on the substrate over a plurality of layers. Thereby, a structure including a substrate and a plurality of chips stacked on the substrate can be efficiently heated after temporary bonding.
- a structure including a substrate and a plurality of chips attached on the substrate according to the present invention is formed by any one of the methods described above.
- a structure including a chip and a substrate with improved conductivity and mechanical strength can be provided by having a clean bonding interface that does not include a residue such as a resin, and the chip and the substrate can be provided.
- a structure including the above can be used for a wider range of applications of electronic components.
- a method for bonding a plurality of chips having a chip side bonding surface having one or a plurality of metal regions to a substrate having a plurality of bonding portions is performed by colliding particles having kinetic energy and hydrophilic treatment treatment by attaching water, and surface activation is performed by colliding particles having a predetermined kinetic energy at the bonding portion of the substrate.
- the step of hydrophilizing by applying water and adhering water and a plurality of chips activated and hydrophilized so that the metal region of the chip is in contact with the bonding portion of the substrate, respectively Mounting on a corresponding joint of a surface activated and hydrophilized substrate, and a plurality of chips mounted on the substrate and the substrate.
- the chips are those thickness was such that 10 [mu] m ⁇ 300 [mu] m.
- the warpage of the chip is suppressed, the collapse of the bumps, which are metal regions, is prevented, and the bumps can be joined well over the entire chip.
- the step of attaching the plurality of chips on the corresponding bonding portions of the substrate may include heating the material constituting the metal region of the chip in a solid state below the melting point. Thereby, melting of the metal region can be prevented, and the chip can be attached with high accuracy. Further, since the strong oxide film is once removed by the surface activation, the oxide film is thin and easily diffused even in the solid phase even if it is oxidized thereafter.
- the bonding method according to the present invention may further include a step of pressing the surface of the metal region with a substrate having a flat surface before the step of attaching the plurality of chips onto the corresponding bonding portion of the substrate. That is, by flattening the bonding surface before the temporary bonding step, even if temporary bonding or main bonding is performed at a relatively low temperature, the substantial bonding area by contact is increased and a good bonding interface is formed. Can do.
- the step of heating the structure may be performed by heating the material constituting the metal region of the chip in a solid state less than the melting point.
- the strong oxide on the surface-activated bonding surface is once removed, and the oxide film generated in the hydrophilization treatment for generating OH groups is thin, and the surface activation treatment produces a crystal.
- the OH group formed by hydrophilization treatment is transformed into a high-strength bond by heating, while forming a good high-strength bond interface between the chip and the substrate. it can. Even if the oxide film remains at the interface, it is thin and does not impair the connection resistance at the semiconductor level.
- the desired temporary bonding strength can be obtained, and the substance that has been attached to the bonding surface such as water and contributed to the temporary bonding is Since it disappears during the main bonding, a clean bonding interface is formed between the chip and the substrate, and a structure including the chip and the substrate having good conductivity and high mechanical strength can be manufactured.
- a configuration in which the heat treatment for main bonding is performed only once after all the chips are mounted on the substrate can bond a plurality of chips on the substrate with high production efficiency.
- the effect is that the three-dimensional mounting body of the electronic device can be manufactured with higher density and higher production efficiency.
- FIG. 1 is a flowchart showing a method for bonding a chip to a substrate according to the first embodiment of the present invention.
- step S1 the surfaces of a plurality of chips that are scheduled to be bonded to the substrate (hereinafter referred to as chip-side bonding surfaces) are subjected to a surface activation process and a hydrophilic process.
- the chip-side bonding surface includes one or a plurality of regions (hereinafter referred to as metal regions) formed of metal.
- step S2 all surface regions (hereinafter referred to as bonding portions) corresponding to the respective chips on the substrate to which the chip-side bonding surface is bonded are subjected to surface activation treatment and hydrophilic treatment.
- bonding surface 41 of the substrate there is a surface layer 42 containing contaminants (impurities) such as oxides of various substances and attached organic substances, It covers the new surface 43 of the material to be joined (see FIG. 2 (a)).
- the surface layer 42 is considered to lower the energy level of the new surface 43 of the material. It is considered that the surface activation process removes this surface layer and exposes the new surface of the material to be joined (see FIG. 2B).
- the surface activation treatment performed by colliding particles having a predetermined kinetic energy also has the effect of further increasing the surface energy level by breaking the bonds between atoms and disrupting the crystal structure in the vicinity of the nascent surface. It is believed that.
- a substance containing water or a hydroxyl group (OH) group is supplied to the new surface exposed by the surface activation treatment.
- a substance containing water or a hydroxyl group (OH) is brought into contact with the nascent surface exposed by the surface activation treatment, a hydroxyl layer 44 is formed on the nascent surface (FIG. 2 (c)) or nascent on the nascent surface.
- a layer of oxide of the material forming the surface is formed. Further, when water is supplied, it is considered that water adheres on the formed hydroxyl layer or oxide layer.
- Process S1 and process S2 may be performed simultaneously in parallel. Further, after step S1, step S2 may be performed. Conversely, step S1 may be performed after step S2.
- the hydrophilic treatment in step S1 or step S2 is preferably performed after the surface activation treatment.
- the hydrophilic treatment may be started before the surface activation treatment is completed.
- step S3 the chips on which the chip-side bonding surfaces have been surface-activated and hydrophilized are attached to the substrate so that the metal regions of the chips contact corresponding bonding portions on the substrate.
- this step S3 is referred to as “temporary joining”.
- the attachment of the chip to the substrate is performed by repeatedly attaching the chips one by one to the joint portion of the substrate until the attachment of a predetermined number of chips to be attached to the substrate is completed. Or you may perform it by repeating until attachment of the predetermined number of chip
- the metal region is substantially crushed by pressing (tens of M to several hundreds of MPa).
- the substantial junction area can be increased by enlarging the contact area or promoting diffusion by heating (eg, 150 ° C.) at about several hundred degrees Celsius to promote the movement of atoms at the junction interface.
- step S4 a heat treatment is performed on the structure composed of the chip and the substrate, which is formed by attaching all of the plurality of chips scheduled to be bonded to the substrate. By heating, a bonded interface having desired conductivity and mechanical strength can be obtained. In the present specification, this step S4 is referred to as “main joining”.
- the surface of the metal region of the chip attached in step S3 and the surface of the bonding portion of the substrate have a surface roughness of atomic level or nanometers to several tens of nanometers. Therefore, when attached in step S3, the substantial bonding area between the surface of the metal region of the chip and the surface of the bonding portion of the substrate is smaller than the apparent bonding area. It is believed that the heat treatment diffuses atoms in the vicinity of the interface between the metal region of the attached chip and the bonding portion of the substrate, thereby increasing the substantial bonding area. In the present specification, this step S4 is referred to as “main joining”.
- the type and flow rate of the gas forming the atmosphere may be adjusted.
- force or pressure can be applied to the bonded body of the chip and the substrate so that a vertical pressure is applied to the bonding interface during the heat treatment.
- a vertical pressure is applied to the bonding interface, the substantial or microscopic bonding area is further increased.
- the temperature or the time profile of the above force or pressure is the conditions of temporary bonding, the thermal characteristics of the material forming the metal region, the thermal characteristics of the material forming the chip or the substrate, the atmosphere during the heat treatment, the heat treatment It can be adjusted according to the characteristics of the device.
- the bonding method according to the present invention can reduce the thermal budget (heat consumption) necessary for bonding, as compared with the conventional bonding technique using resin or the like.
- FIGS. 3A to 3F are schematic views of a cross section of a chip when the chip is cut along a plane perpendicular to the chip-side bonding surface. These drawings are intended to illustrate the shape of the metal region, and do not limit the shape of the metal region.
- the metal region MR is formed on the chip-side bonding surface so as to protrude in a so-called bump (projection) shape.
- the upper end surface of the metal region MR is bonded to the substrate.
- the region NR other than the metal region MR is preferably formed of a non-metal such as silicon (Si) or silicon oxide (SiO 2), but may be formed of other materials such as metal. Materials other than the metal region MR can be selected according to the use of the device, the bonding method, and the like.
- the metal region MR and the region NR other than the metal region are collectively referred to as a chip side bonding surface.
- the region NR other than the metal region MR will be referred to as a non-metal region NR.
- the cross-sectional shape of the upper end portion of the metal region MR may not be flat.
- the plane of the upper end portion has a certain degree of roughness microscopically.
- this roughness is large, even if a relatively low pressure is applied, a sufficient bonding area cannot be formed microscopically, and a desired conductivity or mechanical property between the metal region and the substrate is not obtained. It is possible that strength cannot be established. Therefore, for example, the cross section of the surface of the metal region may be formed as a curved surface, or may be formed as a spherical surface as shown in FIG. Since each metal region MR in FIG.
- the metal region MR may be provided connected to a through electrode (silicon through electrode, TSV, Through Silicon Via) (VA) formed in the silicon chip.
- a through electrode silicon through electrode, TSV, Through Silicon Via
- VA Through Silicon Via
- the metal region MR and the Si through electrode VA may be formed such that the area of the upper end portion of the metal region MR is larger than the region area of TSV (VA). .
- the bonding area is increased, and a relatively high conductivity of electrical connection between stacked chips can be ensured.
- the chip-side bonding surface may be configured such that the metal region MR and the nonmetal region NR are substantially on the same plane.
- the metal region MR and the non-metal region NR may be on the same plane, and the metal region MR is made to be in contact with and bonded to the substrate bonding portion.
- it may be protruded by a height of about 1 ⁇ m (micrometer) or less.
- the protruding height of the metal region MR with respect to the non-metal region NR depends on various parameters such as the material and shape of the metal region MR and the non-metal region NR, the shape, dimensions, and mechanical properties of the entire chip. Thus, adjustment is made so that a junction interface is formed in both the metal region MR and the non-metal region NR.
- the configuration of the chip-side bonding surface in which the metal region MR and the non-metal region NR are substantially on the same plane is, for example, in a predetermined manufacturing stage of the chip. This is realized by performing chemical mechanical polishing (CMP) on the chip side surface.
- CMP chemical mechanical polishing
- the example shown in FIG. 3 (e) corresponds to a chip structure called bumpless TSV.
- this chip when the bonding surface of the substrate to be bonded is a flat surface, both the metal region MR and the non-metal region NR are bonded to the substrate. Therefore, the bonding interface related to the metal region that establishes the electrical connection between the chip and the substrate can be protected by the bonding interface related to the surrounding non-metal region. Furthermore, since the bonding interface between the chip and the substrate is formed not only in the metal region MR but also in the non-metal region NR, the bonding area is remarkably increased, and the bonding strength between the chip and the substrate is increased. Can do. Furthermore, when a plurality of layers are formed and the chips are stacked and mounted on the substrate, the dimension (thickness) in the direction perpendicular to the substrate surface can be reduced.
- a cavity is formed on the chip-side bonding surface, and the metal region MR is formed in this cavity so as to protrude like a bump (projection).
- the bonding interface related to the metal region MR inside the chip is sealed against the external atmosphere by the bonding interface related to the non-metal region NR. Therefore, it is not necessary to seal the joint portion with a resin after the joining process is completed, and the electrical interface at the joint interface due to oxidation due to the intrusion of air, contamination of impurities between the chip and the substrate, etc. Alternatively, deterioration of mechanical properties can be prevented.
- the non-metal region NR is preferably formed of a non-metal such as silicon (Si) or silicon oxide (SiO 2 ), but is not limited thereto.
- part or all of the surface of the non-metal region NR may be subjected to a hydrophobic treatment.
- the chip-side bonding surface has a hydrophobized region, the hydrophilized metal region MR and the corresponding hydrophilized portion on the substrate can be used. Self-alignment can be realized.
- FIGS. 4A to 4C schematically show the arrangement of metal regions formed on the chip-side bonding surface when viewed from a direction perpendicular to the bonding surface.
- a plurality of circular metal regions MR are arranged in a line on the chip side bonding surface.
- the shape and arrangement of the metal region MR are not limited to the examples shown in FIGS.
- the shape of each metal region MR is not limited to a circle but may be a square or a rectangle, for example. 4A to 4C, the plurality of metal regions MR are arranged side by side so as to draw a rectangle, but the present invention is not limited to this.
- a plurality of metal regions MR are formed in different sizes on the chip-side bonding surface.
- the total of the final bonding area with the substrate is equal to that of the chip even though the electrical connection for ensuring the desired conductivity is ensured. It may be less than enough area to achieve sufficient mechanical strength with the substrate.
- a strength metal region MR2 connected to the substrate may be provided in order to improve mechanical strength.
- the metal region MR2 may or may not be electrically joined to the circuit in the chip or the TSV passing through the chip.
- the area, shape, arrangement, etc. of the metal region MR2 are the mechanical strength required between the chip and the substrate, the shapes of the metal region MR and the strength metal region MR2, You may adjust based on a magnitude
- the metal region MR formed for electrical connection shown in FIG. 4A is used as the first metal region.
- a metal region MR3 which is a metal wall, is formed in a closed ring shape so as to surround the first metal region.
- the first and second metal regions are formed so as to protrude with respect to the region other than the metal region on the chip-side bonding surface.
- the closed annular metal region MR3 seals the bonding interface related to the metal region MR inside thereof to the external atmosphere. That is, the external atmosphere cannot reach the bonding interface related to the metal region MR. Therefore, it is not necessary to seal the joint portion with a resin after the joining process is completed, and the electrical interface at the joint interface due to oxidation due to the intrusion of air, contamination of impurities between the chip and the substrate, etc. Alternatively, deterioration of mechanical properties can be prevented.
- the bonding area can be increased and high bonding strength can be achieved. Furthermore, since a material such as lead is not included and a reflow process is not required, a sealing structure for a structure including an environment-friendly chip and a substrate can be provided.
- Each of the above chips may be formed by, for example, cutting a substrate on which a plurality of electronic circuits are formed in the vertical direction and the horizontal direction.
- the joint part UT of the substrate WA is set as a plurality of rectangles or squares defined by equally spaced straight lines drawn vertically and horizontally on the surface of the substrate as shown in FIG. 5, for example. Or may be set discretely at an arbitrary location.
- the substrate is cut (diced) at each bonding portion after the bonding method according to the present invention is completed, and divided into dies. The size of the die given as the final product is determined by the size of the joint set on the substrate.
- Each joint may be set so as to be physically or optically recognizable on the substrate, but is not limited thereto.
- the arrangement of the joints may be recognized based on the position on the stage by a computer system that can recognize the position on the stage that supports the substrate.
- the bonding portion of the substrate may correspond to the metal regions of the plurality of chips, and may be configured to have a plurality of bonding regions that should establish electrical connection with the chips (not shown). ).
- This joining region may be made of metal. In this case, electrical connection between the chip to be bonded and the substrate is realized.
- the bonding portion of the substrate may be formed using a non-metallic material such as silicon (Si) or silicon oxide (SiO 2 ).
- a non-metallic material such as silicon (Si) or silicon oxide (SiO 2 ).
- the metal region of the chip can be bonded to the substrate to increase the bonding strength between the chip and the substrate.
- step S1 and step S2 surface activation treatment is performed by causing particles having a predetermined kinetic energy to collide with the chip-side bonding surface and the bonding portion of the substrate (hereinafter referred to as bonding surface).
- the surface layer can be removed by causing a phenomenon (sputtering phenomenon) in which particles having a predetermined kinetic energy collide to physically blow off the material forming the bonding surface.
- a phenomenon sputtering phenomenon
- the surface activation treatment not only the surface layer is removed to expose the nascent surface of the substance to be bonded, but also the crystal structure near the exposed nascent surface is collided with particles having a predetermined kinetic energy. It is thought that there is also an effect of disturbing and amorphizing. Since the amorphized new surface has a higher surface area at the atomic level and a higher surface energy, it is considered that the number of hydroxyl groups (OH groups) per unit surface area to be bonded in the subsequent hydrophilization treatment is increased.
- OH groups hydroxyl groups
- a rare gas or an inert gas such as neon (Ne), argon (Ar), krypton (Kr), or xenon (Xe) can be used. Since these rare gases have a relatively large mass, it is considered that a sputtering phenomenon can be efficiently generated and the crystal structure of the nascent surface can be disturbed.
- oxygen ions As the particles used for the surface activation treatment, oxygen ions, atoms, molecules, and the like may be employed. By performing the surface activation treatment using oxygen ions or the like, it is possible to cover the new surface with an oxide thin film after removing the surface layer.
- the oxide thin film on the nascent surface is believed to enhance the efficiency of hydroxyl (OH) group bonding or water attachment in subsequent hydrophilization treatments.
- OH hydroxyl
- the oxide thin film formed on the nascent surface is relatively easily decomposed during the heat treatment in the main bonding.
- the kinetic energy of the particles colliding with the surface-activated joint surface is 1 eV to 2 keV. It is considered that the above kinetic energy efficiently causes a sputtering phenomenon in the surface layer.
- a desired value of kinetic energy can also be set from the above kinetic energy range according to the thickness of the surface layer to be removed, the properties such as the material, the material of the new surface, and the like.
- a predetermined kinetic energy can be given to the particles that collide with the surface-activated joint surface by accelerating the particles toward the joint surface.
- Predetermined kinetic energy can be given to particles using a plasma generator.
- a plasma generator By applying an alternating voltage to the bonding surfaces of a plurality of chips or substrates, a plasma containing particles is generated around the bonding surfaces, and the cations of the ionized particles in the plasma are bonded to the bonding surfaces by the voltage.
- a predetermined kinetic energy is given by accelerating toward. Since the plasma can be generated in an atmosphere with a low degree of vacuum of about several pascals (Pa), the vacuum system can be simplified and the steps such as evacuation can be shortened.
- the plasma generator may be used, for example, to operate at 100 W, generate argon (Ar) plasma, and irradiate the bonding surface for about 600 seconds.
- a predetermined kinetic energy can be given to the particles by using a particle beam source such as a neutral atom beam source or an ion beam source (ion gun) disposed at a position separated from the bonding surface. Particles to which a predetermined kinetic energy is applied are emitted from a particle beam source toward bonding surfaces such as a plurality of chips or substrates.
- a particle beam source such as a neutral atom beam source or an ion beam source (ion gun) disposed at a position separated from the bonding surface.
- Particles to which a predetermined kinetic energy is applied are emitted from a particle beam source toward bonding surfaces such as a plurality of chips or substrates.
- the particle beam source operates in a relatively high vacuum, such as 1 ⁇ 10 ⁇ 5 Pa (pascal) or less, for example, to prevent unnecessary oxidation of the nascent surface and adhesion of impurities to the nascent surface after the surface activation treatment. be able to. Furthermore, since the particle beam source can apply a relatively high acceleration voltage, high kinetic energy can be imparted to the particles. Therefore, it is considered that the removal of the surface layer and the amorphization of the new surface can be performed efficiently.
- a fast atom beam source As the neutral atom beam source, a fast atom beam source (FAB, Fast Atom Beam) can be used.
- FABs Fast atom beam sources
- FABs typically generate a plasma of gas, apply an electric field to the plasma, extract the cations of particles ionized from the plasma, and pass them through an electron cloud. It has the composition which becomes.
- the power supplied to the fast atom beam source (FAB) may be set to 1.5 kV (kilovolt), 15 mA (milliampere), or 0.1 To a value between 500 W (watts).
- a fast atom beam source FAB
- 100 W watts
- 200 W watts
- a fast atom beam of argon (Ar) for about 2 minutes
- the oxide, contaminants, etc. (surface) Layer) can be removed to expose the nascent surface.
- the ion beam source may be used to operate at 110 V, 3 A, for example, to accelerate argon (Ar) and irradiate the bonding surface for about 600 seconds.
- the particles used for surface activation may be neutral atoms or ions, may be radical species, and may be a particle group in which these are mixed.
- the removal rate of the surface layer can vary depending on the operating conditions of each plasma or beam source or the kinetic energy of the particles. Therefore, it is necessary to adjust the treatment time required for the surface activation treatment. For example, the presence of oxygen and carbon contained in the surface layer is confirmed using surface analysis methods such as Auger Electron Spectroscopy (AES, Auger Electron Spectroscopy) and X-ray Photoelectron Spectroscopy (XPS, X-ray Photo Electron Spectroscopy). You may employ
- Auger Electron Spectroscopy AES, Auger Electron Spectroscopy
- XPS X-ray Photoelectron Spectroscopy
- the irradiation time of the particles may be set longer than the time necessary for removing the surface layer and exposing the new surface.
- the lengthening time may be set to 10 to 15 minutes, or 5% or more of the time required for removing the surface layer and exposing the new surface.
- the time for making the bonding surface amorphous in the surface activation treatment may be appropriately set according to the type and nature of the material forming the bonding surface and the irradiation conditions of particles having a predetermined kinetic energy.
- the kinetic energy of the irradiated particles is set to be 10% or more higher than the kinetic energy necessary for removing the surface layer and exposing the new surface. Good.
- the kinetic energy of the particles for making the bonding surface amorphous in the surface activation treatment may be appropriately set depending on the type and property of the material forming the bonding surface and the irradiation conditions of the particles.
- the “amorphized surface” or “surface with disordered crystal structure” specifically includes an amorphous layer whose presence has been confirmed by measurement using a surface analysis technique or a layer with a disordered crystal structure, This is a conceptual term that expresses the state of the crystal surface assumed when the particle irradiation time is set to be relatively long or the particle kinetic energy is set to be relatively high. It includes a surface in which the presence of an amorphous layer or a surface having a disordered crystal structure is not confirmed by the measurement used. Also, “amorphize” or “disturb the crystal structure” conceptually represents the operation for forming the amorphized surface or the surface in which the crystal structure is disturbed.
- step S1 and step S2 the hydrophilic treatment is performed after the surface activation treatment. It is considered that a hydroxyl group (OH group) is bonded to the bonding surface by the hydrophilic treatment of the bonding surface. Furthermore, water molecules may adhere on the bonding surface to which a hydroxyl group (OH group) is bonded.
- Oxide treatment may form oxides on the joint surface. Since the oxide is relatively thin (for example, several nm or several atomic layers or less), it is absorbed in the metal material in the heat treatment during the main bonding, or disappears as it escapes from the bonding interface as water. Or it is thought to decrease. Therefore, in this case, it is considered that there is almost no practical problem in the conductivity through the bonding interface between the chip and the substrate.
- the hydrophilization treatment is performed by supplying water to the surface-activated joint surface.
- the water can be supplied by introducing water (H 2 O) into the atmosphere around the surface activated bonding surface.
- Water may be introduced in a gaseous state (in a gaseous state or as water vapor) or in a liquid state (a mist state).
- radicals, ionized OH, or the like may be attached.
- the method of introducing water is not limited to these.
- the hydrophilic treatment process can be controlled by controlling the humidity of the atmosphere around the surface activated joint surface.
- the humidity may be calculated as relative humidity, may be calculated as absolute humidity, or other definitions may be employed.
- gaseous water is formed by passing a carrier gas such as nitrogen (N 2 ), argon (Ar), helium (He), oxygen (O 2 ), etc. into liquid water (bubbling).
- a carrier gas such as nitrogen (N 2 ), argon (Ar), helium (He), oxygen (O 2 ), etc.
- Water is preferably mixed with the carrier gas and introduced into a space or chamber in which a chip or substrate having a surface activated bonding surface is disposed.
- the introduction of water is preferably controlled so that the relative humidity in the atmosphere around at least one or both of the chip-side bonding surface and the bonding portion of the substrate is 10% to 90%.
- the total pressure in the chamber is set to 9.0 ⁇ 10 4 Pa (Pascal), that is, 0.89 atm (Atom).
- the amount of gaseous water in the chamber is 8.6 g / m 3 (grams / cubic meter) or 18.5 g / m 3 (grams / cubic meter) relative to 23 ° C. (23 degrees Celsius) in absolute humidity.
- the humidity can be controlled to be 43% or 91%, respectively.
- the atmospheric concentration of oxygen (O 2 ) in the chamber may be 10%.
- the hydrophilic treatment it is preferable to supply water to the joint surface without exposing the joint surface subjected to the surface activation treatment to the atmosphere.
- the chamber for performing the surface activation process and the chamber for performing the hydrophilization process may be configured to be the same.
- the chamber for performing the surface activation treatment and the chamber for carrying out the hydrophilic treatment may be configured to be connected so that a plurality of chips or substrates are conveyed between them without being exposed to the atmosphere. .
- the surface activation treated bonding surface is not exposed to the atmosphere, thereby preventing unwanted oxidation of the bonding surface, adhesion of impurities, etc. to the bonding surface, and more hydrophilic treatment. It can be easily controlled, and the hydrophilic treatment can be carried out efficiently after the surface activation treatment.
- air outside the chamber having a predetermined humidity may be introduced.
- air it is preferable that the air passes through a predetermined filter in order to prevent unwanted impurities from adhering to the bonding surface.
- water (H 2 O) molecules or clusters may be accelerated and radiated toward the bonding surface.
- the acceleration of the water (H 2 O) may be used, such as particle beam source used for the surface activation treatment.
- a mixed gas of carrier gas and water (H 2 O) generated by bubbling or the like is introduced into the particle beam source, thereby generating a water particle beam, and on the joint surface to be hydrophilized. It can be irradiated towards.
- the joint surfaces 41a and 41b that have been subjected to the surface activation treatment and the hydrophilic treatment are attracted to each other by the action of hydrogen bonding during the subsequent attachment (temporary joining) of the chip to the substrate, and relatively strong temporary joining. Is formed (FIG. 2D). Further, since the bonding interface containing hydrogen and oxygen is formed, the heat treatment in the main bonding releases hydrogen and oxygen to the outside of the bonding interface, and a clean bonding interface 45 can be formed (FIG. 2 (e)).
- step S3 the substrate whose surface on the chip side is subjected to surface activation treatment and subjected to hydrophilic treatment is subjected to surface activation treatment and hydrophilic treatment so that the metal region of the chip contacts the bonding portion of the substrate. Are mounted on the corresponding joints.
- a plurality of position adjustment marks are provided on the chip side, and a plurality of corresponding position adjustment marks are provided on the corresponding joint portion side of the substrate. This may be done by aligning the marks for use.
- the misalignment between both position adjustment marks is that the transmitted light that is transmitted through the chip and the substrate is incident on the bonding surface in the vertical direction from the chip or the substrate side and is imaged by the camera provided on the opposite side. You may comprise so that it may measure by observing the image of the position adjustment mark by.
- the chip-side bonding surface subjected to the hydrophilization treatment and the bonding portion of the substrate are covered with a hydroxyl group (OH) group or water molecule. Temporary joining is performed by attractive forces such as hydrogen bonds acting between them.
- the chip-side bonding surface and the bonded portion of the substrate are at least in the process from when all of the chips to be bonded are mounted to the substrate until heat treatment is performed.
- the chip does not peel off from the substrate or the chip does not deviate from the predetermined mounting position on the substrate. It is fixed with a strong bonding force.
- the humidity of the atmosphere around the plurality of chips and the substrate may be maintained at a predetermined value.
- the metal region of the chip is made of metal such as nickel (Ni), gold (Au), tin (Sn), etc., and is formed in a pad shape of 20 ⁇ m (micrometer) square and 3 ⁇ m (micrometer) to 10 ⁇ m (micrometer) high. In such a case, a pressure of 0.3 MPa (megapascal) to 600 MPa (megapascal) may be applied to the pad in a direction in which the chip and the substrate are close to each other.
- the pressure applied to the pad is adjusted according to the mechanical characteristics and shape of the material in the metal region, the conditions of the heat treatment in the subsequent main bonding, and the like.
- the chip and the substrate are bonded by a relatively strong hydrogen bond, even if the chip is mounted inside or outside the chip mounting system, There is little risk that the chip will slide or peel off the substrate.
- a structure including a plurality of chips and a substrate obtained by temporary bonding is relatively stable, it can be stored in the air for several hours to several days until heat treatment. Therefore, the heat treatment can be performed on the structure including the chip and the substrate at an arbitrary timing.
- a plurality of structures including a plurality of chips and substrates obtained by the above temporary bonding can be subjected to heat treatment. Thereby, there is an effect that a structure including the chip and the substrate that are joined together can be manufactured with high production efficiency. Further, since the chip and the substrate are bonded by a relatively strong hydrogen bond, even if the chip is transferred to the inside or outside of the chip mounting system, the risk that the chip slides or peels off from the substrate is small. In addition, since a structure including a plurality of chips and a substrate obtained by temporary bonding is relatively stable, it can be stored in the air for several hours to several days until heat treatment. Therefore, the heat treatment can be performed on the structure including the chip and the substrate at an arbitrary timing.
- the chips to be temporarily bonded may be configured to perform a predetermined inspection on the chips supplied before the temporary bonding and to select only the chips determined to be good. Thus, by mounting only chips that are determined to be good by inspection, the yield of the final product to be produced can be increased.
- step S4 predetermined electrical conductivity (resistivity) or bonding strength (mechanical strength) between the chip and the substrate is obtained by performing heat treatment on the structure of the plurality of chips and the substrate obtained in step S3. Can be obtained.
- the maximum temperature during the heat treatment is preferably set to 100 ° C. (100 ° C.) or higher and lower than the melting point of the material forming the outer surface of the chip and the substrate.
- the maximum temperature during the heat treatment By setting the maximum temperature during the heat treatment to 100 ° C. (100 degrees Celsius) or higher, it is considered that most of the hydroxyl (OH) groups or water contained in the bonding interface escapes to the outside of the bonding interface. . At this time, it is considered that in the process of water escaping from the temporary bonding interface, the bonding surfaces that have not been in contact with each other come into contact with each other, the substantial bonding interface expands, and the bonding area increases. In addition, by joining the joint surfaces that have been subjected to the hydrophilic treatment after the surface activation treatment according to the present invention, heating at a temperature exceeding 400 ° C. required for joining using the conventional simple hydrophilization treatment becomes unnecessary. Sufficient bonding strength can be obtained by heating at a temperature of about 0 to 250 ° C.
- the maximum temperature during the heat treatment is set to be lower than the melting point of the material forming the bonding surface between the chip and the substrate, sufficient electrical characteristics and mechanical characteristics can be obtained. it can. It is considered that solid phase diffusion of the material occurs in the vicinity of the bonding interface, and the substantial bonding interface is expanded and the bonding area is increased by filling the gap between the bonding surfaces that have not been in contact with each other.
- the positional deviation in the main bonding can be almost eliminated. it can.
- the chip positioning accuracy with respect to a predetermined position on the joint portion of the substrate can be increased, and for example, it can be suppressed to ⁇ 1 ⁇ m or less.
- the chip may be displaced from the position on the substrate attached by temporary bonding. obtain. This positional deviation may be several ⁇ m. If a position shift occurs during the final bonding of the chips, a certain metal region comes into contact with an adjacent metal region, which causes a short circuit. In addition, the bonding area may be reduced, and the bonding strength at the bonding interface may decrease due to a step generated at the bonding interface.
- the positioning of the chip with respect to the corresponding joint portion of the substrate is performed by aligning the position adjustment marks provided on the chip side and the substrate side with light transmitted through the chip and the substrate. Is done. Thereby, for example, a positioning accuracy of ⁇ 1 ⁇ m can be obtained. Furthermore, when the positioning is not sufficient, the chip is once separated from the substrate immediately after the temporary bonding, and the temporary bonding can be repeated after the positioning is performed again until a predetermined positioning accuracy is obtained. Thereby, positioning accuracy of ⁇ 0.2 ⁇ m can be obtained.
- the chip is positioned with respect to a predetermined position on the substrate by using a position adjustment mark or the like, and then temporary bonding is performed. Further, in the main bonding, the heating temperature is changed to a material for forming the bonding surface between the chip and the substrate.
- the positioning accuracy of the chip with respect to a predetermined position on the bonding portion of the substrate can be extremely increased in the final product. Thereby, while suppressing generation
- the chip-side bonding surface and the bonding portion of the substrate are formed of copper (Cu)
- the structure of the chip and substrate after temporary bonding is heated at 150 ° C. (150 degrees Celsius) for 600 seconds.
- 150 ° C. 150 degrees Celsius
- the metal region between the chip-side bonding surface and the bonding portion of the substrate is formed of copper (Cu)
- Cu copper
- Each metal region of the chip is made of a metal such as nickel (Ni), gold (Au), tin (Sn), tin-silver alloy, 20 ⁇ m (micrometer) square, 3 ⁇ m (micrometer) to 10 ⁇ m (micrometer) Meter), a pressure of 0.3 MPa (megapascal) to 600 MPa (megapascal) may be applied to each pad during the heat treatment.
- a metal such as nickel (Ni), gold (Au), tin (Sn), tin-silver alloy, 20 ⁇ m (micrometer) square, 3 ⁇ m (micrometer) to 10 ⁇ m (micrometer) Meter), a pressure of 0.3 MPa (megapascal) to 600 MPa (megapascal) may be applied to each pad during the heat treatment.
- the atmosphere around the structure during the heat treatment may be air or nitrogen or a rare gas atmosphere.
- the humidity of the atmosphere around the structure during the heat treatment may be adjusted. This humidity may be adjusted according to the electrical or mechanical properties of the resulting bonded interface.
- the atmosphere around the structure during the heat treatment is a reducing atmosphere.
- ⁇ Reduction treatment> In bonding after hydrophilization treatment, that is, temporary bonding, most of the bonding surfaces are bonded to other bonding surfaces through OH groups, oxide films, or water molecules (hydroxyl layer, etc.) adhering to these. Is done. Since the surface roughness or unevenness on the surface of the joint surface does not completely disappear due to the contact at the time of temporary joining, the joint interface after provisional joining is formed between the joint surfaces having the unevenness. It is useful to perform reduction treatment at the time of the main bonding with respect to the bonding interface at the time of the temporary bonding and promote the formation of the new surface by removing the oxide film. In other words, the rate of oxide film removal can be improved by accompanying a reduction process in the heating during the main bonding.
- the reducing atmosphere may be formed by introducing a reducing gas into an atmosphere of a structure including a substrate and a plurality of chips, or into a chamber that performs main bonding.
- a reducing gas it is preferable to use hydrogen molecules, hydrogen radicals, hydrogen plasma, formic acid gas, or the like.
- hydrogen molecules and hydrogen-containing gases such as hydrogen radicals are small in size and can enter gaps due to irregularities at the bonding interface. Moreover, it is easy to diffuse also in the junction interface which is actually contacting. Therefore, by using these hydrogen-containing gases, the oxide film at the temporary bonding interface can be efficiently reduced during the main bonding.
- the atmosphere of the structure including the substrate and the plurality of chips or the main bonding chamber Before forming the reducing atmosphere, it is preferable to evacuate the atmosphere of the structure including the substrate and the plurality of chips or the main bonding chamber. There is a minute gap in the temporarily bonded joint interface due to the minute surface roughness of the joint surface. Therefore, by introducing the reducing gas after evacuation, the reducing gas can enter the minute gaps of the evacuated temporary bonding interface more efficiently. Furthermore, oxygen, contaminants, and the like that can hinder removal of the oxide film by the reduction treatment can be removed in advance from the atmosphere by evacuation.
- evacuation and introduction of a reducing gas may be repeated.
- Pressurization may be performed after the reduction treatment. That is, the reduction process of the bonding interface is efficiently performed while there are minute gaps at the bonding interface, and the pressure is applied after the reduction process to eliminate or reduce the gap between the reduction-bonded bonding surface or the new surface.
- the effective bonding area can be increased in a clean state.
- the pressure applied when the chip is attached to the substrate that is, during temporary bonding.
- the temporary bonding it is only necessary to obtain a bonding strength that prevents the chip from being displaced by subsequent handling. Therefore, by reducing the pressure or pressure applied at the time of temporary bonding, the unevenness of the bonding interface after temporary bonding remains without being crushed, and a state where there is a minute gap at the bonding interface can be maintained. By doing so, it becomes easy to introduce the reducing gas into the gap at the bonding interface during the reduction treatment.
- Such a reduction treatment can be applied to bumps (metal regions) formed of copper (Cu), but is not limited thereto, and can also be applied to solder materials, gold (Au), or alloys thereof. .
- the main bonding chamber 81 that performs the main bonding as the heating means 80 is provided with a heater 82, and the structure can be heated to a desired temperature.
- the main bonding chamber 81 has a top plate 82 at the top, and a plurality of openings 83 are opened in the top plate 82 in order to introduce a gas such as hydrogen radical into the chamber.
- the main bonding chamber 81 is provided with a hydrogen radical source (not shown), and hydrogen radicals are introduced into the main bonding chamber 81 from the hydrogen radical source through the opening 82 of the top plate 81.
- a vacuum pump 84 is connected to the main bonding chamber 81, whereby the atmosphere in the chamber 81 can be evacuated.
- a pair of chips CP having provisionally bonded bumps MR is placed in a chamber 81. As shown in FIG. Since the surface activation treatment and the hydrophilization treatment are performed, a thin oxide film or an OH group layer (hydroxyl layer 44) is formed on the surface of the bump MR, or water molecules adhere to the surface. There are layers.
- the main bonding chamber 81 is evacuated by the vacuum pump 84 so that the pressure is about 5 Pa.
- the hydrogen radical source may operate at 250 W and 27 MHz to convert 100% hydrogen gas into plasma, and radical species may be introduced into the main bonding chamber 81 from the plasma.
- the hydrogen radical is introduced at a flow rate of 100 sccm through the opening 83 of the top plate 82 into the main bonding chamber 81 in a down flow, and is maintained for 5 minutes so that the pressure in the main bonding chamber 81 becomes 50 Pa.
- the temperature of the structure is maintained at 150 degrees Celsius.
- a pair of chips is described here as a configuration diagram, it may be performed on a substrate on which a plurality of chips are mounted.
- the pressurizing means is not described here, a means for pressurizing from above or in the vertical direction in the same chamber may be provided. Further, after the reduction treatment, a vacuum atmosphere, an inert atmosphere, or a nitrogen atmosphere may be handled, transferred to a heating and pressurizing chamber, and pressurized.
- a joining apparatus 401 as shown in FIG. 34 may be used.
- the bonding apparatus 401 includes a vacuum chamber 402 for controlling the atmosphere in which the objects to be bonded 491 and 492 are placed, and surface activation processing means 408 for performing surface activation processing on the bonding surfaces of the objects to be bonded 491 and 492.
- the position shift measuring means 428M, 428e, and 428f for measuring the position shift between the objects to be bonded 491 and 492, and the objects to be bonded 491 and 492 on the bonding surface are corrected in order to correct the position shift between the objects to be bonded 491 and 492.
- Vacuuming means 405, 406, 407 and reduction processing means 441, 442, 445 are configured. With these structures, the inside of the chamber (vacuum chamber) 402 can be decompressed using the bonding apparatus 1, and surface treatment, bonding, pressurization, heating, and reduction treatment of the objects to be bonded 491 and 492 can be performed.
- the head 422 is heated by a heater 422 h built in the head 422, and the temperature of the object to be bonded 492 held by the head 422 can be adjusted.
- the stage 412 is heated by a heater 412 h built in the stage 412, and the temperature of the article 491 on the stage 412 can be adjusted.
- the head 422 can also cool the head 422 itself to near room temperature rapidly by an air cooling type cooling device or the like built in the head 422. The same applies to the stage 412.
- the heaters 412h and 422h (particularly 422h) function as heating / cooling means for heating or cooling the metal bumps MR.
- the head 422 is moved (lifted / lowered) in the Z direction by the Z-axis lifting / lowering drive mechanism 426.
- the Z-axis raising / lowering drive mechanism 426 can also control the applied pressure at the time of joining based on signals detected by a plurality of pressure detection sensors (load cells, etc.) 429 and 432.
- the reducing gas source 441 is a hydrogen radical source or a formic acid gas source.
- the reducing gas is introduced from the reducing gas source 441 through the valve 442 and the introduction interval 443 into the chamber 402 at a predetermined flow rate.
- the reduction process and the heating process or the heating and pressurizing process are performed in the same chamber 402, but the present invention is not limited to this.
- the reduction process is performed in one chamber
- the heating (pressurization) process is performed in another chamber
- formic acid is used, the reduction process is performed in the same chamber.
- a configuration for heating (pressurizing) may be adopted.
- ⁇ Production efficiency of COW mounting according to the present invention> By adopting a bonding method having temporary bonding and main bonding according to the present invention, the production efficiency of COW mounting is remarkably improved as compared with the conventional bonding method. For example, by repeatedly performing temporary bonding and main bonding to the bonding portion on the substrate corresponding to each chip, and comparing with a case where a predetermined number of chips are mounted on the substrate, the effect of the present invention can be improved. I can understand.
- the production time can be shortened compared to 14 hours, which is the time required for performing temporary joining and main joining using the conventional joining method described above. Understood. Although the time required for the main bonding depends on the heating temperature, it can be less than 7 hours.
- FIG. 6 has shown the flowchart of the joining method which concerns on the modification of the 1st Embodiment of this invention including this process (process S5).
- the water adhesion treatment may be performed by spraying water on at least the metal region of the chip side joint surface.
- the water to be sprayed may be gaseous (gas or water vapor) or liquid (mist or water droplets), and the form of water is not limited to these.
- the water adhesion treatment may be performed by providing a water tank for storing liquid water and immersing at least the metal region of the chip-side joint surface in this water. As a result, a larger amount of water can be more reliably adhered to the joint surface subjected to the surface activation treatment.
- the chip side bonding surface is brought into contact with the liquid water in a state of facing down (face down), and water is attached to the chip side bonding surface. Can do.
- the metal region protrudes from another region on the chip-side bonding surface, water may be attached only to the protruding metal region by contact with the liquid water.
- Water (H 2 O) is further adhered to the surface once hydrophilized and a water layer is formed, so that the concave portion of the chip side bonding surface is filled with water (H 2 O), and the surface roughness of the bonding surface is increased.
- the thickness can be reduced. It is considered that the substantial bonding area at the time of temporary bonding is increased by contacting the chip-side bonding surface and the bonding portion of the substrate through this water layer.
- OH groups are further adhered by water after that.
- the production density of can be increased sufficiently.
- the humidity is generally 30% to 50%, and the amount of water for generating OH groups may not be sufficient.
- the average thickness of the water layer to be adhered is approximately equal to or greater than the surface roughness of the joint surface before water adhesion.
- the relatively low metal region may not contact the substrate sufficiently unless force is applied to the chip to cause deformation. Even in this case, a layer of water molecules having a thickness approximately equal to or greater than the height difference between the plurality of metal regions is formed on the metal region, so that a predetermined amount of water molecules can be obtained via the water layer. A strong temporary bond is obtained. (See Figure 8)
- the layer of water formed on the bonding surface is in a direction perpendicular to the bonding surface between the bonding surface of the chip and the substrate during the step S3 of attaching the chip to the substrate (temporary bonding). It is considered that there is a function to increase the mutual adsorption force or suction force acting on the. As a result, compared with the case where there is no water layer, the temporary bonding force increases according to the area of the portion where the water layer is formed between the bonding surfaces of the chip and the substrate.
- the water layer formed on the plurality of metal regions of the chip also generates a suction force acting in a direction parallel to the bonding surface, so that by pulling the chip toward the bonding portion of the substrate, Chip self-alignment can be realized.
- a plurality of metal regions of the chip each of which has a water layer formed by water adhesion treatment, and a corresponding bonding region on the substrate, are aligned along a direction perpendicular to the bonding surface.
- the chip When the chips are brought closer to each other, the chip may be displaced in a direction parallel to the bonding surface with respect to the substrate (FIG. 9A).
- the water layers come into contact with each other, and a water layer is formed that bonds between the metal region of the chip and the corresponding bonding region on the substrate (see FIG. 9 (b)).
- a hydrophilized metal region and a hydrophobized region are provided on the chip-side joint surface, and the hydrophilized joint region and the hydrophobic region are formed at the joint portion of the substrate so as to correspond to them. It is also possible to adopt a configuration in which the substrate-side hydrophobized region is provided.
- the chip is attached to the corresponding joint portion of the substrate so that the metal region of the hydrophilic chip and the joint region of the substrate are in contact with each other, there is a hydrophilic region and a hydrophobic region.
- the surface tension generated in the step increases, positioning accuracy is further improved, and the chip can be temporarily bonded at a predetermined position at a high speed.
- the hydrophilized region and the hydrophobized region can be arranged on substantially the same plane. Therefore, the thickness of the final product of the device can be reduced and the density can be increased.
- the adhesion of water after the hydrophilization treatment may be performed only on the metal region of the chip side bonding surface, and in addition to the metal region of the chip side bonding surface, the metal region of the chip side bonding surface is bonded correspondingly. May be performed on the bonding region formed in the bonding portion of the substrate.
- a clean bonding interface is formed between the chip and the substrate, and a structure including the chip and the substrate having good conductivity and high mechanical strength can be manufactured.
- the heat treatment for the main bonding is performed only once, it is possible to bond a plurality of chips on the substrate with high production efficiency. Play.
- the water adhesion treatment sufficient water is adhered to the bonding surface, so that the bonding force between the chip and the substrate by temporary bonding is enhanced.
- FIG. 10 is a flowchart showing a method of bonding a plurality of layers of chips to a substrate according to the second embodiment of the present invention. Since the processing from step S11 to step S13 for attaching the first layer chip to the substrate is the same as the processing from step S1 to step S3 of the first embodiment, description thereof is omitted here.
- one layer of chips is mounted on the substrate, whereas in the second embodiment, a plurality of layers of chips are mounted on the substrate.
- the chips stacked over the plurality of layers are formed with a first bonding surface corresponding to the chip-side bonding surface of the first embodiment. And a second joint surface located on the back side of the first joint surface.
- step S11 to step S13 are completed, a predetermined number of chips for one layer are mounted on the substrate.
- Each chip is mounted on the substrate such that the first bonding surfaces of a predetermined number of chips constituting the second layer are in contact with the second bonding surfaces of the chips constituting the first layer.
- a desired number of chip layers are mounted on the substrate by performing the same mounting operation.
- step S14 Surface activation treatment and hydrophilic treatment are performed on the new (second layer) chip side bonding surface (first bonding surface) (step S14).
- a surface activation process and a hydrophilization process are performed on the second bonding surface of the first layer chip attached to the substrate (step S15).
- step S16 a predetermined number of second layer chips corresponding to the number of first layer chips subjected to step S14 are respectively attached to the second layer chips subjected to step S15.
- the attachment of the second layer chip to the first layer chip is performed by repeating the attachment of the second layer chips one by one until the attachment of a predetermined number of chips to be attached is completed.
- this step S16 is completed, two layers of chips are temporarily bonded onto the substrate (FIG. 11B).
- i-th layer chips are obtained by attaching the first bonding surface of the i-th layer (i is 3 or more) chip to the i-1th layer chip already mounted on the substrate. Is mounted on the substrate.
- step S14 Surface activation treatment and hydrophilization treatment are performed on a new predetermined number of chips until the i-th layer reaches a desired number of layers (N layers), and the predetermined number of chips on the uppermost layer attached are processed.
- step S15 surface activation treatment and hydrophilization treatment are performed (step S15), and temporary bonding (step S16) is repeated (S17, S18) to form an N-layer temporary bonding chip layer on the substrate.
- step S16 temporary bonding
- step S17, S18 temporary bonding
- step S19 the structure including the N-layer temporary bonding chip layer and the substrate thus formed is heated.
- the type and flow rate of the gas forming the atmosphere can be adjusted.
- pressure can be applied to the structure formed by temporary bonding between the chip and the substrate so that pressure is applied to the bonding interface.
- the temperature or the time profile of the above force or pressure is the conditions of temporary bonding, the thermal characteristics of the material forming the bonding interface, the thermal characteristics of the material forming the chip or the substrate, the atmosphere during the heating process, the heating process. It can be adjusted according to the characteristics of the device, the number N of chip layers, and the like.
- the bonding method according to the second embodiment of the present invention the same effects as those of the bonding method according to the first embodiment can be obtained, and further, the resin or the like that reduces the electrical or mechanical characteristics of the bonding interface can be used. There is an effect that a predetermined N-layer chip layer can be formed on the substrate in a clean process without using a substance. Further, in the conventional bonding method, it is necessary to apply a resin every time the temporary bonding of each chip layer is completed. According to the second embodiment of the present invention, such a resin treatment process is performed. Therefore, provisional bonding of a plurality of chips onto a substrate can be performed very efficiently.
- FIG. 12 is a flowchart showing another example of a method for bonding a plurality of layers of chips to a substrate according to the second embodiment of the present invention.
- a water adhesion process process S21
- a hydrophilization process process S11 and process S14
- the layer of water formed on the bonding surface is attached in the step S13 of attaching the chip to the substrate (temporary bonding) and in the step of attaching the i-th layer chip on the i-th layer chip.
- S16 it is considered that there is a function of increasing the mutual adsorption force or suction force acting in the direction perpendicular to the bonding surface between the bonding surfaces of the chip and the substrate and between the bonding surfaces of the chips.
- the temporary bonding force increases according to the area of the portion where the water layer is formed between the bonding surfaces of the chip and the substrate.
- the water layer formed on the plurality of metal regions of the chip also generates a suction force acting in a direction parallel to the bonding surface, so that by pulling the chip toward the bonding portion of the substrate, Chip self-alignment can be realized (see FIG. 9).
- Chip self-alignment can be realized (see FIG. 9).
- the N-layer chip is stacked on the substrate, it is necessary to position the first bonding surface of the upper-layer chip with respect to the second bonding surface of the lower-layer chip between two upper and lower adjacent chips. Since the self-alignment function also works between two layers of chips adjacent to each other in the vertical direction, the positioning accuracy of the bonding apparatus can be set relatively low, which further simplifies the bonding apparatus and speeds up the positioning process. It becomes possible.
- heat treatment may be performed after provisional bonding of the chips of each layer (step 4 (S4)).
- the heat treatment (step 5 (S5)) of the bonded body after the temporary bonding of the N-layer chip may be omitted.
- the plurality of chips bonded to the substrate may include a plurality of types of chips.
- the plurality of types of chips may include a plurality of chips having different sizes and sizes in the XY directions.
- both the first type chip CP11 and the second type chip CP12 may be arranged in each junction set in the vertical and horizontal directions with a dimension of p0. Good.
- the chips CP11 and CP12 are both arranged in the vertical and horizontal directions with a pitch p1, and the pitch p1 is equal to the pitch p0.
- the size of the second type chip CP12 is smaller than the size of the first type chip CP11.
- the size of the second type chip CP12 and the size of the first type chip CP11 are both smaller than the joint portion.
- a clean bonding interface is formed between a chip and a substrate and between the chips, and a structure including a multi-layer chip and a substrate having good conductivity and high mechanical strength is manufactured. Can do. It is said that the heat treatment for the main bonding is performed only once after attaching all the chips over the plurality of layers, so that the chips of the plurality of layers can be bonded on the substrate with high production efficiency. There is an effect.
- the plurality of chips having a clean bonding interface more efficiently.
- a substrate including the substrate can be manufactured.
- FIG. 14 is a top view showing a schematic configuration of a chip mounting system (electronic component mounting system) 1.
- a chip mounting system electronic component mounting system
- directions and the like are shown using an XYZ orthogonal coordinate system for convenience.
- the chip mounting system 1 includes surface activation means, hydrophilization processing means, and chip attachment means for attaching the surface-treated chip to the substrate, and is mounted on a substrate (chip mounting target substrate).
- a substrate chip mounting target substrate
- the chip mounting system 1 can bond a plurality of chips CP1 in the first layer on the target substrate WA.
- the chip mounting system 1 can also stack and bond a plurality of second-layer chips CP2 and the like on a plurality of first-layer chips CP1 arranged on the substrate WA.
- the chip mounting system 1 includes a chip supply device 10 that holds a plurality of chips and individually supplies chips to be bonded, and a chip transport unit from the chip supply device 10.
- a bonding apparatus 30 which is a chip mounting means for mounting the supplied chip on the substrate, a surface treatment apparatus 50 for performing surface activation treatment and hydrophilic treatment on the bonding surfaces of the plurality of chips and the substrate, and from outside the chip mounting system A chip and a substrate to be joined, and a loading / unloading unit 90 for unloading a substrate (a structure including the chip and the substrate) to which the chip is attached to the outside; a plurality of chips, the substrate, and the chip and the substrate; A transporting unit 70 that transports the structure including the transporting unit 90 between the loading / unloading unit 90, the chip supply device 10, the bonding device 30 and the surface treatment device 50 That.
- the heating means is not shown, but the heating means may be configured to be incorporated in the chip mounting system 1 or may be configured separately from the chip mounting system 1.
- the structure including the chip and the substrate is transferred to the heating device after temporary bonding by adopting a configuration in which the heating device is connected to the transfer unit 70. be able to.
- the heating means When the heating means is configured separately from the chip mounting system 1, the heating means may be a heating furnace for performing reflow of the solder material or a general heating furnace. In this case, since a plurality of structures including the chip and the substrate after temporary bonding can be subjected to heat treatment, the main bonding can be efficiently performed.
- the conveyance unit 70 conveys a plurality of chips to be bonded from the carry-in / out unit 90 to the surface treatment apparatus 50, and conveys the chips from the surface treatment apparatus 50 to the chip supply apparatus 10 after the surface activation process and the hydrophilization process are performed. .
- the transport unit 70 transports the substrate from the carry-in / out unit 90 to the surface treatment apparatus 50, and transports the substrate from the surface treatment apparatus 50 to the bonding apparatus 30 after the surface activation process and the hydrophilization process are performed. Further, after a predetermined number of chips are mounted on the substrate, the transport unit 70 transports the structure including the chips and the substrate from the bonding apparatus 30 to the carry-in / out unit 90.
- a surface treatment apparatus 50 shown in FIG. 14 includes a stage 53 that holds a substrate WA or a plurality of chips in a vacuum chamber, a particle beam source 51 that emits particles for surface activation treatment, and a hydrophilic treatment.
- a water inlet 54 for discharging water is provided, and the surface activation treatment and the hydrophilic treatment can be performed on both the plurality of chips and the substrate WA.
- the present invention will be described using the embodiment of the apparatus shown in FIG. 14, but the present invention is not limited thereto.
- the first chip of the uppermost layer in the structure including a plurality of chips and a substrate to which the plurality of chips are already attached is shown.
- the plurality of chips and the plurality of chips are already placed in place of the substrate WA at the position where the substrate WA in FIG. 14 is shown.
- the structure including the attached substrate may be arranged.
- one chamber may be provided for the surface activation treatment and another chamber may be provided for the hydrophilic treatment.
- one chamber is provided for surface treatment (surface activation treatment and hydrophilic treatment) of a plurality of chips, and another chamber is provided for substrate surface treatment (surface activation treatment and hydrophilic treatment). It may be provided.
- a chamber is provided for each treatment, and a total of four chambers are provided. May be. Moreover, it can be set as the structure which provides one or several chambers according to the process aspect of a surface activation process and a hydrophilization process, and the combination of the processing apparatus accommodated in each chamber can also be changed variously. .
- the surface treatment apparatus 50 is connected to a vacuum pump (not shown), and can reduce the atmospheric pressure inside the surface treatment apparatus 50 and increase the degree of vacuum. By increasing the degree of vacuum, the particle beam can be emitted from the particle beam source.
- the vacuum pump preferably has the ability to lower the atmospheric pressure in the surface treatment apparatus 50 to 10 ⁇ 5 Pa. In addition, it is possible to prepare a clean atmosphere by removing floating impurities and water molecules in the surface treatment apparatus 50 in advance by evacuation.
- a relatively small particle beam source or the like can be used, and the apparatus can be reduced in size by a relatively simple configuration.
- the particle beam source 51 may be configured such that particles to which predetermined kinetic energy is applied are radiated radially from a particle beam source toward a part of a substrate having a bonding surface in which a plurality of bonding portions are set. Good. At this time, by changing the position and orientation of the particle beam source, it is possible to irradiate the entire region where the bonding surface is set.
- the particle beam source 51 is attached to the oblique upper part of the stage 53 in the surface treatment apparatus 50, and emits particles to which predetermined kinetic energy is applied toward the surface of the substrate transported on the stage 53.
- the stage 53 is circular and can be rotated with the central axis of the stage 53 as a rotation axis. By rotating the stage 53 during the surface activation process, the amount of particles irradiated per unit area of the surface of the substrate WA is made uniform across the surface of the substrate WA, and the removal amount (thickness) of the surface layer is made uniform. Can be.
- the arrangement of the particle beam source in the chamber or the arrangement with respect to the object irradiated with the particle beam is not limited to the embodiment shown in FIG.
- Particle beam sources such as a neutral atom beam source, an ion beam source, and a fast atom beam source may be of a line type as shown in FIG.
- the line-type particle beam source has a line-type (linear) or elongated particle beam emission port, and can emit a particle beam in a line-type (linear) from the emission port.
- the length of the radiation port is preferably larger than the diameter of the substrate irradiated with the particle beam. When the substrate is not circular, the length of the radiation aperture is preferably larger than the maximum dimension in the direction in which the radiation aperture associated with the substrate moved relative to the particle beam source extends.
- the particle beam emitted from the line type particle beam source irradiates a linear region on the surface of the substrate at a certain time during the surface activation process.
- the line-type particle beam source is scanned in a direction perpendicular to the direction in which the radiation port extends while emitting the particle beam toward the substrate having the bonding surface.
- the irradiation region of the linear particle beam passes over all the joints of the substrate.
- the entire substrate is irradiated with the particle beam and surface activated.
- the line type particle beam source is suitable for irradiating the surface of a substrate having a relatively large area with a particle beam relatively uniformly. Further, the line type particle beam source can irradiate the particle beam relatively uniformly corresponding to various shapes of the substrate.
- the given kinetic energy is applied to the particles by applying an alternating voltage to the bonding surfaces of a plurality of chips or substrates using a plasma generator to generate a plasma containing particles around the bonding surfaces. And the ions of the ionized particles in the plasma can be accelerated toward the bonding surface by the voltage. Since the plasma can be generated in an atmosphere with a low degree of vacuum of about several pascals (Pa), the vacuum system can be simplified and the steps such as evacuation can be shortened.
- Pa pascals
- the plasma generator is preferably configured so that the kinetic energy of particles colliding with the surface-activated joint surface can be controlled in the range of 1 eV to 2 keV. It is considered that the above kinetic energy efficiently causes a sputtering phenomenon in the surface layer.
- a desired value of kinetic energy can be set from the range of the kinetic energy according to properties such as the thickness and material of the surface layer to be removed and the material of the new surface.
- the water gas supply unit 55, the valve 56, the gas supply pipe, and the water introduction port 54 constitute a hydrophilization treatment means for hydrophilizing the joint surface.
- the gaseous or liquid water supplied from the water gas supply unit 55 is introduced into the chamber of the surface treatment apparatus 50 from the water inlet 54 through the gas supply pipe according to the opening of the valve 56.
- the valve 56 may function as a mass flow and adjust the supply amount of water according to the degree of opening.
- the hydrophilic treatment means mixes the water gas (gaseous water or mist water) with the carrier gas in the water gas supply unit 55, so that the mixture of the water gas and the carrier gas becomes the surface treatment device 50. It may be configured to be introduced into the chamber. Furthermore, the hydrophilization treatment means is configured to adjust the humidity of the atmosphere in the surface treatment apparatus 50 by adjusting the mixing ratio of the water gas and the carrier gas and the flow rate of the gas passing through the valve 56. Also good.
- the hydrophilizing means may be configured to introduce air outside the chamber or outside the bonding apparatus into the chamber.
- the chip supply device 10 is a device that takes out each chip CP from the diced substrate and supplies each chip CP (CPi) to the bonding apparatus 30.
- the chip supply device 10 includes a protrusion 11 that lifts and supports only one chip from a plurality of chips, a chip transfer device 13 that conveys the chip lifted by the protrusion 11 to the bonding apparatus 30, and the like.
- the chip transfer device 13 includes a die picker 131 and a chip feeder 135. (See Figure 17)
- the chip supply device 10 may be configured such that a plurality of chips CP are generated by performing a dicing process therein. Specifically, a substrate WC having a plurality of electronic circuits is cut into chips in the vertical and horizontal directions.
- a plurality of chips CP that have already been subjected to dicing processing may be transported to the chip supply apparatus 10 after being subjected to surface activation processing and hydrophilization processing while being supported by the support substrate.
- production of the contamination particle etc. by a dicing process can be suppressed.
- a plurality of diced chips CP are placed on the dicing tape TE.
- Each chip CP is placed on the dicing tape TE in a face-up state (a state where a solder bump BU (not shown) as a metal region is directed upward).
- the cut chips CP are pushed up one by one by the protruding upper part (protruding needle) 11 of the chip supplying device 10 and delivered to the die picker 131 at the position PG1.
- the chip CP in the face-up state is turned upside down by the die picker 131 having a reversing mechanism and supplied to the bonding apparatus 30 in the face-down state.
- the die picker 131 sucks the chip CP in the face-up state at the tip (lower end) suction part, and is turned upside down by the reversing mechanism, and further moved upward in the face-down state, and then delivered to the chip feeder 135.
- the chip supplier 135 sucks the upper surface of the chip CP in the face-down state and moves toward the chip transport unit 39 side.
- a chip transport unit 39 which is a chip transport means, is a device that delivers the chips supplied from the chip supply device 10 one by one to the bonding unit 33 (specifically, the head unit 33H). .
- the chip transport unit 39 includes a plurality of (N; here, three) plate portions 391.
- Each plate portion 391 has a thin plate shape, and has a thickness of, for example, about several mm (millimeter) (preferably about 1 mm to 2 mm or less).
- the plurality of plate portions 391 are arranged at equiangular intervals around the axis AX in a top view.
- the chip transport unit 39 also includes a drive unit 392 that rotationally drives the plurality of plate units 391 all at once.
- the chip transport unit 39 can rotate the plurality of plate units 391 around a predetermined vertical axis AX using the drive unit 392.
- the chip CP supplied from the chip supply device 10 is supplied by any one of the three plate portions 391 (specifically, 391a, 391b, 391c) of the chip transfer portion 39 (for example, 391b). Received. Thereafter, after the plate portion 391 rotates 180 degrees, the chip on the plate portion 391 is delivered to the bonding portion 33 (head portion 33H).
- a certain chip CP is received by the plate portion 391b at the delivery position PR1 and held by the plate portion 391b.
- another chip CP is already received and held on the plate portion 391a by the plate portion 391a having advanced to the position PR9.
- the chip transport section 391 rotates around the axis AX (clockwise) by an angle ⁇ (60 degrees), as shown in FIG. 19, the chip CP on the plate section 391a is positioned immediately below the head section 33H.
- the head portion 33H is slightly lowered from the reference position where it does not interfere with the chip CP, sucks the chip CP at the front end portion (lower end portion) of the head portion 33H, and receives the chip CP from the plate portion 391a.
- the head portion 33H slightly rises and returns to the reference position. Thereby, the chip CP on the plate portion 391a is transferred to the head portion 33H. In this way, the chip CP is transferred from the plate portion 391a to the head portion 33H.
- the chip transport section 391 (specifically, its plate section 391a) is located between the upper chip CP and the lower substrate WT at the delivery position PR2 (the same position as the bonding position on the XY plane).
- the plate portion 391c moves to the receiving position PR1. In this state, another chip CP is received by the plate portion 391c at the receiving position PR1. At this time, the chip CP is already placed on the plate portion 391b by the above-described operation.
- Rotation of this angle ⁇ causes the plate portion 391a to move away from the position directly below the head portion 33H.
- the bonding position (X, Y) can be directly seen from the head portion 33H.
- the head portion 33H is lowered, and the chip CP attracted and held by the head portion 33H is lowered to a position PG7 (not shown).
- the chip CP adsorbed at the tip of the head portion 33H is placed on the substrate WA installed on the stage 31.
- an alignment operation or the like as described later is executed, and the chip CP is placed at a desired position on the substrate WA.
- the head portion 33H rises and returns to the reference position again, and interference between the plate portion 391a and the head portion 33H is avoided.
- the plate portion 391b reaches the delivery position PR2, and the delivery operation of the chip CP from the plate portion 391b to the head portion 33H is executed.
- the rotation operation of the angle ⁇ is further performed, and the plate portion 391a is moved to the receiving position PR1 this time, and the receiving operation of the chip CP by the plate portion 391a is performed.
- each chip CP can be supplied for each rotation operation of the angle ⁇ by the rotary chip transport unit 39. Specifically, after a certain chip is placed, the next chip can be supplied by rotational movement at an angle ⁇ (for example, 60 degrees). Accordingly, it is possible to sequentially supply a plurality of chips CP at a relatively short time interval as compared with the case where the chips CP are conveyed one by one (reciprocal conveyance) from the position PR1 to the position PR2. That is, it is possible to shorten the cycle time in chip supply. In particular, the larger the number of plate portions 391, the shorter the time interval for attaching the chips.
- chip protrusions are placed downward on the three plate portions 391 of the chip transport unit 39, but it is preferable that the metal regions of the chips do not contact the chip transport unit 39. .
- the three plate portions 391 of the chip transport unit 39 may be configured to support a part of the chip-side bonding surface so as not to touch the metal region of the chip. Thereby, the metal state of the chip can maintain the surface state when the hydrophilic treatment is completed after the hydrophilic treatment is completed and before the temporary bonding is performed.
- a concave portion 63 may be formed so that the bump does not contact the plate portion 391 at a portion corresponding to the inner support portion 61, the outer support portion 62, and the bump so as to support both or any one of the portions.
- FIG. 20 a configuration in which the chip is supported by the inner support portion 61 and the outer support portion 62 is shown, but the chip may be supported by either the inner support portion 61 or the outer support portion 62 ( FIG. 21 (a) and (b)).
- the outer support part 62 is in contact with the outer peripheral part of the chip, and the area surrounded by the concave portion 63 of the plate part 391 and the surface on the side where the chip is supported is vacuum-adsorbed.
- the chip By evacuating the hole 64, the chip can be fixed and supported on the plate portion 391 (FIG. 21B).
- the bonding apparatus 30 includes a stage 31 that supports a substrate, a bonding unit 33 that holds and attaches a chip to the substrate, an imaging unit (camera) 35, a position recognition unit (not shown), and the like.
- the bonding unit 33 includes a head unit 33H that holds the chip and moves it in the Z direction, and a head drive unit 36 that moves the head unit 33H in the Z direction or rotationally moves it in the ⁇ direction.
- the imaging units (cameras) 35a and 35b are attached to the bonding unit 33, pass through the mark portion attached to the chip from the substrate and the head 33H in the Z direction, and are optical path changing members (not shown) provided in the bonding unit 33. ) To image light reflected in the horizontal direction (X direction). Using the imaging units (cameras) 35a and 35b, the chip marks and the corresponding marks on the substrate are imaged, and the XY direction position of the stage and the ⁇ of the head 33H are set so that these marks have a predetermined positional relationship. Directional position can be controlled. Thereby, the positioning of the chip on the substrate can be efficiently performed with high accuracy.
- the chip transport unit 39 When the chip transport unit 39 receives the chip CP from the chip supplier 135 at the position PG3 in FIG. 17 and the position PR1 in FIG. 18, the chip CP is rotated around the central axis AX by the head unit 33H ( The sheet is conveyed to PG5 in FIG. 17 and position PR2 in FIG. The chip CP reaches the delivery position PG5 in the face-down state through such a transport operation.
- the head portion 33H of the bonding portion 33 receives the chip CP by suction.
- the stage 31 is moved in the X direction and the Y direction, and a portion (substrate bonding portion) where the chip CP of the substrate WA is to be temporarily bonded is disposed directly below the head portion 33H.
- positioning between the chip substrates is performed using the imaging units (cameras) 35a and 35b, and the head unit 33H of the bonding unit 33 is lowered to bring the chip-side bonding surface into contact with the corresponding bonding unit on the substrate.
- the bonding portion may be configured so that pressure can be applied between the chip-side bonding surface and the bonding portion of the substrate at the time of contact.
- a heater for heating the held chip may be provided in the head portion 33H of the bonding portion 33.
- the portion corresponding to the bonding portion 33 is in the horizontal direction or in-plane direction (XY direction) parallel to the substrate surface along the beam of the cantilever structure supported in the horizontal direction in the apparatus. It is configured to be able to move to.
- the cantilever structure has low rigidity, and when a force is applied during chip mounting, the cantilever beam bends in the Z direction. For this reason, the force that can be applied at the time of contact between the chip and the substrate is extremely limited, and usually only a maximum force of 2 to 3 kgf (weight kilogram), that is, about 20 to 30 N can be applied.
- a pressure of 20 to 30 N is sufficient because the chip is temporarily temporarily bonded with resin or flux. Also, even if solder bonding is performed on the spot, it is heated and melted, so a large pressing force is not required.
- the head (or bonding part) is moved, and in some cases a plurality of A configuration having a head was employed to increase the speed.
- bonding is performed at a temperature lower than the melting point of the metal region as in the bonding method of the present invention, only a portion in contact with the interface can be bonded, and thus a relatively high pressure is required.
- the pressurization at the time of temporary joining can be a current solution that enables mass production of joining. Therefore, in order to form a good bonding interface even below the melting point of the metal region, a high pressure is applied to the bonding interface between the chip and the substrate to promote deformation of the metal region and increase the substantial bonding area. Can be made. In addition, water molecules remaining at the interface can be pushed out to ensure a strong bond between OH groups.
- FIG. 31 shows an example of a bonding apparatus (bonding apparatus 30) configured to be able to apply a high pressure when the chip is attached to the substrate.
- the bonding portion 33 is fixed, and is configured to move in the Z direction and the rotation direction with respect to the bonding portion 33 to which the head 33H is fixed. That is, the bonding apparatus 30 includes a stage 31, a bonding unit 33, and a frame 34 that fixes the stage 31 in the Z direction and fixes the bonding unit 33 in the XY direction.
- the frame 34 is a stage support part 34A that supports the stage 31 so that it is movable in the XY direction and does not move in the Z direction, and a bonding part support that fixes and supports the bonding part 33 so as not to move in the XY direction. It may be configured to include a portion 34B, and a column portion 34C that fixes and connects the stage support portion 34A and the bonding portion support portion 34B in a predetermined positional relationship.
- the stage support part 34A and the bonding part support part 34B are configured in a plate shape in the XY directions, and the column part 34C fixes the stage support part 34A and the bonding part support part 34B so as to be parallel to each other.
- the support column part 34C is configured to have a plurality of support columns.
- the stage support unit 34A and the bonding unit 33 are fixed at a predetermined interval. It is preferable that Furthermore, it is preferable that the head 33H is fixed so as to be perpendicular to the surface of the substrate WA through the bonding portion support portion 34B.
- the rigid frame 34 can be configured, and the head 33H can press the chip CP to be supported against the substrate WA with a high pressure.
- the frame 34 is preferably formed of a cast metal such as steel.
- Chip supply to the bonding unit 33 that does not move with respect to the frame 34 or the bonding apparatus 30 is performed from the chip supply apparatus 10 using the chip transport unit 39.
- Chip-side bonding of chips to be bonded after completion of the above hydrophilization process, before the chip is mounted on the substrate, or before the chip is mounted on the second bonding surface of the chip already mounted on the substrate You may provide the apparatus (water adhesion means or water adhesion apparatus) which has a hole for making water adhere to a surface or a 1st junction surface.
- the water adhesion device may be provided in the chip transport unit 39, or may be provided in the chip supply device 10 or the bonding device 30.
- the water adhering means may be configured such that the hole is formed as a water injection port 65 and water is injected from the water injection port 65.
- the water injection port 65 may be provided in a portion attached to the plate portion 391 so as to be opened in the same direction as the vacuum suction hole 64.
- the water injection port 65 is disposed on a rotation circle around the axis AX of the vacuum suction hole 64.
- the vacuum suction hole 64 and the water injection port 65 form an angle ( ⁇ ) with the axis AX of the rotation center of the chip transport unit 39 as a reference.
- the plate portion 391 rotates by an angle ( ⁇ ), and the chip-side bonding surface (first bonding) of the chip in which the water ejection port is adsorbed to the head portion 33H When coming to a position facing the surface), gas or liquid water is ejected from the water ejection port toward the chip side joining surface (first joining surface) of the chip.
- the water injection port is disposed in each of the N plate portions 391 of the chip transfer unit 39.
- the chip-side bonding surface of the chip is opened by opening the water injection port provided in the plate portion 391 that has transferred the chip.
- water can be sprayed toward the first joint surface.
- the vacuum suction hole 64 may function as a water ejection port as a modification of the water ejection port.
- the vacuum suction hole 64 is configured to be connected to a water supply source as well as to a vacuum pump (not shown).
- the vacuum suction hole 64 is connected to a vacuum pump when the chip is sucked and while the chip is sucked, and is disconnected from the water supply source to vacuum suck the chip.
- the connection to the vacuum pump is cut off and the water supply source is connected so that the gaseous or liquid water flows in the direction opposite to the direction in which the gas flows during evacuation.
- it is configured.
- the vacuum suction hole 64 as a water ejection port in this way, the vacuum suction provided on the plate portion 391 of the chip transport portion 39 immediately after the chip is transferred from the plate portion 391 to the head portion 33H. Water can be sprayed toward the chip-side joint surface through the water injection port that is a hole. (See Figure 23)
- water molecular gas can be ejected from each vacuum suction hole of the N plate portions 391 of the chip transport unit 39.
- the water molecular gas is jetted from the vacuum adsorption holes provided in the plate portion 391 that has transferred the chip.
- the water injection port 65 is fixed to the chip supply apparatus 10 or the bonding apparatus 30 and is in a movement path from the chip take-out position to the bonding position. It may be provided. Even if the head portion 33H of the bonding portion 33 is disposed at the tip of each plate portion 391, it is configured so that water can be ejected to the chip-side joint surface when the conveyed chip passes through the water ejection port 65. Good.
- the plate unit 391 of the chip transport unit 39 is configured to transport the chip with the chip face-down (downward) and the chip-side joint surface opened downward, and the water ejection port is configured to supply the chip.
- the device 10 or the bonding device 30 may be configured to be fixed upward at a predetermined position on the chip movement path by the rotation of the chip transport unit 39.
- a head section 33H of the bonding section 33 may be disposed at the tip of each plate section 391 as shown in FIG. .
- the configuration in which the chip-side joining surface is opened downward and conveyed is not limited to the embodiment shown in FIG.
- the plate portion 391 receives the bump (metal region) in a face-up state, and the water injection port is from above in the movement path from the chip take-out position to the joining position. It may be configured to inject water downward.
- the water injection port is configured to inject water from bottom to top in the movement path from the chip take-out position to the joining position, and the plate portion 391 receives the chip in a face-up state.
- the plate portion 391 may be configured to rotate around the longitudinal axis of the plate portion 391 so that the chip-side bonding surface or the first bonding surface faces the water injection port when passing over the water injection port.
- an even number (particularly, four or more) of plate portions 391 are arranged around the axis AX at substantially equal angular intervals (at intervals of angle ⁇ ).
- the head portion 33H of the bonding portion 33 is disposed at the tip of each plate portion 391. Therefore, by arranging the even number of plate portions 391, every time the chip transport portion 39 rotates by the angle ⁇ , the chip receiving operation at the position PR1, the chip temporary bonding operation at the position PR2, and the position PR3. Since the water adhesion operation is performed at the same timing, the time required for a series of steps of chip delivery, water adhesion operation, and temporary bonding can be shortened.
- the chip supply device 10 or the bonding device 30 is used as a device (water adhesion device) for adhering water to the metal region of the chip-side bonding surface or the first bonding surface.
- the water tank 66 is preferably disposed at a predetermined position on the chip passage route in the chip supply device 10 or the bonding device 30 by the rotation of the chip transport unit 39.
- the water tank 66 may be disposed at a position where the water injection port 65 of FIG. 24 is provided.
- a configuration in which the head portion 33H of the bonding portion 33 is disposed at the tip of each plate portion 391 may be employed.
- the chip adsorbed on the head portion 33H is positioned on the water tank and moves downward ( ⁇ Z direction), so that the chip-side joint surface comes into contact with liquid water contained in the water tank. By contact with the water in the water tank, a large amount of water can be reliably adsorbed on the chip-side joint surface.
- the metal area of the chip-side bonding surface is formed in a bump shape (as a protrusion)
- only the metal area on the bump can be brought into contact with liquid water by controlling the amount of descending of the chip. It becomes possible.
- the position in the vertical direction (Z direction) of the water surface of the chip in the water tank may be controlled to a constant or predetermined position by a sensor (not shown) that detects the water level in the water tank.
- a water tank may be provided with a lid (not shown) so that the water tank can be opened and closed.
- a lid By capping the water tank with the lid, for example, when the water tank is not used, unnecessary evaporation of water molecules into the chip supply device 10 or the bonding device 30 can be prevented.
- Example 1 In the first and second embodiments, at the time of temporary bonding, it is preferable to pressurize the chip-side bonding surface to be bonded and the bonding portion of the substrate while heating them at a relatively low temperature. This is preferable because it does not require strict conditions for flatness.
- the upper end portion of the metal region MR of the flatly formed chip is generally not polished in many cases.
- the surface roughness of the upper end portion of the unpolished metal region MR is, for example, 100 nm to 200 nm Ra.
- the surface roughness is relatively high, so even after the surface activation treatment and the hydrophilic treatment are performed on the surface of the metal region MR. In some cases, sufficient bonding strength cannot be obtained by bonding. Therefore, in this case, at the time of temporary bonding, the chip metal region MR is heated to a temperature of 100 ° C.
- the substantial contact area is increased when the flatness of the bonding surface is increased (for example, when the surface roughness is several nanometers), the bonding by the original hydroxyl group (OH group) becomes a strong bonding, It is possible to obtain sufficient bonding strength even at low pressure bonding.
- the flatness of the joint surface is low (for example, the surface roughness is several tens to several hundreds of nanometers)
- the metal region is substantially crushed by pressing (tens of M to several hundreds of MPa).
- the substantial junction area can be increased by enlarging the contact area or promoting diffusion by heating (eg, 150 ° C.) at about several hundred degrees Celsius to promote the movement of atoms at the junction interface.
- a chip having about 500 circular metal regions with a diameter of 30 ⁇ m was heated so that the metal region was 150 ° C. to 200 ° C., and temporarily bonded to the silicon substrate under the condition of applying a pressure of 50 MPa to 400 MPa to the metal region. .
- the shear strength was 5 gf per one metal region. This strength is a sufficient bonding strength so that the chip does not deviate from a predetermined mounting position on the substrate when the structure of the chip and the substrate is transported after the temporary bonding.
- the main assembly was performed by heating the structure including the chip and the substrate temporarily bonded under the above heating and pressure conditions at 200 ° C. for 1 hour.
- a shear test was performed on the structure including the chip and the substrate that were joined together, it was found that the shear strength was 20 gf per metal region, which was relatively high.
- heating may be performed using a heater embedded in the head portion 33H of the bonding portion 33.
- the heat from the heater passes through the head portion 33H and is transmitted to the chip CP adsorbed by the head portion 33H, and as a result, the metal region of the chip is heated.
- Heat may be emitted as a pulse using the heater of the head portion 33H (pulse heating is performed).
- the temperature of the chip can be raised from about 60 ° C. to about 150 ° C. within one second (FIG. 32).
- FIG. 32 illustrates this example.
- the heater starts pulse heating, and the temperature of the chip reaches 60 ° C. to 150 ° C. in about 0.5 seconds.
- the contact state and the chip temperature are maintained for 0.5 seconds. Thereafter, the contact state is released by starting to raise the head portion, and at the same time, the heating of the heater is stopped and cooled.
- the temperature of the chip returns to about 60 ° C. again. Therefore, even if the temperature starts to be increased after contact, the chip can be efficiently heated to a desired temperature within a sufficiently short time. Thereby, if it heats before joining, a joint surface will be oxidized and it can avoid or suppress that a joint failure arises.
- the head portion 33H is always heated while the temporary bonding is repeated over a plurality of chips. Accordingly, since the chip CP is heated from the time when the chip CP is delivered to the head portion 33H, the metal region MR can be heated to a predetermined temperature in a short time, for example, 1 second to several seconds.
- a heater may be embedded in the stage 31.
- the bonded portion of the substrate is heated by the metal region of the heated chip coming into contact with the bonded portion of the substrate. Is preferred.
- the stage 31 is formed of a glass material, heat radiation from the heated substrate to the stage 31 is limited, so that the bonded portion of the substrate can be heated more efficiently.
- the chips are temporarily bonded one by one, only the bonded portion of the substrate corresponding to the heated metal region is heated. It is possible to minimize the change in the surface state of the substrate bonding portion.
- the method for heating the joint is not limited to the above-described mode.
- the chip-side bonding surface is generally formed by polishing so that the metal region MR and the non-metal region NR are substantially on the same plane.
- the polished metal region MR has a relatively high flatness, and the surface roughness is, for example, 1 nmRa or less.
- the structure including the chip and the substrate after the temporary bonding and the main bonding can be obtained by applying a pressure of 1 MPa or less to the bonding surfaces even when heating is performed, that is, at room temperature. Sufficient bonding strength can be obtained. Depending on the surface roughness of the metal region MR, the structure including the chip and the substrate after the temporary bonding and the main bonding is sufficient even if the pressure applied to the bonding surface at the time of temporary bonding is set to 0.3 MPa. Can obtain a high bonding strength.
- Example 3 When the chip non-metal region NR contains a resin, particles activated with the chip-side bonding surface are subjected to surface activation treatment using a particle beam source disposed at a position separated from the bonding surface. It is preferable to carry out by radiating toward the joint surface.
- RIE reactive ion etching
- an alternating voltage is applied to the bonding surface to generate a plasma containing particles around the bonding surface.
- the surface activation treatment is performed by accelerating the ionized particles toward the bonding surface by the above voltage, the following contamination of the bonding surface may occur. That is, the resin components and impurities that are blown off by the sputtering phenomenon of the surface activation treatment and exist in the atmosphere around the joint surface can be accelerated and collide so as to be attracted to the joint surface by the voltage. As a result, resin components and impurities adhere to the surface of the metal region subjected to the surface activation treatment, and the joint surface is contaminated. As a result, in a structure including a chip and a substrate, high bonding strength may not be obtained.
- RIE reactive ion etching
- the surface activation treatment is performed using a neutral atom beam source such as an ion beam source or a fast atom beam source (FAB, Fast Atom Beam), so that the ion beam source or the neutral atom beam source is used.
- a neutral atom beam source such as an ion beam source or a fast atom beam source (FAB, Fast Atom Beam)
- FAB Fast Atom Beam
- the problem of contamination of the joint surface due to the reattachment of the resin to the metal region is reduced, and a structure including a chip and a substrate having higher joint strength can be manufactured.
- a thin chip refers to a chip having a thickness of 10 ⁇ m to 300 ⁇ m.
- the inventor of the present application has a problem of “warping” of a chip in a thin chip on which a bump for electrical connection (see the protruding metal region MR shown in FIGS. 3 and 4) is mounted. I found.
- the bump diameter tends to become smaller, and the control of the pressurizing force for these microelements is several tens of grams / chip or less, and the control becomes difficult. Further, this warp cannot be corrected with a force of about several tens of grams, and it is necessary to push with at least one digit higher force. Even if the temporary bonding can be pushed with a high pressure, if the solder is melted at the time of the main bonding, the chip is warped against the warping force at that time, resulting in a bonding failure. Further, solder is eutectic by melting, and reliability is improved by raising the remelting temperature after eutectic.
- the inventor of the present application has invented a substrate / chip bonding method that achieves reliable electrical connection with a substrate even in the case of a thin chip, as a solution to the thin chip problem.
- the solution is provisional joining under solid-phase joining conditions. That is, temporary bonding is performed by applying a predetermined pressure between the chip and the substrate at a temperature lower than the melting temperature of the solder bump (under a temperature at which the solder bump becomes a solid phase). After temporary bonding, main bonding (treatment for stabilizing the bonding between the chip and the substrate, such as promoting eutectic by promoting grain boundary diffusion in the solid phase state) is performed by “post-heating”. Heating is also performed under solid-state bonding conditions (however, the temperature for post-heating does not necessarily have to be the same as the temperature at the time of temporary bonding, and does not necessarily have to be kept constant during the post-heating process). To be implemented.
- Table 1 shows bonding conditions as experimental examples when Sn—Ag solder material (melting temperature is about 230 ° C.) is used as the solder bump material.
- the surface activation conditions were a driving power of 80 V, a current of 3 A, and an irradiation time of 120 seconds by ion gun treatment using Ar as a reaction gas.
- Hydrophilization conditions were carried out by exposing to nitrogen (N 2 ) gas mixed with 75% water gas.
- N 2 nitrogen
- Temporary bonding was heated by pulse heat. That is, as shown in FIG. 32, heating started at the same time as contact, reached a predetermined temperature after approximately 0.5 seconds, and this temperature was maintained for the remaining time.
- a temperature suitable as a processing temperature at the time of temporary bonding, a pressure applied during temporary bonding (unit Newton), or an equivalent pressure (unit megapascal), and a processing time (unit) Each has a range.
- the temperature at the time of temporary bonding may be in the range of 130 ° C. to 220 ° C.
- the applied pressure (pressure) at the time of temporary bonding is in the range of 50 N to 300 N per chip, that is, 75 MPa to 450 MPa pressure per bump.
- the temporary bonding time is expected to be 0.2 seconds or longer. There is no upper limit for the time required for temporary joining, but the lower limit is better for productivity.
- FIG. 28 shows an example based on solid-phase bonding conditions. This is a photograph obtained when temporary bonding was performed at a heating temperature of 200 ° C., a pressurizing pressure of 100 N, and 1 second as shown in Experimental Example 3, and no crushed solder bumps were generated, and good bonding was obtained. It was.
- the temporary joining conditions were a temperature of 150 ° C. and a pressure of 100 MPa, and a shear strength of 9 N was obtained. Although the strength was slightly lower than in Experimental Examples 1 to 4, almost the same shear strength was obtained. be able to.
- the temporary joining conditions are a temperature of 150 ° C. and a pressure of 150 MPa, and a shear strength of 10.5 N is obtained.
- the temporary joining conditions were a temperature of 150 ° C. and a pressure of 50 MPa, and almost no strength was obtained.
- the temporary bonding conditions were a temperature of 100 ° C. and a pressure of 150 MPa, and almost no strength was obtained.
- the Cu bump requires a pressure of 150 MPa or more and a heating of 150 ° C. or more, and requires a relatively high pressure compared to the solder bump.
- the applied pressure must be relatively weak.
- the solid-phase bonding method using solder bumps of the present invention is effective when bonding is performed at a relatively weak pressure, and the solder bonding portion effectively absorbs the stress caused by the thermal expansion difference between the chip and the substrate. Suitable for working.
- solder and Cu may be properly used as bump materials depending on circumstances.
- the processing temperature and heating time for main bonding also vary, and the numbers listed in Table 1 are only examples.
- the post-heating temperature may be in the range of 130 ° C. to 220 ° C.
- the post-heating time is the time required to form the eutectic at the interface and is in the range of 1 to 24 hours. It's okay. Needless to say, the post-heating time should be short as long as the desired bonding is ensured.
- the material of the bump MR is Sn-Ag (solder material having a melting point of about 230 ° C.), the bump diameter is ⁇ 20 ⁇ m, the bump height is 20 ⁇ m, and mounted on the chip.
- the number of bumps was 2,300, the bump spacing was 30 ⁇ m, and the chip thickness was 200 ⁇ m.
- Table 2 shows the bonding conditions when the bump material is Cu and the bump bonding partner (bonding surface on the substrate) is Cu.
- the surface activation conditions were a driving power of 110 V, a current of 3 A, and an irradiation time of 300 seconds by ion gun treatment using Ar as a reaction gas.
- Hydrophilization conditions were carried out by exposing to nitrogen (N 2 ) gas mixed with 75% water gas.
- the temperature of the bonding conditions for temporary bonding may be in the range of 130 ° C to 300 ° C.
- the applied pressure (or equivalent pressure) for temporary joining may be generally the same as the range described with respect to Table 1, and the time for temporary joining may be generally within the range described with respect to Table 1.
- the processing temperature may be the same as the value described with reference to Table 1 (for example, a temperature of 200 ° C. may be used).
- the post-heating time may be in the range of 0.4 to 8 hours. Specifically, as described in Table 2, 1 hour of post-heating was sufficient. Even in the shear fracture test conducted after post-heating, sufficient shear strength could be secured.
- Table 2 shows that 37N, 35N, 35N, 29N, 30N, and 35N were obtained for Experimental Examples 1, 2, 3, 4, 5, and 6 in Table 2, respectively. That is, it has been found that sufficient bonding can be obtained between the chip and the substrate via Cu bumps.
- Experimental Example 9 In order to investigate the effect of pressure during temporary bonding, 400 MPa was applied in Experimental Example 9.
- the temperature in Experimental Example 9 was 200 ° C., the same as the temperature in Experimental Example 4.
- the shear strength of Experimental Example 9 was 35 N, which was almost equivalent to the shear strength of Experimental Examples 1, 2, 3, and 6. Therefore, it was found that if the pressure at the time of temporary joining is 150 MPa or more, a sufficiently high shear strength can be obtained.
- the temporary joining conditions were a temperature of 150 ° C. and a pressure of 150 MPa, and a shear strength of 30 N was obtained. Although the strength was slightly lower than in Experimental Examples 1, 2, 3, and 6, the shear strength was almost equivalent. It can be said that it was obtained.
- the temporary bonding conditions were a temperature of 150 ° C. and a pressure of 100 MPa, and almost no strength was obtained.
- the temporary bonding conditions were a temperature of 100 ° C. and a pressure of 150 MPa, and almost no strength was obtained.
- a bump (metal region) of a conventional chip there is a bump (metal region) in which an Sn—Ag solder material (MR2) is placed on a copper TSV (MR1) to form a bonding surface.
- the joint surface of the solder material has a spherical surface or a convex curved surface corresponding to the surface tension in the liquid phase because it is formed through melting by a heat treatment after being applied onto copper and a cooling step ( FIG. 29 (a)).
- the solder material (MR2) melted by the contact is mixed to form a bonding interface. Thereby, the positioning accuracy between the bumps can be maintained (FIG. 29B).
- the bump (metal region) MR2 is not heated at the time of contact or is heated at a temperature lower than the melting point, so that it contacts in a solid state.
- the bumps in contact with each other are pressed or not pressed, the bumps can slip from each other and be displaced from a desired position.
- appropriate bonding between the bumps is not performed, and predetermined conductivity and mechanical strength at the bonding interface cannot be obtained.
- the bump is not bonded to the bump to be bonded, and the non-metal region NR. There is a case where it contacts with the substrate surface which should not be originally bonded (FIG. 29C).
- an object of the present invention is to provide a bonding method in which a positional deviation does not occur or a positional deviation is minimized by sliding when a bump (metal region) is bonded in a solid phase state.
- the bonding method according to the present invention includes flattening (leveling) the bonding surface of at least one bump (metal region) between the chip and the substrate before the chip is attached to the substrate. (FIGS. 30A and 30B).
- the bump (metal region) that contacts in the solid state does not shift in the bonding surface direction (shear direction) at the time of contact at the time of temporary bonding, and good positional accuracy can be maintained even when pressed.
- This embodiment is particularly preferably applied to bonding of chips having fine pitch bumps.
- the planarization is preferably performed so that the surface of the bump (metal region) after planarization is substantially parallel to the surface of the average height of the bonding surface of the chip or substrate.
- the planarization is preferably performed so that the surface of the chip or the substrate becomes a surface substantially perpendicular to the direction in which a pressing force is applied during contact.
- the flattened surface is less likely to be subjected to a force in the pruning direction due to pressing at the time of contact, and prevents or keeps the bump from slipping out of a predetermined position due to slipping. be able to.
- the flattening can be performed by, for example, pressing a substrate (flattening member) having a flat surface against the bumps.
- a flat surface having a sufficient surface area i.e. an area larger than a chip or substrate having bumps, may be pressed against the bumps while being kept substantially parallel to the surface having the bumps.
- the bumps can be planarized uniformly and efficiently over the entire surface of the chip or substrate or over a wide area.
- the bumps are softened, and the planarization can be performed under the condition where the pressure is suppressed. Thereby, when an element is provided under the bump, damage to the chip due to pressure can be avoided. Further, by reducing the pressure, it becomes easy to planarize the bumps at the wafer level.
- a silicon semiconductor substrate may be used as the planarizing member.
- the planarizing member is not limited to this, and may be a member having a surface having a desired surface roughness and flatness.
- the planarizing member may be a member formed of another semiconductor material, metal, ceramics, glass, or the like other than silicon.
- the planarization of the bump (metal region) of the chip may be performed while the chip is held by the chip transport unit 39.
- the upper surface of the plate portion 39 of the chip transport portion 39 is configured as a flat surface of the flattening member so that the chip is face-down on the upper surface of the plate portion 39 and the bonding surface of the bump is in contact with the upper surface of the plate portion 39. It may be arranged to press the plate portion 39 from the back surface of the chip. In this case, a support member that opposes the pressing from the lower surface of the plate portion 39 may be provided.
- the chip is placed face-up on the upper surface of the plate portion 39, and a bump (metal region) facing upward is used by using a planarizing member provided separately from the plate portion 39, and downward You may make it press on.
- the planarization of the bump (metal region) may be performed immediately before the attachment step.
- a substrate having flat ends for example, a silicon substrate
- the chip and the substrate may be pressed so as to approach the substrate. It is preferable that both surfaces of the substrate are parallel to each other.
- the planarized surface of the bump (metal region) on the chip side after pressing and the planarized surface of the (metal region) on the substrate side can be formed to be substantially parallel (FIG. 30). (C) and (d)).
- planarization is performed, the chip and the substrate are separated again, the planarization member is retracted from the space between the chip and the substrate, and temporary bonding is performed by bringing the bonding surface between the chip and the substrate into contact with each other. Can do.
- planarization is performed at the bonding position (the vertical position of PG5 and PG7 in FIG. 17), so there is no need to define another position for planarization, and the planarization member is placed between the chip substrates. Since the mechanism to be inserted can be easily configured, it is possible to easily configure a joining apparatus having a flattening mechanism, and furthermore, the transition from the flattening step to the temporary joining step can be performed smoothly.
- planarization is performed after the surface activation treatment and the hydrophilization treatment are performed, but is not limited thereto.
- planarization leveling
- planarization may be performed before performing the surface activation process.
- contamination of the contaminated joint surface due to contact with the planarization member can be avoided or reduced.
- the bumps (metal regions) of the chips are individually flattened.
- the present invention is not limited to this, and the bumps (metal regions) of a plurality of chips may be flattened collectively. Good.
- the planarizing member may be pressed against all or a part of the bonding surfaces held in the substrate shape while the substrate is in a substrate shape before dicing each chip. Thereby, planarization can be efficiently performed for a large number of chips.
- only predetermined chips may be collected, placed on a flat support in a face-up or face-down state, and flattened collectively.
- a chip sorter after dicing, and the chip sorter is used as a support to a bump (metal region) of the entire chip held by the chip sorter.
- Flattening may be performed collectively by pressing the flattening member.
- the bump (metal region) on the substrate (wafer) side to which the chip is bonded may be planarized.
- the bump (metal region) on the substrate (wafer) side to which the chip is bonded may be planarized.
- the bump (metal region) is planarized for both the chip and the substrate. May be performed (FIGS. 30C and 30D).
- ⁇ Modification 4> When the planarization process is performed at a relatively low temperature, for example, 100 ° C. or less or at room temperature with a pressurization of about 1 second, the metal region cannot be sufficiently deformed to obtain a desired flatness. In some cases, the contact area or the bonding interface does not increase, and desired conductivity and mechanical characteristics cannot be obtained. Unlike the conventional joining method in which the metal region is melted, when the heating temperature does not exceed the melting point of the metal region as in the present invention, pressurization is performed before temporary joining and heating is performed under this pressurization to increase or increase the temperature. It is preferable to increase the substantial bonding surface at the time of temporary bonding by extending the pressure time and performing the planarization process in advance.
- the temperature is increased to a temperature of 200 ° C., a pressure of 200 N, and a pressurization time. It is possible to perform sufficient planarization by increasing the flattening treatment conditions for 1 second or the flattening treatment conditions by increasing the pressing time to a temperature of 150 ° C., a pressure of 200 N, and a pressing time of 60 seconds.
- the degree of hydrophilization can vary depending on the type of chip, the conditions for surface activation treatment, the conditions for temporary bonding, etc., in addition to the conditions for the hydrophilization treatment, and can also be adjusted.
- Table 3 when the metal region is formed of copper (Cu) bumps and the non-metal region is formed of SiO 2 (silicon oxide), surface activation treatment conditions, hydrophilization treatment conditions, The result of the comparative experiment regarding the possibility of temporary joining with respect to the conditions of temporary joining is shown.
- organic matter containing carbon other than water is floating in the atmosphere, and it is considered that the organic matter adheres to the joint surface, thereby reducing the activity of the joint surface or reducing the amount of OH groups generated.
- the humidity can be easily controlled and the humidity can be increased to, for example, 90%, and the organic matter in the atmosphere Introduction into the chamber can be prevented. As a result, good OH groups are generated at a high density on the activated surface, and it is considered that bonding at a lower temperature was successful.
- the configuration of the bump (metal region) MR to be planarized has been described as having a TSV (MR1) formed of copper and a solder material portion (MR2) for forming a bonding interface at the tip thereof. It is not limited to this.
- the TSV (MR1) portion may be formed of a metal other than copper
- the tip region (MR2) of the bump (metal region) may be formed of a solder material other than Sn-Ag and other metals. .
- planarization has been described as being performed inside the bonding apparatus 1, it is not limited thereto.
- the planarization of the bump (metal region) may be performed outside the bonding unit 1.
- the spherical surface or curved surface is shown as the shape of the bump (metal region) before flattening, it is not limited to this. This is effective when the bumps have various surface shapes or physical properties that cause a problem of sliding in a direction other than the pressing direction, such as the bonding surface direction, when contacting the bumps.
- the flattening member may be at room temperature or may be configured to heat the bump (metal region) to be pressed. That is, the planarizing member may include a heating mechanism.
- the bump (metal region) is planarized immediately before the attachment step (contact or temporary bonding) as in the first embodiment, the bump (metal region) is brought to a temperature not lower than the melting point and not lower than the room temperature by the planarizing member. It is preferable to heat.
- the bump (metal region) is heated at a predetermined temperature by the head portion 33H or the like, this makes it possible to prevent a decrease in temperature or the like.
- a chip or a substrate having bumps (metal regions) subjected to planarization is an extremely effective solution for various bonding processes performed in a solid state.
- planarization is performed by pressing a planarizing member against a bump on a substrate having a flat surface, but is not limited thereto.
- the planarization may be performed by grinding or polishing in a direction parallel to the surface of the chip or substrate to be bonded.
Abstract
Description
<1.1 第1の実施形態>
図1は、本願発明の第1の実施形態に係るチップの基板への接合方法を示すフローチャートである。
チップ側接合面又は基板の接合部(以下、接合面と称する。)41上には、様々な物質の酸化物、付着した有機物などの汚染物(不純物)などを含む表面層42が存在し、接合すべき材料の新生表面43を覆っている(図2(a)参照)。上記表面層42は、材料の新生表面43のエネルギーレベルを低くしていると考えられる。表面活性化処理により、この表面層が除去され、接合すべき材料の新生表面が露出させられると考えられる(図2(b)参照)。さらには、所定の運動エネルギーを有する粒子を衝突させて行う表面活性化処理には、新生表面近傍において原子間の結合を切断し結晶構造を乱すことで、表面エネルギーのレベルを一層高める効果もあると考えられている。
図3(a)から(f)は、チップ側接合面に垂直な平面でチップを切断した場合の、チップの断面の模式図である。これらの図は、金属領域の形状を例示的に示すことを意図するもので、金属領域の形状を限定するものではない。
基板WAの接合部UTは、例えば、図5に示されているように、基板の面上に縦方向及び横方向に引かれた等間隔の直線で画定される複数の長方形又は正方形として設定されてもよく、また離散的に任意の箇所に設定されてもよい。典型的に、上記基板は、本願発明に係る接合方法の工程が完了した後に、接合部毎に切断(ダイシング)され、ダイ(die)に分割される。最終製品として与えられたダイの大きさは、基板上に設定された接合部の大きさにより定められる。
工程S1及び工程S2において、チップ側接合面及び基板の接合部(以下、接合面と称する)に、所定の運動エネルギーを有する粒子を衝突させることで表面活性化処理を行う。
工程S1及び工程S2において、親水化処理は、上記表面活性化処理の後に行われる。接合面の親水化処理により、接合面に水酸基(OH基)が結合されると考えられている。さらには、水酸基(OH基)が結合された接合面上に水分子が付着してもよい。
工程S3で、チップ側接合面が表面活性化処理され親水化処理されたチップが、それぞれ、チップの金属領域が基板の接合部に接触するように、表面活性化処理され親水化処理された基板の対応する接合部上に取り付けられる。
工程S4では、工程S3で得られた複数のチップと基板との構造体に加熱処理を行うことにより、チップと基板との間の所定の導電性(抵抗率)又は接合強度(機械的強度)を得ることができる。
親水化処理の後の接合、すなわち仮接合では、接合面の大部分がOH基、酸化膜又はこれらの上に付着している水分子(水酸基の層等)を介して他の接合面と接合される。接合面表面にあった表面粗さ又は凹凸は、仮接合時の接触により完全にはなくならないので、仮接合後の接合界面はこの凹凸のある接合面間で形成されている。この仮接合時の接合界面に対して、本接合時に還元処理を行い、酸化膜の除去により新生表面の形成を促進させることは有用である。すなわち、本接合の際の加熱に還元処理を伴うことで酸化膜除去の速度を向上させることができる。さらに、接合界面に対して加圧することで、酸化膜の除去により新生表面の形成と、接合面近傍での原子拡散と同時に、接合面にあった凹凸を低くし実質的な接合面積を効率よく大きくさせることができる。
還元処理には、図34に示すような接合装置401を用いてもよい。
接合装置401は、被接合物491及び492が置かれる雰囲気を制御するための真空チャンバ402と、被接合物491及び492の接合面に対して表面活性化処理を行う表面活性化処理手段408と、被接合物491及び492間の位置ずれを測定する位置ずれ測定手段428M,428e,428fと、被接合物491及び492間の位置ずれを補正するために被接合物491及び492を接合面の面内方向に相対的に移動させるアライメント手段423と、被接合物491及び492を接合面にほぼ垂直方向に遠ざけ、近づけ又は接触させ、或いは接触させた上で加圧するための相対移動手段426と、真空引き手段405,406,407と、還元処理手段441,442,445とを有して構成される。これらの構成により、接合装置1を用いて、チャンバ(真空チャンバ)402内を減圧し、被接合物491及び492の表面処理、接合、加圧、加熱及び還元処理を行うことができる。
ヘッド422は、当該ヘッド422に内蔵されたヒータ422hによって加熱され、ヘッド422に保持された被接合物492の温度を調整することができる。同様に、ステージ412は、当該ステージ412に内蔵されたヒータ412hによって加熱され、ステージ412上の被接合物491の温度を調整することができる。また、ヘッド422は、当該ヘッド422に内蔵された空冷式の冷却装置等によって当該ヘッド422自身を室温付近にまで急速に冷却することもできる。ステージ412も同様である。ヒータ412h,422h(特に422h)は、金属バンプMRを加熱または冷却する加熱冷却手段として機能する。
また、ヘッド422は、Z軸昇降駆動機構426によって、Z方向に移動(昇降)される。ステージ412とヘッド422とがZ方向に相対的に移動することによって、ステージ412に保持された被接合物491とヘッド422に保持された被接合物492とが接触している際に、加圧するように構成されてもよいされて接合される。なお、Z軸昇降駆動機構426は、複数の圧力検出センサ(ロードセル等)429,432により検出された信号に基づいて、接合時の加圧力を制御することも可能である。
還元性ガス源441は、水素ラジカル源又はギ酸ガス源である。還元性ガスは、還元性ガス源441から、弁442、導入間443を通り、所定の流量でチャンバ402内へ導入される。
本願発明に係る仮接合と本接合とを有する接合方法を採用することで、COW実装の生産効率が従来の接合方法と比較して著しく向上する。例えば、チップ毎に対応する基板上の接合部に仮接合及び本接合をすることを繰り返し行い、所定の数のチップを基板上に実装する場合と比較することにより、本願発明の効果をよりよく理解することができる。
従来のようにチップ毎に仮接合と本接合とを繰り返す場合には、チップあたり60秒ほど掛かるといわれている。したがって、例えば、1つの基板上に5000個のチップを本接合するためには、(60秒/チップ)×(5000チップ)=300000秒=約83時間掛かる。チップ毎の仮接合及び本接合を10秒で行うとしても、1つの基板上に5000個のチップを本接合するためには、(10秒/チップ)×(5000チップ)=50000秒=約14時間掛かる。
上記の親水化処理(工程S1)が完了したチップを基板の対応する接合部に取り付ける(工程S3)前に、チップ側接合面に水(H2O)を付着させてもよい(工程S5)。図6は、この工程(工程S5)を含む、本願発明の第1の実施形態の変形例に係る接合方法のフローチャートを示している。
(図8を参照)
図10は、本願発明の第2の実施形態に係る、複数の層のチップを基板へ接合する方法を示すフローチャートである。基板に1層目のチップを取り付ける工程S11から工程S13の処理は、第1の実施形態の工程S1から工程S3と同様であるので、ここではその説明を省略する。
<2.1 システム構成>
図14は、チップ実装システム(電子部品実装システム)1の概略構成を示す上面図である。なお、図14等においては、便宜上、XYZ直交座標系を用いて方向等を示している。
搬送部70は、接合すべき複数のチップを、搬出入部90から表面処理装置50へ搬送し、表面活性化処理と親水化処理が行われた後に表面処理装置50からチップ供給装置10へ搬送する。また、搬送部70は、基板を、搬出入部90から表面処理装置50へ搬送し、表面活性化処理と親水化処理が行われた後に表面処理装置50からボンディング装置30へ搬送する。さらに、搬送部70は、所定数のチップが基板上に取り付けられた後に、チップと基板とを含む構造体をボンディング装置30から搬出入部90へ搬送する。
図14に示す表面処理装置50は、真空チャンバ内に基板WA又は複数のチップを保持するステージ53と、表面活性化処理のために粒子を放射する粒子ビーム源51と、親水化処理のために水を放出する水導入口54とを備え、複数のチップと基板WAとの両方に対して表面活性化処理と親水化処理とを行うことができる構成となっている。以下、便宜的に、図14に示す装置の実施例を用いて本願発明を説明するが、これに限定されない。
所定の運動エネルギーが付与された粒子(破線で図示)は、図15に示されるように、粒子ビーム源51から複数の接合部が設定された接合面を有する基板WA全体に向けて放射状に放出されてもよい。比較的小型の粒子ビーム源などを使うことができ、装置を比較的単純に構成することで小型化できる。
中性原子ビーム源、イオンビーム源、高速原子ビーム源などの粒子ビーム源は、図16に示されるように、ライン型でもよい。ライン型の粒子ビーム源は、ライン型(線状)の又は細長い粒子ビーム放射口を有し、この放射口からライン型(線状)に粒子ビームを放射することができる。放射口の長さは、粒子ビームが照射される基板の直径より大きいことが好ましい。基板が円形でない場合には、放射口の長さは、粒子ビーム源に対して相対的に移動させられる基板に係る放射口が延びる方向の最大寸法より大きいことが好ましい。
プラズマ発生装置を用いても、粒子に所定の運動エネルギーを与えることができる。粒子への所定の運動エネルギーの付与は、プラズマ発生装置を用いて、複数のチップ又は基板などの接合面に対して、交番電圧を印加することで、接合面の周りに粒子を含むプラズマを発生させ、プラズマ中の電離した粒子の陽イオンを、上記電圧により接合面に向けて加速させることで行うことができる。プラズマは数パスカル(Pa)程度の低真空度の雰囲気で発生させることができるので、真空システムを簡易化でき、かつ真空引きなどの工程を短縮化することができる。
図14に示される実施形態においては、水ガス供給部55と、弁56と、ガス供給管と、水導入口54とから、接合面を親水化処理する親水化処理手段が構成される。水ガス供給部55から供給される気体状又は液体状の水は、弁56の開放に応じて、ガス供給管を通って水導入口54から表面処理装置50のチャンバ内に導入される。弁56は、マスフローとして機能し、その開放度に応じて水の供給量を調節するようにしてもよい。
チップ供給装置10は、ダイシングされた基板から各チップCPを取り出し、ボンディング装置30に各チップCP(CPi)を供給する装置である。チップ供給装置10は、複数のチップから一つのチップのみを上方に持ち上げて支持する突上部11と、突上部11により持ち上げられたチップをボンディング装置30に搬送するチップ移載装置13等を備える。チップ移載装置13は、ダイピッカ131とチップ供給機135とを有する。
(図17参照)
図18において、チップ搬送手段であるチップ搬送部(ターレットとも称する)39は、チップ供給装置10から供給されたチップを一つずつボンディング部33(詳細にはヘッド部33H)に受け渡す装置である。
ボンディング装置30は、基板を支持するステージ31、チップを保持して基板に取り付けるボンディング部33、撮像部(カメラ)35、位置認識部(不図示)等を備える。
従来のボンディング装置においては、ボンディング部33に対応する部位が、装置内で水平方向に支持された片持ち梁構造のビームに沿って、水平方向、又は基板表面に平行面内方向(XY方向)に移動できるように構成されている。しかし、片持ち梁構造は剛性が低く、チップの取り付けの際に力を加えると、片持ち梁がZ方向にたわむ。このため、チップと基板との接触の際に印加することのできる力は極めて制限され、通常、最大で2~3kgf(重量キログラム)すなわち20~30N程度の力しか印加することができない。従来のNCPやハンダバンプ接合方法では、チップを樹脂やフラックスで一旦、仮接合するのみなので20~30Nの加圧力で十分あった。また、その場でハンダ接合させるにしても加熱して溶融させるので大きな加圧力は不要であり、装置の簡易化と高速化のためにヘッド(又はボンディング部)を移動させて、場合によっては複数ヘッドを有する構成を採用して高速化を図っていた。しかし、本願発明の接合方法のように金属領域の融点未満で接合を行う場合には、界面の接触した部分しか接合できないため、比較的高い圧力が必要になる。例えば、金属領域(バンプ)に対して、通常のウエハ表面の研磨に有効なCMP研磨方法を用いても、表面粗さを数nm以下にすることは困難である。そのため、研削方法も用いられる。このようにして準備された、金属領域の表面の一般的な表面粗さは、測定したところ、Ra10nm以上であり200nmにも達するものもあった。そのため、ウエハ同士を接合させようとする場合には、数百トンレベルの力を印加することが必要となり、現実的ではなかった。しかし、COW接合することで、1チップあたりに印加する圧力は同じでも必要な力は小さくて済み、1チップあたりに印加することができる力を増大させることができる。仮接合時の加圧は、接合の量産を可能にする現時的な解となりうる。そこで、金属領域の融点未満であっても良好な接合界面を形成するために、チップと基板との接合界面により高い圧力を掛けることで、金属領域の変形を促し、実質的な接合面積を増加させることができる。また、界面に残った水分子を押し出して、OH基同士の強度の高い接合を確保することができる。
上記の親水化処理の完了後、チップが基板上に取り付けられる前に、またはチップが基板上に既に取り付けられたチップの第二接合面上に取り付けられる前に、接合されるチップのチップ側接合面又は第一接合面に水を付着させるための孔部を有する装置(水付着手段又は水付着装置)を設けてもよい。水付着装置は、チップ搬送部39に設けられてもよく、あるいはチップ供給装置10内やボンディング装置30内に設けられてもよい。
図22に示されるように、水付着手段として、上記孔部を水噴射口65としてなし、当該水噴射口65から水を噴射する構成としてもよい。この水噴射口65は、プレート部391に付設された部分に、真空吸着孔64と同じ向きに開口されるように設けてもよい。この水噴射口65は、真空吸着孔64の軸AXを中心とした回転円上に配置される。チップ搬送部39の回転中心の軸AXを基準として、真空吸着孔64と水噴射口65とは角(φ)をなしている。
図23に示されているように、水噴射口の変形例として、真空吸着孔64を水噴射口として機能させてもよい。真空吸着孔64は、真空ポンプ(図示せず)に接続されるとともに水供給源にも接続されるように構成される。そして、真空吸着孔64は、チップを吸着する時及び吸着している間は、真空ポンプと接続され、水供給源との接続が遮断されて、チップを真空吸着する。水噴射口として機能するときは、真空ポンプとの接続が遮断され、水供給源と接続されて、真空引きの際に気体が流れる方向と逆方向に気体状又は液体状の水が流れるように構成されるのが好ましい。
図24に示されるように、水付着手段のさらなる変形例として、水噴射口65は、チップ供給装置10又はボンディング装置30に対して固定され、チップの取出し位置から接合位置までの移動経路中に設けられてもよい。各プレート部391の先端にボンディング部33のヘッド部33Hを配置し、搬送されるチップが水噴射口65を通過する際に、チップ側接合面に対して水を噴射できるように構成されてもよい。
親水化処理の完了後、チップが基板上に取り付けられる前に、チップ側接合面又は第一接合面の金属領域に水を付着する装置(水付着装置)として、チップ供給装置10又はボンディング装置30内に液体の水を収容する水槽66を設けてもよい。(図26を参照)
第1の実施形態及び第2の実施形態において、仮接合時に、接合されるチップ側接合面と基板の接合部とを比較的低温で加熱しつつ加圧することが好ましい。これにより、平坦度に対して厳しい条件を必要としないため好ましい。
図3(e)又は図3(f)に示すような、金属領域MRと非金属領域NRとがほぼ同一面上にあるようにチップ側接合面は、一般的に、研磨により形成される場合が多い。研磨された金属領域MRは比較的に平坦度が高く、表面粗さは、例えば、1nmRa以下である。
チップ非金属領域NRが樹脂を含む場合には、チップ側接合面の表面活性化処理を、接合面から離間した位置に配置された粒子ビーム源を用いて、所定の運動エネルギーが付与された粒子を接合面に向けて放射することで行うことが好ましい。
デバイスに対する不断の高密度化三次元化要求に合わせて、チップにもバンプの微細化、薄膜化が進行している。本願において、薄型チップとは、厚さが10μm~300μmのチップを指すものとする。ここにおいて、本願発明者は、電気接続用のバンプ(図3、図4に示した突起状の金属領域MR参照)を搭載した薄型チップにあっては、チップの「反り」が問題になることを見出した。
従来のチップのバンプ(金属領域)の一例として、銅のTSV(MR1)上にSn-Ag系のはんだ材料(MR2)を載せて接合面を形成したバンプ(金属領域)がある。はんだ材料の接合面は、銅上に塗布された後に熱処理による溶融、そして冷却工程を経て形成されるために、液相での表面張力に応じた球面又は凸形状の曲面を有している(図29(a))。従来のバンプの接合方法では、接触に先立ちバンプを融点以上の温度まで加熱するために、接触により溶融したはんだ材料(MR2)同士が混ざり合って、接合界面が形成される。これにより、バンプ同士の位置決め精度を保つこともできる(図29(b))。
バンプ(金属領域)の平坦化は、取付けステップの直前に行ってもよい。例えば、チップがボンディング部33のヘッド部33Hに保持され基板上に配置された段階で、チップと基板との間に平坦化部材として両端が平坦な基板(たとえば、シリコン基板)を挿入し、当該基板に対してチップと基板とを近づけるように押圧させてもよい。当該基板の両面は互いに平行であることが好ましい。これにより、押圧後のチップ側のバンプ(金属領域)の平坦化された面と基板側の(金属領域)の平坦化された面とをほぼ平行となるように形成することができる(図30(c)及び(d))。
本実施例の上記説明及び変形例1においては、チップのバンプ(金属領域)を個別に平坦化したが、これに限られず、複数のチップのバンプ(金属領域)を一括して平坦化してもよい。
チップ側と同様に、チップが接合される基板(ウエハ)側のバンプ(金属領域)についても平坦化を行ってもよい。この場合は、基板(ウエハ)側のバンプ(金属領域)のみについて平坦化を行っても(図30(a)及び(b))、チップと基板との両方についてバンプ(金属領域)の平坦化を行ってもよい(図30(c)及び(d))。
平坦化工程を比較的低温、例えば100℃以下又は常温で、1秒程度の加圧で行う場合には、金属領域を十分に変形させて所望の平坦度が得ることができず、実質的に接触面積又は接合界面が大きくならず、所望の導電性、機械的特性を得ることが出来ない場合がある。従来の金属領域を溶融させる接合方法と異なり、本願発明のように加熱温度が金属領域の融点を超えない場合には、仮接合前に加圧し、この加圧下で加熱し温度を上げ、又は加圧時間を長くして、事前に平坦化処理を行うことで、仮接合時の実質的な接合面を増大させておくことが好ましい。
親水化の程度は、親水化処理の条件の他に、チップの種類、表面活性化処理の条件、仮接合の条件などによって変わり得るものであり、また調節もされ得る。以下の表3において、金属領域が銅(Cu)のバンプで形成され、非金属領域がSiO2(酸化ケイ素)で形成されている場合の、表面活性化処理の条件、親水化処理の条件、仮接合の条件に対する、仮接合の可否に関する比較実験の結果を示す。
平坦化されるバンプ(金属領域)MRの構成として、銅で形成されたTSV(MR1)とその先端部に接合界面を形成するためのはんだ材料部(MR2)を有する構成について説明してきたが、これに限られない。TSV(MR1)の部分は銅以外の金属で形成されていてもよく、バンプ(金属領域)の先端領域(MR2)はSn-Ag系以外のはんだ材料でも他の金属により形成されていてもよい。
10 チップ供給装置
11 突上部
13 チップ移載装置
30 ボンディング装置
31 ボンディング用ステージ
33 ボンディング部
34 フレーム
33H ヘッド部
39 チップ搬送部
41 接合面
42 表面層
43 新生表面
44 水酸基の層
45 接合界面
50 表面処理装置
51 粒子ビーム源
53 表面処理用ステージ
54 水導入口
55 水ガス供給部
56 弁
61 内側支持部
62 外側支持部
63 凹部
64 真空吸着孔
65 水噴射口
66 水槽
70 搬送部
71 搬送ロボット
80 加熱手段
90 搬出入部
131 ダイピッカ
135 チップ供給機
391 プレート部
392 駆動部
AX チップ搬送部の回転軸
CP チップ
WA 基板
MR 金属領域
NR 非金属領域
UT 接合部
Claims (52)
- 一つ又は複数の金属領域を有するチップ側接合面を有する複数のチップを、複数の接合部を有する基板に接合する方法であって、
チップ側接合面の少なくとも金属領域を、所定の運動エネルギーを有する粒子を衝突させることにより表面活性化処理し、かつ水を付着させることにより親水化処理するステップと、
基板の接合部を、所定の運動エネルギーを有する粒子を衝突させることにより表面活性化処理し、かつ水を付着させることにより親水化処理するステップと、
表面活性化処理されかつ親水化処理された複数のチップを、それぞれ、チップの金属領域が基板の接合部に接触するように、表面活性化処理されかつ親水化処理された基板の対応する接合部上に取り付けるステップと、
基板と基板上に取り付けられた複数のチップとを含む構造体を加熱するステップと、
を備えた方法。 - 前記複数のチップを基板の対応する接合部上に取り付けるステップは、チップの金属領域が基板の接合部に接触する際に、0.1秒から10秒に亘り、チップの金属領域及び基板の接合部を摂氏100度から摂氏350度の温度となるように加熱することで行われる、請求項1に記載の方法。
- 前記チップ側接合面への水の付着及び基板の接合部への水の付着は、それぞれ、チップ側接合面及び基板の接合部の周りの雰囲気における相対湿度が10%から100%となるように制御されることで行われる、請求項1又は2に記載の方法。
- 前記チップ側接合面への水の付着及び基板の接合部への水の付着は、表面活性化処理の後、チップ側接合面及び基板の接合部をそれぞれ大気に暴露することなくチャンバ内で行われる、請求項3に記載の方法。
- 前記チップ側接合面を親水化処理するステップの後、前記複数のチップを基板の対応する接合部上に取り付けるステップの前に、チップ側接合面に水を付着させる水付着ステップを更に備える、請求項1から4のいずれか一項に記載の方法。
- 前記水付着ステップは、チップ側接合面の金属領域に水を吹き付けることで行われる、請求項5に記載の方法。
- 前記水付着ステップは、チップ側接合面の金属領域を液体状の水に浸漬させることで行われる、請求項5に記載の方法。
- 前記粒子は、Ne,Ar,Kr,Xeからなる群から選ばれる元素の中性原子、イオン若しくはラジカル又はこれらを混合したものである、請求項1から7のいずれか一項に記載の方法。
- 前記粒子の運動エネルギーは、1eVから2keVである、請求項1から8のいずれか一項に記載の方法。
- 複数のチップ又は基板に対して交番電圧を印加することで、チップ側接合面又は基板の接合部の周りに前記粒子を含むプラズマを発生させ、プラズマ中の前記粒子を前記電圧によりチップ側接合面又は基板の接合部に向けて加速させることにより、粒子に所定の運動エネルギーを付与する、請求項9に記載の方法。
- 前記チップ側接合面又は基板の接合部から離間された位置から、前記チップ側接合面又は基板の接合部に向けて所定の運動エネルギーを有する粒子を放射する、請求項9に記載の方法。
- 前記チップ側接合面は金属領域以外の領域に非金属領域を有し、当該非金属領域は樹脂により形成される、請求項11に記載の方法。
- 前記複数のチップを基板の対応する接合部上に取り付けるステップは、前記チップと前記基板とを互いに近接する方向に加圧するステップを含み、当該加圧ステップは、金属領域に対して0.3~600MPaの圧力で行われる、請求項1から12のいずれか一項に記載の方法。
- 前記加圧ステップは、チップあたり100N以上の力、又は金属領域に対して150MPa以上の圧力を印加することで行われる、請求項13に記載の方法。
- 前記基板と基板上に取り付けられた複数のチップとを含む構造体を加熱するステップは、摂氏100度以上、前記金属領域を形成する金属の融点未満の温度で、10分から100時間に亘って行われる、請求項1から14のいずれか一項に記載の方法。
- 前記基板と基板上に取り付けられた複数のチップとを含む構造体を加熱するステップは、前記基板と前記基板に接合された複数のチップとを、互いに近接する方向に加圧するステップを含む、請求項1から15のいずれか一項に記載の方法。
- 前記基板と基板上に取り付けられた複数のチップとを含む構造体を加熱するステップは、還元雰囲気中で行われる還元処理ステップを含む、請求項15又は16に記載の方法。
- 前記還元処理ステップ前に、前記構造体の周りの雰囲気を真空引きし、
前記還元雰囲気は水素を含むガスである、
請求項17に記載の方法。 - 前記還元処理ステップ後に、前記基板と前記基板に接合された複数のチップとを、互いに近接する方向に加圧するステップを行う、請求項17又は18に記載の方法。
- 前記金属領域は、銅(Cu)、はんだ材料、金(Au)及びこれらの合金からなる群から選ばれる材料により形成されている、請求項1から19のいずれか一項に記載の方法。
- チップ側接合面は金属領域以外の領域に非金属領域を有し、金属領域と非金属領域の表面はほぼ同一面上にある、請求項1から20のいずれか一項に記載の方法。
- チップ側接合面の非金属領域は、疎水化処理されたチップ側疎水化領域を有し、
基板の接合部は、チップの金属領域に対応する接合領域と、疎水化処理された基板側疎水化領域とを有し、
前記複数のチップを基板の対応する接合部上に取り付けるステップは、チップの金属領域と基板の親水化処理された接合領域とが接触するように行われる、請求項21に記載の方法。 - 前記金属領域は、チップ側接合面の金属領域以外の領域に対して突出するように形成されている、請求項1から20のいずれか一項に記載の方法。
- 前記金属領域は、一つ又は複数の第一の金属領域と当該第一の金属領域を囲むように形成された閉じた環状の第二の金属領域とを有する、請求項23に記載の方法。
- チップに所定の検査を行い、良好と判断されたチップのみを供給するステップを更に含む、請求項1から24のいずれか一項に記載の方法。
- 前記親水化処理ステップの後に、親水化処理ステップにより生成したOH基を残し、付着した水分子をチップ側接合面上から除去するステップを更に備える、請求項1から25のいずれか一項に記載の方法。
- 一つ又は複数の金属領域を有する第一接合面と当該第一接合面の裏側に位置する第二接合面とを有する所定数のチップからなるチップ層を、複数の層に亘り、複数の接合部を有する基板上に積層して接合する方法であって、
当該方法は、
チップの第一接合面の少なくとも金属領域を、所定の運動エネルギーを有する粒子を衝突させることにより表面活性化処理し、かつ水を付着させることにより親水化処理するステップと、
基板の接合部を、所定の運動エネルギーを有する粒子を衝突させることにより表面活性化処理し、かつ水を付着させることにより親水化処理するステップと、
表面活性化処理されかつ親水化処理された所定数のチップを、それぞれ、チップの金属領域が基板の接合部に接触するように、表面活性化処理されかつ親水化処理された基板の対応する接合部上に取り付けるステップと、
次に取り付けるべき所定数のチップの第一接合面の少なくとも金属領域を、所定の運動エネルギーを有する粒子を衝突させることにより表面活性化処理し、かつ水を付着させることにより親水化処理するステップと、
基板上に積層されているチップの中で最上層の所定数のチップの第二接合面を、所定の運動エネルギーを有する粒子を衝突させることにより表面活性化し、かつ水を付着させることにより親水化処理するステップと、
表面活性化処理されかつ親水化処理された前記次に取り付けるべき所定数のチップを、それぞれ、当該チップの金属領域が前記最上層の所定数のチップの第二接合面に接触するように、表面活性化処理されかつ親水化処理された前記最上層の所定数のチップ上に取り付けるステップと、
複数のチップ層に亘りチップを基板上に取り付けた後に、基板と基板上に取り付けられたチップとを含む構造体を加熱するステップと、
を備えた方法。 - 一つ又は複数の金属領域を有するチップ側接合面を有する複数のチップを、複数の接合部を有する基板に接合する装置であって、
チップ側接合面の少なくとも金属領域を表面活性化処理するために、所定の運動エネルギーを有する粒子を当該チップ側接合面に対して衝突させるチップ用表面活性化処理手段と、
基板の接合部を表面活性化処理するために、所定の運動エネルギーを有する粒子を当該基板の接合部に対して衝突させる基板用表面活性化処理手段と、
表面活性化処理されたチップの金属領域を親水化処理するために、当該チップの金属領域に水を付着させるチップ用親水化処理手段と、
表面活性化処理された基板の接合部を親水化処理するために、当該基板の接合部に水を付着させる基板用親水化処理手段と、
複数のチップを、それぞれ、チップの金属領域が基板の接合部に接触するように、基板の対応する接合部上に取り付けるチップ取付手段と、
を備えた装置。 - 前記チップ用表面活性化処理手段により表面活性化処理され、前記チップ用親水化処理手段により親水化処理されたチップ側接合面に水を付着させる水付着手段を更に備えた、請求項28に記載の装置。
- 前記チップ取付手段は、チップを基板に向けて搬送するチップ搬送手段と、当該チップ搬送手段により搬送されたチップを受け取って基板上に載置するチップ載置手段とを有して構成され、
前記水付着手段は、チップ搬送手段に設けられて、チップ載置手段がチップを受け取った後にチップ側接合面に水を吹き付ける、請求項29に記載の装置。 - 前記水付着手段は、チップ搬送手段に形成された孔部を有して構成され、当該孔部を通して水がチップ側接合面に吹き付けられる、請求項30に記載の装置。
- 前記孔部は、チップを真空吸着するためにも使用される、請求項31に記載の装置。
- 前記水付着手段は、チップ取付手段によりチップが移動させられる経路上に配置されて、チップが水付着手段を通過するときにチップ側接合面に向かって水を吹き付ける、請求項29に記載の装置。
- 前記水付着手段は、チップ取付手段によりチップが移動させられる経路上に配置されて、液体状の水を収容する水槽を含む、請求項29に記載の装置。
- チップ用表面活性化処理手段と基板用表面活性化処理手段とは、それぞれ、複数のチップと基板とに対して交番電圧を印加することで、チップ側接合面と基板の接合部との周りに前記粒子を含むプラズマを発生させ、プラズマ中の前記粒子を前記電圧によりチップ側接合面と基板の接合部とに向けて加速させることにより、粒子に所定の運動エネルギーを付与する、プラズマ発生装置を有して構成される、請求項28から34のいずれか一項に記載の装置。
- チップ用表面活性化処理手段と基板用表面活性化処理手段とは、それぞれ、チップ側接合面と基板の接合部とから離間されて配置され、チップ側接合面と基板の接合部とに向けて所定の運動エネルギーを有する粒子を放射する、粒子ビーム源を有して構成される、請求項28から35のいずれか一項に記載の装置。
- チップ用親水化処理手段と基板用親水化処理手段とは、一つの親水化処理手段により実現される、請求項28から36のいずれか一項に記載の装置。
- チップ用表面活性化処理手段とチップ用親水化処理手段とは、共通の粒子ビーム源を有する、請求項28から37のいずれか一項に記載の装置。
- 前記チップ取付手段は、基板の表面に対してチップを垂直方向に移動させるように構成されたヘッドを有し、
前記装置は、
前記チップの移動方向に垂直な面方向に基板を移動可能に支持するステージと、
当該ステージをチップの移動方向に対して固定し、チップ取付手段を前記チップの移動方向に垂直な面方向に対して固定するように支持するフレームと、
を更に有し、
接触しているチップと基板とに対して、チップに対して100N以上の力又はチップの金属領域に対して150MPa以上の圧力を印加することができる、請求項28から38のいずれか一項に記載の装置。 - 前記チップ取付手段は、チップを基板の対応する接合部上に取り付ける際に、前記チップと前記基板とを互いに近接する方向に加圧する手段を更に有し、前記加圧手段は、チップの金属領域に0.3~600MPaの圧力を印加する、請求項28から39のいずれか一項に記載の装置。
- 前記複数のチップと前記基板とを含む構造体を加熱するための加熱手段を更に備えた、請求項28から40のいずれか一項に記載の装置。
- 前記複数のチップと前記基板とを含む構造体を加熱する際に、当該構造体の雰囲気に還元性ガスを導入する還元処理手段を更に備えた、請求項41に記載の装置。
- 前記還元処理手段は、前記還元性ガスとして、水素を含むガスを前記構造体の雰囲気に導入するように構成され、
前記構造体の雰囲気を真空引きする真空引き手段を更に有する、請求項42に記載の装置。 - 一つ又は複数の金属領域を有する第一接合面を有する複数のチップからなるチップ層を、複数の層に亘り、複数の接合部を有する基板上に積層して接合する装置であって、
チップの第一接合面を表面活性化処理するために、チップの第一接合面に対して所定の運動エネルギーを有する粒子を衝突させる第一接合面用表面活性化処理手段と、
チップの第一接合面の裏側に位置する第二接合面を表面活性化処理するために、チップの第二接合面に対して所定の運動エネルギーを有する粒子を衝突させるチップ第二接合面用表面活性化処理手段と、
基板の接合部を表面活性化処理するために、基板の接合部に対して所定の運動エネルギーを有する粒子を衝突させる基板用表面活性化処理手段と、
表面活性化処理されたチップの第一接合面を親水化処理するために、チップの第一接合面に水を付着させるチップ第一接合面用親水化処理手段と、
表面活性化処理されたチップの当該第一接合面の裏側に位置する第二接合面を親水化処理するために、チップの第二接合面に水を付着させるチップ第二接合面用親水化処理手段と、
基板の接合部を親水化処理するために、基板の接合部に水を付着させる基板用親水化処理手段と、
チップの金属領域が基板の接合部に接触するように、チップを基板の対応する接合部上に取り付け、基板上に取り付けられているチップの第二接合面に次に取り付けられるチップの第一接合面が接触するように、当該チップを基板上に取り付けられているチップ上に取り付けるチップ取付手段と、
を備えた装置。 - 前記基板と前記基板上に複数の層に亘り積層された複数のチップとを含む構造体を加熱するための加熱手段を更に備えた、請求項44に記載の装置。
- 基板と基板上に取り付けられた複数のチップとを含む構造体であって、請求項1から26のいずれか一項に記載の、一つ又は複数の金属領域を有するチップ側接合面を有する複数のチップを、複数の接合部を有する基板に接合する方法により形成された、基板と基板上に取り付けられた複数のチップとを含む構造体。
- 基板と基板上に複数層に亘り取り付けられたチップとを含む構造体であって、請求項27に記載の、一つ又は複数の金属領域を有する第一接合面と当該第一接合面の裏側に位置する第二接合面とを有する所定数のチップからなるチップ層を、複数の層に亘り、複数の接合部を有する基板上に積層して接合する方法により形成された、基板と基板上に複数層に亘り取り付けられたチップとを含む構造体。
- 一つ又は複数の金属領域を有するチップ側接合面を有する複数のチップを、複数の接合部を有する基板に接合する方法であって、
チップ側接合面の少なくとも金属領域を、所定の運動エネルギーを有する粒子を衝突させることにより表面活性化処理し、かつ水を付着させることにより親水化処理するステップと、
基板の接合部を、所定の運動エネルギーを有する粒子を衝突させることにより表面活性化処理し、かつ水を付着させることにより親水化処理するステップと、
表面活性化処理されかつ親水化処理された複数のチップを、それぞれ、チップの金属領域が基板の接合部に接触するように、表面活性化処理されかつ親水化処理された基板の対応する接合部上に取り付けるステップと、
基板と基板上に取り付けられた複数のチップとを含む構造体を加熱するステップと、
を備え、
前記チップは厚さが10μm~300μmである、
方法。 - 前記複数のチップを基板の対応する接合部上に取り付けるステップは、チップの金属領域を構成する材料を融点未満の固相状態に加熱することを含む、請求項48に記載の方法。
- 前記複数のチップを基板の対応する接合部上に取り付けるステップの前に、平坦な表面を有する基板で金属領域の表面を押圧するステップを更に備える、請求項48又は49に記載の方法。
- 前記構造体を加熱するステップは、チップの金属領域を構成する材料を融点未満の固相状態で加熱することで行われる、請求項48から50のいずれか一項に記載の方法。
- 一つ又は複数の金属領域を有するチップ側接合面を有する複数のチップを、複数の接合部を有する基板に接合する方法であって、
表面活性化処理された複数のチップを表面活性化処理された基板の対応する接合部上に取り付けるステップと、
基板と基板上に取り付けられた複数のチップとを含む構造体を加熱するステップと、
を備え、
前記複数のチップを前記基板の対応する接合部上に取り付けるステップは、チップの金属領域を構成する材料を融点未満の固相状態で加熱することで行われる、
方法。
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Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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JP2015151453A (ja) * | 2014-02-13 | 2015-08-24 | リンテック株式会社 | 伸長可能シートおよび積層チップの製造方法 |
JP2016117092A (ja) * | 2014-12-22 | 2016-06-30 | ボンドテック株式会社 | 接合方法、接合装置及び接合物を含む構造体 |
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JP2021097234A (ja) * | 2019-12-16 | 2021-06-24 | エーエスエム・テクノロジー・シンガポール・ピーティーイー・リミテッド | ダイホルダーモーションテーブルを備えたダイボンドヘッド装置 |
US11145618B2 (en) | 2018-03-06 | 2021-10-12 | Sharp Kabushiki Kaisha | Bonding equipment |
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Families Citing this family (38)
Publication number | Priority date | Publication date | Assignee | Title |
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KR102365660B1 (ko) | 2019-08-27 | 2022-02-18 | 세메스 주식회사 | 다이 픽업 모듈 및 이를 포함하는 다이 본딩 장치 |
US11335828B2 (en) * | 2019-12-08 | 2022-05-17 | Mikro Mesa Technology Co., Ltd. | Method of handling micro device |
US20220059406A1 (en) * | 2020-08-21 | 2022-02-24 | Advanced Semiconductor Engineering, Inc. | Method for manufacturing semiconductor package |
CN112289695B (zh) * | 2020-09-22 | 2023-03-21 | 中国电子科技集团公司第二十九研究所 | 一种用于多焊件自动共晶的通用共晶装置及共晶方法 |
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US11735575B2 (en) | 2021-05-27 | 2023-08-22 | International Business Machines Corporation | Bonding of bridge to multiple semiconductor chips |
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US11756925B2 (en) * | 2021-10-22 | 2023-09-12 | Applied Materials, Inc. | Methods and apparatus for vacuum processing a substrate |
WO2023144972A1 (ja) * | 2022-01-27 | 2023-08-03 | 東京エレクトロン株式会社 | 基板処理装置、及び基板処理方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003308889A (ja) * | 2002-04-15 | 2003-10-31 | Bridgestone Corp | 太陽電池及びその製造方法 |
JP2003306992A (ja) * | 2002-04-15 | 2003-10-31 | Bridgestone Corp | 防汚性パネル建材 |
JP2011060941A (ja) * | 2009-09-09 | 2011-03-24 | Tokyo Electron Ltd | 半導体装置の製造方法 |
JP2011192663A (ja) * | 2010-03-11 | 2011-09-29 | Tokyo Electron Ltd | 実装方法及び実装装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5283468A (en) * | 1988-05-30 | 1994-02-01 | Canon Kabushiki Kaisha | Electric circuit apparatus |
JP2786700B2 (ja) * | 1989-11-29 | 1998-08-13 | 株式会社日立製作所 | 半導体集積回路装置の製造方法および製造装置 |
JP2003152027A (ja) | 2001-11-13 | 2003-05-23 | Matsushita Electric Ind Co Ltd | 半導体実装体の製造装置および製造方法 |
JP4797677B2 (ja) * | 2006-02-14 | 2011-10-19 | 旭硝子株式会社 | マルチチップ素子とその製造方法 |
JP2009110995A (ja) * | 2007-10-26 | 2009-05-21 | Toray Eng Co Ltd | 3次元実装方法及び装置 |
JP5732652B2 (ja) * | 2009-11-04 | 2015-06-10 | ボンドテック株式会社 | 接合システムおよび接合方法 |
-
2013
- 2013-04-24 KR KR1020147031522A patent/KR102103811B1/ko active IP Right Grant
- 2013-04-24 US US14/397,038 patent/US9142532B2/en active Active
- 2013-04-24 JP JP2014512656A patent/JP6337400B2/ja active Active
- 2013-04-24 WO PCT/JP2013/062100 patent/WO2013161891A1/ja active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003308889A (ja) * | 2002-04-15 | 2003-10-31 | Bridgestone Corp | 太陽電池及びその製造方法 |
JP2003306992A (ja) * | 2002-04-15 | 2003-10-31 | Bridgestone Corp | 防汚性パネル建材 |
JP2011060941A (ja) * | 2009-09-09 | 2011-03-24 | Tokyo Electron Ltd | 半導体装置の製造方法 |
JP2011192663A (ja) * | 2010-03-11 | 2011-09-29 | Tokyo Electron Ltd | 実装方法及び実装装置 |
Cited By (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011119717A (ja) * | 2009-11-04 | 2011-06-16 | Bondtech Inc | 接合システムおよび接合方法 |
JP2015151453A (ja) * | 2014-02-13 | 2015-08-24 | リンテック株式会社 | 伸長可能シートおよび積層チップの製造方法 |
TWI657550B (zh) * | 2014-02-13 | 2019-04-21 | 日商琳得科股份有限公司 | 可延伸片材以及積層晶片之製造方法 |
KR102619737B1 (ko) * | 2014-04-23 | 2024-01-02 | 소니그룹주식회사 | 반도체 장치 및 그 제조 방법 |
KR20230030021A (ko) * | 2014-04-23 | 2023-03-03 | 소니그룹주식회사 | 반도체 장치 및 그 제조 방법 |
US11476291B2 (en) | 2014-04-23 | 2022-10-18 | Sony Corporation | Semiconductor device and method of manufacturing thereof |
JP2016117092A (ja) * | 2014-12-22 | 2016-06-30 | ボンドテック株式会社 | 接合方法、接合装置及び接合物を含む構造体 |
JP2017028156A (ja) * | 2015-07-24 | 2017-02-02 | 新光電気工業株式会社 | 実装構造体及びその製造方法 |
JP2018531405A (ja) * | 2015-08-11 | 2018-10-25 | オラクル・インターナショナル・コーポレイション | 自己組立てられ且つ縦方向に整列されるマルチチップモジュール |
JP7039458B2 (ja) | 2015-08-11 | 2022-03-22 | オラクル・インターナショナル・コーポレイション | 自己組立てられ且つ縦方向に整列されるマルチチップモジュール |
CN107871684A (zh) * | 2016-09-26 | 2018-04-03 | 捷进科技有限公司 | 倒装芯片贴装机以及半导体器件的制造方法 |
US11145618B2 (en) | 2018-03-06 | 2021-10-12 | Sharp Kabushiki Kaisha | Bonding equipment |
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Also Published As
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US9142532B2 (en) | 2015-09-22 |
KR102103811B1 (ko) | 2020-04-23 |
KR20150006845A (ko) | 2015-01-19 |
JP6337400B2 (ja) | 2018-06-06 |
US20150048523A1 (en) | 2015-02-19 |
JPWO2013161891A1 (ja) | 2015-12-24 |
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