CN104518085B - 具有横向偏移的beva/teva的rram单元结构 - Google Patents
具有横向偏移的beva/teva的rram单元结构 Download PDFInfo
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- CN104518085B CN104518085B CN201310746001.6A CN201310746001A CN104518085B CN 104518085 B CN104518085 B CN 104518085B CN 201310746001 A CN201310746001 A CN 201310746001A CN 104518085 B CN104518085 B CN 104518085B
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- 238000010276 construction Methods 0.000 title abstract description 6
- 230000001413 cellular effect Effects 0.000 title abstract description 3
- 230000004888 barrier function Effects 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 41
- 239000002184 metal Substances 0.000 claims description 41
- 239000004065 semiconductor Substances 0.000 claims description 40
- 238000000034 method Methods 0.000 claims description 23
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- 238000003860 storage Methods 0.000 claims description 13
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- 125000006850 spacer group Chemical group 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 238000007598 dipping method Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims 1
- 230000008859 change Effects 0.000 abstract description 4
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000013500 data storage Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
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- 239000004642 Polyimide Substances 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
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- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
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- 238000007667 floating Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- 230000037361 pathway Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920000636 poly(norbornene) polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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Abstract
本发明涉及一种具有轴偏移或横向偏移的顶电极通孔(TEVA)和底电极通孔(BEVA)的电阻式随机存取存储器(RRAM)单元架构。具有同轴的TEVA和BEVA的传统RRAM单元能够引起高接触电阻变化率。本发明中的轴偏移的TEVA和BEVA促使TEVA远离RRAM单元上方的绝缘层,这样能够提高接触电阻变化率。本发明也涉及一种具有矩形RRAM单元的存储器件,该RRAM单元具有能够降低形成电压且提高数据保持的较大区域。本发明还公开了具有横向偏移的BEVA/TEVA的RRAM单元结构。
Description
技术领域
本发明涉及半导体技术领域,更具体地,涉及具有横向偏移的BEVA/TEVA的RRAM单元结构。
背景技术
非易失性存储器用于各式各样的商业和军用电子器件和设备中。嵌入式闪存存储器件用于将数据和可执行程序保存在集成芯片中。随着集成芯片的功能性增加,对更大存储容量的需求也增加,这就使得集成芯片的设计者和制造商必须提高可用存储容量,同时还要降低集成芯片的尺寸和功耗。为了实现这个目标,在过去的几十年里,已经明显地缩小了存储单元组件的尺寸。由于将工艺技术转移到较小的单元尺寸中,所以,对于嵌入式闪存存储来说,集成浮栅和高k金属栅极变得复杂且昂贵。由于简单的结构和涉及CMOS逻辑兼容工艺技术,所以电阻式随机存取存储器(RRAM)是用于下一代非易失性存储器技术的一个有前景的候选者。
RRAM单元是夹在顶电极和底电极之间的金属氧化物材料。然而,传统的RRAM单元能够在顶电极通孔处引起高的接触电阻变化率。本发明目的在于降低接触电阻变化率、减小形成电压以及提高数据保持。
发明内容
为了解决现有技术中所存在的问题,根据本发明的一个方面,提供了一种电阻式随机存取存储器(RRAM)器件,包括:
电阻式随机存取存储器(RRAM)单元,具有第一表面和第二表面;
第一导电互连件,在第一位置处与所述第一表面邻接;以及
第二导电互连件,在第二位置处与所述第二表面邻接,其中,所述第一位置和所述第二位置彼此横向偏移。
在可选实施例中,所述RRAM单元包括:可变电阻式介电层,具有顶面和底面;顶电极,设置在所述可变电阻式介电层的上方且与所述顶面邻接;底电极,设置在所述可变电阻式介电层的下方且与所述底面邻接;顶电极通孔(TEVA),与所述顶电极邻接;以及,底电极通孔(BEVA),与所述底电极邻接。
在可选实施例中,所述TEVA与所述第一导电互连件相对应且设置在所述第一位置,并且,所述BEVA与所述第二导电互连件结构相对应且设置在所述第二位置,所述第一位置和所述第二位置彼此横向偏移。
在可选实施例中,所述RRAM器件还包括:半导体区,包括设置在形成于所述半导体区上方的极低k介电层内的金属;介电保护层,具有位于所述金属上方的开口区,其中,所述介电保护层的侧壁终止于所述金属上方的圆形端;绝缘层,与位于所述开口区上方的所述顶电极邻接;以及,间隔件,位于所述顶电极的每一侧。
在可选实施例中,所述底电极通孔(BEVA)位于所述介电保护层上方的限定区的上方,以浸渍的方式遵循所述介电保护层的所述圆形端的形状,且位于与所述半导体区中的所述金属相接触的所述开口区的上方;所述底电极设置在所述BEVA的整个上方;所述可变电阻式介电层设置在所述BE的整个上方;所述顶电极位于所述可变电阻式介电层上方的限定区的上方;以及,所述TEVA位于与所述开口区和所述绝缘层横向偏移的位置处。
在可选实施例中,所述RRAM单元包括构成一个区域的长度尺寸和宽度尺寸,并且,上覆导电互连件和下伏导电互连件设置在所述区域内。
在可选实施例中,所述RRAM单元的形状为矩形。
在可选实施例中,所述顶电极包括氮化钽(TaN)或钛(Ti),所述底电极包括氮化钛(TiN),所述TEVA包括铜(Cu),所述BEVA包括TaN,所述可变电阻式介电层包括氧化铪(HfO),所述间隔件包括氮化硅(SiN),以及所述绝缘层包括氮氧化硅(SiON)。
根据本发明的另一方面,还提供了一种电阻式随机存取存储器(RRAM)器件,包括:
半导体主体,具有被沟道区水平分隔开的源极区和漏极区;
栅极结构,连接至所述沟道区;
第一接触件和第二接触件,分别从所述漏极区和所述源极区向上延伸;
第一导电互连件,形成在所述第一接触件的上方且电连接至所述第一接触件;
电阻式随机存取存储器(RRAM)单元,形成在所述第一导电互连件的上方且具有第一表面和第二表面,其中,所述第一表面在第一位置处连接至所述第一导电互连件;以及
第二导电互连件,形成在所述RRAM单元的上方且在第二位置处与所述第二表面邻接,其中,所述第一位置和所述第二位置彼此横向偏移。
在可选实施例中,所述栅极结构连接至字线。
在可选实施例中,所述栅极结构包括形成在栅极电介质上方的多晶硅栅电极,所述栅极电介质将所述栅电极与所述沟道区电隔离。
在可选实施例中,一个或多个金属接触件和一个或多个金属接触通孔存在于所述源极区和所述第二接触件之间以及所述漏极区和所述第一接触件之间。
在可选实施例中,所述源极区连接至源极线,且所述漏极区连接至位线。
在可选实施例中,所述源极区和所述漏极区具有第一导电率且所述半导体主体具有第二导电率。
根据本发明的另一方面,还提供了一种形成电阻式随机存取存储器(RRAM)器件的方法,包括:
在第一位置形成与RRAM单元的第一表面邻接的上覆导电互连件;以及
在第二位置形成与所述RRAM单元的第二表面邻接的下伏导电互连件,其中,所述第一位置和所述第二位置彼此横向偏移。
在可选实施例中,所述RRAM单元包括半导体区、介电保护层、底电极通孔(BEVA)、底电极(BE)、可变电阻式介电层以及顶电极(TE),其中所述半导体区包括设置在极低k介电层内的金属层。
在可选实施例中,所述方法还包括:在所述顶电极的上方形成抗反射层;光刻图案化和蚀刻所述顶电极(TE);在所述半导体主体的整个上方沉积间隔件材料层;蚀刻所述间隔件材料层以在所述顶电极的每一侧形成间隔件、以及露出两端位置上的所述可变电阻式介电层;光刻图案化和蚀刻堆叠件,所述堆叠件包括所述可变电阻式介电层、底电极和所述BEVA;以及,形成与所述TE邻接的顶电极通孔(TEVA)。
在可选实施例中,在蚀刻所述顶电极之后,在所述顶电极的上方保留所述抗反射层的一部分。
在可选实施例中,所述顶电极通孔横向偏移于所述抗反射层的所述一部分。
在可选实施例中,在蚀刻所述顶电极期间,完全去除所述抗反射层。
附图说明
图1A示出了根据本发明的电阻式随机存取存储器(RRAM)器件的一些实施例的顶视图。
图1B示出了根据本发明一些实施例的图1A中RRAM器件的RRAM单元中的一个的截面图。
图2示出了根据本发明的用于形成RRAM器件的方法的一些实施例的流程图。
图3示出了根据本发明的用于在RRAM单元上形成顶电极通孔的方法的一些实施例的流程图。
图4示出了根据本发明的存储单元上的横向偏移的顶电极通孔(TEVA)和底电极通孔(BEVA)的一些实施例的截面图。
图5A-图5D示出了根据本发明的横向偏移结构和非横向偏移结构的一些实施例。
图6示出了根据本发明的具有横向偏移TEVA和BEVA的RRAM器件的一些实施例的截面图。
图7A-图7F示出了根据本发明的形成TEVA的方法的截面图的实施例。
图8示出了具有邻接顶电极的无绝缘材料的横向偏移的TEVA和BEVA的RRAM器件的一些实施例的截面图。
具体实施方式
参见附图作出本文的描述,其中,在整篇描述中,相同的参考数字通常用于表示相同的元件,并且,无需按比例绘制不同结构。在以下描述中,为了说明的目的,给出很多具体说明以便理解。然而,对于本领域的技术人员,根据较少程度的这些具体说明就可实施本文的一个或多个方面是显而易见的。在其他情况下,以框图的形式示出了已知结构和器件以便理解。
RRAM单元包括两个电极,这两个电极具有设置在两个电极之间的电阻式开关元件。电阻式开关元件或可变电阻式介电层使用“形成工艺”制备存储器件以备使用。通常在工厂、组装或初始系统配置中应用形成工艺。电阻式开关材料通常是绝缘的,但是施加给电阻式开关材料的足够的电压(被称为形成电压)会在电阻式开关材料中形成一个或多个导电通路。通过适当地施加不同的电压(例如,置位电压和复位电压),可调整导电通路以形成高电阻状态或低电阻状态。例如,电阻式开关材料可根据施加的置位电压从第一电阻率改变为第二电阻率且根据施加的复位电压从第二电阻率回到第一电阻率。
RRAM单元可被视为存储逻辑位元,其中,当电阻式开关元件具有增大的电阻时,可认为RRAM单元存储“0”位元;当电阻式开关元件具有降低的电阻时,RRAM单元可被视为存储“1”位元,反之亦然。通过将读取电压施加给两个电极且测量流经电阻式开关元件的相应的电流,电路可用于读出电阻式开关元件的电阻状态。如果流经电阻式开关元件的电流大于某一预定的基准电流,则认为电阻式开关元件处于降低的电阻状态,并因此,RRAM单元存储逻辑“1”。另一个方面,如果流经电阻式开关元件的电流小于某一预定的基准电流,则认为电阻式开关元件处于增加的电阻状态,并因此RRAM单元存储逻辑“0”。
RRAM单元具有导电互连件,导电互连件包括将顶电极和底电极连接至器件的剩余部分的顶电极通孔(TEVA)和底电极通孔(BEVA)。在传统的RRAM单元中,TEVA和BEVA沿着相同的纵轴设置。在这种情况下,如果TEVA设置在那个位置,可保持在顶电极上方的抗反射层会引起TEVA上的高接触电阻。
因此,本发明涉及一种新的用于RRAM单元的体系结构,该体系结构能够提高顶电极通孔处的接触电阻变化率。在一些实施例中,包括TEVA和BEVA的导电互连件是横向偏移的,以便TEVA远离能够降低接触电阻变化率的绝缘抗反射层。而且,以下面的这种方式选择RRAM单元的形状和尺寸:使得RRAM单元将导电互连件容纳在RRAM单元的区域内的两端处。小单元尺寸和高密度存储可给相关的逻辑电路带来不利影响,如,引起不规则的杂质扩散和结漏的RRAM区域周围的应力、较低产率和可靠性问题等。这能造成形成电压的增加。较大区域会有助于减小形成电压同时也提高存储器件的数据保持。
图1A示出了根据一些实施例的存储器件100a的俯视图,存储器件100a包括以一系列的列和行布置的多个存储单元。存储阵列101包括配置为存储数据的多个存储单元。为了说明的目的,图1A中的存储单元以两行和两列布置,其中,单个的单元被标记为C行-列,虽然典型的实施例会包含共同构成存储数字数据的存储阵列的数千、数百万或其他数量的行和列。存储单元C22包括夹在顶电极通孔104和底电极通孔106之间的RRAM单元102。底电极通孔106和与区域108相关联的第一金属接触件接触。参考数字110表示上方设置有存储单元的半导体衬底。
图1B示出了沿着存储单元C21的RRAM单元的长度方向的存储单元C21的截面图。RRAM单元位于半导体区108的上方,半导体区108包括诸如金属的导电区108a,并且在导电区108a的每一侧具有极低k介电区108b。介电保护层112位于半导体区108的正上方,该介电保护层112具有位于金属区108a上方的开口区,其中,介电保护层112的侧壁终止于金属108a上方的圆形端。介电保护层112保护半导体区108免受随后的蚀刻步骤的影响。在一个实施例中,底电极通孔(BEVA)106位于介电保护层上方的限定区的上方,以浸渍的方式遵循介电保护层112的圆形端的形状且位于与半导体区108中的金属108a接触的开口区上方。底电极(BE)114位于BEVA的上方且邻接BEVA的顶面。可变电阻式介电层或电阻式开关元件116设置为邻接BE的整个表面。顶电极(TE)118位于限定区处的可变电阻式介电层116的上方。在一个实施例中,顶电极118包括第一TE层118a和位于第一TE层118a的顶部的第二TE层118b。两个间隔件120a和120b各设置在TE层118的一侧。间隔件120a和120b也位于可变电阻式介电层116的两端上。顶电极通孔(TEVA)位于第二TE层118b的一侧。这种布局使得TEVA横向偏移于BEVA/金属界面或导电互连件,其中导电互连件将RRAM单元的底部连接至器件的剩余部分。抗反射层122设置在第二TE层118b的上方但不同于TEVA位置的位置处。抗反射层122位于金属区108a的垂直上方、TE层118b上方的凹陷中且由于制造工艺附带地位于这样的位置中,通过下文会有更详细地了解。
图2示出了根据本发明的用于形成具有横向偏移的BEVA和TEVA的RRAM器件的方法200的一些实施例的流程图。
虽然下面将公开的方法200示出和描述为一系列的步骤或事件,但是应该理解,不能限制性地解释这些步骤或事件的示出顺序。例如,有些步骤可以以不同的顺序进行和/或与除了示出的和/或描述的步骤或事件以外的其他步骤或事件同时进行。此外,无需所有示出的步骤来实现本说明书中的一个或多个方面或实施例。而且,可以以一个或多个单独的步骤和/或阶段进行本文描述的一个或多个步骤。
在202中,在第一位置处形成与RRAM单元的第一表面邻接的第一导电互连件。
在204中,在第二位置处形成与RRAM单元的第二表面邻接的第二导电互连件,这使得第一位置和第二位置彼此横向偏移。在一个实施例中,第一表面是RRAM单元的底面,而第二表面是RRAM单元的顶面。
图3示出了根据本发明的用于在RRAM单元上形成顶电极通孔(TEVA)的方法300的一些实施例的流程图。
虽然下面将公开的方法300示出和描述为一系列的步骤或事件,但是应该理解,不能限制性地解释这些步骤或事件的示出顺序。例如,有些步骤可以以不同的顺序进行和/或与除了示出的和/或描述的步骤或事件以外的其他步骤或事件同时进行。此外,无需进行示出的所有步骤来完成本发明的一个或多个方面或实施例。并且,可以以一个或多个单独的步骤和/或阶段进行本文描述的一个或多个步骤。
在302中,在RRAM单元的顶电极上方沉积抗反射/绝缘层。该抗反射层保护RRAM表面免受随后可能发生在RRAM单元上方的光刻图案化和蚀刻步骤的损害。在一些实施例中,沉积在TE上方的抗反射层包括氮氧化硅(SiON)。
在304中,进行包括各向异性蚀刻的光刻步骤以图案化和蚀刻顶电极,从而留下可变电阻式介电层开口或露出两端。在一些实施例中,光刻步骤没有完全去除覆在顶电极上面的位置处的抗反射层,且留下一些抗反射层在金属区的垂直上方的中心位置,其中,金属区形成与BEVA相关联的底接触件。在一些实施例中,在蚀刻步骤中完全去除抗反射层。
在306中,在半导体主体的整个上方沉积间隔件材料,以在整个RRAM单元的上方形成单层。在一些实施例中,间隔件材料包括氮化硅(SiN)。
在308中,蚀刻间隔件材料以在顶电极的两端形成间隔件。间隔件位于可变电阻式介电层的开放、暴露的端部位置上。
在310中,进行另一光刻步骤,该光刻步骤蚀刻限定区处的底电极,留下底电极两端的保护性介电层开口。
在312中,在横向远离中心位置的位置处形成与顶电极邻接的顶电极通孔(TEVA)。这样保证了TEVA不与绝缘抗反射层接触,由此不会像传统的布置那样增加接触电阻。TEVA也与将RRAM单元的底部连接至器件的剩余部分的导电互连件发生横向偏移。
图4示出了根据本发明的RRAM器件400的一些实施例的截面图,其中,RRAM器件400具有相互横向偏移的上覆导电互连件和下伏导电互连件。RRAM单元402夹在横向偏移的两个导电互连件之间。参考数字404表示与RRAM单元402的顶面402a邻接的上覆导电互连件,且参考数字406表示与RRAM单元402的底面402b邻接的下伏导电互连件。顶面402a上的突出虚线区表示上覆导电互连件所处的第一位置403a,且底面402b上的突出虚线区403b表示下伏导电互连件所处的第二位置403b。第一位置403a和第二位置403b彼此横向偏移。下列附图会详细解释横向偏移的概念。
图5A-图5D示出了横向偏移对象和未横向偏移对象的一些实施例。为了解释横向偏移的两个对象,引入了垂直于水平面且穿过两个对象的中心的两个轴线。如果两个轴线分隔开非零距离,那么可以说这两个对象是横向偏移或轴偏移。
图5A示出了沿着水平轴或横轴502的两个横向偏移对象504和506的布置500a。508是穿过对象504的中心的第一轴线,且510是穿过对象506的中心的第二轴线。参考数字512表示两个轴线之间观测到的非零距离。在这里,虽然两个对象看来沿着水平轴502重叠了一段距离,但是两个轴线之间的距离512表示对象504和508彼此横向偏移或轴偏移。
图5B表示横向偏移对象的另一个实施例的布置500b。在这种情况下,对象504和506的角部沿着横轴502在单一一点处接触。然而,两个垂直轴线508和510之间具有非零距离512,因此对象504和506彼此横向偏移或轴偏移。
图5C示出了布置500c中的横向偏移对象的另一个实施例。此处的对象504和506沿着水平轴502没有连接区。因此,轴线508和510之间具有非常明显的非零距离,且对象彼此横向偏移或轴偏移。
图5D表示布置500d,布置500d示出了两个对象没有横向偏移或同轴的一个实施例。两个轴线508和510之间没有距离或两个轴线彼此重叠,这就使得两个对象504和506彼此同轴或没有横向偏移。
图6示出了根据本发明的具有横向偏移的TEVA和BEVA的RRAM器件600的一些实施例的截面图。多个这样的RRAM器件形成配置为用于存储数据的存储阵列。在一个实施例中,选择晶体管与每个RRAM器件相关联。选择晶体管配置为抑制潜通路泄露(即,防止用于特定存储单元的电流流经邻近的存储单元),同时给存储单元的操作提供充足的驱动电流。图6包括常规的平面MOSFET选择晶体管601。选择晶体管601包括位于半导体主体602内的源极604和漏极606,源极604和漏极606被沟道区605水平地隔开。栅电极608位于半导体主体602上的一个位置,而该位置位于沟道区605的上方。在一些实施例中,栅电极包括多晶硅。通过横向延伸在半导体主体602的表面上方的栅极氧化层或栅极介电层607将栅电极608与源极604和漏极606分隔开。漏极606通过第一金属接触件612a连接至数据存储元件或RRAM单元620。源极604与第二金属接触件612b连接。栅电极连接至字线614a,源极通过第二金属接触件612b连接至选择线614b,且RRAM单元620通过附加金属接触件612g进一步连接至包括在上部金属化层中的位线614c。使用字线和位线可选择性地访问期望的RRAM器件以用于读出、写入和清除操作。有助于将RRAM存储器件连接至外部电路的包括612c、612d、612e和612f的一个或多个金属接触件和包括610a、610b、610c、610d、610e和610f等的金属接触通孔可存在于漏极和第一金属接触件之间以及源极和第二金属接触件之间。在一些实施例中,金属接触件包括铜(Cu)。
RRAM单元620包括夹在顶电极622和底电极623之间的电阻式开关元件/可变电阻式介电层621。在一些实施例中,顶电极包括钛(Ti)和氮化钽(TaN),底电极包括氮化钛(TiN),且电阻式开关元件包括二氧化铪(HfO2)。顶电极通孔(TEVA)624将存储单元620的顶电极622连接至上部金属化层612g,且底电极通孔(BEVA)625将RRAM单元620的底电极623连接至第一金属接触件/下部金属化层612a。为了降低TEVA624和下方绝缘层(未示出)之间可累积的接触电阻,将TEVA624和BEVA625以彼此横向偏移的方式设置,其中,绝缘层位于顶电极622上方的中心位置处。RRAM单元620也具有扩大的常规矩形区或细长区,以容纳横向偏移的TEVA和BEVA。较大的细长区能够降低形成电压和提高RRAM单元中的数据保持。
图7A-图7F示出了根据本发明的形成顶电极通孔(TEVA)的相应方法300的不同实施例的截面图。
图7A示出了包括RRAM单元、BEVA和下方的金属互连件的半导体主体700a的一个实施例的截面图。半导体主体700a包括半导体区702,半导体区702包括设置在绝缘层(诸如极低k介电层)704内的导电金属区703。在一些实施例中,金属区包括铜(Cu)且极低k介电层包括多孔二氧化硅、氟化硅玻璃、聚酰亚胺、聚降冰片烯、苯并环丁烯或PTFE。具有位于金属上方的开口区的介电保护层706设置在半导体区702的上方,其中,由于蚀刻,介电保护层的侧壁终止于金属上方的圆形端。在一些实施例中,介电保护层包括碳化硅(SiC)。底电极通孔(BEVA)708共形地位于介电保护层706上方的限定区的上方。底电极通孔708以浸渍的方式遵循介电保护层的圆形端的形状且也位于与半导体区702中的金属703接触的开口区的上方。在一些实施例中,BEVA包括氮化钽(TaN)。底电极(BE)710位于整个BEVA的上方,且可变电阻式介电层712位于BE的上方。可变电阻式介电层通常为绝缘的,但是,施加给可变电阻式介电材料的足够电压会在可变电阻式电介质中形成一个或多个导电通路。通过适当地施加不同电压(如,置位电压和复位电压),可调整导电通路以形成高电阻状态或低电阻状态。在一些实施例中,BE710包括氮化钛(TiN)且可变电阻式介电层包括二氧化铪(HfO2)。第一顶电极层714位于可变电阻式介电层712的顶部,且第二顶电极层716设置为邻接第一顶电极层714。在一些实施例中,第一顶电极层包括钛(Ti)且第二顶电极层包括TaN。绝缘抗反射层718设置为邻接整个第二顶电极层716。抗反射层718保护下伏层免受随后的蚀刻步骤的影响,且通过降低引起驻波的光反射提高图案化。在一些实施例中,抗反射层包括SiON。
图7B示出了在光刻图案化和蚀刻顶电极(TE)之后的半导体主体700b的实施例。在一些实施例中,执行各向异性蚀刻步骤,在两端位置上形成用于可变电阻式介电层的开放的暴露端713。在一个实施例中,光刻步骤没有从第二顶电极层716完全去除抗反射层718,且留下一些抗反射层718在金属区垂直上方的中心位置处。在另一个实施例中,在蚀刻步骤中完全去除抗反射层。
图7C示出了在半导体主体的整个上方沉积间隔件材料以在半导体主体的整个上方形成间隔层720之后的半导体主体700c的实施例。在一些实施例中,间隔件材料包括氮化硅(SiN)。
图7D示出了在蚀刻间隔层720以在顶电极的两端形成间隔件720a和720b之后的半导体主体700d的实施例。间隔件720a和720b位于可变电阻式介电层的开放的端位置上。
图7E示出了进行另一个光刻步骤来蚀刻限定区的底电极710和可变电阻式介电层712之后的半导体主体700e的实施例。这个蚀刻步骤将留下保护介电层在其两端位置处开放。
图7F示出了在远离浸渍区的位置形成顶电极通孔(TEVA)722之后的半导体主体700f的实施例。这将保证TEVA不与绝缘抗反射层718接触,因此,这种构造比常规设计明显提高了接触电阻变化率。所以,TEVA横向偏移于将RRAM单元的底部连接至器件的剩余部分的导电互连件。
图8示出了根据本发明的具有横向偏移的TEVA和BEVA以及没有绝缘抗反射层的顶电极表面的RRAM器件800的实施例。在这种情况下,在方法300的步骤304期间完全去除了抗反射层。
应该理解,在全文中引用示例性结构来讨论所描述的方法的方面,但这些方法并不受示出的相应结构的限制。相反,这些方法(和结构)被视为彼此独立且能够单独存在并且无需考虑附图所示的任何特定方面就可实施。此外,能够以诸如旋涂、溅射、生长和/或沉积技术等的任何合适的方式形成本文所描述的层。
并且,基于阅读和/或理解本说明书和附图,本领域的技术人员可想到等同的改变和/或修改。本公开包括所有这样的修改和改变并且通常不旨在限制于此。例如,虽然本文中提供的附图被示出和描述成具有特定的掺杂类型,但是应该理解,本领域的技术人员应该知道,也可使用可选的掺杂类型。
此外,虽然只通过若干实现的其中一个公开了一个特定部件或方面,但是如期望的那样,这样的部件或方面可与其他实现的一个或多个其他部件和/或方面结合。并且,在某种程度上,本文中使用了术语“包括”、“具有”、“有”、“带有”和/或其变体,这些术语旨在包含的意思,如“包括”。并且,“示例性的”仅意味着实例,而不是最佳实例。也应该理解,为了简化和便于理解,本文所述的部件、层和/或元件示出为具有特定尺寸和/或相互之间的方位,并且实际的尺寸和/或方位可基本不同于本文示出的尺寸和/或方位。
本发明涉及一种电阻式随机存取存储器(RRAM)器件,RRAM器件包括具有第一表面和第二表面的电阻式随机存取存储器(RRAM)单元、在第一位置处与第一表面邻接的第一导电互连件以及在第二位置处与第二表面邻接的第二导电互连件,其中,第一位置和第二位置是横向偏移的。
在一些实施例中,本发明涉及一种电阻式随机存取存储器(RRAM)器件,RRAM器件包括具有通过沟道区水平分隔开的源极区和漏极区的半导体主体、连接至沟道区的栅极结构、分别从漏极区和源极区向上延伸的第一接触件和第二接触件、形成在第一接触件的上方且电连接至第一接触件的第一导电互连件、形成在第一导电互连件的上方且具有第一表面和第二表面的电阻式随机存取存储器(RRAM)单元,形成在RRAM单元的上方且在第二位置处与第二表面邻接的第二导电互连件,其中,第一表面在第一位置处连接至第一导电互连件,并且,第一位置和第二位置是横向偏移的。
在另一个实施例中,本发明涉及一种形成电阻式随机存取存储器(RRAM)器件的方法,该方法包括:在第一位置处形成与RRAM单元的第一表面邻接的上覆导电互连件,以及在第二位置处形成与RRAM单元的第二表面邻接的下伏导电互连件,其中,第一位置和第二位置是横向偏移的。
Claims (18)
1.一种电阻式随机存取存储器(RRAM)器件,包括:
电阻式随机存取存储器(RRAM)单元,具有第一表面和第二表面;
顶电极通孔,在第一位置处与所述第一表面邻接;以及
底电极通孔,在第二位置处与所述第二表面邻接,其中,所述第一位置和所述第二位置彼此横向偏移;
其中,所述电阻式随机存取存储器单元包括顶电极和抗反射层,所述顶电极具有位于所述顶电极上方的凹陷,所述顶电极通孔位于所述顶电极的一侧,所述抗反射层设置在所述顶电极的上方的所述凹陷中但不同于所述顶电极通孔的位置的位置处。
2.根据权利要求1所述的电阻式随机存取存储器器件,其中,所述电阻式随机存取存储器单元包括:
可变电阻式介电层,具有顶面和底面;
所述顶电极,设置在所述可变电阻式介电层的上方且与所述顶面邻接;
底电极,设置在所述可变电阻式介电层的下方且与所述底面邻接;
其中,所述顶电极通孔与所述顶电极邻接,
所述底电极通孔与所述底电极邻接。
3.根据权利要求2所述的电阻式随机存取存储器器件,还包括:
半导体区,包括设置在形成于所述半导体区上方的极低k介电层内的金属;
介电保护层,具有位于所述金属上方的开口区,其中,所述介电保护层的侧壁终止于所述金属上方的圆形端;
绝缘层,与位于所述开口区上方的所述顶电极邻接;以及
间隔件,位于所述顶电极的每一侧。
4.根据权利要求3所述的电阻式随机存取存储器器件,其中:
所述底电极通孔位于所述介电保护层上方的限定区的上方,以浸渍的方式遵循所述介电保护层的所述圆形端的形状,且位于与所述半导体区中的所述金属相接触的所述开口区的上方;
所述底电极设置在所述底电极通孔的整个上方;
所述可变电阻式介电层设置在所述底电极的整个上方;
所述顶电极位于所述可变电阻式介电层上方的限定区的上方;以及
所述顶电极通孔位于与所述开口区和所述绝缘层横向偏移的位置处。
5.根据权利要求1所述的电阻式随机存取存储器器件,其中,所述电阻式随机存取存储器单元包括构成一个区域的长度尺寸和宽度尺寸,并且,所述顶电极通孔和所述底电极通孔设置在所述区域内。
6.根据权利要求1所述的电阻式随机存取存储器器件,其中,所述电阻式随机存取存储器单元的形状为矩形。
7.根据权利要求3所述的电阻式随机存取存储器器件,其中,所述顶电极包括氮化钽TaN或钛Ti,所述底电极包括氮化钛TiN,所述顶电极通孔包括铜Cu,所述底电极通孔包括TaN,所述可变电阻式介电层包括氧化铪HfO,所述间隔件包括氮化硅SiN,以及所述绝缘层包括氮氧化硅SiON。
8.一种电阻式随机存取存储器(RRAM)器件,包括:
半导体主体,具有被沟道区水平分隔开的源极区和漏极区;
栅极结构,连接至所述沟道区;
第一接触件和第二接触件,分别从所述漏极区和所述源极区向上延伸;
底电极通孔,形成在所述第一接触件的上方且电连接至所述第一接触件;
电阻式随机存取存储器(RRAM)单元,形成在所述底电极通孔的上方且具有第一表面和第二表面,其中,所述第一表面在第一位置处连接至所述底电极通孔;以及
顶电极通孔,形成在所述电阻式随机存取存储器单元的上方且在第二位置处与所述第二表面邻接,其中,所述第一位置和所述第二位置彼此横向偏移;
其中,所述电阻式随机存取存储器单元包括顶电极和抗反射层,所述顶电极具有位于所述顶电极上方的凹陷,所述顶电极通孔位于所述顶电极的一侧,所述抗反射层设置在所述顶电极的上方的所述凹陷中但不同于所述顶电极通孔的位置的位置处。
9.根据权利要求8所述的电阻式随机存取存储器器件,其中,所述栅极结构连接至字线。
10.根据权利要求8所述的电阻式随机存取存储器器件,其中,所述栅极结构包括形成在栅极电介质上方的多晶硅栅电极,所述栅极电介质将所述栅电极与所述沟道区电隔离。
11.根据权利要求8所述的电阻式随机存取存储器器件,其中,一个或多个金属接触件和一个或多个金属接触通孔存在于所述源极区和所述第二接触件之间以及所述漏极区和所述第一接触件之间。
12.根据权利要求8所述的电阻式随机存取存储器器件,其中,所述源极区连接至源极线,且所述漏极区连接至位线。
13.根据权利要求8所述的电阻式随机存取存储器器件,其中,所述源极区和所述漏极区具有第一导电率且所述半导体主体具有第二导电率。
14.一种形成电阻式随机存取存储器(RRAM)器件的方法,包括:
在第一位置形成与电阻式随机存取存储器单元的第一表面邻接的顶电极通孔;以及
在第二位置形成与所述电阻式随机存取存储器单元的第二表面邻接的底电极通孔,其中,所述第一位置和所述第二位置彼此横向偏移;
其中,所述电阻式随机存取存储器单元包括顶电极和抗反射层,所述顶电极具有位于所述顶电极上方的凹陷,所述顶电极通孔位于所述顶电极的一侧,所述抗反射层设置在所述顶电极的上方的所述凹陷中但不同于所述顶电极通孔的位置的位置处。
15.根据权利要求14所述的方法,其中,所述电阻式随机存取存储器单元还包括半导体区、介电保护层、底电极、可变电阻式介电层,其中所述半导体区包括设置在极低k介电层内的金属层。
16.根据权利要求15所述的方法,还包括:
光刻图案化和蚀刻所述顶电极;
在所述半导体主体的整个上方沉积间隔件材料层;
蚀刻所述间隔件材料层以在所述顶电极的每一侧形成间隔件、以及露出两端位置上的所述可变电阻式介电层;
光刻图案化和蚀刻堆叠件,所述堆叠件包括所述可变电阻式介电层、底电极和所述底电极通孔;以及
形成与所述顶电极邻接的所述顶电极通孔。
17.根据权利要求16所述的方法,其中,在蚀刻所述顶电极之后,在所述顶电极的上方保留所述抗反射层的一部分。
18.根据权利要求17所述的方法,其中,所述顶电极通孔横向偏移于所述抗反射层的所述一部分。
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US10700275B2 (en) | 2020-06-30 |
US9112148B2 (en) | 2015-08-18 |
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US11723292B2 (en) | 2023-08-08 |
US20150090949A1 (en) | 2015-04-02 |
US10199575B2 (en) | 2019-02-05 |
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US20150325786A1 (en) | 2015-11-12 |
US20200335694A1 (en) | 2020-10-22 |
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US9425392B2 (en) | 2016-08-23 |
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