JP5062180B2 - 抵抗変化素子及びその製造方法 - Google Patents
抵抗変化素子及びその製造方法 Download PDFInfo
- Publication number
- JP5062180B2 JP5062180B2 JP2008550007A JP2008550007A JP5062180B2 JP 5062180 B2 JP5062180 B2 JP 5062180B2 JP 2008550007 A JP2008550007 A JP 2008550007A JP 2008550007 A JP2008550007 A JP 2008550007A JP 5062180 B2 JP5062180 B2 JP 5062180B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- transition metal
- resistance change
- metal oxide
- change element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of the switching material, e.g. layer deposition
- H10N70/026—Formation of the switching material, e.g. layer deposition by physical vapor deposition, e.g. sputtering
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
- H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
- G11C2213/32—Material having simple binary metal oxide structure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/50—Resistive cell structure aspects
- G11C2213/55—Structure including two electrodes, a memory active layer and at least two other layers which can be a passive or source or reservoir layer or a less doped memory active layer
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/50—Resistive cell structure aspects
- G11C2213/56—Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/79—Array wherein the access device being a transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
Description
図9は、上述した抵抗変化素子を用いたReRAMの一例を示す断面図である。ここでは、本発明をスタック型ReRAMに適用した例を示している。また、ここでは、メモリセルがn型トランジスタにより構成されているものとする。
図10〜図12は、上述したReRAMの製造方法を工程順に示す断面図である。通常、半導体基板上にはメモリセルと同時に駆動回路(書き込み回路及び読み出し回路等)を構成するn型トランジスタ及びp型トランジスタを形成しているが、ここではそれらの図示は省略している。
Claims (4)
- 抵抗値の変化を利用してデータを記憶する抵抗変化素子において、
貴金属又は貴金属酸化物からなる接地側電極及び正極側電極と、
前記接地側電極に接して形成された遷移金属膜と、
前記遷移金属膜と前記正極側電極との間に形成された遷移金属酸化膜と
により構成されていて、
前記遷移金属酸化膜中の遷移金属と、前記遷移金属膜を構成する遷移金属とが同一種であることを特徴とする抵抗変化素子。 - 前記遷移金属膜がNiからなり、前記遷移金属酸化膜がNiOx(但し、xは任意の正数)からなることを特徴とする請求項1に記載の抵抗変化素子。
- 前記遷移金属膜の厚さが5nm以上、20nm以下であり、かつ前記遷移金属酸化膜の厚さが5nm以上、65nm以下であることを特徴とする請求項1に記載の抵抗変化素子。
- 半導体基板の上方に貴金属又は貴金属酸化物からなる第1の貴金属膜を形成する工程と、
前記第1の貴金属膜の上に遷移金属膜を形成する工程と、
前記遷移金属膜の上にスパッタ法により遷移金属酸化膜を形成する工程と、
前記遷移金属酸化膜の上に貴金属又は貴金属酸化物からなる第2の貴金属膜を形成する工程と
を有し、
前記遷移金属酸化膜中の遷移金属と、前記遷移金属膜を構成する遷移金属とを同一種とすることを特徴とする抵抗変化素子の製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2006/325297 WO2008075413A1 (ja) | 2006-12-19 | 2006-12-19 | 抵抗変化素子及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2008075413A1 JPWO2008075413A1 (ja) | 2010-04-02 |
JP5062180B2 true JP5062180B2 (ja) | 2012-10-31 |
Family
ID=39536052
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008550007A Expired - Fee Related JP5062180B2 (ja) | 2006-12-19 | 2006-12-19 | 抵抗変化素子及びその製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8106377B2 (ja) |
EP (1) | EP2099071B1 (ja) |
JP (1) | JP5062180B2 (ja) |
KR (1) | KR101187374B1 (ja) |
WO (1) | WO2008075413A1 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101176422B1 (ko) | 2009-06-23 | 2012-08-30 | 광주과학기술원 | 비휘발성 저항 변화 메모리 소자 |
WO2012044276A1 (en) | 2010-09-27 | 2012-04-05 | Hewlett-Packard Development Company, L.P. | Device structure for long endurance memristors |
US20120104346A1 (en) * | 2010-10-29 | 2012-05-03 | Wei Yi | Semiconductor device for providing heat management |
US8791445B2 (en) | 2012-03-01 | 2014-07-29 | Intermolecular, Inc. | Interfacial oxide used as switching layer in a nonvolatile resistive memory element |
TWI484490B (zh) * | 2012-11-14 | 2015-05-11 | Univ Nat Chiao Tung | 電阻式記憶體裝置及其操作方法 |
US9112148B2 (en) | 2013-09-30 | 2015-08-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | RRAM cell structure with laterally offset BEVA/TEVA |
US9425308B2 (en) * | 2013-12-31 | 2016-08-23 | Delta Electronics, Inc. | Power semiconductor device and method for fabricating the same |
WO2015134035A1 (en) | 2014-03-07 | 2015-09-11 | Hewlett-Packard Development Company, L.P. | Memristor devices with a thermally-insulating cladding |
US9178144B1 (en) | 2014-04-14 | 2015-11-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | RRAM cell with bottom electrode |
US9209392B1 (en) | 2014-10-14 | 2015-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | RRAM cell with bottom electrode |
US10381561B2 (en) | 2018-01-10 | 2019-08-13 | Internatoinal Business Machines Corporation | Dedicated contacts for controlled electroforming of memory cells in resistive random-access memory array |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005175457A (ja) * | 2003-12-08 | 2005-06-30 | Sharp Corp | Rramメモリセル電極 |
JP2005203389A (ja) * | 2004-01-13 | 2005-07-28 | Sharp Corp | 不揮発性半導体記憶装置の製造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7242469B2 (en) | 2003-05-27 | 2007-07-10 | Opto Trace Technologies, Inc. | Applications of Raman scattering probes |
KR100773537B1 (ko) | 2003-06-03 | 2007-11-07 | 삼성전자주식회사 | 한 개의 스위칭 소자와 한 개의 저항체를 포함하는비휘발성 메모리 장치 및 그 제조 방법 |
DE10342026A1 (de) | 2003-09-11 | 2005-04-28 | Infineon Technologies Ag | Speicherzelle mit Ionenleitungsspeichermechanismus und Verfahren zu deren Herstellung |
US7402456B2 (en) * | 2004-04-23 | 2008-07-22 | Sharp Laboratories Of America, Inc. | PCMO thin film with memory resistance properties |
KR100657911B1 (ko) | 2004-11-10 | 2006-12-14 | 삼성전자주식회사 | 한 개의 저항체와 한 개의 다이오드를 지닌 비휘발성메모리 소자 |
JP5049483B2 (ja) | 2005-04-22 | 2012-10-17 | パナソニック株式会社 | 電気素子,メモリ装置,および半導体集積回路 |
WO2006114904A1 (en) * | 2005-04-22 | 2006-11-02 | Matsushita Electric Industrial Co., Ltd. | Non volatile memory cell and semiconductor memory device |
JP4575837B2 (ja) * | 2005-05-19 | 2010-11-04 | シャープ株式会社 | 不揮発性記憶素子及びその製造方法 |
US20070048990A1 (en) * | 2005-08-30 | 2007-03-01 | Sharp Laboratories Of America, Inc. | Method of buffer layer formation for RRAM thin film deposition |
US20100090192A1 (en) * | 2006-08-31 | 2010-04-15 | Nxp, B.V. | Method for controlled formation of the resistive switching material in a resistive switching device and device obtained thereof |
-
2006
- 2006-12-19 KR KR1020097012525A patent/KR101187374B1/ko not_active IP Right Cessation
- 2006-12-19 JP JP2008550007A patent/JP5062180B2/ja not_active Expired - Fee Related
- 2006-12-19 EP EP06842901A patent/EP2099071B1/en not_active Not-in-force
- 2006-12-19 WO PCT/JP2006/325297 patent/WO2008075413A1/ja active Application Filing
-
2009
- 2009-06-18 US US12/519,913 patent/US8106377B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005175457A (ja) * | 2003-12-08 | 2005-06-30 | Sharp Corp | Rramメモリセル電極 |
JP2005203389A (ja) * | 2004-01-13 | 2005-07-28 | Sharp Corp | 不揮発性半導体記憶装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP2099071A1 (en) | 2009-09-09 |
EP2099071A4 (en) | 2011-01-19 |
KR20090090345A (ko) | 2009-08-25 |
US8106377B2 (en) | 2012-01-31 |
KR101187374B1 (ko) | 2012-10-02 |
US20100252796A1 (en) | 2010-10-07 |
WO2008075413A1 (ja) | 2008-06-26 |
JPWO2008075413A1 (ja) | 2010-04-02 |
EP2099071B1 (en) | 2012-08-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5062180B2 (ja) | 抵抗変化素子及びその製造方法 | |
KR101188198B1 (ko) | 저항 변화 소자 및 그 제조 방법 | |
US8102003B2 (en) | Resistance memory element, method of manufacturing resistance memory element and semiconductor memory device | |
US8258493B2 (en) | Nonvolatile semiconductor memory apparatus and manufacturing method thereof | |
JP6180700B2 (ja) | 不揮発性半導体記憶装置及びその製造方法 | |
US9123889B2 (en) | Resistance change nonvolatile memory device, semiconductor device, and method of manufacturing resistance change nonvolatile memory device | |
US8471235B2 (en) | Nonvolatile memory element having a resistance variable layer and manufacturing method thereof | |
JP5039857B2 (ja) | 記憶装置およびその製造方法 | |
JP5007725B2 (ja) | 抵抗変化素子の製造方法 | |
JPWO2008126166A1 (ja) | 不揮発性半導体記憶装置及びその読み出し方法 | |
JP2008294103A (ja) | 抵抗変化メモリ及びその製造方法 | |
JP5352966B2 (ja) | 抵抗変化メモリ装置の製造方法 | |
JP5062181B2 (ja) | 抵抗変化素子及びその製造方法 | |
CN113629098B (zh) | 电阻式存储器装置 | |
US20230284540A1 (en) | Resistive memory device with ultra-thin barrier layer and methods of forming the same | |
US20230157187A1 (en) | Resistive memory device with enhanced local electric field and methods of forming the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120501 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120606 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120710 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120723 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150817 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |