CN104009012B - 半导体芯片和半导体器件 - Google Patents

半导体芯片和半导体器件 Download PDF

Info

Publication number
CN104009012B
CN104009012B CN201410055843.1A CN201410055843A CN104009012B CN 104009012 B CN104009012 B CN 104009012B CN 201410055843 A CN201410055843 A CN 201410055843A CN 104009012 B CN104009012 B CN 104009012B
Authority
CN
China
Prior art keywords
substrate
pad
pads
row
mentioned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201410055843.1A
Other languages
English (en)
Chinese (zh)
Other versions
CN104009012A (zh
Inventor
棈松高志
別井隆文
黒田淳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of CN104009012A publication Critical patent/CN104009012A/zh
Application granted granted Critical
Publication of CN104009012B publication Critical patent/CN104009012B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
CN201410055843.1A 2013-02-22 2014-02-19 半导体芯片和半导体器件 Expired - Fee Related CN104009012B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2013-033097 2013-02-22
JP2013033097 2013-02-22
JP2013126533A JP6118652B2 (ja) 2013-02-22 2013-06-17 半導体チップ及び半導体装置
JP2013-126533 2013-06-17

Publications (2)

Publication Number Publication Date
CN104009012A CN104009012A (zh) 2014-08-27
CN104009012B true CN104009012B (zh) 2018-04-13

Family

ID=51346595

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201410055843.1A Expired - Fee Related CN104009012B (zh) 2013-02-22 2014-02-19 半导体芯片和半导体器件
CN201420070435.9U Expired - Lifetime CN203746832U (zh) 2013-02-22 2014-02-19 半导体芯片和半导体器件

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201420070435.9U Expired - Lifetime CN203746832U (zh) 2013-02-22 2014-02-19 半导体芯片和半导体器件

Country Status (4)

Country Link
US (2) US20140239493A1 (enExample)
JP (1) JP6118652B2 (enExample)
KR (1) KR20140105394A (enExample)
CN (2) CN104009012B (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6118652B2 (ja) * 2013-02-22 2017-04-19 ルネサスエレクトロニクス株式会社 半導体チップ及び半導体装置
JP6342221B2 (ja) 2014-06-02 2018-06-13 ルネサスエレクトロニクス株式会社 半導体装置
WO2016063459A1 (ja) * 2014-10-24 2016-04-28 株式会社ソシオネクスト 半導体集積回路装置
US9929095B2 (en) 2014-11-06 2018-03-27 Qualcomm Incorporated IO power bus mesh structure design
KR102264548B1 (ko) 2014-11-21 2021-06-16 삼성전자주식회사 반도체 패키지 및 그 제조 방법
CN112868094B (zh) * 2018-10-19 2024-05-28 株式会社索思未来 半导体芯片
US20200335463A1 (en) * 2019-04-22 2020-10-22 Mikro Mesa Technology Co., Ltd. Electrical binding structure and method of forming the same
CN114203681A (zh) * 2021-12-08 2022-03-18 通富微电子股份有限公司 防止热压焊空洞形成的基板及多层堆叠存储器

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5028986A (en) * 1987-12-28 1991-07-02 Hitachi, Ltd. Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices
CN1540754A (zh) * 2003-03-27 2004-10-27 ���µ�����ҵ��ʽ���� 半导体器件
CN102487020A (zh) * 2010-12-03 2012-06-06 新科金朋有限公司 形成引线上凸块互连的半导体器件和方法
CN102760721A (zh) * 2011-04-28 2012-10-31 瑞萨电子株式会社 半导体器件、半导体器件设计方法、半导体器件设计装置以及程序
CN203746832U (zh) * 2013-02-22 2014-07-30 瑞萨电子株式会社 半导体芯片和半导体器件

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5796171A (en) * 1996-06-07 1998-08-18 Lsi Logic Corporation Progressive staggered bonding pads
JP2781787B2 (ja) * 1996-08-29 1998-07-30 日本電気アイシーマイコンシステム株式会社 半導体チップのボンディングパッド配置構成及びその最適化方法
JPH10173087A (ja) 1996-12-09 1998-06-26 Hitachi Ltd 半導体集積回路装置
US6031258A (en) * 1998-03-06 2000-02-29 S3 Incorporated High DC current stagger power/ground pad
JP3407025B2 (ja) * 2000-06-08 2003-05-19 Necエレクトロニクス株式会社 半導体装置及びその製造方法
US6404043B1 (en) * 2000-06-21 2002-06-11 Dense-Pac Microsystems, Inc. Panel stacking of BGA devices to form three-dimensional modules
JP2002270779A (ja) * 2001-03-14 2002-09-20 Kawasaki Microelectronics Kk 半導体装置
JP2002280453A (ja) * 2001-03-19 2002-09-27 Mitsubishi Electric Corp 半導体集積回路
US6977440B2 (en) * 2001-10-09 2005-12-20 Tessera, Inc. Stacked packages
JP2004095923A (ja) * 2002-09-02 2004-03-25 Murata Mfg Co Ltd 実装基板およびこの実装基板を用いた電子デバイス
JP2005294406A (ja) * 2004-03-31 2005-10-20 Nec Electronics Corp 半導体集積回路装置および半導体集積回路装置の配線方法
US7683492B2 (en) * 2004-07-26 2010-03-23 System Fabrication Technologies, Inc. Semiconductor device
JP2006237459A (ja) * 2005-02-28 2006-09-07 Matsushita Electric Ind Co Ltd 配線基板およびそれを用いた半導体装置
US8841779B2 (en) * 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
US20070111376A1 (en) * 2005-04-29 2007-05-17 Stats Chippac Ltd. Integrated circuit package system
US7663216B2 (en) * 2005-11-02 2010-02-16 Sandisk Corporation High density three dimensional semiconductor die package
JP4740765B2 (ja) * 2006-02-24 2011-08-03 エルピーダメモリ株式会社 半導体装置及びその製造方法
JP5018155B2 (ja) * 2007-03-16 2012-09-05 富士通セミコンダクター株式会社 配線基板、電子部品の実装構造、及び半導体装置
KR101224426B1 (ko) * 2007-12-28 2013-01-22 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치 및 그 제조 방법
JP2009164195A (ja) * 2007-12-28 2009-07-23 Panasonic Corp 半導体チップ
JP2010010492A (ja) * 2008-06-27 2010-01-14 Sony Corp 半導体装置および半導体集積回路
JP4918069B2 (ja) 2008-06-30 2012-04-18 パナソニック株式会社 半導体装置
US8659172B2 (en) * 2008-12-31 2014-02-25 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material with solder mask patch
JP5503466B2 (ja) * 2010-08-31 2014-05-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5709309B2 (ja) * 2011-03-28 2015-04-30 京セラサーキットソリューションズ株式会社 配線基板
US8946900B2 (en) * 2012-10-31 2015-02-03 Intel Corporation X-line routing for dense multi-chip-package interconnects
KR20140143567A (ko) * 2013-06-07 2014-12-17 삼성전기주식회사 반도체 패키지 기판 및 반도체 패키지 기판 제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5028986A (en) * 1987-12-28 1991-07-02 Hitachi, Ltd. Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices
CN1540754A (zh) * 2003-03-27 2004-10-27 ���µ�����ҵ��ʽ���� 半导体器件
CN102487020A (zh) * 2010-12-03 2012-06-06 新科金朋有限公司 形成引线上凸块互连的半导体器件和方法
CN102760721A (zh) * 2011-04-28 2012-10-31 瑞萨电子株式会社 半导体器件、半导体器件设计方法、半导体器件设计装置以及程序
CN203746832U (zh) * 2013-02-22 2014-07-30 瑞萨电子株式会社 半导体芯片和半导体器件

Also Published As

Publication number Publication date
US20140239493A1 (en) 2014-08-28
US9190378B2 (en) 2015-11-17
US20140284818A1 (en) 2014-09-25
JP2014187343A (ja) 2014-10-02
JP6118652B2 (ja) 2017-04-19
CN203746832U (zh) 2014-07-30
CN104009012A (zh) 2014-08-27
KR20140105394A (ko) 2014-09-01

Similar Documents

Publication Publication Date Title
CN104009012B (zh) 半导体芯片和半导体器件
JP4438006B2 (ja) 半導体装置及び半導体装置の製造方法
JP7001530B2 (ja) 半導体装置
US20110169170A1 (en) Semiconductor device
JP4719009B2 (ja) 基板および半導体装置
JPH08298269A (ja) 半導体装置及びその製造方法
JPH07153903A (ja) 半導体装置パッケージ
CN102376681A (zh) 封装基板
US11367679B2 (en) Semiconductor package including an in interposer and method of fabricating the same
KR20100069589A (ko) 반도체 디바이스
KR101740878B1 (ko) 반도체 장치
KR101096455B1 (ko) 방열 유닛 및 그 제조방법과 이를 이용한 스택 패키지
TWI770287B (zh) 半導體裝置
US10553558B2 (en) Semiconductor device
JP2009188275A (ja) 半導体チップ、半導体装置、半導体装置の製造方法、および液晶モジュール
JP2012234863A (ja) 半導体装置
TWI567910B (zh) 薄膜覆晶封裝體及薄膜封裝基板
CN101465341B (zh) 堆叠式芯片封装结构
TWI435667B (zh) 印刷電路板組件
US8039941B2 (en) Circuit board, lead frame, semiconductor device, and method for fabricating the same
TWI360877B (en) Stackable window bga semiconductor package and sta
JP2013026291A (ja) 半導体装置
TW201306197A (zh) 以金屬柱銲接為晶片連接之半導體封裝構造
JP5103155B2 (ja) 半導体装置およびその製造方法
CN118198024A (zh) 薄膜覆晶封装结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
CB02 Change of applicant information

Address after: Tokyo, Japan

Applicant after: Renesas Electronics Corporation

Address before: Kanagawa, Japan

Applicant before: Renesas Electronics Corporation

COR Change of bibliographic data
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20180413

Termination date: 20210219

CF01 Termination of patent right due to non-payment of annual fee