CN103782349A - 在电子器件中使用的富碳的碳氮化硼介电膜 - Google Patents

在电子器件中使用的富碳的碳氮化硼介电膜 Download PDF

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CN103782349A
CN103782349A CN201280043509.3A CN201280043509A CN103782349A CN 103782349 A CN103782349 A CN 103782349A CN 201280043509 A CN201280043509 A CN 201280043509A CN 103782349 A CN103782349 A CN 103782349A
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dielectric film
atomic percents
dielectric
carbon
layer
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桑·范·恩古叶恩
A·格瑞尔
T·J海格
S·麦合塔
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International Business Machines Corp
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Abstract

提供一种介电常数等于或小于3.6的富碳的碳氮化硼介电膜，它可被用作各种电子器件中的组件。富碳的碳氮化硼介电膜具有式子CxByNz，其中，x为35原子百分比或更大，y为6原子百分比到32原子百分比，以及z为8原子百分比到33原子百分比。

Description

在电子器件中使用的富碳的碳氮化硼介电膜
技术领域
本发明涉及在各种电子器件中使用的介电膜，更具体地，涉及富碳的碳氮化硼介电膜。本发明还涉及包括所述富碳的碳氮化硼介电膜的电子器件以及形成所述富碳的碳氮化硼介电膜的方法。
背景技术
电子器件的规模不断扩大要求降低RC(电阻/电容)延迟以便增大器件电路中的计时速度。通过采用新材料用于前端制程(FEOL)集成和/或后端制程(BEOL)集成，能够实现寄生电容的降低。例如，为了满足标准的BEOL可靠性要求，需要具有小于4.0的低介电常数(k)的新介电膜。另外，FEOL应用需要具有小于4.0的介电常数的新介电膜。
发明内容
本公开提供了一种具有低介电常数k的富碳的碳氮化硼介电膜。“低介电常数”或“低k”意味着本公开的富碳的碳氮化硼介电膜具有等于或小于3.6的介电常数。“富碳”意味着本公开的富碳的碳氮化硼介电膜具有35原子百分比或更大的碳含量。本公开的富碳的碳氮化硼介电膜可被用作各种电子器件中的绝缘体，例如包括用作互连结构的介电盖、金属氧化物半导体(MOS)场效应晶体管(FET)的间隔物、或者用作在含石墨烯器件中使用的介电材料。
在本发明的一个实施例中，提供了一种介电膜，所述介电膜具有式子CxByNz，其中，x是35原子百分比或更大，y是6原子百分比到32原子百分比，z是8原子百分比到33原子百分比。
在再一个实施例中，提供了一种电子器件，所述电子器件包括衬底和位于所述衬底表面上的介电膜。位于衬底表面上的介电膜具有式子CxByNz，其中，x是35原子百分比或更大，y是6原子百分比到32原子百分比，z是8原子百分比到33原子百分比。
在又一个实施例中，提供了一种形成介电膜的方法。具体地，本公开的方法包括：把衬底置于反应室中；向反应室提供至少包括C、B和N原子的至少一种前体；以及在衬底的表面上淀积介电膜。淀积的介电膜具有式子CxByNz，其中，x是35原子百分比或更大，y是6原子百分比到32原子百分比，z是8原子百分比到33原子百分比。
附图说明
图1是图解说明可在本发明的一个实施例中采用的初始结构的横截面图。
图2是图解说明在其上形成富碳的碳氮化硼介电膜之后，图1的初始结构的横截面图。
图3是图解说明可在本发明中采用的另一种初始结构的横截面图，其中，在其上形成富碳的碳氮化硼介电膜。
图4A、4B和4C是描述包括富碳的碳氮化硼介电膜的一些例证电子器件的横截面图。
图5是描述包括富碳的碳氮化硼介电膜作为栅极间隔物的电子器件的横截面图。
图6A和6B是描述包括位于一层碳基衬底上的富碳的碳氮化硼介电膜的电子器件的横截面图。
具体实施方式
下面将参考伴随本申请的以下讨论和附图，更详细地说明本公开，本公开涉及一种富碳的碳氮化硼介电膜、包括富碳的碳氮化硼介电膜的电子器件、和形成富碳的碳氮化硼介电膜的方法。注意，本申请的附图是出于举例说明的目的提供的，因而这些附图不是按比例绘制的。
在下面的说明中，记载了众多的具体细节，比如特定的结构、组件、材料、尺寸、处理步骤和技术，以便充分理解本公开。然而，本领域的技术人员会理解，可以在没有这些具体细节的情况下，利用可行的备选处理选项来实践本公开。在其它情况下，没有详细说明公知的结构或处理步骤，以避免模糊本公开的各个实施例。
应明白，当作为层、区域或衬底的元件被称为在另一个元件上或上方时，该元件可以直接在所述另一个元件上，或者也可存在居间元件。相反，当元件被称为直接在另一个元件上或上方时，则不存在居间元件。另外应明白，当元件被称为在另一个元件下或下面时，该元件可以直接在所述另一个元件下或下面，或者可能存在居间元件。相反，当元件被称为直接在另一个元件下或下面时，则不存在居间元件。
如上所述，本发明的实施例提供了一种碳含量为35原子百分比或更大的富碳的碳氮化硼介电膜。特别地，提供了一种包含35原子百分比或更大量的碳原子，6原子百分比到32原子百分比的量的硼原子，和8原子百分比到33原子百分比的量的氮原子的富碳的碳氮化硼介电膜。本公开的富碳介电膜还可包括作为可选元素的氧和氢至少之一。本发明的实施例的富碳的碳氮化硼介电膜具有等于或小于3.6的介电常数。
在一个实施例中，富碳的碳氮化硼介电膜可被用作各种电子器件中的绝缘体组件，例如包括用作互连结构的介电盖、金属氧化物半导体(MOS)场效应晶体管(FET)的间隔物、或者用作在含石墨烯器件中使用的介电材料。当富碳的碳氮化硼介电膜能被用作介电盖时，富碳介电膜降低互连结构的总有效电容，从而提高器件性能。
现在参考图1，图1图解说明了可在本发明的一个实施例中采用的初始结构10。图1中描述的初始结构包括衬底12。优选采用的衬底12包括半导体材料、绝缘材料、导电材料或者它们的任何组合，包括多层结构。
在一个实施例中，当衬底12是或者包括半导体材料时，半导体材料可以是具有半导体性质的任何材料，例如包括Si、Ge、SiGe、SiGeC、SiC、GaAs、InAs、InP和其它III/V或II/VI化合物半导体。分层的半导体材料，比如Si/SiGe、Si/Ge、Si/SiC、绝缘体上硅(SOI)或者绝缘体上硅锗(SGOI)也可被用作衬底12。
当衬底12是或者包括绝缘材料时，绝缘材料可以是有机绝缘体、无机绝缘体或者它们的组合(包括多层)。当衬底12是或者包括导电材料时，导电材料12可包括例如掺杂B、P或As的多晶硅、单质金属、单质金属的合金、金属硅化物、金属氮化物和它们的组合(包括多层)。
在另一个实施例中，衬底12包括半导体材料和绝缘材料的组合、半导体材料和导电材料的组合、或者半导体材料、绝缘材料和导电材料的组合。
在另一个实施例中，衬底12是碳基材料，例如包括石墨烯、石墨和碳纳米管。在其它实施例中，碳基材料可以位于基础衬底上，所述基础衬底可以是半导体材料、介电材料、导电材料或者它们的任何组合(包括多层堆叠)。
这里，术语“石墨烯”用于描述密集聚集在蜂窝晶格中的sp2-键合碳原子的单原子厚度平面片材。可被用作衬底12的石墨烯具有六角形晶体键合结构。石墨烯可包括单层石墨烯(名义上厚度为0.34nm)，几层石墨烯(2到10层石墨烯)，多层石墨烯(>10层石墨烯)，单层、几层和多层石墨烯的混合物，或者与非晶和/或无序碳相混合的石墨烯层的任何组合。如果需要，这还可包括取代、填隙和/或插层掺杂物。当石墨烯被用作衬底12时，可以利用本领域中公知的技术来形成石墨烯。例如，可以利用石墨的机械剥离，碳化硅上的外延生长，金属衬底上的外延生长，肼还原法(其中将氧化石墨烯纸置于纯肼溶液中，该纯肼溶液把氧化石墨烯纸还原成单层石墨烯)，以及乙醇的钠还原法(即，利用金属钠还原乙醇，随后热解乙氧基产物，并洗涤以除去钠盐)，来形成石墨烯。形成石墨烯的另一种方法可以是从碳纳米管形成石墨烯。
当碳纳米管被用作衬底12时，碳纳米管可以是单壁或多壁的。碳纳米管一般具有折叠的六角形晶体键合结构。尽管可以使用单个碳纳米管，但一般使用碳纳米管的阵列。当碳纳米管被用作衬底12时，可以利用本领域的技术人员公知的技术来形成碳纳米管。可用于形成碳纳米管的适当技术的例子包括(但不限于)电弧放电、激光消融、化学气相淀积和等离子体增强化学气相淀积。
可被用作衬底12的其它可能的碳基材料包括具有短程六角形和非晶晶体键合结构的石墨，以及具有轻微变形的六角形晶体键合结构的各种形式的碳材料，比如蓝丝黛尔石或者密集聚集的六角形键合相富勒烯。
参见图2，图中图解说明了在衬底12的表面上形成富碳的碳氮化硼介电膜14之后，图1的初始结构10。如上所述，富碳的碳氮化硼介电膜14包含碳(C)原子、硼(B)原子和氮(N)原子。富碳的碳氮化硼介电膜14还可包括氧和氢之一作为可存在于其中的可选元素。富碳的碳氮化硼介电膜14也可被称为具有式子CxByNz的富碳介电膜，其中，x是存在于膜中的碳的原子百分比，y是存在于膜中的硼的原子百分比，z是存在于膜中的氮的原子百分比。这里，将在下面更详细地讨论x、y和z的值。
本公开的富碳的碳氮化硼介电膜14具有等于或小于3.6的介电常数。在一个实施例中，富碳的碳氮化硼介电膜14具有为2.5到3.2的介电常数。除非另有说明，否则所有的介电常数都是相对于真空的。在另一个实施例中，富碳的碳氮化硼介电膜14具有小于2.5的介电常数。在一个实施例中，富碳的碳氮化硼介电膜14是无孔的。在另一个实施例中，富碳的碳氮化硼介电膜14是多孔的。‘多孔’意味着膜中存在孔隙。
如上所述，本发明的富碳介电膜14是富碳的。‘富碳’意味着富碳的碳氮化硼介电膜14具有大于或等于35原子百分比的碳含量(即，x)。在另一个实施例中，富碳的碳氮化硼介电膜14中的碳含量(即,x)为35原子百分比到约70原子百分比。
富碳的碳氮化硼介电膜14还包括硼。富碳的碳氮化硼介电膜14中的硼含量(即，y)为6原子百分比到32原子百分比。在另一个实施例中，富碳的碳氮化硼介电膜14中的硼含量(即，y)为15原子百分比到约32原子百分比。
富碳的碳氮化硼介电膜14还包括氮。富碳的碳氮化硼介电膜14中的氮含量(即，z)为8原子百分比到33原子百分比。在另一个实施例中，富碳的碳氮化硼介电膜14中的氮含量(即，y)为15原子百分比到33原子百分比。在一些实施例中，氮均匀地分布在整个富碳的碳氮化硼介电膜14中。在本公开的另一个实施例中，在富碳的碳氮化硼介电膜14的选择区域中提供氮，从而提供在氮含量方面分级的介电膜。
在一些实施例中，x(碳含量)、y(硼含量)和z(氮含量)之和为100原子百分比。在这样的实施例中，在富碳的碳氮化硼介电膜14中，不存在除碳、硼和氮以外的其它元素。在一些其它实施例中，x(碳含量)、y(硼含量)和z(氮含量)之和不为100原子百分比。在这样的实施例中，在富碳的碳氮化硼介电膜14中，可以存在诸如氧和/或氢之类的元素。
当在富碳的碳氮化硼介电膜14中存在氧时，氧的含量为1原子百分比到10原子百分比。在另一个实施例中，当在富碳的碳氮化硼介电膜14中存在氧时，氧含量为1原子百分比到4原子百分比。
当在富碳的碳氮化硼介电膜14中存在氢时，氢的含量可从10原子百分比变化到40原子百分比。在另一个实施例中，当在富碳的碳氮化硼介电膜14中存在氢时，氢含量可为10原子百分比到25原子百分比。
在一个实施例中，富碳的碳氮化硼介电膜14具有40GPa到90GPa的模量。在另一个实施例中，对于淀积态富碳的碳氮化硼介电膜来说，富碳介电膜具有200MPa到800MPa的压应力。在另一个实施例中，对于UV固化(450秒到1450秒)的富碳的碳氮化硼介电膜来说，富碳介电膜具有150MPa到50MPa的压应力。
可以通过首先把衬底10置于反应室中，向反应室提供至少包含C、B和N原子的至少一种前体，以及在衬底12的表面上淀积富碳的碳氮化硼介电膜14，来形成富碳的碳氮化硼介电膜14。在一个实施例中，可以利用等离子体增强化学气相淀积(PECVD)工艺来进行富碳的碳氮化硼介电膜14的淀积。在另一个实施例中，可以利用化学气相淀积(CVD)、原子层淀积(ALD)或者旋涂工艺，来进行富碳的碳氮化硼介电膜14的淀积。其它淀积工艺也是可能的，只要所述其它淀积工艺能够形成上面说明的富碳的碳氮化硼介电膜。
富碳的碳氮化硼介电膜14的厚度可变；富碳的碳氮化硼介电膜14的一般范围为1nm到500nm，厚度一般为5nm到200nm。
可以利用各种前体来淀积富碳的碳氮化硼介电膜14，所述各种前体可以是液态、气态或蒸汽态。在一个实施例中，可以利用全气态前体来形成富碳的碳氮化硼介电膜14。在这个实施例中，可以采用含硼前体、含氮前体和含烃前体。在一些实施例中，含硼前体和含氮前体可被组合成单个前体。在另外的其它实施例中，含硼前体、含氮前体和含烃前体可全被组合成单个前体。
在另一个实施例中，可以利用至少一种气态前体和至少一种液态前体来形成富碳的碳氮化硼介电膜14。例如，可以利用含硼和氮的液态前体和含烃的气态前体来形成富碳的碳氮化硼介电膜14。
当采用含硼前体(液态、蒸汽态或气态)形成富碳的碳氮化硼介电膜14时，含硼前体可包括包含硼的任何材料。可在本公开中采用的含硼前体的例子包括(但不限于)乙硼烷、三乙基硼烷、三氯化硼和三氟化硼。
当采用含氮前体(液态、蒸汽态或气态)形成富碳的碳氮化硼介电膜14时，含氮前体可包括包含氮的任何材料。可在本公开中采用的含氮前体的例子包括(但不限于)N2和NH3。预期在氮含量方面无分级和分级的富碳介电膜。通过改变引入反应器的含氮前体的量来实现分级。
可用于形成富碳的碳氮化硼介电膜14的含烃前体(液态、蒸汽态或气态)是具有一个或多个碳原子之间的双键或三键的不饱和烃。这里，具有双键的含不饱和烃前体可被称为烯烃，并被表征为具有式子CnH2n，其中，n是等于或大于2的整数，n的值一般取2到16。可被用作含烃前体的烯烃的例子包括(但不限于)C2H4、C2H6、C3H6和C4H8。
这里，包含三键的不饱和烃可被称为炔烃，并被表征为具有式子CmH2m-2，其中，m是等于或大于2的整数，m的值一般取2到16。可被用作含烃前体的炔烃的例子包括(但不限于)C2H2。
当采用组合的含氮和硼的前体形成富碳的碳氮化硼介电膜14时，所述组合的含氮和硼的前体在单个化合物中包含氮和硼两者。可在本公开中采用的组合的含氮和硼的前体的例子包括(但不限于)环硼氮烷、烷基环硼氮烷、乙烯基环硼氮烷和乙烯基烷基环硼氮烷。
当采用组合的含氮、硼和烃的前体形成富碳的碳氮化硼介电膜14时，所述组合的含氮、硼和烃的前体在单个化合物中包含氮、硼和烃。可以采用的组合的含氮、硼和烃的前体的例子包括(但不限于)乙硼烷、NH3和烯烃的组合。在一些实施例中，可以使用乙硼烷、NH3与单烷基、二烷基、三烷基和四烷基乙硼烷的组合。在其它实施例中，可以使用具有氨和三甲胺烷基硼烷的前体。
在一个实施例中，能够利用包括提供平行板反应器的步骤的方法来淀积富碳的碳氮化硼介电膜14，所述平行板反应器具有85cm2到1600cm2的衬底夹盘导电面积，衬底和上电极之间的间隙为1cm到12cm。可以0.45MHz到200MHz的频率，向电极之一施加高频RF功率。可选地，可向电极之一施加另外的低频功率。本具体实施例中，用于淀积步骤的条件可根据期望的富碳的碳氮化硼介电膜14的最终介电常数而变化。大致地，用于形成介电常数等于或小于3.6的富碳的碳氮化硼介电膜14的条件包括：把衬底温度设定在200℃到425℃的温度；把高频RF功率密度设定在0.1W/cm2到1.5W/cm2的范围内；把液态含硼前体流速设定在100mg/min到3000mg/min的范围内(或者把气态含硼前体流速设定在50sccm到1000sccm的范围内)，把含氮前体流速设定在20sccm到1000sccm的范围内，以及把含烃前体流速设定在50sccm到2000sccm的范围内；可选地，把诸如氦气(或/和氩气)之类的惰性载气流速设定在50sccm到2000sccm的范围内；把反应器压力设定在从1000mTorr到7000mTorr范围内的压力；以及把高频RF功率设定在75W到1000W的范围内。可选地，可在30W到400W的范围内，向等离子体增加超低频功率。当按系数X改变衬底夹盘导电面积时，施加于衬底夹盘的RF功率也按系数X被改变。可以使用其它条件和前体，只要它们能够淀积上面说明的富碳的碳氮化硼介电膜14。
在淀积富碳的碳氮化硼介电膜14之后，淀积的富碳的碳氮化硼介电膜14可视情况经受在非氧化环境中进行的固化步骤。“固化”意味着视情况(不过不一定)在加热循环的至少一个循环中，在不低于300℃的温度下，最好在300℃到420℃的温度下，热处理淀积的富碳的碳氮化硼介电膜14至少0.10小时。“非氧化环境”意味着氧含量小于20ppm的气氛。在一些实施例中，可以采用氧含量小于10ppm的非氧化环境。注意，固化可在淀积富碳的碳氮化硼介电膜14时使用的同一个反应室中进行，或者固化可在单独的反应室中进行。热处理步骤(即，固化)可包括快速热退火、炉退火、激光退火或尖峰退火。在一些实施例中，在无氧气氛，比如惰性气体(例如，He、Ar或其混合物)中进行固化。
在本公开的另外的其它实施例中，可在单个温度下进行固化步骤。在本公开的再一些实施例中，可在两个或者更多个不同温度下进行固化步骤。例如，在一个实施例中，可在不高于300℃的温度下持续第一段时间进行固化，随后在不低于400℃的温度下持续第二段时间进行固化，所述第二段时间长于第一段时间。在一些实施例中，第二段时间至少10倍长于第一段时间。
也可利用高能淀积后处理步骤来固化富碳的碳氮化硼介电膜14。可在比上面提及的热固化更短的时间内进行这种高能淀积后处理步骤。具体地，可以利用高能源来处理富碳的碳氮化硼介电膜14。可以用于后处理步骤的适当能源包括化学能源、紫外(UV)光、电子束(E-beam)、微波和等离子体。可以按小于或等于5分钟的较短固化时间单独地或者与热固化一起使用上述能源的组合。利用热和/或高能UV/E-Beam固化的后处理使在利用含烃前体的等离子体淀积期间并入膜结构中的任何游离烃上升。这种处理将在富碳的碳氮化硼介电膜14中产生少量的纳米孔隙。“小”意味着富碳的碳氮化硼介电膜14的纳米孔隙为0.5nm到3nm，其中通常的优选范围为0.5nm到1.2nm。
可通过在一般把晶片温度维持在25℃到500℃的温度(典型的温度为300℃到420℃)的同时，利用能够产生波长500nm到150nm的光的光源来照射衬底，进行UV光处理步骤。波长小于370nm的照射不具有足以离解或活化重要键的能量，从而在本公开中一般采用150到370nm的波长范围。利用文献数据和对淀积的富碳介电膜测得的吸收光谱，发明人发现，由于富碳介电膜的退化，小于170nm的照射并不可取。此外，由于310到370nm范围内，每个光子的能量较低，因此与150到310nm的范围相比，310到370nm的能量范围不太有益。在150到310nm范围内，可视情况利用与淀积膜的吸收光谱的最佳重叠和膜性质(比如疏水性)的最小退化来选择UV光谱的最有效范围，以便改变富碳介电膜的性质。
在把晶片温度保持在25℃到500℃的温度的同时，通过利用能够以0.5keV到25keV的能量和0.1mA/cm2到100mA/cm2的电流密度在晶片上产生均匀电子通量的源，来进行电子束处理步骤。在一个实施例中，在电子束处理步骤中使用的电子的剂量从50mC/cm2到500mC/cm2不等。在一个实施例中，对400到900nm厚的UV固化(450到1450秒)的富碳的碳氮化硼介电膜来说，富碳介电膜具有在30GPa到90GPa范围内的模量、150MPa到800MPa的压应力、以及在3.2到5.0范围内的介电常数。
现在参考图3，图3图解说明了在互连结构20的表面上形成的富碳的碳氮化硼介电膜14。互连结构20包括其中嵌有至少一种导电材料24的互连介电材料22。可以利用本领域技术人员公知的常规处理步骤来形成互连结构20。例如，可以采用单镶嵌或双镶嵌工艺。在这个具体实施例中，富碳的碳氮化硼介电膜14充当互连结构20的介电盖。在本公开的一些实施例中，富碳的碳氮化硼介电膜14完全覆盖互连结构20的整个上表面。在另一个实施例中，富碳的碳氮化硼介电膜14只位于所述至少一种导电材料24之上。在又一个实施例中，富碳的碳氮化硼介电膜部分覆盖所述至少一种导电材料24，并且部分或者完全覆盖互连介电材料22。
互连介电材料22包括任何层间或层内电介质，包括无机电介质或有机电介质。互连介电材料22可以是多孔的、无孔的或者包含多孔的区域和/或表面以及无孔的其它区域和/或表面。可被用作互连介电材料22的适当电介质的一些例子包括(但不限于)二氧化硅、倍半硅氧烷、包括Si、C、O和H原子的掺碳氧化物(即，有机硅酸盐)、热固性聚亚芳基醚、或者它们的多层。本申请中利用术语“聚亚芳基”表示通过键、稠环或者惰性连接基团，比如氧、硫、砜、亚砜、羰基等连接在一起的芳基部分或者惰性取代的芳基部分。所述至少一种导电材料24可包括例如多晶硅、单质金属、单质金属的合金、金属硅化物和/或金属氮化物。可以通过利用本领域中公知的常规技术，例如包括化学气相淀积、等离子体增强化学气相淀积、蒸镀和旋涂，来形成互连介电材料22。同样地，可以通过利用本领域中公知的常规淀积技术，例如包括电镀、溅射、物理气相淀积、蒸镀和化学气相淀积，来形成所述至少一种导电材料24。
图4A、4B和4C中示出了另外的可包含富碳的碳氮化硼膜的电子器件。应注意，图4A、4B和4C中所示的器件仅仅是说明性的例子。
在图4A中，示出了在半导体衬底32上构成的电子器件60。在衬底32之上，首先形成第一互连介电材料层34，在其中嵌入第一导电材料区域36。在对第一导电材料区域36进行CMP处理之后，在第一互连介电材料层34和第一导电材料区域36之上，形成第二互连介电材料层38。第一和第二互连介电材料层可适当地由上面关于互连介电材料22提及的介电材料之一形成，而第一导电材料区域36可包含上面关于导电材料24提及的金属之一。随后在继之以蚀刻的光刻处理中，第二互连介电材料层38被图案化，并在上面淀积导体层40(它可以是与第一导体层36相同或不同的材料)。在进行对导体层40的CMP处理之后，覆盖第二互连介电材料层38和导体层40而形成第三互连介电材料层44(它可以是与第一和第二互连介电层相同或不同的介电材料)。导体层40与第一导电材料区域36电连通。
在进行对第三互连介电材料层44的光刻处理，接下来的蚀刻和随后对第二导体材料的淀积处理之后，形成第二导电材料区域50。第二导电材料区域50可以是上面关于导电材料24提及的材料之一。第二导电材料区域50与第一导电材料区域40电连通，并被嵌入第三互连介电材料层44中。第三互连介电材料层44与第二互连介电材料层38密切接触，在一些实施例中，第二互连介电材料层38可由本发明的富碳的碳氮化硼膜构成。
图4A还示出淀积在第二互连介电材料层38和第三互连介电材料层44之间的介电盖层62。介电盖层62可包括本发明的富碳的碳氮化硼膜。介电盖层62起到扩散阻挡层的作用，用于防止第一导体层40扩散到第三互连材料层44中，或者扩散到下面的各层中，尤其是扩散到层34和层32中。
图4B图解说明备选的电子器件70。在电子器件70中，利用了充当RIE掩模和CMP(化学机械抛光)抛光终止层的额外两个介电盖层72和74。第一介电盖层72淀积在第二互连介电材料层38之上，并用作RIE掩模和CMP终止层，从而在CMP之后，第一导体层40和层72近似共面。第二介电盖层74的作用与层72类似，然而，层74用于使第二导体层50平面化。抛光终止层74可通过淀积适当的介电材料，比如氧化硅、氮化硅、氮氧化硅、碳化硅、氧碳化硅(SiCO)、氮氧碳化硅(SiCON)或者它们的加氢化合物来形成。另一方面，本公开的富碳的碳氮化硼介电膜可被用作抛光终止层74的材料。
图4C图解说明了另外一种备选的电子器件80。在这个实施例中，淀积额外的介电材料层82，从而把第三互连介电材料层44分成独立的两层84和86。在一个实施例中，所述额外的介电材料层82可包括本公开的富碳的碳氮化硼介电膜。在上介电层74之上还淀积额外的扩散阻挡层96(它可由本公开的富碳的碳氮化硼介电膜构成)。电子器件80提供的额外益处在于：介电层82充当提供优良的互连深度控制的RIE蚀刻终止层。从而，选择层82的成分，以提供相对于层86的蚀刻选择性。
另一个备选实施例可包括把绝缘材料层作为配线结构中的层内或层间电介质的电子器件，所述配线结构包括：预处理的半导体衬底，所述半导体衬底具有嵌入第一绝缘材料层中的第一金属区域，嵌入第二绝缘材料层中的第一导体区域，其中，第二绝缘材料层与第一绝缘材料层密切接触，并且第一导体区域与第一金属区域电连通；与第一区域的导体电连通并且嵌入第三层绝缘材料中的第二导体区域，其中，第三层绝缘材料与第二层绝缘材料密切接触；第二绝缘材料层和第三绝缘材料层之间的第一介电盖层；以及第三绝缘材料层之上的第二介电盖层，其中，第一和第二介电盖层由富碳的碳氮化硼介电膜形成。
再一个备选实施例可包括把绝缘材料层作为配线结构中的层内或层间电介质的电子器件，所述配线结构包括：预处理的半导体衬底，所述半导体衬底具有嵌入第一绝缘材料层中的第一金属区域，嵌入第二绝缘材料层中的第一导体区域，第二绝缘材料层与第一绝缘材料层密切接触，第一导体区域与第一金属区域电连通；与第一导体区域电连通并且嵌入第三绝缘材料层中的第二导体区域，第三绝缘材料层与第二绝缘材料层密切接触；以及由淀积在第二绝缘材料层和第三绝缘材料层中的至少一个上的富碳的碳氮化硼介电膜形成的扩散阻挡层。
又一个备选实施例可包括把绝缘材料层作为配线结构中的层内或层间电介质的电子器件，所述配线结构包括：预处理的半导体衬底，所述半导体衬底具有嵌入第一绝缘材料层中的第一金属区域，嵌入第二绝缘材料中的第一导体区域，第二绝缘材料层与第一绝缘材料层密切接触，第一导体区域与第一金属区域电连通；与第一导体区域电连通并且嵌入第三绝缘材料层中的第二导体区域，第三绝缘材料层与第二绝缘材料层密切接触；在第二绝缘材料层之上的反应离子蚀刻(RIE)硬掩模/抛光终止层；以及在RIE硬掩模/抛光终止层之上的扩散阻挡层，其中，RIE硬掩模/抛光终止层和扩散阻挡层由本公开的富碳的碳氮化硼介电膜形成。
又一个备选实施例可包括把绝缘材料层作为配线结构中的层内或层间电介质的电子器件，所述配线结构包括：预处理的半导体衬底，所述半导体衬底具有嵌入第一绝缘材料层中的第一金属区域，嵌入第二绝缘材料层中的第一导体区域，第二绝缘材料层与第一绝缘材料层密切接触，第一导体区域与第一金属区域电连通；与第一导体区域电连通并且嵌入第三绝缘材料层中的第二导体区域，第三绝缘材料层与第二绝缘材料层密切接触；在第二绝缘材料层之上的第一RIE硬掩模/抛光终止层；在第一RIE硬掩模/抛光终止层之上的第一扩散阻挡层；在第三绝缘材料层之上的第二RIE硬掩模/抛光终止层；以及在第二RIE硬掩模/抛光终止层之上的第二扩散阻挡层，其中，RIE硬掩模/抛光终止层和扩散阻挡层由本公开的富碳的碳氮化硼介电膜形成。
现在参考图5，图5图解说明了包括富碳的碳氮化硼介电间隔物114的电子器件100。在本实施例中，可利用任何常规的FET工艺流程(包括置换栅极工艺)来制备电子器件100。在一些实施例中，可使用的FET工艺包括各个材料层的淀积、光刻和蚀刻。
关于间隔物应用的平面器件几何形状的以下讨论只是用于举例说明的目的，因而，本公开并不局限于平面器件体系结构。相反，富碳的碳氮化硼介电间隔物也可以用在诸如finFET、三栅、两栅和Si纳米线器件中。
电子器件100包括半导体衬底102，半导体衬底102包括上述半导体材料之一。位于栅极叠层106之下的半导体衬底102的一部分定义器件的沟道区104。栅极叠层106包括至少一种栅极介电材料108和位于其上的栅极导体110。在栅极叠层108的覆盖区并且位于半导体衬底102中，存在源极区112和漏极区113。源极区112和漏极区113经由沟道区104连接。
最好，一种栅极介电材料108可包括氧化物、氮化物、氮氧化物或者它们的多层叠层。在一个实施例中，所述至少一种栅极介电材料108包括半导体氧化物、半导体氮化物或者半导体氮氧化物。在另一个实施例中，所述至少一种栅极介电材料108包括具有比氧化硅的介电常数，例如3.9大的介电常数的介电金属氧化物或混合金属氧化物。一般，所述至少一种栅极介电材料108的电介质之一具有大于4.0的介电常数，更典型地，大于8.0的介电常数。这里把这种介电材料称为高k电介质。例证的高k电介质包括(但不限于)HfO2、ZrO2、La2O3、A12O3、TiO2、SrTiO3、LaA1O3、Y2O3、HfOxNy、ZrOxNy、La2OxNy、Al2OxNy、TiOxNy、SrTiOxNy、LaAlOxNy、Y2OxNy、SiON、SiNx、其硅酸盐及其合金。这些高k材料的多层叠层也可被用作所述至少一种栅极介电材料108。每个x值独立地选自0.5到3，每个y值独立地选自0到2。所述至少一种栅极介电材料108的厚度一般从1nm到10nm，典型地，所述厚度范围从2nm到5nm。
栅极导体110包括导电材料，比如(但不限于)多晶硅、多晶硅锗、单质金属(例如，钨、钛、钽、铝、镍、钌、钯和铂)、至少一种单质金属的合金、单质金属氮化物(例如，氮化钨、氮化铝和氮化钛)、单质金属硅化物(例如，硅化钨、硅化镍和硅化钛)以及它们的多层组合。在一个实施例中，可被用作栅极导体110的导电材料可由nFET金属栅极构成。在另一个实施例中，可被用作栅极导体110的导电材料可由pFET金属栅极构成。在又一个实施例中，可被用作栅极导体110的导电材料可由多晶硅构成。可以单独地或者与另一种导电材料（比如金属导电材料和/或金属硅化物材料）结合使用多晶硅导电材料。栅极导体110一般具有1nm到100nm的厚度，更典型的是厚度为3nm到30nm。
如图5中所示，富碳的碳氮化硼间隔物114位于栅极叠层106的侧壁。在本实施例中，通过首先在该结构上淀积如上所述的富碳的碳氮化硼膜，随后蚀刻该膜以便在栅极叠层106的侧壁上形成间隔物114，来形成富碳的碳氮化硼间隔物114。本公开的富碳的碳氮化硼间隔物114在栅极叠层106的侧壁上的存在减小了FET器件中的寄生电容。这里说明的关于富碳的碳氮化硼介电膜的多层循环PECVD工艺能够以低的微负载实现优异的逐步覆盖，并且富碳的碳氮化硼介电膜的疏水性产生了在间隔物应用中非常期望的良好抗湿蚀刻性。
现在参考图6A和6B，图6A和6B图解说明了包括位于碳基材料衬底层之上的富碳的碳氮化硼介电膜的例证电子器件。首先参考图6A，图中图解说明了可利用任何常规的FET工艺流程（包括置换栅极工艺）制备的一种电子器件150。在一些实施例中，可以使用的FET工艺包括各个材料层的淀积、光刻和蚀刻。
特别地，图6A图解说明了包括作为衬底152的碳基材料的电子器件150，其中，一部分碳基材料限定器件沟道154。至少一个界面介电材料层156位于器件沟道154的上表面上。界面介电材料156包括本公开的富碳的碳氮化硼介电膜。至少一个介电材料层158位于所述至少一个界面介电材料层156的最上面的表面上，以及至少一个导电材料层160位于所述至少一个介电材料层158的最上面的表面上。注意，在本公开的本具体实施例中提及的介电材料158和导电材料160由上面关于图5中的至少一种栅极介电材料108和栅极导体110提及的介电材料和导电材料之一构成。图6A中所示的电子器件150还包括与碳基材料152的与器件沟道154相邻的部分电接触的至少两个区域162、162'。所述两个区域162、162'是电子器件150的源极/漏极区，并且它们包括上面关于栅极导体110提及的导电材料之一。在一个实施例中，所述至少两个区域162、162'由石墨烯或碳基材料构成。所述至少两个区域162、162'是利用淀积、光刻和蚀刻形成的。在一个实施例中(未示出)，所述至少两个区域162、162'直接接触碳基材料152。这种器件是通过利用蚀刻除去所述至少一个界面介电材料层156的多个部分来实现的。在另一个实施例中，所述至少两个区域162、162'直接接触所述至少一个界面介电材料层156的一部分。在电子结构150中，界面介电材料156具有与下面的碳基材料152结合的高亲合力。
现在参见图6B，图中图解说明了包括作为衬底的碳基材料152的第二种电子器件150'，其中，碳基材料的一部分限定器件沟道154。在这种电子结构中，存在背栅层151，并且该背栅层可被图案化，或者可以作为覆盖层存在于整个器件阵列中。背栅层包含导电材料，包括掺杂的含Si材料、导电金属、导电金属合金、导电金属氮化物和/或导电金属硅化物。至少一个界面介电材料层156(它由本公开的富碳的碳氮化硼介电膜构成)位于器件沟道154的上表面上。至少一个介电材料层158位于所述至少一个界面介电材料层156的最上面的表面上，以及至少一个导电材料层160位于所述至少一个介电材料层158的最上面的表面上。注意，在本公开的本具体实施例内提及的介电材料158和导电材料160由上面关于图5中的至少一种栅极介电材料108和栅极导体110提及的介电材料和导电材料之一构成。图6B中所示的电子器件150'还包括与碳基材料152的与器件沟道154相邻的部分电接触的至少两个区域162、162'。所述两个区域162、162'是电子器件150'的源极/漏极区，它们包括上面关于栅极导体110提及的导电材料之一。在一个实施例中，所述至少两个区域162、162'由石墨烯或碳基材料构成。所述至少两个区域162、162'是借助淀积、光刻和蚀刻形成的。在一个实施例中(未示出)，所述至少两个区域162、162'与碳基材料152直接接触。这种器件是通过利用蚀刻除去所述至少一个界面介电材料层156的多个部分来实现的。在另一个实施例中，所述至少两个区域162、162'直接接触所述至少一个界面介电材料层156的一部分。在电子结构150'中，界面介电材料156具有用于与下面的碳基材料152结合的高亲合力。
尽管关于本公开的优先实施例，特别表示和说明了本公开，不过，本领域的技术人员会理解，可以作出形式和细节方面的上述和其它变化，而不脱离本公开的精神和范围。于是，本公开并不局限于说明和图示的严格形式和细节，而是在附加权利要求的范围内。
工业应用性
本发明可在采用并入集成电路中的富碳的碳氮化硼电介质的电子器件的设计和制备方面获得工业应用，所述集成电路可用在各种电子和电气设备中。

Claims (20)

1.一种具有式子CxByNz的介电膜，其中，x为35原子百分比或更大，y为6原子百分比到32原子百分比，以及z为8原子百分比到33原子百分比。
2.按照权利要求1所述的介电膜，进一步包括等于或小于3.6的介电常数。
3.按照权利要求2所述的介电膜，其中，所述介电常数的范围为2.5到3.2。
4.按照权利要求1所述的介电膜，其中，x为35原子百分比到70原子百分比，y为15原子百分比到32原子百分比，以及z为15原子百分比到33原子百分比。
5.按照权利要求1所述的介电膜，其中，所述氮均匀地分布在整个介电膜中。
6.按照权利要求1所述的介电膜，其中，在介电膜的深度内，在选择的区域中提供所述氮，从而提供分级膜。
7.一种电子器件(60)，包括：
衬底(32)；和
位于所述衬底的表面上的介电膜(14)，其中，所述介电膜具有式子CxByNz，其中，x为35原子百分比或更大，y为6原子百分比到32原子百分比，以及z为8原子百分比到33原子百分比。
8.按照权利要求7所述的电子器件，其中，所述衬底是具有位于其中的至少一种导电材料(24)的互连介电材料(22)，以及其中，所述介电膜(14)位于所述至少一种导电材料(20)的至少一个暴露表面上。
9.按照权利要求7所述的电子器件，其中，所述衬底(32)是图案化的栅极叠层(106)，以及所述介电膜位于所述图案化的栅极叠层的侧壁(114)上。
10.按照权利要求7所述的电子器件，其中，所述衬底(32)是碳基材料。
11.按照权利要求10所述的电子器件，其中，所述碳基材料选自包含石墨烯、石墨和碳纳米管的组。
12.按照权利要求10所述的电子器件，进一步包括位于所述介电膜之上的至少一个介电材料层和至少一个导电材料层。
13.按照权利要求7所述的电子器件，其中，所述介电膜具有等于或小于3.6的介电常数。
14.按照权利要求7所述的电子器件，其中，x为35原子百分比到70原子百分比，y为15原子百分比到32原子百分比，以及z为15原子百分比到33原子百分比。
15.按照权利要求7所述的半导体结构，其中，在所述介电膜的深度内，在选择的区域中提供所述氮，从而提供分级膜。
16.一种形成介电膜的方法，包括：
把衬底(32)置于反应室中；
向反应室供给至少包括C、B和N原子的至少一种前体；和
在所述衬底(32)的表面上淀积介电膜(14)，其中，所述介电膜具有式子CxByNz，其中，x为35原子百分比或更大，y为6原子百分比到32原子百分比，以及z为8原子百分比到33原子百分比。
17.按照权利要求16所述的方法，其中，所述至少一种前体至少包括含硼的气态前体、含氮的气态前体和含烃的气态前体。
18.按照权利要求16所述的方法，其中，所述至少一种前体包括组合的含硼和氮的液态前体和含烃的气态前体。
19.按照权利要求16所述的方法，其中，所述淀积包括等离子体增强的化学气相淀积、化学气相淀积、原子层淀积或旋涂工艺。
20.按照权利要求16所述的方法，其中进一步包括处理富碳的碳氮化硼介电膜，其中，所述处理选自包含热处理、化学处理、UV处理、电子束处理、微波处理、等离子体处理和它们的任意组合的组。
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US8476743B2 (en) 2013-07-02
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