CN103745955A - 显示装置、阵列基板及其制造方法 - Google Patents

显示装置、阵列基板及其制造方法 Download PDF

Info

Publication number
CN103745955A
CN103745955A CN201410004069.1A CN201410004069A CN103745955A CN 103745955 A CN103745955 A CN 103745955A CN 201410004069 A CN201410004069 A CN 201410004069A CN 103745955 A CN103745955 A CN 103745955A
Authority
CN
China
Prior art keywords
film
layer
gate insulation
insulation layer
grid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410004069.1A
Other languages
English (en)
Other versions
CN103745955B (zh
Inventor
袁广才
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201410004069.1A priority Critical patent/CN103745955B/zh
Publication of CN103745955A publication Critical patent/CN103745955A/zh
Priority to PCT/CN2014/076477 priority patent/WO2015100894A1/zh
Priority to US14/420,774 priority patent/US9685461B2/en
Application granted granted Critical
Publication of CN103745955B publication Critical patent/CN103745955B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H01L21/441—Deposition of conductive or insulating materials for electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
    • H01L21/47635—After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

Abstract

本发明公开了一种阵列基板的制造方法、阵列基板和显示装置，该阵列基板包括第一薄膜晶体管以及像素电极，其中，第一薄膜晶体管的有源层和源漏电极以及像素电极通过一次构图工艺形成。本发明仅需要通过三道光刻工艺即可制作出性能良好的阵列基板，大大缩短薄膜晶体管的制作周期，提高薄膜晶体管的特性，同时大大提高产品的良率。

Description

显示装置、阵列基板及其制造方法
技术领域
本发明涉及显示技术领域，尤其涉及一种显示装置、阵列基板及其制作方法。
背景技术
近年来，显示技术得到快速的发展，如薄膜晶体管技术由原来的a-Si（非晶硅）薄膜晶体管发展到现在的LTPS（低温多晶硅）薄膜晶体管、MILC（金属诱导横向晶化）薄膜晶体管、Oxide（氧化物）薄膜晶体管等。而发光技术也由原来的LCD（液晶显示器）、PDP（等离子显示屏）发展为现在的OLED（有机发光二极管）、AMOLED（主动式矩阵有机发光二极管）等。有机发光显示器是新一代的显示器件，与液晶显示器相比，具有很多优点，如：自发光，响应速度快，宽视角等等，可以用于柔性显示，透明显示，3D（三维立体）显示等。但无论液晶显示还是有机发光显示，都需要为每一个像素配备用于控制该像素的开关—薄膜晶体管，通过驱动电路，可以独立控制每一个像素，而不会对其他像素造成串扰等影响。
目前广泛应用的Oxide薄膜晶体管采用氧化物半导体作为有源层，具有迁移率大、开态电流高、开关特性更优、均匀性更好的特点，可以适用于需要快速响应和较大电流的应用，如高频、高分辨率、大尺寸的显示器以及有机发光显示器等。
现有技术中Oxide薄膜晶体管制作过程通常需要6次mask（曝光），分别用于形成栅线及栅极，栅极绝缘层、有源层，刻蚀阻挡层，源漏极，钝化层及过孔。研究表明，通过六次mask曝光工艺导致器件性能不稳定、制作周期较长，并且导致制作成本相应增加。
发明内容
（一）要解决的技术问题
本发明要解决的技术问题是：提供一种能够有效降低成本、简化工艺、提高Oxide薄膜晶体管的稳定性显示装置、阵列基板及其制作方法。
（二）技术方案
为解决上述问题，本发明公开了如下的技术方案：
本发明一方面提供一种阵列基板的制作方法，所述阵列基板包括第一薄膜晶体管以及像素电极，所述第一薄膜晶体管中的有源层和源漏电极以及像素电极通过一次构图工艺形成。
优选地，所述源漏电极和像素电极均由透明电极材料制成。
优选地，所述阵列基板还包括第二薄膜晶体管，所述第一薄膜晶体管和第二薄膜晶体管中的有源层和源漏电极以及像素电极通过一次构图工艺形成。
优选地，在形成所述第一薄膜晶体管、第二薄膜晶体管以及像素电极之前还包括：
在基板上沉积栅金属薄膜，通过一次构图工艺形成包括第一薄膜晶体管和第二薄膜晶体管的栅极、栅线的图案；
在完成前述步骤的基板上形成栅绝缘层，通过构图工艺形成过孔，所述栅绝缘层的过孔形成于第二薄膜晶体管栅极的上方。
优选地，所述栅绝缘层经过退火工艺处理。
优选地，所述栅绝缘层为一层，所述栅绝缘层采用氧化硅薄膜、氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜或氧化钕薄膜、氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；或者
所述栅绝缘层为两层，即包括第一栅绝缘层和第二栅绝缘层，所述第一栅绝缘层贴近栅极层，所述第二栅绝缘层贴近有源层，所述第一栅绝缘层图案采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；所述第二栅绝缘层采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜中的一种；或者
所述栅绝缘层为三层，包括第三栅绝缘层、第四栅绝缘层和第五栅绝缘层，所述第三栅绝缘层贴近栅极层，所述第五栅绝缘层贴近有源层，所述第四栅绝缘层位于第三栅绝缘层和第五栅绝缘层之间，所述第三栅绝缘层采用氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；所述第四栅绝缘层采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜和氮氧化钕薄膜中的一种；所述第五栅绝缘层图案采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜薄膜中的一种。
优选地，其特征在于，所述第一薄膜晶体管和第二薄膜晶体管中的有源层和源漏极以及像素电极通过一次构图工艺形成，具体包括：
沉积有源层薄膜、源漏金属层和像素电极层；
涂覆光刻胶；
采用双色调掩膜工艺进行曝光显影，其中，第一薄膜晶体管漏极与第二薄膜晶体管栅极的连接区域、数据线和电源线区域、第一薄膜晶体管和第二薄膜晶体管的源漏电极区域、以及像素电极区域为光刻胶完全保留区域；
第一薄膜晶体管的第一沟道区域和第二薄膜晶体管的第二沟道区域为光刻胶部分保留区域；
形成上述区域之外区域为光刻胶完全去除区域；
通过第一次刻蚀工艺，去除光刻胶完全去除区域对应的像素电极层、源漏金属层以及有源层薄膜，
通过灰化工艺除去所述部分保留区域对应的光刻胶，形成第一沟道区域和第二沟道区域；
通过第二次刻蚀工艺，去除光刻胶部分保留区域对应的像素电极层和源漏金属层；
剥离剩余光刻胶层，形成第一薄膜晶体管漏极与第二薄膜晶体管栅极的连接区域的图案、数据线和电源线区域的图案、第一薄膜晶体管和第二薄膜晶体管的源漏电极区域的图案以及像素电极的图案。
优选地，源漏金属层包括第一金属层和第二金属层。
优选地，有源层采用IGZO、ITZO、IZO、Cu2O、GZO、AZO、HfIZO、ZnoN材料中的一种或多种，或者采用非晶硅、多晶硅、微晶硅材料中的一种或多种。
优选地，有源层采用氧化物半导体材料时，对氧化物半导体进行不同气氛的等离子体处理。
优选地，有源层采用氧化物半导体材料时，在氮气、氧气或空气条件下，对氧化物半导体层进行退火处理，所述退火温度为200～500℃。
再一方面，本发明还提供一种利用上述制造方法制备的阵列基板，包括：
基板，
所述基板上设有栅极层、栅绝缘层、有源层、源漏电极层和像素电极层，所述源漏电极层和像素电极层直接接触连接。
优选地，所述栅极层包括第一薄膜晶体管的第一栅极和第二薄膜晶体管的第二栅极；
所述有源层包括第一薄膜晶体管的第一有源层和第二薄膜晶体管的第二有源层；所述源漏电极层包括第一薄膜晶体管的第一源极、第一漏极以及第二薄膜晶体管的第二源极、第二漏极。
优选地，所述栅绝缘层上设有过孔，所述第一薄膜晶体管的第一漏极通过过孔与第二薄膜晶体管的第二栅极连接。
优选地，所述源漏电极层包括第一金属层和第二金属层。
优选地，所述栅极层和源漏电极层采用铜、铜合金、MO、MO-Al-MO合金、MO/Al-Nd/Mo叠成结构、AL、AL合金、MO/Nd/Cu/Ti/Cu合金中的一种或多种。
优选地，所述栅绝缘层为一层，所述栅绝缘层采用氧化硅薄膜、氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜或氧化钕薄膜、氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；或者
所述栅绝缘层为两层，即包括第一栅绝缘层和第二栅绝缘层，所述第一栅绝缘层贴近栅极层，所述第二栅绝缘层贴近有源层，所述第一栅绝缘层图案采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；所述第二栅绝缘层采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜中的一种；或者
所述栅绝缘层为三层，包括第三栅绝缘层、第四栅绝缘层和第五栅绝缘层，所述第三栅绝缘层贴近栅极层，所述第五栅绝缘层贴近有源层，所述第四栅绝缘层位于第三栅绝缘层和第五栅绝缘层之间，所述第三栅绝缘层采用氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；所述第四栅绝缘层采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜和氮氧化钕薄膜中的一种；所述第五栅绝缘层图案采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜薄膜中的一种。
再一方面，本发明还提供一种显示装置，包括上述的阵列基板。
（三）有益效果
本发明提供一种显示装置、阵列基板及其制作方法，通过对阵列基板制作工艺流程的调整，可大大缩短薄膜晶体管的制作周期，同时由于经历比较少的工艺步骤，可以很好的提高薄膜晶体管的特性，使得薄膜晶体管的阈值电压不会发生较大的漂移，同时可提高产品的良率，而且使器件的稳定和可靠性更加适合于长时间的使用。
附图说明
图1为本发明实施例阵列基板制作方法流程图；
图2～图9为本发明实施例阵列基板制作方法各步骤结构示意图；
图10为本发明实施例阵列基板的平面示意图；
图11为本发明实施例阵列基板A1-A1剖视图。
具体实施方式
下面结合附图及实施例对本发明进行详细说明如下。
本发明实施例提供一种阵列基板的制作方法，该阵列基板包括第一薄膜晶体管以及像素电极，第一薄膜晶体管的有源层和源漏电极以及像素电极通过一次构图工艺形成。其中，该源漏电极和像素电极均由透明电极材料制成，例如采用ITO材料制成。
将有源层、源漏电极和像素电极采用一次构图工艺完成，可大大缩短薄膜晶体管的制作周期，同时由于经历比较少的工艺步骤，可以很好的提高薄膜晶体管的特性，使得薄膜晶体管的阈值电压不会发生较大的漂移，同时可提高产品的良率，而且使器件的稳定和可靠性更加适合于长时间的使用。
通过该制作方法制作出的阵列基板适用于普通的LCD显示器件。
另外，本发明还提供一种适用于顶发射的OLED结构的阵列基板的制作方法。
实施例一
本发明提供一种阵列基板的制作方法，所述阵列基板包括第一薄膜晶体管、第二薄膜晶体管以及像素电极，其中，第一薄膜晶体管和第二薄膜晶体管中的有源层和源漏电极以及像素电极通过一次构图工艺形成。
具体的，本发明实施例提供一种底栅极的阵列基板制作方法，本发明所称的构图工艺包括光刻胶涂覆、掩模、曝光、刻蚀和光刻胶剥离等工艺，光刻胶以正性光刻胶为例。
如图1所述，该步骤具体包括：
步骤1、在基板321上沉积栅金属薄膜，通过一次构图工艺形成包括栅线11、第一薄膜晶体管中的第一栅极3221和第二薄膜晶体管中的第二栅极3222；参考图2。
步骤2、在完成步骤101的基板上形成栅绝缘层323，通过构图工艺形成过孔323a。其中，该栅绝缘层的过孔形成于第二薄膜晶体管栅极的上方，参考图3。
步骤3、在完成步骤102的基板上，通过一次构图工艺形成第一薄膜晶体管和第二薄膜晶体管中的有源层和源漏极以及像素电极。
该步骤具体包括：
步骤301、沉积有源层薄膜324、源漏金属层和像素电极层327；
源漏金属层可以为单层结构，本实施例中以双层结构为例。该源漏金属层包括第一金属层325和第二金属层326，该第一金属层形成源漏电极层，第二金属层形成金属保护层，保护源漏电极层不被外界环境破坏，参见图4。
步骤302、涂覆一层光刻胶328，参考图5。
步骤303、采用双色调掩膜工艺进行曝光显影，第一薄膜晶体管漏极与第二薄膜晶体管栅极的连接区域、数据线12和电源线14区域、第一薄膜晶体管和第二薄膜晶体管的源漏电极区域、以及像素电极区域为光刻胶完全保留区域；第一薄膜晶体管的第一沟道区域和第二薄膜晶体管的第二沟道区域为光刻胶部分保留区域，形成上述区域之外区域为光刻胶完全去除区域。参考图6。
步骤304、通过第一次刻蚀工艺，去除光刻胶完全去除区域对应的像素电极层、源漏金属层以及有源层薄膜，即刻蚀至栅绝缘层323。参考图7。
步骤305、通过灰化工艺去除所述部分保留区域对应的光刻胶，露出沟道区域，参考图8。
步骤306、通过第二次刻蚀工艺，去除光刻胶部分保留区域对应的像素电极层和源漏金属层，形成第一薄膜晶体管中的第一沟道图形以及第二薄膜晶体管的第二沟通图形，参考图9。
步骤307、剥离剩余光刻胶层，形成第一薄膜晶体管漏极与第二薄膜晶体管栅极的连接区域的图案、数据线和电源线区域的图案、第一薄膜晶体管和第二薄膜晶体管的源漏电极区域的图案以及像素电极的图案，参见图10以及图11。
其中，上述步骤中涉及到的刻蚀工艺可以为湿法刻蚀、干法刻蚀或干法湿法结合刻蚀。
其中，有源层采用IGZO、ITZO、IZO、Cu2O、GZO、AZO、HfIZO、ZnoN材料中的一种或多种，或者采用非晶硅、多晶硅、微晶硅材料中的一种或多种。
有源层采用氧化物半导体材料时，对氧化物半导体进行不同气氛的等离子体处理。该气氛例如可以为氧气、氩气、一氧化氮、氢气、或可以对氧化物半导体进行表面改性的气体。具体的，例如采用氢等离子体在空气中对半导体材料进行腐蚀处理。
或者，在氮气、氧气或空气条件下，对氧化物半导体层进行退火处理，所述退火温度为200～500℃。
实施例二
基于实施例一中所采用的阵列基板制作方法，本发明实施例提供一种阵列基板，图10为本发明阵列基板实施例的平面图，所反映的是一个像素单元的结构，图11为图10中A1-A1向的剖面图。如图4和图5所示，本实施例以OLED（Organic Light Emitting Diode，有机发光二极管）阵列基板的主体结构包括栅线11、数据线12、电源线14，数据线12和电源线14与栅线11垂直，并与二个相邻的栅线11一起限定了像素区域，像素区域内分别形成有作为寻址元件的第一薄膜晶体管（也称开关薄膜晶体管）、用于控制有机发光二极管的第二薄膜晶体管（也称驱动薄膜晶体管）和像素电极，第一薄膜晶体管位于栅线11与数据线12交叉点的位置，第二薄膜晶体管位于栅线11与电源线14交叉点的位置，其中第一薄膜晶体管的第一漏极3261做到第二薄膜晶体管栅极所在位置，直接作为第二栅极3222。
具体的，该阵列基板包括基板321，所述基板321上设有栅极层322、栅绝缘层323、有源层324、源漏电极层和像素电极层327，所述源漏电极层和像素电极层直接接触连接。其中，该源漏金属层包括第一金属层325和第二金属层326，该第一金属层形成普通的源漏电极层，第二金属层形成金属保护层，保护源漏电极层不被外界环境破坏。
其中，栅极层包括第一薄膜晶体管的第一栅极3221和第二薄膜晶体管的第二栅极3222；第一栅极3221和第二栅极3222以及栅线11通过一次构图工艺完成。其中第一栅极3221与栅线11连接，第二栅极3222不与栅线11相连，同时第一栅极3221与第二栅极3222不相连；栅绝缘层323形成在第一栅极3221、第二栅极3222、栅线11上。
其中，栅绝缘层323上设有过孔323a，过孔323a位于第二栅极3222的上方。所述第一薄膜晶体管的第一漏极3261通过过孔323a与第二薄膜晶体管的第二栅极3222连接。
有源层324包括第一薄膜晶体管的第一有源层和第二薄膜晶体管的第二有源层；
所述源漏电极层包括第一薄膜晶体管的第一源极3251、第一漏极3261以及第二薄膜晶体管的第二源极3252、第二漏极3262。
其中，本实施例中的栅极层322和源漏电极层采用铜、铜合金、MO、MO-Al-MO合金、MO/Al-Nd/Mo叠成结构、AL、AL合金、MO/Nd/Cu/Ti/Cu合金中的一种或多种。
需要说明的是，薄膜晶体管源极和漏极的名称，因电流的流动方向不同而异，在本发明中为了方便描述，称与像素电极相连接的为漏极。所述沟道区域为源电极和漏电极相对应的空隙区域。
其中，栅绝缘层323可以为一层，即第一栅绝缘层，所述栅绝缘层采用氧化硅薄膜、氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜或氧化钕薄膜、氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种。为了保证更好的器件特性，在本实施例中，可以对第一栅极绝缘层进行退火工艺（即第一栅极绝缘层为经过退火工艺处理的绝缘层），来降低栅极绝缘层中氢元素及氢的复合物对氧化物半导体特性的影响。
具体退火工艺方法包括：在PECVD设备中加入氮气或空气的加热腔室，对第一栅极绝缘层进行脱氢工艺；其中，退火腔室温度为200℃～350℃，退火时间为15min～90min。
其中，该栅绝缘层323可以为两层，即包括第一栅绝缘层和第二栅绝缘层，所述第一栅绝缘层贴近栅极，所述第二栅绝缘层贴近有源层。
其中，第一栅绝缘层采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；所述第二栅绝缘层图案采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜中的一种。第一栅绝缘层和/或第二栅绝缘层为经过退火工艺处理的绝缘层。第一栅极绝缘的材料可以很好地遏制栅电极（尤其当采用铜或铜合金时）产生的不良。第二栅极绝缘层的作用是可以很好的实现与氧化物半导体的匹配，达到提高器件性能的作用。由于第二栅极绝缘层的材料多为氧化物绝缘层，其对H+，OH-等基团的防扩散的能力比较差，所以在制作完第一栅极绝缘层时，优选地需要对其进行退火工艺处理，其作用是为了降低第一栅极绝缘层中可能发生断裂扩散的H+，OH-等基团，进而达到了提升器件稳定性的作用。
具体退火工艺方法包括：在PECVD设备中加入氮气或空气的加热腔室，对第一栅极绝缘层和/或第二栅极绝缘层进行脱氢工艺；其中，退火腔室温度为200℃～350℃，退火时间为15min～90min。其中，该栅绝缘层323为三层，即包括第三栅绝缘层、第四栅绝缘层和第五栅绝缘层，所述第三栅绝缘层贴近栅极，所述第五栅绝缘层贴近有源层，第四栅绝缘层位于第三栅绝缘层和第五栅绝缘层之间。所述第三栅绝缘层图案采用氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；第四栅绝缘层图案采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜和氮氧化钕薄膜中的一种；第五栅绝缘层图案采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜薄膜中的一种。
本实施例中，第三栅极绝缘层采用氮化硅或氮氧化硅薄膜等无机绝缘材料，由于该材料直接与氧化物半导体层接触时会造成氧化物半导体曾的性能下降，但它却可以较好地遏制与栅极金属（尤其是当采用铜及其合金作为栅极时）接触产生不良现象，因此设置该第一栅极绝缘层紧贴栅极，并远离有源层。将第四栅极绝缘层设置在中间层，由于由氮氧化硅薄膜等无机绝缘材料制成的第四栅极绝缘层自身含有的H+，OH-等基团比较少，同时对H+，OH-等基团具有一定的防渗透能力，可以很好的遏制H+，OH-等基团向氧化物半导体层进行扩散，达到了提高器件稳定性的目的。同时，为了最大程度的提高器件的特性，将第五栅极绝缘层与氧化物半导体紧贴，可以较好地实现与氧化物半导体的匹配，达到提高器件稳定性的作用。
本发明实施例还进一步提供一种显示器件，其包括上述阵列基板。所述显示器件可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。

Claims (18)

1.一种阵列基板的制作方法，所述阵列基板包括第一薄膜晶体管以及像素电极，其特征在于，所述第一薄膜晶体管中的有源层和源漏电极以及像素电极通过一次构图工艺形成。
2.如权利要求1所述的阵列基板的制作方法，其特征在于，所述源漏电极和像素电极均由透明电极材料制成。
3.如权利要求1所述的阵列基板的制作方法，其特征在于，所述阵列基板还包括第二薄膜晶体管，所述第一薄膜晶体管和第二薄膜晶体管中的有源层和源漏电极以及像素电极通过一次构图工艺形成。
4.如权利要求3所述的阵列基板的制作方法，其特征在于，在形成所述第一薄膜晶体管、第二薄膜晶体管以及像素电极之前还包括：
在基板上沉积栅金属薄膜，通过一次构图工艺形成包括第一薄膜晶体管和第二薄膜晶体管的栅极、栅线的图案；
在完成前述步骤的基板上形成栅绝缘层，通过构图工艺形成过孔，所述栅绝缘层的过孔形成于第二薄膜晶体管栅极的上方。
5.如权利要求3所述的阵列基板的制作方法，其特征在于，所述栅绝缘层经过退火工艺处理。
6.如权利要求5所述的阵列基板的制作方法，其特征在于，所述栅绝缘层为一层，所述栅绝缘层采用氧化硅薄膜、氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜或氧化钕薄膜、氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；或者
所述栅绝缘层为两层，即包括第一栅绝缘层和第二栅绝缘层，所述第一栅绝缘层贴近栅极层，所述第二栅绝缘层贴近有源层，所述第一栅绝缘层图案采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；所述第二栅绝缘层采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜中的一种；或者
所述栅绝缘层为三层，包括第三栅绝缘层、第四栅绝缘层和第五栅绝缘层，所述第三栅绝缘层贴近栅极层，所述第五栅绝缘层贴近有源层，所述第四栅绝缘层位于第三栅绝缘层和第五栅绝缘层之间，所述第三栅绝缘层采用氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；所述第四栅绝缘层采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜和氮氧化钕薄膜中的一种；所述第五栅绝缘层图案采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜薄膜中的一种。
7.如权利要求3-6任一权利要求所述的阵列基板的制作方法，其特征在于，所述第一薄膜晶体管和第二薄膜晶体管中的有源层和源漏极以及像素电极通过一次构图工艺形成，具体包括：
沉积有源层薄膜、源漏金属层和像素电极层；
涂覆光刻胶；
采用双色调掩膜工艺进行曝光显影，其中，第一薄膜晶体管漏极与第二薄膜晶体管栅极的连接区域、数据线和电源线区域、第一薄膜晶体管和第二薄膜晶体管的源漏电极区域、以及像素电极区域为光刻胶完全保留区域；
第一薄膜晶体管的第一沟道区域和第二薄膜晶体管的第二沟道区域为光刻胶部分保留区域；
形成上述区域之外区域为光刻胶完全去除区域；
通过第一次刻蚀工艺，去除光刻胶完全去除区域对应的像素电极层、源漏金属层以及有源层薄膜，
通过灰化工艺除去所述部分保留区域对应的光刻胶，形成第一沟道区域和第二沟道区域；
通过第二次刻蚀工艺，去除光刻胶部分保留区域对应的像素电极层和源漏金属层；
剥离剩余光刻胶层，形成第一薄膜晶体管漏极与第二薄膜晶体管栅极的连接区域的图案、数据线和电源线区域的图案、第一薄膜晶体管和第二薄膜晶体管的源漏电极区域的图案以及像素电极的图案。
8.如权利要求1-6任一权利要求所述的阵列基板的制造方法，其特征在于，源漏金属层包括第一金属层和第二金属层。
9.如权利要求1-6任一权利要求所述的阵列基板的制造方法，其特征在于，有源层采用IGZO、ITZO、IZO、Cu2O、GZO、AZO、HfIZO、ZnoN材料中的一种或多种，或者采用非晶硅、多晶硅、微晶硅材料中的一种或多种。
10.如权利要求1-6任一权利要求所述的阵列基板的制造方法，其特征在于，有源层采用氧化物半导体材料时，对氧化物半导体进行不同气氛的等离子体处理。
11.如权利要求1-6任一权利要求所述的阵列基板的制造方法，其特征在于，有源层采用氧化物半导体材料时，在氮气、氧气或空气条件下，对氧化物半导体层进行退火处理，所述退火温度为200～500℃。
12.一种利用权1-11任一权利要求所述的制造方法制备的阵列基板，其特征在于，包括：
基板，
所述基板上设有栅极层、栅绝缘层、有源层、源漏电极层和像素电极层，所述源漏电极层和像素电极层直接接触连接。
13.如权利要求12所述的阵列基板，其特征在于，
所述栅极层包括第一薄膜晶体管的第一栅极和第二薄膜晶体管的第二栅极；
所述有源层包括第一薄膜晶体管的第一有源层和第二薄膜晶体管的第二有源层；所述源漏电极层包括第一薄膜晶体管的第一源极、第一漏极以及第二薄膜晶体管的第二源极、第二漏极。
14.如权利要求13所述的阵列基板，其特征在于，所述栅绝缘层上设有过孔，所述第一薄膜晶体管的第一漏极通过过孔与第二薄膜晶体管的第二栅极连接。
15.如权利要求12所述的阵列基板，其特征在于，所述源漏电极层包括第一金属层和第二金属层。
16.如权利要求12所述的阵列基板，其特征在于，所述栅极层和源漏电极层采用铜、铜合金、MO、MO-Al-MO合金、MO/Al-Nd/Mo叠成结构、AL、AL合金、MO/Nd/Cu/Ti/Cu合金中的一种或多种。
17.如权利要求12-16任一权利要求所述的阵列基板，其特征在于，所述栅绝缘层为一层，所述栅绝缘层采用氧化硅薄膜、氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜或氧化钕薄膜、氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；或者
所述栅绝缘层为两层，即包括第一栅绝缘层和第二栅绝缘层，所述第一栅绝缘层贴近栅极层，所述第二栅绝缘层贴近有源层，所述第一栅绝缘层图案采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；所述第二栅绝缘层采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜中的一种；或者
所述栅绝缘层为三层，包括第三栅绝缘层、第四栅绝缘层和第五栅绝缘层，所述第三栅绝缘层贴近栅极层，所述第五栅绝缘层贴近有源层，所述第四栅绝缘层位于第三栅绝缘层和第五栅绝缘层之间，所述第三栅绝缘层采用氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；所述第四栅绝缘层采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜和氮氧化钕薄膜中的一种；所述第五栅绝缘层图案采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜薄膜中的一种。
18.一种显示装置，其特征在于，包括如权利要求12-17任一权利要求所述的阵列基板。
CN201410004069.1A 2014-01-03 2014-01-03 显示装置、阵列基板及其制造方法 Active CN103745955B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201410004069.1A CN103745955B (zh) 2014-01-03 2014-01-03 显示装置、阵列基板及其制造方法
PCT/CN2014/076477 WO2015100894A1 (zh) 2014-01-03 2014-04-29 显示装置、阵列基板及其制造方法
US14/420,774 US9685461B2 (en) 2014-01-03 2014-04-29 Display device, array substrate and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410004069.1A CN103745955B (zh) 2014-01-03 2014-01-03 显示装置、阵列基板及其制造方法

Publications (2)

Publication Number Publication Date
CN103745955A true CN103745955A (zh) 2014-04-23
CN103745955B CN103745955B (zh) 2017-01-25

Family

ID=50502965

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410004069.1A Active CN103745955B (zh) 2014-01-03 2014-01-03 显示装置、阵列基板及其制造方法

Country Status (3)

Country Link
US (1) US9685461B2 (zh)
CN (1) CN103745955B (zh)
WO (1) WO2015100894A1 (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015100894A1 (zh) * 2014-01-03 2015-07-09 京东方科技集团股份有限公司 显示装置、阵列基板及其制造方法
CN105702585A (zh) * 2016-03-31 2016-06-22 京东方科技集团股份有限公司 一种薄膜晶体管和显示基板及其制作方法、显示器件
WO2016180016A1 (en) * 2015-05-12 2016-11-17 Boe Technology Group Co., Ltd. Thin film transistor, array substrate and display device having the same, and method of manufacturing thereof
CN106876405A (zh) * 2015-12-11 2017-06-20 三星显示有限公司 液晶显示器及其制造方法
WO2018103599A1 (zh) * 2016-12-08 2018-06-14 惠科股份有限公司 主动开关阵列基板及其制备方法
CN108962827A (zh) * 2018-07-13 2018-12-07 京东方科技集团股份有限公司 阵列基板中双层金属层的制造方法以及阵列基板
CN109449086A (zh) * 2018-11-08 2019-03-08 中山大学 薄膜晶体管及其制备方法、显示器设备

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105140131A (zh) * 2015-07-15 2015-12-09 京东方科技集团股份有限公司 氧化物薄膜晶体管的制备方法
CN105185840A (zh) * 2015-10-28 2015-12-23 深圳市华星光电技术有限公司 一种薄膜晶体管、阵列基板及其制成方法
KR102660829B1 (ko) * 2016-10-20 2024-04-25 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
JP2018170324A (ja) 2017-03-29 2018-11-01 株式会社ジャパンディスプレイ 表示装置
CN108922966A (zh) * 2018-06-19 2018-11-30 信利半导体有限公司 一种有机薄膜晶体管及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101656232A (zh) * 2008-08-19 2010-02-24 北京京东方光电科技有限公司 薄膜晶体管阵列基板制造方法
US20120320299A1 (en) * 2006-06-30 2012-12-20 Kim Young-Joo Liquid crystal display device and method for fabricating the same
CN103123910A (zh) * 2012-10-31 2013-05-29 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI220029B (en) * 2000-10-12 2004-08-01 Au Optronics Corp Thin film transistor liquid crystal display and its manufacturing method
CN100405560C (zh) 2004-07-28 2008-07-23 中华映管股份有限公司 薄膜晶体管制造方法
KR100726090B1 (ko) 2004-12-30 2007-06-08 엘지.필립스 엘시디 주식회사 박막 트랜지스터 어레이 기판 및 그 제조 방법
KR101191402B1 (ko) * 2005-07-25 2012-10-16 삼성디스플레이 주식회사 포토레지스트 스트리퍼 조성물, 이를 이용하는 배선 형성방법 및 박막 트랜지스터 기판의 제조 방법
KR101245210B1 (ko) 2006-02-08 2013-03-19 엘지디스플레이 주식회사 액정 표시장치 및 그 제조 방법
KR101235106B1 (ko) * 2006-06-30 2013-02-20 엘지디스플레이 주식회사 액정표시장치용 어레이 기판과 그 제조방법
TWI559501B (zh) * 2009-08-07 2016-11-21 半導體能源研究所股份有限公司 半導體裝置和其製造方法
SG10201408329SA (en) * 2009-12-25 2015-02-27 Semiconductor Energy Lab Memory device, semiconductor device, and electronic device
CN102148195B (zh) * 2010-04-26 2013-05-01 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
KR101682078B1 (ko) * 2010-07-30 2016-12-05 삼성디스플레이 주식회사 박막 트랜지스터 표시판의 제조 방법
CN102651343B (zh) * 2012-03-16 2014-12-24 京东方科技集团股份有限公司 一种阵列基板的制作方法、阵列基板及显示装置
CN203085533U (zh) 2012-10-26 2013-07-24 京东方科技集团股份有限公司 阵列基板和显示装置
CN103745955B (zh) 2014-01-03 2017-01-25 京东方科技集团股份有限公司 显示装置、阵列基板及其制造方法
CN103745954B (zh) 2014-01-03 2017-01-25 京东方科技集团股份有限公司 显示装置、阵列基板及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120320299A1 (en) * 2006-06-30 2012-12-20 Kim Young-Joo Liquid crystal display device and method for fabricating the same
CN101656232A (zh) * 2008-08-19 2010-02-24 北京京东方光电科技有限公司 薄膜晶体管阵列基板制造方法
CN103123910A (zh) * 2012-10-31 2013-05-29 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015100894A1 (zh) * 2014-01-03 2015-07-09 京东方科技集团股份有限公司 显示装置、阵列基板及其制造方法
US9685461B2 (en) 2014-01-03 2017-06-20 Boe Technology Group Co., Ltd. Display device, array substrate and method for manufacturing the same
US10008612B2 (en) 2015-05-12 2018-06-26 Boe Technology Group Co., Ltd. Thin film transistor, array substrate and display device having the same, and method of manufacturing thereof
EP3295475A4 (en) * 2015-05-12 2018-12-19 BOE Technology Group Co., Ltd. Thin film transistor, array substrate and display device having the same, and method of manufacturing thereof
WO2016180016A1 (en) * 2015-05-12 2016-11-17 Boe Technology Group Co., Ltd. Thin film transistor, array substrate and display device having the same, and method of manufacturing thereof
US9806199B2 (en) 2015-05-12 2017-10-31 Boe Technology Group Co., Ltd. Thin film transistor, array substrate and display device having the same, and method of manufacturing thereof
CN106876405A (zh) * 2015-12-11 2017-06-20 三星显示有限公司 液晶显示器及其制造方法
CN106876405B (zh) * 2015-12-11 2022-03-04 三星显示有限公司 液晶显示器及其制造方法
CN105702585A (zh) * 2016-03-31 2016-06-22 京东方科技集团股份有限公司 一种薄膜晶体管和显示基板及其制作方法、显示器件
CN105702585B (zh) * 2016-03-31 2019-08-27 京东方科技集团股份有限公司 一种薄膜晶体管和显示基板及其制作方法、显示器件
WO2018103599A1 (zh) * 2016-12-08 2018-06-14 惠科股份有限公司 主动开关阵列基板及其制备方法
US10770488B2 (en) 2016-12-08 2020-09-08 HKC Corporation Limited Active switch array substrate and method for manufacturing the same
CN108962827A (zh) * 2018-07-13 2018-12-07 京东方科技集团股份有限公司 阵列基板中双层金属层的制造方法以及阵列基板
CN108962827B (zh) * 2018-07-13 2020-12-08 京东方科技集团股份有限公司 阵列基板中双层金属层的制造方法以及阵列基板
CN109449086A (zh) * 2018-11-08 2019-03-08 中山大学 薄膜晶体管及其制备方法、显示器设备

Also Published As

Publication number Publication date
CN103745955B (zh) 2017-01-25
WO2015100894A1 (zh) 2015-07-09
US20150372021A1 (en) 2015-12-24
US9685461B2 (en) 2017-06-20

Similar Documents

Publication Publication Date Title
CN103745978A (zh) 显示装置、阵列基板及其制造方法
CN103745955A (zh) 显示装置、阵列基板及其制造方法
CN107819005B (zh) 包含多种类型薄膜晶体管的有机发光显示装置及其制造方法
US9589995B2 (en) TFT substrate having three parallel capacitors
CN105514116B (zh) Tft背板结构及其制作方法
CN104282769B (zh) 薄膜晶体管的制备方法、阵列基板的制备方法
US8829511B2 (en) Hybrid thin film transistor, manufacturing method thereof and display panel having the same
TW201714296A (zh) 陣列基板、顯示裝置及陣列基板的製備方法
US20100182223A1 (en) Organic light emitting display device
CN103489894A (zh) 有源矩阵有机电致发光显示器件、显示装置及其制作方法
CN106057735A (zh) Tft背板的制作方法及tft背板
CN108172595A (zh) 薄膜晶体管基底
CN103745954A (zh) 显示装置、阵列基板及其制造方法
US9443875B2 (en) Manufacturing method for an array substrate that can avoid electrical leakage of thin film transistors
CN104091810A (zh) 阵列基板及其制作方法、显示装置
CN103022149A (zh) 薄膜晶体管、阵列基板及制造方法和显示器件
CN106098699A (zh) 一种阵列基板、其制作方法、显示面板及其制作方法
CN105470196A (zh) 薄膜晶体管、阵列基板及其制造方法、和显示装置
CN102709283B (zh) 低温多晶硅薄膜晶体管阵列基板及其制作方法
CN101924122B (zh) 一种有源矩阵有机发光显示器及其制造方法
CN104022079A (zh) 薄膜晶体管基板的制造方法
CN105552035B (zh) 低温多晶硅tft阵列基板的制作方法及其结构
CN104157610A (zh) 氧化物半导体tft基板的制作方法及其结构
CN203521417U (zh) 有源矩阵有机电致发光显示器件及显示装置
CN106920814A (zh) Oled像素版图以及oled器件的制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant