WO2018103599A1 - 主动开关阵列基板及其制备方法 - Google Patents

主动开关阵列基板及其制备方法 Download PDF

Info

Publication number
WO2018103599A1
WO2018103599A1 PCT/CN2017/114369 CN2017114369W WO2018103599A1 WO 2018103599 A1 WO2018103599 A1 WO 2018103599A1 CN 2017114369 W CN2017114369 W CN 2017114369W WO 2018103599 A1 WO2018103599 A1 WO 2018103599A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
metal
molybdenum
metal composite
patterned
Prior art date
Application number
PCT/CN2017/114369
Other languages
English (en)
French (fr)
Inventor
卓恩宗
Original Assignee
惠科股份有限公司
重庆惠科金渝光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 惠科股份有限公司, 重庆惠科金渝光电科技有限公司 filed Critical 惠科股份有限公司
Priority to US16/317,045 priority Critical patent/US10770488B2/en
Publication of WO2018103599A1 publication Critical patent/WO2018103599A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate

Definitions

  • the present application relates to the field of display technologies, and in particular, to an active switch array substrate, and a method for fabricating the active switch array substrate.
  • An existing active switch array substrate includes a source, a drain, and a channel between the source and the drain.
  • a passivation layer is formed on the channel, and ITO is deposited on the passivation layer (Indium) Tin Oxide, indium tin oxide film.
  • the sputtering process may cause damage to the passivation layer, resulting in the damaged passivation layer not effectively protecting the channel, causing the sputtering process to damage the channel, resulting in poor quality of the thin film transistor. .
  • the photolithography process also easily damages the passivation layer, causing the photolithography process to cause damage to the channel, thereby making the thin film transistor Poor quality.
  • the present application provides a method for fabricating an active switch array substrate, which can solve the problem of poor quality of the active switch array substrate prepared in the exemplary technology to some extent.
  • a method for preparing an active switch array substrate according to the present application includes the following steps:
  • a channel, a source and a drain are formed on the second metal layer, and the source and the drain are respectively located on both sides of the channel.
  • forming the channel comprises the steps of:
  • the binary mask being a mask having two transmittances
  • the first portion of the photoresist film is irradiated; the first portion of the photoresist film is removed, and the second portion of the photoresist film is not removed;
  • the light-transmissive conductive layer, the passivation layer, and the patterned second metal layer not covered by the second portion of the photoresist film are removed to form the channel.
  • the channel has a width of 2 to 5 microns.
  • plating the first metal layer on the substrate comprises: plating a first composite metal layer on the surface of the substrate, the first metal composite layer being a molybdenum-aluminum metal composite layer, and a molybdenum-aluminum alloy composite a layer, a titanium-aluminum metal composite layer, or a copper-molybdenum metal composite layer.
  • plating the amorphous metal layer to form the second metal layer comprises: plating a second metal composite layer on the surface of the amorphous silicon layer, the second metal composite layer being molybdenum-aluminum-molybdenum a metal composite layer, a titanium-aluminum-titanium metal composite layer, or a copper-molybdenum metal composite layer.
  • the light-transmissive conductive layer is a translucent or transparent conductive metal layer.
  • the present application further provides an active switch array substrate, where the active switch array substrate includes:
  • the gate being disposed on the substrate
  • An amorphous silicon layer being disposed on a surface of the substrate and the gate;
  • Patterning a second metal layer the patterned second metal layer being disposed on a surface of the amorphous silicon layer;
  • a passivation layer formed on the surface of the patterned second metal layer and the amorphous silicon layer, wherein the passivation layer is provided with a through hole;
  • a pixel electrode formed on the passivation layer, the pixel electrode contacting the patterned second metal layer through the via hole, the patterned second metal layer, the passivation layer And the pixel electrode is jointly formed by a photolithography process to form a channel, the channel separating the patterned second metal layer into a source and a drain.
  • the channel has a width of 2 to 5 microns.
  • the gate is a first metal composite layer
  • the first metal composite layer is a molybdenum-aluminum metal composite layer, a molybdenum-aluminum alloy composite layer, a titanium-aluminum metal composite layer, or a copper-molybdenum metal. Composite layer.
  • the second metal layer is a second metal composite layer
  • the second metal composite layer is a molybdenum-aluminum-molybdenum metal composite layer, a titanium-aluminum-titanium metal composite layer, or a copper-molybdenum metal. Composite layer.
  • the pixel electrode is indium tin oxide.
  • the passivation layer is made of SiNx, having a thickness of 100 to 250 microns, and x is 1 or 4/3.
  • the amorphous silicon layer includes a SiNx layer, an ⁇ -Si layer, and an N+ layer sequentially formed on the substrate and the gate. ⁇ -Si layer.
  • a data line interleaved with the gate is formed on the substrate.
  • the present application further provides another active switch array substrate, where the active switch array substrate includes:
  • the gate is disposed on the substrate, the gate is a first metal composite layer, and the first metal composite layer is a molybdenum-aluminum metal composite layer, a molybdenum-aluminum alloy composite layer, and a titanium-aluminum metal composite a layer, or a copper-molybdenum metal composite layer;
  • An amorphous silicon layer being disposed on a surface of the substrate and the gate;
  • the patterned second metal layer is disposed on a surface of the amorphous silicon layer, the second metal layer is a second metal composite layer, and the second metal composite layer is molybdenum-aluminum a molybdenum metal composite layer, a titanium-aluminum-titanium metal composite layer, or a copper-molybdenum metal composite layer;
  • a passivation layer formed on the surface of the patterned second metal layer and the amorphous silicon layer, wherein the passivation layer is provided with a through hole;
  • a pixel electrode formed on the passivation layer, the pixel electrode contacting the patterned second metal layer through the via hole, the patterned second metal layer, the passivation layer And the pixel electrode is formed by a photolithography process to form a channel, the channel separating the patterned second metal layer into a source and a drain, wherein the channel has a width of 2 to 5 micrometers.
  • the present application performs a fourth photolithography process on the light-transmissive conductive layer, the passivation layer, and the patterned second metal layer on the transparent conductive layer, the passivation layer, and the A channel, a source and a drain are formed on the patterned second metal layer, and the source and the drain are respectively located on both sides of the channel. Since the channel is not affected by the plating process or other photolithography process, the channel has better quality, such as better uniformity, and the stability of the active switch array substrate prepared by the method is better.
  • FIG. 1 is a flow chart of preparing an active switch array substrate according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a gate formed on a substrate of an active switch array substrate of the present application.
  • FIG 3 is a schematic diagram of a gate electrode and an amorphous silicon layer formed on a substrate of an active switch array substrate of the present application.
  • FIG. 4 is a schematic diagram of a gate, an amorphous silicon layer, and a patterned second metal layer formed on a substrate of an active switch array substrate of the present application.
  • FIG. 5 is a schematic diagram of a gate, an amorphous silicon layer, a patterned second metal layer, and a passivation layer formed on a substrate of an active switch array substrate of the present application.
  • FIG. 6 is a schematic diagram of a gate, an amorphous silicon layer, a patterned second metal layer, a passivation layer, and a light-transmissive conductive layer formed on a substrate of the active switch array substrate of the present application.
  • FIG. 7 is a schematic diagram of an embodiment of an active switch array substrate of the present application.
  • FIG. 8 is a schematic diagram of another angle of the active switch array substrate shown in FIG. 7.
  • FIG. 8 is a schematic diagram of another angle of the active switch array substrate shown in FIG. 7.
  • FIG. 9 is a schematic diagram of still another angle of the active switch array substrate shown in FIG. 7.
  • FIG. 9 is a schematic diagram of still another angle of the active switch array substrate shown in FIG. 7.
  • first”, “second”, and the like in this application are used for the purpose of description only, and are not to be construed as indicating or implying their relative importance or implicitly indicating the number of technical features indicated.
  • features defining “first” or “second” may include at least one of the features, either explicitly or implicitly.
  • the technical solutions between the various embodiments may be combined with each other, but must be based on the realization of those skilled in the art, and when the combination of the technical solutions is contradictory or impossible to implement, it should be considered that the combination of the technical solutions does not exist. Nor is it within the scope of protection required by this application.
  • the application provides a method for preparing an active switch array substrate.
  • a method for preparing the active switch array substrate includes the following steps:
  • the transparent conductive layer 60 is plated on the passivation layer 50, wherein the transparent conductive layer 60 is in contact with the patterned second metal layer 40 through the through hole 51;
  • the source 41 and the drain 43 are respectively located at two sides of the channel 70, so that an active switch can be formed (for example, TFT) on the substrate 10.
  • the amorphous silicon layer 30 includes sequentially formed on the substrate 10 and the gate 20SiNx layer, the ⁇ -Si layer, and the N+ ⁇ -Si layer.
  • the transparent conductive layer 60 may be made of a transparent or translucent conductive metal having a thickness of 0.03 to 0.05 ⁇ m.
  • the transparent or translucent conductive metal may be: indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), cadmium oxide (CdO), cadmium indium (CdIn2O4), cadmium stannate (Cd2SnO4), Zinc stannate (Zn2SnO4), indium oxide-zinc oxide (In2O3-ZnO), or indium oxide-tin (In2O3:Sn).
  • the light-transmissive conductive layer 60, the passivation layer 50, and the patterned second metal layer 40 the light-transmissive conductive layer 60, the blunt A channel 70, a source 41 and a drain 43 are formed on the patterned layer 50 and the patterned second metal layer 40.
  • the source 41 and the drain 43 are respectively located on opposite sides of the channel 70. Since the channel 70 is not affected by the plating process or other photolithography process, the channel 70 has better quality, such as better uniformity, and the stability of the active switch array substrate prepared by the method is better. Therefore, it has better quality.
  • Forming the channel 70 includes the following steps:
  • the binary mask being a mask having two transmittances; shielding the photoresist film with the binary mask;
  • the first portion of the photoresist film is irradiated, and the second portion of the photoresist film is not irradiated; the first portion of the photoresist film is removed, and the second portion of the photoresist film is not removed. ;
  • the light-transmissive conductive layer 60, the passivation layer 50, and the patterned second metal layer 40, which are not covered by the second portion of the photoresist film, are removed to form the via 70.
  • channels 70 may be formed.
  • the binary mask is composed of a light shielding portion and a light transmitting portion.
  • the light shielding portion covers a first portion of the photoresist film, the light transmitting portion is disposed in other regions of the photoresist film, and ultraviolet light is irradiated to the first portion of the photoresist film through the light transmitting portion, and second Part of the photoresist film is not irradiated.
  • the binary mask is composed only of the light shielding portion and the light transmitting portion, the photoresist film of the first portion and the photoresist film of the second portion can be clearly defined, so that the light that is not the second portion can be accurately used by etching
  • the light-transmissive conductive layer 60, the passivation layer 50, and the patterned second metal layer 40 covered by the resist film are removed to form the channel 70.
  • the plurality of channels 70 have consistency.
  • the channel 70 has a width of 2 to 5 microns.
  • the channel 70 of the present application has a width of 2 to 5 micrometers, and the channel 70 is formed by a fourth photolithography process, and has a better quality.
  • the step of plating the first metal layer on the substrate 10 is: plating a first composite metal layer on the substrate 10, the first metal composite layer being a molybdenum-aluminum metal composite layer, a molybdenum-aluminum alloy composite layer, A titanium-aluminum metal composite layer or a copper-molybdenum metal composite layer.
  • the molybdenum metal layer is plated on a surface of the substrate 10
  • the aluminum metal layer is plated on the molybdenum metal layer
  • the molybdenum The metal layer has a thickness of 0.3 to 0.5 ⁇ m, optionally 0.39 ⁇ m
  • the aluminum metal layer has a thickness of 0.04 to 0.08 ⁇ m, optionally 0.06 ⁇ m.
  • the first metal composite layer is a molybdenum-aluminum alloy composite layer
  • the molybdenum metal layer is plated on a surface of the substrate 10
  • the aluminum alloy layer is plated on the molybdenum metal layer, the molybdenum metal layer
  • the thickness is 0.3 to 0.5 micrometers, optionally 0.39 micrometers
  • the thickness of the aluminum alloy layer is 0.04 to 0.08 micrometers, optionally 0.06 micrometers.
  • the first metal composite layer is a titanium-aluminum metal composite layer
  • the titanium metal layer is plated on the surface of the substrate 10
  • the aluminum alloy layer is plated on the titanium metal layer, the titanium metal layer
  • the thickness is 0.3 to 0.5 micrometers, optionally 0.39 micrometers
  • the thickness of the aluminum alloy layer is 0.04 to 0.08 micrometers, optionally 0.06 micrometers.
  • the first metal composite layer is a copper-molybdenum metal composite layer
  • the copper metal layer is plated on the surface of the substrate 10
  • the molybdenum metal layer is plated on the copper metal layer, the copper metal layer
  • the thickness is 0.3 to 0.5 micrometers, optionally 0.39 micrometers, and the thickness of the molybdenum metal layer is 0.04 to 0.08 micrometers, optionally 0.06 micrometers.
  • the present application applies a first metal layer on the substrate 10, and the first metal layer may be a composite metal layer to make the first metal layer have better conductivity.
  • the step of forming the second metal layer on the amorphous silicon layer 30 is: plating a second metal composite layer on the amorphous silicon layer 30, the second metal composite layer being a molybdenum-aluminum-molybdenum metal composite a layer, a titanium-aluminum-titanium metal composite layer, or a copper-molybdenum metal composite layer.
  • the second metal composite layer is a molybdenum-aluminum-molybdenum composite layer
  • the molybdenum metal layer and the aluminum metal layer and the molybdenum metal layer are sequentially plated on the surface of the amorphous silicon layer 30, the molybdenum metal
  • the thickness of the layer and the aluminum metal layer and the molybdenum metal layer are respectively 0.005 to 0.015 micrometers, 0.2 to 0.4 micrometers, and 0.03 to 0.04 micrometers, and may be selected to be 0.01 micrometers, 0.3 micrometers, and 0.035 micrometers, respectively.
  • the second metal composite layer is a titanium-aluminum-titanium composite layer
  • the titanium metal layer and the aluminum metal layer and the titanium metal layer are sequentially plated on the surface of the amorphous silicon layer 30, the titanium metal
  • the thickness of the layer and the aluminum metal layer and the titanium metal layer are respectively 0.005 to 0.015 micrometers, 0.2 to 0.4 micrometers, and 0.03 to 0.04 micrometers, and may be selected to be 0.01 micrometers, 0.3 micrometers, and 0.035 micrometers, respectively.
  • the copper metal layer and the molybdenum metal layer are sequentially plated on the surface of the amorphous silicon layer 30, and the copper metal layer and the molybdenum metal layer are
  • the thicknesses are respectively 0.005 to 0.015 micrometers and 0.2 to 0.4 micrometers, and may be selected to be 0.01 micrometers and 0.3 micrometers, respectively.
  • the present application is plated on the amorphous silicon layer 30 to form a second metal layer, and the second metal layer may be a composite metal layer to make the second metal layer have better conductivity.
  • the transparent conductive layer 60 may be made of a transparent or translucent conductive metal having a thickness of 0.03 to 0.05 ⁇ m.
  • the transparent or translucent conductive metal may be: indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), cadmium oxide (CdO), cadmium indium (CdIn2O4), cadmium stannate (Cd2SnO4), Zinc stannate (Zn2SnO4), indium oxide-zinc oxide (In2O3-ZnO), or indium oxide-tin (In2O3:Sn).
  • the light-transmitting conductive layer 60 of the present application is a transparent or translucent conductive metal layer, so that the light-transmitting conductive layer 60 is transparent or translucent and has better conductivity.
  • the present application further provides an active switch array substrate prepared by the method for preparing the active switch array substrate, which includes a substrate 10, a gate electrode 20 disposed on the substrate 10, and a substrate An amorphous silicon layer 30 on a surface of the substrate 10 and the gate electrode 20, the active switch array substrate further includes a patterned second metal layer 40 disposed on a surface of the amorphous silicon layer 30, formed on the pattern a passivation layer 50 on the surface of the second metal layer 40 and the amorphous silicon layer 30, and a pixel electrode 61 formed on the passivation layer, the passivation layer 50 is provided with a through hole 51, and the pixel electrode Passing through the through hole 51 to contact the patterned second metal layer 40, the patterned second metal layer 40, the passivation layer 50 and the pixel electrode 61 are formed together by a photolithography process. 70, the channel 70 separates the patterned second metal layer 40 into a source 41 and a drain 43.
  • a data line 45 interleaved with the gate is formed on the substrate 10.
  • the channel 70 of the present application is obtained by photolithography processing the patterned second metal layer 40, the passivation layer 50 and the pixel electrode 61, since the channel 70 is not subjected to plating or other photolithography processing.
  • the effect of the channel 70 is of better quality, while the active switch array substrate also has better quality.
  • the channel 70 has a width of 2 to 5 microns.
  • the channel 70 of the present application has a width of 2 to 5 micrometers, and the channel 70 is formed by a fourth photolithography process, and has a better quality.
  • the gate electrodes 20 are all a first metal composite layer, and the first metal composite layer is a molybdenum-aluminum metal composite layer, a molybdenum-aluminum alloy composite layer, a titanium-aluminum metal composite layer, or a copper-molybdenum metal composite layer.
  • the molybdenum metal layer is plated on a surface of the substrate 10
  • the aluminum metal layer is plated on the molybdenum metal layer
  • the molybdenum The metal layer has a thickness of 0.3 to 0.5 ⁇ m, optionally 0.39 ⁇ m
  • the aluminum metal layer has a thickness of 0.04 to 0.08 ⁇ m, optionally 0.06 ⁇ m.
  • the first metal composite layer is a molybdenum-aluminum alloy composite layer
  • the molybdenum metal layer is plated on a surface of the substrate 10
  • the aluminum alloy layer is plated on the molybdenum metal layer, the molybdenum metal layer
  • the thickness is 0.3 to 0.5 micrometers, optionally 0.39 micrometers
  • the thickness of the aluminum alloy layer is 0.04 to 0.08 micrometers, optionally 0.06 micrometers.
  • the first metal composite layer is a titanium-aluminum metal composite layer
  • the titanium metal layer is plated on the surface of the substrate 10
  • the aluminum alloy layer is plated on the titanium metal layer, the titanium metal layer
  • the thickness is 0.3 to 0.5 micrometers, optionally 0.39 micrometers
  • the thickness of the aluminum alloy layer is 0.04 to 0.08 micrometers, optionally 0.06 micrometers.
  • the first metal composite layer is a copper-molybdenum metal composite layer
  • the copper metal layer is plated on the surface of the substrate 10
  • the molybdenum metal layer is plated on the copper metal layer, the copper metal layer
  • the thickness is 0.3 to 0.5 micrometers, optionally 0.39 micrometers, and the thickness of the molybdenum metal layer is 0.04 to 0.08 micrometers, optionally 0.06 micrometers.
  • the present application applies a first metal layer on the substrate 10, and the first metal layer may be a composite metal layer to make the first metal layer have better conductivity.
  • the metal layer plated on the amorphous silicon layer 30 is a second metal composite layer, and the second metal composite layer is a molybdenum-aluminum-molybdenum metal composite layer, a titanium-aluminum-titanium metal composite layer, or a copper-molybdenum layer. Metal composite layer.
  • the second metal composite layer is a molybdenum-aluminum-molybdenum composite layer
  • the molybdenum metal layer and the aluminum metal layer and the molybdenum metal layer are sequentially plated on the surface of the amorphous silicon layer 30, the molybdenum metal
  • the thickness of the layer and the aluminum metal layer and the molybdenum metal layer are respectively 0.005 to 0.015 micrometers, 0.2 to 0.4 micrometers, and 0.03 to 0.04 micrometers, and may be selected to be 0.01 micrometers, 0.3 micrometers, and 0.035 micrometers, respectively.
  • the second metal composite layer is a titanium-aluminum-titanium composite layer
  • the titanium metal layer and the aluminum metal layer and the titanium metal layer are sequentially plated on the surface of the amorphous silicon layer 30, the titanium metal
  • the thickness of the layer and the aluminum metal layer and the titanium metal layer are respectively 0.005 to 0.015 micrometers, 0.2 to 0.4 micrometers, and 0.03 to 0.04 micrometers, and may be selected to be 0.01 micrometers, 0.3 micrometers, and 0.035 micrometers, respectively.
  • the copper metal layer and the molybdenum metal layer are sequentially plated on the surface of the amorphous silicon layer 30, and the copper metal layer and the molybdenum metal layer are
  • the thicknesses are respectively 0.005 to 0.015 micrometers and 0.2 to 0.4 micrometers, and may be selected to be 0.01 micrometers and 0.3 micrometers, respectively.
  • the present application is plated on the amorphous silicon layer 30 to form a second metal layer, and the second metal layer may be a composite metal layer to make the second metal layer have better conductivity.
  • the passivation layer 50 is made of SiNx, has a thickness of 100 to 250 microns, and x is 1 or 4/3.
  • the passivation layer 50 of the present application is made of SiNx and has a thickness of 100 to 250 ⁇ m, so that the passivation layer 50 can protect the source 41 and the drain 43.
  • the present application also provides a display (not shown) including a color filter, a liquid crystal, and the active switch array substrate.
  • the liquid crystal is located between the active switch array substrate and the color filter. Since the display adopts all the technical solutions of all the above embodiments, at least the effects brought by the technical solutions of the foregoing embodiments are not repeatedly described herein.
  • the display also includes other components that perform display functions, such as horizontal polarizers, vertical polarizers, and the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种主动开关阵列基板及其制备方法，包括：提供基板（10）；在基板上镀覆第一金属层；对第一金属层进行第一次光刻处理，形成栅极（20）；于基板、栅极上沉积非晶硅层（30）；在非晶硅层上镀覆形成第二金属层；对第二金属层进行第二次光刻处理，以形成图案化第二金属层（40）；于图案化第二金属层上涂覆钝化层（50）；对钝化层进行第三次光刻处理，以形成通孔（51）于钝化层上；于钝化层上镀覆透光导电层（60）；对透光导电层、钝化层、及图案化第二金属层进行第四次光刻处理，于透光导电层、钝化层、及图案化第二金属层上形成通道（70）、源极（41）及漏极（43）。

Description

主动开关阵列基板及其制备方法
技术领域
本申请涉及显示器技术领域，特别涉及一种主动开关阵列基板，及该主动开关阵列基板的制备方法。
背景技术
现有的主动开关阵列基板包括源极、漏极和位于所述源极和漏极之间的通道。传统的制备主动开关阵列基板的过程中需在所述通道上形成钝化层，再于所述钝化层上溅镀ITO（Indium tin oxide，氧化铟锡）膜。然而，所述溅镀处理会对钝化层造成损坏，导致损坏后的钝化层不能有效地保护通道，导致所述溅镀处理也会对所述通道造成损坏，使得薄膜晶体管的品质较差。
进一步地，在对ITO进行光刻处理的过程中，所述光刻处理也易对钝化层造成损坏，导致所述光刻处理也会对所述通道造成损坏，从而使得所述薄膜晶体管的品质较差。
发明内容
本申请提供一种主动开关阵列基板的制备方法，其可在一定程度上解决示例性技术中制得的主动开关阵列基板品质差的问题。
本申请提出的一种主动开关阵列基板的制备方法，包括以下步骤:
提供一基板；
在所述基板上镀覆第一金属层；
对所述第一金属层进行第一次光刻处理，以形成栅极；
于所述基板、所述栅极上沉积非晶硅层；
在所述非晶硅层上镀覆形成第二金属层；
对所述第二金属层进行第二次光刻处理，以形成图案化第二金属层；
于所述图案化第二金属层上涂覆钝化层；
对所述钝化层进行第三次光刻处理，以形成通孔于所述钝化层上；
于所述钝化层上镀覆透光导电层，其中所述透光导电层穿过所述通孔与所述图案化第二金属层接触；以及
对所述透光导电层、所述钝化层、及所述图案化第二金属层进行第四次光刻处理，于所述透光导电层、所述钝化层、及所述图案化第二金属层上形成通道、源极及漏极，所述源极和所述漏极分别位于所述通道的两侧。
在一实施例中，形成通道包括以下步骤：
于所述透光导电层上涂覆光阻膜；
提供二元掩模，所述二元掩膜为具有两种透过率的掩膜；
采用所述二元掩模遮蔽所述光阻膜；
紫外光穿过所述二元掩膜后，照射第一部分的光阻膜；第一部分的光阻膜被去除，第二部分的光阻膜未被去除；
去除未被第二部分的光阻膜覆盖的透光导电层、钝化层、及图案化第二金属层，形成所述通道。
在一实施例中，所述通道的宽度为2~5微米。
在一实施例中，在所述基板上镀覆第一金属层包括：在基板表面镀覆第一复合金属层，所述第一金属复合层为钼-铝金属复合层、钼-铝合金复合层、钛-铝金属复合层、或铜-钼金属复合层。
在一实施例中，在所述非晶硅层上镀覆形成第二金属层包括：在非晶硅层表面镀覆第二金属复合层，所述第二金属复合层为钼-铝-钼金属复合层、钛-铝-钛金属复合层、或铜-钼金属复合层。
在一实施例中，所述透光导电层为半透明或透明的导电金属层。
本申请还提出一种主动开关阵列基板，所述主动开关阵列基板包括：
基板；
栅极，所述栅极设于所述基板；
非晶硅层，所述非晶硅层设于所述基板和所述栅极的表面；
图案化第二金属层，所述图案化第二金属层设于所述非晶硅层表面；
钝化层，所述钝化层形成于所述图案化第二金属层及所述非晶硅层表面，所述钝化层开设有通孔；以及
像素电极，所述像素电极形成于所述钝化层，所述像素电极穿过所述通孔与所述图案化第二金属层接触，所述图案化第二金属层、所述钝化层及所述像素电极通过光刻处理共同形成有通道，所述通道将所述图案化第二金属层分隔为源极和漏极。
在一实施例中，所述通道的宽度为2~5微米。
在一实施例中，所述栅极为第一金属复合层，所述第一金属复合层为钼-铝金属复合层、钼-铝合金复合层、钛-铝金属复合层、或铜-钼金属复合层。
在一实施例中，所述第二金属层为第二金属复合层，所述第二金属复合层为钼-铝-钼金属复合层、钛-铝-钛金属复合层、或铜-钼金属复合层。
在一实施例中，所述像素电极为铟锡氧化物。
在一实施例中，所述钝化层的材质为SiNx，厚度为100~250微米，x为1或三分之四。
在一实施例中，所述非晶硅层包括依次形成于所述基体和所述栅极上SiNx层、α-Si层、N+ α-Si层。
在一实施例中，所述基板上形成有与栅极交错设置的数据线。
本申请还提出另一种主动开关阵列基板，所述主动开关阵列基板包括：
基板；
栅极，所述栅极设于所述基板，所述栅极为第一金属复合层，所述第一金属复合层为钼-铝金属复合层、钼-铝合金复合层、钛-铝金属复合层、或铜-钼金属复合层；
非晶硅层，所述非晶硅层设于所述基板和所述栅极的表面；
图案化第二金属层，所述图案化第二金属层设于所述非晶硅层表面，所述第二金属层为第二金属复合层，所述第二金属复合层为钼-铝-钼金属复合层、钛-铝-钛金属复合层、或铜-钼金属复合层；
钝化层，所述钝化层形成于所述图案化第二金属层及所述非晶硅层表面，所述钝化层开设有通孔；以及
像素电极，所述像素电极形成于所述钝化层，所述像素电极穿过所述通孔与所述图案化第二金属层接触，所述图案化第二金属层、所述钝化层及所述像素电极通过光刻处理共同形成有通道，所述通道将所述图案化第二金属层分隔为源极和漏极，其中，所述通道的宽度为2~5微米。
本申请在对所述透光导电层、所述钝化层、及所述图案化第二金属层进行第四次光刻处理，于所述透光导电层、所述钝化层、及所述图案化第二金属层上形成通道、源极及漏极，所述源极和所述漏极分别位于所述通道的两侧。由于通道不会受到镀覆处理或其它的光刻处理的影响，使得通道具有较佳的品质，如均匀性较佳，同时由所述方法制得的主动开关阵列基板的稳定性较佳。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的步骤获得其他的附图。
图1为本申请主动开关阵列基板一实施例的制备流程图。
图2为本申请主动开关阵列基板的基板上形成有栅极的示意图。
图3为本申请主动开关阵列基板的基板上形成有栅极及非晶硅层的示意图。
图4为本申请主动开关阵列基板的基板上形成有栅极、非晶硅层及图案化第二金属层的示意图。
图5为本申请主动开关阵列基板的基板上形成有栅极、非晶硅层、图案化第二金属层及钝化层的示意图。
图6为本申请主动开关阵列基板的基板上形成有栅极、非晶硅层、图案化第二金属层、钝化层及透光导电层的示意图。
图7为本申请主动开关阵列基板一实施例的示意图。
图8为图7所示主动开关阵列基板另一角度的示意图。
图9为图7所示主动开关阵列基板又一角度的示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，本申请实施例中所有方向性指示（诸如上、下、左、右、前、后……）仅用于解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，在本申请中涉及“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提供一种主动开关阵列基板的制备方法。
参照图1-9，在本申请实施例中，该主动开关阵列基板的制备方法，包括以下步骤：
提供一基板10；
在所述基板10上镀覆第一金属层；
对所述第一金属层进行第一次光刻处理，以形成栅极20；
于所述基板10、所述栅极20上沉积非晶硅层30；
在所述非晶硅层30上镀覆形成第二金属层；
对所述第二金属层进行第二次光刻处理，以形成图案化第二金属层40；
于所述图案化第二金属层40上涂覆钝化层50；
对所述钝化层50进行第三次光刻处理，以形成通孔51于所述钝化层50上；
于所述钝化层50上镀覆透光导电层60，其中所述透光导电层60穿过所述通孔51与所述图案化第二金属层40接触；
对所述透光导电层60、所述钝化层50、及所述图案化第二金属层40进行第四次光刻处理，于所述透光导电层60、所述钝化层50、及所述图案化第二金属层40上形成通道70、源极41及漏极43，所述源极41和所述漏极43分别位于所述通道70的两侧，因此，可形成主动开关(例如TFT)于基板10上。
在一实施例中，所述非晶硅层30包括依次形成于所述基板10和所述栅极20SiNx层、α-Si层、及N+ α-Si层。
所述透光导电层60的材质可为透明或半透明的导电金属，其厚度为0.03~0.05微米。所述透明或半透明的导电金属可为：氧化铟（In2O3）、氧化锡（SnO2）、氧化锌（ZnO）、氧化镉（CdO）、铟酸镉（CdIn2O4）、锡酸镉（Cd2SnO4）、锡酸锌（Zn2SnO4）、氧化铟-氧化锌（In2O3-ZnO）、或氧化铟-锡（In2O3:Sn）等。
本申请在对所述透光导电层60、所述钝化层50、及所述图案化第二金属层40进行第四次光刻处理时，于所述透光导电层60、所述钝化层50、及所述图案化第二金属层40上形成通道70、源极41及漏极43，所述源极41和所述漏极43分别位于所述通道70的两侧。由于通道70不会受到镀覆处理或其它的光刻处理的影响，使得通道70具有较佳的品质，如均匀性较佳，同时由所述方法制得的主动开关阵列基板的稳定性较佳，从而具有较佳的品质。
形成通道70包括以下步骤：
于所述透光导电层60上涂覆光阻膜；
提供二元掩模，所述二元掩膜为具有两种透过率的掩膜；采用所述二元掩模遮蔽所述光阻膜；
紫外光穿过所述二元掩膜后，照射第一部分的光阻膜，第二部分的光阻膜未被照射；第一部分的光阻膜被去除，第二部分的光阻膜未被去除；
去除未被第二部分的光阻膜覆盖的透光导电层60、钝化层50、及图案化第二金属层40，形成所述通道70。
可以理解的，可形成若干个通道70。
可以理解的，所述二元掩模由遮光部分和透光部分组成。所述遮光部分遮住所述光阻膜的第一部分，所述透光部分设于所述光阻膜的其它区域，紫外光通过所述透光部分照射到第一部分的光阻膜，第二部分的光阻膜未被照射。由于二元掩模仅由遮光部分和透光部分组成，第一部分的光阻膜和第二部分的光阻膜可被清楚地限定，使得可精确地使用蚀刻方式将未被第二部分的光阻膜覆盖的所述透光导电层60、所述钝化层50、及所述图案化第二金属层40去除，形成所述通道70。当具有若个通道70时，所述若干通道70具有一致性。
所述通道70的宽度为2~5微米。
本申请的通道70的宽度为2~5微米，所述通道70经过第四次光刻处理时形成，具有较佳的品质。
在所述基板10上镀覆第一金属层的步骤为：在基板10上镀覆第一复合金属层，所述第一金属复合层为钼-铝金属复合层、钼-铝合金复合层、钛-铝金属复合层、或铜-钼金属复合层。
其中，所述第一金属复合层为钼-铝金属复合层时，所述钼金属层镀覆于所述基板10的表面，所述铝金属层镀覆于所述钼金属层，所述钼金属层的厚度为0.3~0.5微米，可选为0.39微米，所述铝金属层的厚度为0.04~0.08微米，可选为0.06微米。
所述第一金属复合层为钼-铝合金复合层时，所述钼金属层镀覆于所述基板10的表面，所述铝合金层镀覆于所述钼金属层，所述钼金属层的厚度为0.3~0.5微米，可选为0.39微米，所述铝合金层的厚度为0.04~0.08微米，可选为0.06微米。
所述第一金属复合层为钛-铝金属复合层时，所述钛金属层镀覆于所述基板10的表面，所述铝合金层镀覆于所述钛金属层，所述钛金属层的厚度为0.3~0.5微米，可选为0.39微米，所述铝合金层的厚度为0.04~0.08微米，可选为0.06微米。
所述第一金属复合层为铜-钼金属复合层时，所述铜金属层镀覆于所述基板10的表面，所述钼金属层镀覆于所述铜金属层，所述铜金属层的厚度为0.3~0.5微米，可选为0.39微米，所述钼金属层的厚度为0.04~0.08微米，可选为0.06微米。
本申请在所述基板10上镀覆第一金属层，所述第一金属层可为复合金属层，以使所述第一金属层具有较佳的导电性。
在所述非晶硅层30上镀覆形成第二金属层的步骤为：在非晶硅层30上镀覆第二金属复合层，所述第二金属复合层为钼-铝-钼金属复合层、钛-铝-钛金属复合层、或铜-钼金属复合层。
其中，所述第二金属复合层为钼-铝-钼复合层时，所述钼金属层和铝金属层及钼金属层依次镀覆于所述非晶硅层30的表面，所述钼金属层和铝金属层及钼金属层的厚度分别为0.005~0.015微米、0.2~0.4微米、0.03~0.04微米，分别可选为0.01微米、0.3微米、0.035微米。
其中，所述第二金属复合层为钛-铝-钛复合层时，所述钛金属层和铝金属层及钛金属层依次镀覆于所述非晶硅层30的表面，所述钛金属层和铝金属层及钛金属层的厚度分别为0.005~0.015微米、0.2~0.4微米、0.03~0.04微米，分别可选为0.01微米、0.3微米、0.035微米。
其中，所述第二金属复合层为铜-钼复合层时，所述铜金属层和钼金属层依次镀覆于所述非晶硅层30的表面，所述铜金属层和钼金属层的厚度分别为0.005~0.015微米、0.2~0.4微米，分别可选为0.01微米、0.3微米。
本申请在所述非晶硅层30上镀覆形成第二金属层，所述第二金属层可为复合金属层，以使所述第二金属层具有较佳的导电性。
所述透光导电层60的材质可为透明或半透明的导电金属，其厚度为0.03~0.05微米。所述透明或半透明的导电金属可为：氧化铟（In2O3）、氧化锡（SnO2）、氧化锌（ZnO）、氧化镉（CdO）、铟酸镉（CdIn2O4）、锡酸镉（Cd2SnO4）、锡酸锌（Zn2SnO4）、氧化铟-氧化锌（In2O3-ZnO）、或氧化铟-锡（In2O3:Sn）等。
本申请的透光导电层60为透明或半透明的导电金属层，使得透光导电层60透明或半透明，并具有较佳的导电性。
请参图7-9，本申请还提供一种由上述主动开关阵列基板的制备方法所制得的主动开关阵列基板，其包括基板10、设于所述基板10的栅极20、设于所述基板10和所述栅极20的表面的非晶硅层30，所述主动开关阵列基板还包括设于所述非晶硅层30表面的图案化第二金属层40、形成于所述图案化第二金属层40及所述非晶硅层30表面的钝化层50、及形成于所述钝化层的像素电极61，所述钝化层50开设有通孔51，所述像素电极61穿过所述通孔51与所述图案化第二金属层40接触，所述图案化第二金属层40、所述钝化层50及所述像素电极61通过光刻处理共同形成有通道70，所述通道70将所述图案化第二金属层40分隔为源极41和漏极43。
所述基板10上形成有与栅极交错设置的数据线45。
本申请的通道70由对所述图案化第二金属层40、所述钝化层50及所述像素电极61进行光刻处理而制得，由于通道70不会受到镀覆或其它光刻处理的影响，使得通道70具有较佳的品质，同时，所述主动开关阵列基板也具有较佳的品质。
所述通道70的宽度为2~5微米。
本申请的通道70的宽度为2~5微米，所述通道70经过第四次光刻处理时形成，具有较佳的品质。
所述栅极20均为第一金属复合层，所述第一金属复合层为钼-铝金属复合层、钼-铝合金复合层、钛-铝金属复合层、或铜-钼金属复合层。
其中，所述第一金属复合层为钼-铝金属复合层时，所述钼金属层镀覆于所述基板10的表面，所述铝金属层镀覆于所述钼金属层，所述钼金属层的厚度为0.3~0.5微米，可选为0.39微米，所述铝金属层的厚度为0.04~0.08微米，可选为0.06微米。
所述第一金属复合层为钼-铝合金复合层时，所述钼金属层镀覆于所述基板10的表面，所述铝合金层镀覆于所述钼金属层，所述钼金属层的厚度为0.3~0.5微米，可选为0.39微米，所述铝合金层的厚度为0.04~0.08微米，可选为0.06微米。
所述第一金属复合层为钛-铝金属复合层时，所述钛金属层镀覆于所述基板10的表面，所述铝合金层镀覆于所述钛金属层，所述钛金属层的厚度为0.3~0.5微米，可选为0.39微米，所述铝合金层的厚度为0.04~0.08微米，可选为0.06微米。
所述第一金属复合层为铜-钼金属复合层时，所述铜金属层镀覆于所述基板10的表面，所述钼金属层镀覆于所述铜金属层，所述铜金属层的厚度为0.3~0.5微米，可选为0.39微米，所述钼金属层的厚度为0.04~0.08微米，可选为0.06微米。
本申请在所述基板10上镀覆第一金属层，所述第一金属层可为复合金属层，以使所述第一金属层具有较佳的导电性。
镀覆于所述非晶硅层30的金属层为第二金属复合层，所述第二金属复合层为钼-铝-钼金属复合层、钛-铝-钛金属复合层、或铜-钼金属复合层。
其中，所述第二金属复合层为钼-铝-钼复合层时，所述钼金属层和铝金属层及钼金属层依次镀覆于所述非晶硅层30的表面，所述钼金属层和铝金属层及钼金属层的厚度分别为0.005~0.015微米、0.2~0.4微米、0.03~0.04微米，分别可选为0.01微米、0.3微米、0.035微米。
其中，所述第二金属复合层为钛-铝-钛复合层时，所述钛金属层和铝金属层及钛金属层依次镀覆于所述非晶硅层30的表面，所述钛金属层和铝金属层及钛金属层的厚度分别为0.005~0.015微米、0.2~0.4微米、0.03~0.04微米，分别可选为0.01微米、0.3微米、0.035微米。
其中，所述第二金属复合层为铜-钼复合层时，所述铜金属层和钼金属层依次镀覆于所述非晶硅层30的表面，所述铜金属层和钼金属层的厚度分别为0.005~0.015微米、0.2~0.4微米，分别可选为0.01微米、0.3微米。
本申请在所述非晶硅层30上镀覆形成第二金属层，所述第二金属层可为复合金属层，以使所述第二金属层具有较佳的导电性。
所述钝化层50的材质为SiNx，厚度为100~250微米，x为1或三分之四。
本申请的钝化层50的材质为SiNx，厚度为100~250微米，使得所述钝化层50可对所述源极41、漏极43进行保护。
本申请还提供一种显示器（未图示），其包括彩色滤光片、液晶及所述主动开关阵列基板。所述液晶位于所述主动开关阵列基板与所述彩色滤光片之间。由于所述显示器采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有效果，在此不再一一赘述。
可以理解的，所述显示器还包括实施显示功能的其他组件，如水平偏光片、垂直偏光片等。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的申请构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (15)

  1. 一种主动开关阵列基板的制备方法，包括以下步骤：
    提供一基板；
    在所述基板上镀覆第一金属层；
    对所述第一金属层进行第一次光刻处理，以形成栅极；
    于所述基板、所述栅极上沉积非晶硅层；
    在所述非晶硅层上镀覆形成第二金属层；
    对所述第二金属层进行第二次光刻处理，以形成图案化第二金属层；
    于所述图案化第二金属层上涂覆钝化层；
    对所述钝化层进行第三次光刻处理，以形成通孔于所述钝化层上；
    于所述钝化层上镀覆透光导电层，其中所述透光导电层穿过所述通孔与所述图案化第二金属层接触；以及
    对所述透光导电层、所述钝化层、及所述图案化第二金属层进行第四次光刻处理，于所述透光导电层、所述钝化层、及所述图案化第二金属层上形成通道、源极及漏极，所述源极和所述漏极分别位于所述通道的两侧。
  2. 如权利要求1所述的主动开关阵列基板的制备方法，其中，形成通道包括以下步骤：
    于所述透光导电层上涂覆光阻膜；
    提供二元掩模，所述二元掩膜为具有两种透过率的掩膜；
    采用所述二元掩模遮蔽所述光阻膜；
    紫外光穿过所述二元掩膜后，照射第一部分的光阻膜；第一部分的光阻膜被去除，第二部分的光阻膜未被去除；
    去除未被第二部分的光阻膜覆盖的透光导电层、钝化层、及图案化第二金属层，形成所述通道。
  3. 如权利要求1所述的主动开关阵列基板的制备方法，其中，所述通道的宽度为2~5微米。
  4. 如权利要求1所述的主动开关阵列基板的制备方法，其中，在所述基板上镀覆第一金属层包括：在基板表面镀覆第一复合金属层，所述第一金属复合层为钼-铝金属复合层、钼-铝合金复合层、钛-铝金属复合层、或铜-钼金属复合层。
  5. 如权利要求4所述的主动开关阵列基板的制备方法，其中，在所述非晶硅层上镀覆形成第二金属层包括：在非晶硅层表面镀覆第二金属复合层，所述第二金属复合层为钼-铝-钼金属复合层、钛-铝-钛金属复合层、或铜-钼金属复合层。
  6. 如权利要求1所述的主动开关阵列基板的制备方法，其中，所述透光导电层为半透明或透明的导电金属层。
  7. 一种主动开关阵列基板，所述主动开关阵列基板包括：
    基板；
    栅极，所述栅极设于所述基板；
    非晶硅层，所述非晶硅层设于所述基板和所述栅极的表面；
    图案化第二金属层，所述图案化第二金属层设于所述非晶硅层表面；
    钝化层，所述钝化层形成于所述图案化第二金属层及所述非晶硅层表面，所述钝化层开设有通孔；以及
    像素电极，所述像素电极形成于所述钝化层，所述像素电极穿过所述通孔与所述图案化第二金属层接触，所述图案化第二金属层、所述钝化层及所述像素电极通过光刻处理共同形成有通道，所述通道将所述图案化第二金属层分隔为源极和漏极。
  8. 如权利要求7所述的主动开关阵列基板，其中，所述通道的宽度为2~5微米。
  9. 如权利要求7所述的主动开关阵列基板，其中，所述栅极为第一金属复合层，所述第一金属复合层为钼-铝金属复合层、钼-铝合金复合层、钛-铝金属复合层、或铜-钼金属复合层。
  10. 如权利要求7所述的主动开关阵列基板，其中，所述第二金属层为第二金属复合层，所述第二金属复合层为钼-铝-钼金属复合层、钛-铝-钛金属复合层、或铜-钼金属复合层。
  11. 如权利要求7所述的主动开关阵列基板，其中，所述像素电极为铟锡氧化物。
  12. 如权利要求7所述的主动开关阵列基板，其中，所述钝化层的材质为SiNx，厚度为100~250微米，x为1或三分之四。
  13. 如权利要求7所述的主动开关阵列基板，其中，所述非晶硅层包括依次形成于所述基体和所述栅极上SiNx层、α-Si层、N+ α-Si层。
  14. 如权利要求7所述的主动开关阵列基板，其中，所述基板上形成有与栅极交错设置的数据线。
  15. 一种主动开关阵列基板，其中，所述主动开关阵列基板包括：
    基板；
    栅极，所述栅极设于所述基板，所述栅极为第一金属复合层，所述第一金属复合层为钼-铝金属复合层、钼-铝合金复合层、钛-铝金属复合层、或铜-钼金属复合层；
    非晶硅层，所述非晶硅层设于所述基板和所述栅极的表面；
    图案化第二金属层，所述图案化第二金属层设于所述非晶硅层表面，所述第二金属层为第二金属复合层，所述第二金属复合层为钼-铝-钼金属复合层、钛-铝-钛金属复合层、或铜-钼金属复合层；
    钝化层，所述钝化层形成于所述图案化第二金属层及所述非晶硅层表面，所述钝化层开设有通孔；以及
    像素电极，所述像素电极形成于所述钝化层，所述像素电极穿过所述通孔与所述图案化第二金属层接触，所述图案化第二金属层、所述钝化层及所述像素电极通过光刻处理共同形成有通道，所述通道将所述图案化第二金属层分隔为源极和漏极，其中，所述通道的宽度为2~5微米。
PCT/CN2017/114369 2016-12-08 2017-12-04 主动开关阵列基板及其制备方法 WO2018103599A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/317,045 US10770488B2 (en) 2016-12-08 2017-12-04 Active switch array substrate and method for manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201611127220.6 2016-12-08
CN201611127220.6A CN106601689B (zh) 2016-12-08 2016-12-08 主动开关阵列基板及其制备方法

Publications (1)

Publication Number Publication Date
WO2018103599A1 true WO2018103599A1 (zh) 2018-06-14

Family

ID=58598147

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/114369 WO2018103599A1 (zh) 2016-12-08 2017-12-04 主动开关阵列基板及其制备方法

Country Status (3)

Country Link
US (1) US10770488B2 (zh)
CN (1) CN106601689B (zh)
WO (1) WO2018103599A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106601689B (zh) * 2016-12-08 2019-04-09 惠科股份有限公司 主动开关阵列基板及其制备方法
CN108054214B (zh) * 2017-11-03 2020-12-29 惠科股份有限公司 晶体管结构和晶体管的制作方法
CN109637933B (zh) * 2018-12-25 2021-03-19 惠科股份有限公司 薄膜晶体管及其制作方法
CN109786258A (zh) * 2019-01-18 2019-05-21 惠科股份有限公司 薄膜晶体管的制备方法及显示装置
CN110212036A (zh) * 2019-06-11 2019-09-06 惠科股份有限公司 一种金属氧化物薄膜晶体管器件及其制作方法
CN112002753B (zh) * 2020-07-27 2023-06-27 北海惠科光电技术有限公司 栅极单元及其制备方法、阵列基板的制备方法、显示机构

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103227148A (zh) * 2013-04-02 2013-07-31 京东方科技集团股份有限公司 一种阵列基板制备方法及阵列基板和显示装置
CN103489876A (zh) * 2013-09-27 2014-01-01 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN103745955A (zh) * 2014-01-03 2014-04-23 京东方科技集团股份有限公司 显示装置、阵列基板及其制造方法
CN106601689A (zh) * 2016-12-08 2017-04-26 惠科股份有限公司 主动开关阵列基板及其制备方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100570863C (zh) * 2006-01-13 2009-12-16 中华映管股份有限公司 像素结构及其制造方法
JP2007250982A (ja) * 2006-03-17 2007-09-27 Canon Inc 酸化物半導体を用いた薄膜トランジスタ及び表示装置
CN100549791C (zh) * 2007-01-31 2009-10-14 友达光电股份有限公司 阵列基板的制作方法
CN102446925B (zh) * 2010-09-30 2015-05-20 京东方科技集团股份有限公司 阵列基板、液晶显示器及阵列基板的制造方法
CN102468306B (zh) * 2010-10-29 2014-04-16 京东方科技集团股份有限公司 阵列基板、液晶显示器及阵列基板的制造方法
CN102646699B (zh) * 2012-01-13 2014-12-10 京东方科技集团股份有限公司 一种氧化物薄膜晶体管及其制备方法
TWI621270B (zh) * 2013-02-07 2018-04-11 群創光電股份有限公司 薄膜電晶體元件與薄膜電晶體顯示裝置
KR20160053261A (ko) * 2014-10-31 2016-05-13 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 이의 제조 방법
TW201622158A (zh) * 2014-12-10 2016-06-16 中華映管股份有限公司 薄膜電晶體以及其製作方法
CN105679714B (zh) * 2016-01-27 2019-05-31 深圳市华星光电技术有限公司 阵列基板及其制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103227148A (zh) * 2013-04-02 2013-07-31 京东方科技集团股份有限公司 一种阵列基板制备方法及阵列基板和显示装置
CN103489876A (zh) * 2013-09-27 2014-01-01 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN103745955A (zh) * 2014-01-03 2014-04-23 京东方科技集团股份有限公司 显示装置、阵列基板及其制造方法
CN106601689A (zh) * 2016-12-08 2017-04-26 惠科股份有限公司 主动开关阵列基板及其制备方法

Also Published As

Publication number Publication date
CN106601689A (zh) 2017-04-26
US20190305015A1 (en) 2019-10-03
CN106601689B (zh) 2019-04-09
US10770488B2 (en) 2020-09-08

Similar Documents

Publication Publication Date Title
WO2018103599A1 (zh) 主动开关阵列基板及其制备方法
WO2014137192A2 (ko) 금속 세선을 포함하는 투명 기판 및 그 제조 방법
WO2016024760A1 (ko) 터치윈도우
AU2015368103B2 (en) Window cover and display apparatus having the same and method of manufacturing display apparatus
WO2020091307A1 (ko) 변동 저저항 라인 비휘발성 메모리 소자 및 이의 동작 방법
WO2014003346A1 (en) Light emitting diode for surface mount technology, method of manufacturing the same, and method of manufacturing light emitting diode module
WO2015065162A1 (ko) 전도성 구조체 및 이의 제조방법
WO2015076572A1 (ko) 전도성 구조체 및 이의 제조방법
WO2016171421A1 (ko) 터치 윈도우
WO2016204525A1 (ko) 터치 패널 및 표시 장치
WO2020222445A1 (ko) 디스플레이용 기판
WO2015174683A1 (en) Touch window
WO2013097487A1 (zh) 简易空中鼠标的实现方法、视频终端及系统
WO2020184777A1 (ko) 산화물 반도체 박막 트랜지스터의 제조 방법
WO2013159482A1 (zh) 图标智能显示的方法和装置
WO2019076087A1 (zh) 电视机及其显示图效控制方法、计算机可读存储介质
WO2021101149A1 (ko) 디스플레이용 기판
WO2017107384A1 (zh) 液晶显示器的图像显示方法及液晶显示器
WO2017031780A1 (zh) 一种阵列基板和液晶显示面板
WO2017069528A1 (ko) 편광판 일체형 윈도우 기판 및 이의 제조 방법
WO2018223602A1 (zh) 显示终端、画面对比度提高方法及计算机可读存储介质
WO2020130760A1 (ko) 표시 장치 및 그 제조방법
WO2022164168A1 (ko) 발광 소자, 발광 소자를 포함하는 발광 소자 유닛, 및 표시 장치
WO2018113244A1 (zh) 一种侦测异常画面的色偏补偿方法及显示装置
WO2014089801A1 (zh) 检测方法及检测装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17877635

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17877635

Country of ref document: EP

Kind code of ref document: A1