CN105185840A - 一种薄膜晶体管、阵列基板及其制成方法 - Google Patents

一种薄膜晶体管、阵列基板及其制成方法 Download PDF

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CN105185840A
CN105185840A CN201510716083.9A CN201510716083A CN105185840A CN 105185840 A CN105185840 A CN 105185840A CN 201510716083 A CN201510716083 A CN 201510716083A CN 105185840 A CN105185840 A CN 105185840A
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copper
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周志超
武岳
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/908,087 priority patent/US9646999B1/en
Priority to PCT/CN2015/097899 priority patent/WO2017071023A1/zh
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Abstract

本申请公开了一种薄膜晶体管、阵列基板及其制成方法，其中，该薄膜晶体管包括栅极、源极和漏极，所述源极和漏极均设置在所述栅极的同一侧，其中，所述栅极包括依序叠置的第一缓冲层、第一铜层、第二铜层及第二缓冲层，且所述第二缓冲层设置在靠近所述源极和漏极一侧；和/或，所述源极和漏极均包括依序叠置的第一缓冲层、第一铜层、第二铜层及第二缓冲层，且所述第一缓冲层设置在靠近所述栅极一侧；所述第一铜层以第一功率沉积得到，所述第二铜层以第二功率沉积得到，且所述第一功率高于所述第二功率。通过上述方式，能够防止蚀刻时光阻脱落。

Description

一种薄膜晶体管、阵列基板及其制成方法
技术领域
本申请涉及显示技术领域，特别是涉及一种薄膜晶体管、阵列基板及其制成方法。
背景技术
在液晶显示领域中，设有薄膜晶体管(英文：thinfilmtransistor，简称：TFT)的阵列基板作为液晶显示面板的开关，其结构与工艺对该液晶显示面板的显示效果影响至关重要。而为响应目前大尺寸化需求，且降低信号传输过程中的RC延迟等问题，低成本，低阻抗铜显然制成TFT的栅极、源极、漏极的不二选择。
在目前的TFT制程工艺中，TFT的栅极、源极、漏极常采用钼层与铜层叠置或钛层与铜层叠置的结构，其中，钼层和钛层作为缓冲层。在TFT制作过程中，先分别沉积缓冲层和铜层，再经蚀刻得到对应栅极、源极、或漏极的图案。在蚀刻过程中，易产生光阻脱落，进而导致过刻。
发明内容
本申请提供一种薄膜晶体管、阵列基板及其制成方法，能够防止蚀刻时光阻脱落。
本申请第一方面提供一种薄膜晶体管，其特征在于，包括栅极、源极和漏极，所述源极和漏极均设置在所述栅极的同一侧，其中，所述栅极包括依序叠置的第一缓冲层、第一铜层、第二铜层及第二缓冲层，且所述第二缓冲层设置在靠近所述源极和漏极一侧；和/或，所述源极和漏极均包括依序叠置的第一缓冲层、第一铜层、第二铜层及第二缓冲层，且所述第一缓冲层设置在靠近所述栅极一侧；所述第一铜层以第一功率沉积得到，所述第二铜层以第二功率沉积得到，且所述第一功率高于所述第二功率。
其中，所述第一功率位于50KW至70KW之间，所述第二功率位于20KW至40KW之间。
其中，所述第一缓冲层的厚度位于至之间，所述第一铜层的厚度位于至之间，所述第二铜层的厚度位于至之间，所述第二缓冲层的厚度位于至之间。
其中，所述第一缓冲层和所述第二缓冲层为钼膜、钛膜、或叠置的钼膜和钛膜。
其中，所述第一缓冲层、第一铜层、第二铜层及第二缓冲层中的至少一层由物理气相沉积制成。
其中，还包括设置在所述栅极与所述源极和漏极之间的栅极绝缘层和沟道层。
本申请第二方面提供一种阵列基板，包括基板和设置于基板上的多个薄膜晶体管，其中，所述薄膜晶体管为上述的薄膜晶体管。
本申请第三方面提供一种阵列基板的制成方法，包括：在基板上形成薄膜晶体管的栅极；在所述栅极上形成所述薄膜晶体管的源极和漏极；其中，所述形成栅极，和/或形成源极和漏极包括：依序形成第一缓冲层、第一铜层、第二铜层和第二缓冲层，其中，以第一功率制成，所述第二铜层以第二功率制成，且所述第一功率高于所述第二功率；在所述第二缓冲层上涂覆光阻，并进行蚀刻。
其中，所述第一缓冲层、第一铜层、第二铜层及第二缓冲层中的至少一层由物理气相沉积制成。
其中，所述第一功率位于50KW至70KW之间，所述第二功率位于20KW至40KW之间，所述第一缓冲层的厚度位于至之间，所述第一铜层的厚度位于至之间，所述第二铜层的厚度位于至之间，所述第二缓冲层的厚度位于至之间。
上述方案中，TFT的栅极、源极、漏极的至少一极采用第一缓冲层、第一铜层、第二铜层及第二缓冲层结构构成，其中第一铜层的制成功率比第二铜层的制成功率高。第二缓冲层对第二铜层起到保护作用，避免了直接蚀刻铜层而导致光阻脱落问题。而且，由于第二铜层的制成功率较低，保证了第二铜层的表面平整性，进而保证第二缓冲层对第二铜层覆盖的均匀性和平整性，进一步防止了光阻脱落问题，并且第一铜层的高制成功率也保证了TFT的生成效率。
附图说明
图1是本申请阵列基板一实施方式的结构示意图；
图2是本申请薄膜晶体管一实施方式的结构示意图；
图3是本申请薄膜晶体管另一实施方式的结构示意图；
图4是本申请阵列基板的制成方法一实施方式的流程图；
图5是图4所示的步骤410和/或420的子步骤流程图。
具体实施方式
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、接口、技术之类的具体细节，以便透彻理解本申请。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施方式中也可以实现本申请。在其它情况中，省略对众所周知的装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请的描述。
请参阅图1，图1是本申请阵列基板一实施方式的结构示意图。本实施方式中，阵列基板100包括基板110和多个TFT120(图1仅示范性示出基板110上的一个TFT120进行说明)。其中，所述基板110可以为玻璃基板或其他绝缘材料构成的透明基板。TFT120包括设置在所述基板110上的栅极121、源极122、漏极123。该源极122和漏极123均设置在该栅极121远离基板110的同一侧。
本实施方式中，TFT120还可包括设置在栅极121与源极122、漏极1225之间的栅绝缘层(英文：gateinsulator，简称：GI)124、沟道层125。所述栅绝缘层124叠置在所述栅极121和沟道层125之间，以将所述栅极121和沟道层125绝缘。所述源极122和漏极123位于沟道层125上的同一层，当栅极121获得大于或等于开启电压的电压时，沟道层125感应出电子，使源极122和漏极123导通。其中，该栅绝缘层124可为氮化铝(化学式：AlN)薄膜，该沟道层125可由金属氧化物构成，例如为铟镓锌氧化物(英文：indiumgalliumzincoxide，简称：IGZO)。
可选地，TFT120还包括设置在所述沟道层125上的刻蚀阻挡层126和覆盖在所述源极122和漏极123上的钝化层127，且所述刻蚀阻挡层126设置在所述源极122和漏极123之间。
可选地，为增加像素电极的开口率，源极、漏极和像素电极可是一体结构，由透明导电薄膜构成。
上述栅极121、源极122和漏极123的图案均由蚀刻如湿刻、干刻等工艺而得到。具体地，请结合参阅图2，图2是本申请薄膜晶体管一实施方式中栅极、源极、漏极的任意一极的结构示意图。本实施方式的栅极121、源极122及漏极123均包括以下结构：依序叠置的第一缓冲层a1、第一铜层a2、第二铜层a3及第二缓冲层a4。其中，栅极121的第二缓冲层a4设置在靠近所述源极122和漏极123一侧，源极122和漏极123的第一缓冲层a1设置在靠近所述栅极121一侧。该第一铜层a2以第一功率沉积得到，即由沉积设备以第一功率运作时沉积该第一铜层a2。所述第二铜层以第二功率沉积得到，即由沉积设备以第二功率运作时沉积该第二铜层a3。且所述第一功率高于所述第二功率。
具体地，第一缓冲层a1、第一铜层a2、第二铜层a3及第二缓冲层a4中的至少一层采用如物理气相沉积(英文：PhysicalVaporDeposition，简称：PVD)等沉积方式生成。
其中，第一缓冲层a1和所述第二缓冲层a4均为金属层，可用于保护铜层并阻止铜层的铜离子扩散。具体，第一缓冲层a1和所述第二缓冲层a4可为钼膜、钛膜、或叠置的钼膜和钛膜。如在图3所示的另一实施方式中，该第一缓冲层a1包括叠置的钼膜a11和钛膜a12，第二缓冲层a4包括叠置的钼膜a41和钛膜a42。
本实施方式中，该第一功率优选但不限定位于50KW至70KW之间，所述第二功率优选但不限定位于20KW至40KW之间。所述第一缓冲层的厚度优选但不限定位于至之间，所述第一铜层的厚度优选但不限定位于至之间，所述第二铜层的厚度优选但不限定位于至之间，所述第二缓冲层的厚度优选但不限定位于至之间。在一应用实施例中，第一功率为52.5KW，所述第二功率为32.5KW。所述第一缓冲层的厚度为所述第一铜层的厚度为所述第二铜层的厚度为所述第二缓冲层的厚度为
可以理解的是，在其他实施方式中，TFT的栅极、源极、漏极未必均设置为上述结构。在其他实施方式中，还可根据实际应用情况，仅对TFT的栅极设置为上述结构，或者仅对TFT的源极和漏极设置为上述结构。
针对上述TFT的栅极、源极和漏极采用第一缓冲层和第二缓冲层将铜层夹置其中的结构，可达如下效果：
1)上述第一缓冲层、第二缓冲层可改善了对应铜层与基板或其他结构的附着性，且阻止其所在极的铜离子扩散，进而防止了I-V特性下降；
2)第二缓冲层对铜层起到保护作用，在蚀刻时，利用铜层与第二缓冲层的蚀刻选择比降低金属蚀刻下角(英文：Taper)，也避免GI搭线不良，进而减少静电防护(英文简称：ESD)风险，以保证良率；
3)对于边缘场开关(英文：FringeFieldSwitching，简称：FFS)或平面转换(英文：In-PlaneSwitching，简称：IPS)等液晶显示技术需要使用到的有机平坦层(英文简称：PFA)材料时，源极和漏极的第二缓冲层可防止其铜层与PFA搭配不良的问题。
针对上述TFT的栅极、源极和漏极采用制成功率不同的第一铜层和第二铜层作为导电层，进行如下分析：
高功率沉积的第一铜层可提高了铜层的制成速率，进而提高了TFT的生产效率。但第一铜层在成膜时会引起铜层表面局部的起伏度较大如图2、3所示，经试验其厚度的均匀性即U％一般为15％，难以形成理论上的绝对平整表面。由于缓冲层作为辅助层，其厚度相对铜层较小。以第一铜层厚度为为例，其第一铜膜厚区与薄区的差异往往超过而第二缓冲层一般不超过(铜酸蚀刻缓冲层速率较慢，因此缓冲层往往较薄)。显然，第二缓冲层往往不能有效地覆盖第一铜层表面，而导致第一铜层局部未覆盖有第二缓冲层。故在蚀刻过程中，未覆盖有第二缓冲层的第一铜层部分往往会受到酸液的择优攻击，使得光阻仍易与底层金属发生脱离。故在第一铜层之上继续沉积制成功率较低的第二铜层。低功率沉积可有效改善第二铜层的表面平整性，进而使得第二铜层上的第二缓冲层覆盖的更加均匀和完整。故本申请铜层先采用高功率制成一部分再由低功率制成剩余部分，即保证了铜层的制成效率及生产节拍(Tacttime)，也保证了铜层表面平整性，进一步防止光阻脱落问题。
可以理解的是，图2、3仅示意性表示出高功率铜层表面的实际常态，并不代表本申请每个TFT的第一铜层的表面均形成图2、3所示的起伏。而且值得注意的是该起伏非为本申请第一铜层的限定特征，本申请第一铜层理论上是要制成平整的，该起伏仅是由于第一铜层的高功率而产生的效果。
本申请还提供一种TFT的实施例，具体，该TFT的结构与上面实施方式中TFT的结构，故在此不作赘述。
请参阅图4和5，图4是本申请阵列基板的制成方法一实施方式的流程图，图5是图4所示的步骤410和/或420的子步骤流程图。所述方法包括：
410：在基板上形成薄膜晶体管的栅极。
420：在所述栅极上形成所述薄膜晶体管的源极和漏极。
其中，所述上述410中的所述形成栅极，和/或上述420中的所述形成源极和漏极可包括以下子步骤：
411：依序形成第一缓冲层、第一铜层、第二铜层和第二缓冲层，其中，以第一功率制成，所述第二铜层以第二功率制成，且所述第一功率高于所述第二功率。
该第一缓冲层、第一铜层、第二铜层及第二缓冲层中的至少一层采用如PVD等沉积方式生成。该第一缓冲层和所述第二缓冲层均为金属层，如为钼膜、钛膜、或叠置的钼膜和钛膜。
本实施方式中，该第一功率优选但不限定位于50KW至70KW之间，所述第二功率优选但不限定位于20KW至40KW之间。所述第一缓冲层的厚度优选但不限定位于至之间，所述第一铜层的厚度优选但不限定位于至之间，所述第二铜层的厚度优选但不限定位于至之间，所述第二缓冲层的厚度优选但不限定位于至之间。
412：在所述第二缓冲层上涂覆光阻，并进行蚀刻。其中，该蚀刻方式包括湿刻和干刻等方式。
在另一实施方式中，在上述410之后，所述制成方法还可包括：在栅极上形成栅绝缘层、沟道层，其中，所述栅绝缘层叠置在所述栅极和沟道层之间，且所述栅绝缘层可为AlN薄膜；上述420具体为在所述沟道层上形成源极和漏极。
在再一实施方式中，在上述420之后，所述制成方法还可包括：在沟道层上的源极和漏极形成刻蚀阻挡层，且刻蚀阻挡层设置源极和漏极之间；在源极和漏极上形成钝化层。
上述方案中，TFT的栅极、源极、漏极的至少一极采用第一缓冲层、第一铜层、第二铜层及第二缓冲层结构构成，其中第一铜层的制成功率比第二铜层的制成功率高。第二缓冲层对第二铜层起到保护作用，避免了直接蚀刻铜层而导致光阻脱落问题。而且，由于第二铜层的制成功率较低，保证了第二铜层的表面平整性，进而保证第二缓冲层对第二铜层覆盖的均匀性和平整性，进一步防止了光阻脱落问题，并且第一铜层的高制成功率也保证了TFT的生成效率。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

1.一种薄膜晶体管，其特征在于，包括栅极、源极和漏极，所述源极和漏极均设置在所述栅极的同一侧，其中，
所述栅极包括依序叠置的第一缓冲层、第一铜层、第二铜层及第二缓冲层，且所述第二缓冲层设置在靠近所述源极和漏极一侧；
和/或，所述源极和漏极均包括依序叠置的第一缓冲层、第一铜层、第二铜层及第二缓冲层，且所述第一缓冲层设置在靠近所述栅极一侧；
所述第一铜层以第一功率沉积得到，所述第二铜层以第二功率沉积得到，且所述第一功率高于所述第二功率。
2.根据权利要求1所述的薄膜晶体管，其特征在于，所述第一功率位于50KW至70KW之间，所述第二功率位于20KW至40KW之间。
3.根据权利要求1所述的薄膜晶体管，其特征在于，所述第一缓冲层的厚度位于至之间，所述第一铜层的厚度位于至之间，所述第二铜层的厚度位于至之间，所述第二缓冲层的厚度位于至之间。
4.根据权利要求1所述的薄膜晶体管，其特征在于，所述第一缓冲层和所述第二缓冲层为钼膜、钛膜、或叠置的钼膜和钛膜。
5.根据权利要求1所述的薄膜晶体管，其特征在于，所述第一缓冲层、第一铜层、第二铜层及第二缓冲层中的至少一层由物理气相沉积制成。
6.根据权利要求1所述的薄膜晶体管，其特征在于，还包括设置在所述栅极与所述源极和漏极之间的栅极绝缘层和沟道层。
7.一种阵列基板，其特征在于，包括基板和设置于基板上的多个薄膜晶体管，其中，所述薄膜晶体管为权利要求1至6任一项所述的薄膜晶体管。
8.一种阵列基板的制作方法，其特征在于，包括：
在基板上形成薄膜晶体管的栅极；
在所述栅极上形成所述薄膜晶体管的源极和漏极；
其中，所述形成栅极，和/或形成源极和漏极包括：
依序形成第一缓冲层、第一铜层、第二铜层和第二缓冲层，其中，以第一功率制成，所述第二铜层以第二功率制成，且所述第一功率高于所述第二功率；
在所述第二缓冲层上涂覆光阻，并进行蚀刻。
9.根据权利要求8所述的方法，其特征在于，所述第一缓冲层、第一铜层、第二铜层及第二缓冲层中的至少一层由物理气相沉积制成。
10.根据权利要求8或9所述的方法，其特征在于，所述第一功率位于50KW至70KW之间，所述第二功率位于20KW至40KW之间，所述第一缓冲层的厚度位于至之间，所述第一铜层的厚度位于至之间，所述第二铜层的厚度位于至之间，所述第二缓冲层的厚度位于至之间。
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