CN110098259A - 非晶硅薄膜晶体管及其制作方法 - Google Patents

非晶硅薄膜晶体管及其制作方法 Download PDF

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CN110098259A
CN110098259A CN201910283998.3A CN201910283998A CN110098259A CN 110098259 A CN110098259 A CN 110098259A CN 201910283998 A CN201910283998 A CN 201910283998A CN 110098259 A CN110098259 A CN 110098259A
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layer
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drain electrode
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李家鑫
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to PCT/CN2019/083675 priority patent/WO2020206723A1/zh
Priority to US16/496,441 priority patent/US11387370B2/en
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Abstract

一种非晶硅薄膜晶体管及其制作方法,其中所述非晶硅薄膜晶体管包括基板、栅极层、栅极绝缘层、有源层、源漏极层、N+掺杂层、绝缘保护层及钝化层。栅极层设置在所述基板上。栅极绝缘层设置在所述栅极层上。有源层设置在所述栅极绝缘层上。源漏极层设置在有源层上。N+掺杂层设置在所述有源层和所述源漏极层之间。绝缘保护层设置在所述源漏极层上,其中沟道开设在所述源漏极层之间并贯穿所述N+掺杂层和所述绝缘保护层。钝化层覆盖所述沟道和所述绝缘保护层上,其中所述绝缘保护层与所述源漏极层在所述沟道内齐平设置。借此,通过绝缘保护层保护源漏极层避免干刻时遭到刻蚀而损伤。

Description

非晶硅薄膜晶体管及其制作方法
技术领域
本发明涉及一种薄膜晶体管显示领域,尤指一种非晶硅薄膜晶体管及其制作方法。
背景技术
在a-Si(非晶硅)TFT器件的底部栅极结构中,沟道有源层的干刻步骤一般安排在去光阻之前(Channel Etch—Stripper),但近年来有发展先去光阻再进行沟道干刻的反向(reverse)工艺(Stripper—Channel Etch)。该工艺的优势是可以完全消除沟道内的N+掺杂层(N+tail),在同等设备工艺水平下,可以将器件宽度进一步缩小,以实现窄边框和高透过率。然而此工艺的瓶颈在于Stripper—Channel Etch工艺中,干刻沟道的有源层时,第二层电极金属(一般为铜或者铝)已经完全裸露在外,等离子体(电浆)在电场作用下会损伤其表面,如图1所示。图1所示的第二层电极金属通过等离子体的刻蚀后均已变色的情况。
发明内容
本发明的目的之一,在于提供一种非晶硅薄膜晶体管及其制作方法,通过绝缘保护层保护源漏极层避免干刻时遭到刻蚀而损伤。
为达到本发明前述目的,本发明提供一种非晶硅薄膜晶体管,包括基板、栅极层、栅极绝缘层、有源层、源漏极层、N+掺杂层、绝缘保护层及钝化层。栅极层设置在所述基板上。栅极绝缘层设置在所述栅极层上。有源层设置在所述栅极绝缘层上。源漏极层设置在有源层上。N+掺杂层设置在所述有源层和所述源漏极层之间。绝缘保护层设置在所述源漏极层上,其中沟道开设在所述源漏极层之间并贯穿所述N+掺杂层和所述绝缘保护层。钝化层覆盖所述沟道和所述绝缘保护层上,其中所述绝缘保护层与所述源漏极层在所述沟道内齐平设置。
在本发明的一实施例中,还包括开设在所述钝化层的穿孔和设置在所述栅极绝缘层上的像素电极层,所述像素电极层通过所述穿孔电性连接所述源漏极层。
在本发明的一实施例中,所述绝缘保护层通过铜酸刻蚀,使所述绝缘保护层与所述源漏极层在所述沟道内齐平设置。
在本发明的一实施例中,所述绝缘保护层为氮化硅(SiNx),且所述绝缘保护层的厚度介于500埃至1000埃之间。
再者,本发明还提供一种非晶硅薄膜晶体管的制作方法,包括以下步骤:
S10、提供基板,在所述基板上形成栅极层;
S20、在所述栅极层上形成栅极绝缘层;
S30、在所述栅极绝缘层上形成有源层;
S40、在所述有源层上形成源漏极层,其中所述源漏极层由含铜或铝金属制成;
S50、在所述有源层和所述源漏极层之间形成N+掺杂层;
S60、在所述源漏极层上形成绝缘保护层,其中沟道还形成在所述源漏极层之间并贯穿所述N+掺杂层和所述绝缘保护层;及
S70、在所述沟道和所述绝缘保护层上涂布钝化层,其中所述绝缘保护层与所述源漏极层在所述沟道内齐平设置。
在本发明的一实施例中,在步骤S60中,在尚未形成所述沟道前,在所述源漏极层上涂布光阻,通过含有添加剂的铜酸蚀刻所述绝缘保护层和所述源漏极层,以形成所述沟道。
在本发明的一实施例中,在步骤S60后,将去除光阻的所述非晶硅薄膜晶体管进入干刻机干蚀刻,通过等离子气体刻蚀所述绝缘保护层和所述N+掺杂层,使所述绝缘保护层和所述N+掺杂层齐平设置。
在本发明的一实施例中,所述添加剂为氟离子。
在本发明的一实施例中,所述等离子气体包括加入三氟化氮(NF3)及氦气(He),以刻蚀所述绝缘保护层至所述绝缘保护层厚度介于500埃至1000埃之间。
在本发明的一实施例中,还包括以下步骤:
S80、在所述钝化层形成穿孔;及
S90、形成在所述栅极绝缘层上的像素电极层,所述像素电极层通过所述穿孔电性连接所述源漏极层。
本发明还具有以下功效,本发明避免干刻工艺中,使用等离子气体损伤源漏极层表面,从而使器件性能一致性、工艺简单、稳定性好,可见光透过率高,且不影响后续制程。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单介绍,显而易见地,下面描述中的附图仅仅是发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是现有技术非晶硅薄膜晶体管的平面示意程图;
图2是本发明非晶硅薄膜晶体管的平面示意图;
图3是本发明非晶硅薄膜晶体管的横截面图;
图4A至图4D是本发明非晶硅薄膜晶体管的制作方法的步骤横截面图;及
图5是本发明非晶硅薄膜晶体管的制作方法的方块流程图。
具体实施方式
在具体实施方式中提及“实施例”意指结合实施例描述的特定特征、结构或特性可以包含在本发明的至少一个实施例中。在说明书中的不同位置出现的相同用语并非必然被限制为相同的实施方式,而应当理解为与其它实施例互为独立的或备选的实施方式。在本发明提供的实施例所公开的技术方案启示下,本领域的普通技术人员应理解本发明所描述的实施例可具有其他符合本发明构思的技术方案结合或变化。
请参照图2及图3所示,图2为本发明非晶硅薄膜晶体管的平面示意图;图3为本发明非晶硅薄膜晶体管的横截面图。如图2及图3所示,本发明提供一种非晶硅薄膜晶体管1(a-Si TFT),包括基板11、栅极层12、栅极绝缘层13、有源层14、源漏极层16、N+掺杂层15、绝缘保护层17及钝化层18。多个非晶硅薄膜晶体管1阵列排列构成显示基板(未标示),如图2所示。栅极层12形成显示基板的扫描线,源漏极层形成显示基板的信号线。
基板11采用刚性材料或柔性材料,其中刚性材料采用刚性玻璃和硅片中的一种;柔性材料则采用聚萘二甲酸乙二醇酯、聚对苯二甲酸乙二醇酯、聚酰亚胺中和柔性玻璃的一种。栅极层12设置在所述基板11上。有源层14设置在所述栅极绝缘层13上。栅极绝缘层13设置在所述栅极层12上。所述栅极绝缘层13采用氧化硅、氮化硅、氧化铝、氧化铪、氧化钽、氧化锆和有机介质中的一种或多种构成,且所述栅极绝缘层13的厚度范围介于5奈米(nm)~400奈米。源漏极层15设置在有源层14上,其中所述源漏极层由含铜或铝金属制成。
N+掺杂层15设置在所述有源层14和所述源漏极层16之间,其中通过用高浓度的n型杂质掺杂的半导体而形成在所述有源层14上。绝缘保护层17设置在所述源漏极层16上,其中沟道181开设在所述源漏极层16之间并贯穿所述N+掺杂层15和所述绝缘保护层17。钝化层18覆盖所述沟道181和所述绝缘保护层17上,其中所述绝缘保护层17与所述源漏极层16在所述沟道181内齐平设置。在如图2及图3所示的实施例中,还包括开设在所述钝化层18的穿孔182和设置在所述栅极绝缘层13上的像素电极层19,所述像素电极层19通过所述穿孔182电性连接所述源漏极层16。
所述绝缘保护层17通过铜酸刻蚀,使所述绝缘保护层17与所述源漏极层16在所述沟道181内齐平设置。也就是说,通过绝缘保护层17保护源漏极层16避免进入干刻机台干刻时遭到刻蚀而损伤,达到更好的器件性能一致性、工艺简单、稳定性佳、可见光透过率高等优点,且不影响后续制程。所述绝缘保护层17为氮化硅(SiNx),且所述绝缘保护层17的厚度介于500埃至1000埃之间,其中米=0.1奈米。
请一并参照图4A-4D及图5所示,本发明还提供一种非晶硅薄膜晶体管1的制作方法,包括以下步骤:S10、提供基板11,在所述基板11上形成栅极层12;S20、在所述栅极层12上形成栅极绝缘层13;S30、在所述栅极绝缘层13上形成有源层14;S40、在所述有源层14上形成源漏极层16,其中所述源漏极层16由含铜或铝金属制成;S50、在所述有源层14和所述源漏极层16之间形成N+掺杂层15;S60、在所述源漏极层16上形成绝缘保护层17,其中沟道181还形成在所述源漏极层16之间并贯穿所述N+掺杂层15和所述绝缘保护层17;及S70、在所述沟道181和所述绝缘保护层17上涂布钝化层18,其中所述绝缘保护层17与所述源漏极层16在所述沟道181内齐平设置。
具体而言,如图4A所示,在步骤S60中,在尚未形成所述沟道181前,在所述源漏极层16上涂布光阻2,通过含有添加剂的铜酸蚀刻所述绝缘保护层17和所述源漏极层16,以形成所述沟道181。如图4B及图4C所示,在步骤S60后,将去除光阻2的所述非晶硅薄膜晶体管1进入干刻机干蚀刻,通过等离子气体3刻蚀所述绝缘保护层17和所述N+掺杂层15,使所述绝缘保护层17和所述N+掺杂层15齐平设置,如图4D所示。
也就是说,如图4A所示的结构,通过4道光刻(4-Mask)工艺进行两次湿刻和1次干刻去除像素区域的所述有源层14(a-Si)。当完成剥膜去光阻2前,仅需要保留源漏极层16上的绝缘保护层17。如图4B及图4C所示,接下来进行去光阻2工艺,再进入干刻机台进行干刻,通过干刻时间和制程条件将大部分或全部的绝缘保护层17去除,以形成图4D所示的结构。
在此所指的绝缘保护层17可采用氮化硅(SiNx),通过例如含有添加剂的铜酸刻蚀氮化硅(SiNx),其中添加剂可为氟离子(F);也就是说,在铜酸中提高F离子的含量即可蚀刻氮化硅。所述等离子气体包括加入三氟化氮(NF3)及氦气(He),以刻蚀所述绝缘保护层至所述绝缘保护层厚度介于500埃至1000埃之间。具体而言,所述干蚀刻的制程条件约为以三氟化氮(NF3)1000ppm加入氦气(He)1500ppm及压力30mta,干刻蚀速度约20A/每秒,可视实际厚度改变蚀刻时间。
本发明的制作方法还包括以下步骤:S80、在所述钝化层18形成穿孔182;及S90、形成在所述栅极绝缘层13上的像素电极层19,所述像素电极层19通过所述穿孔182电性连接所述源漏极层16。因此,本发明通过绝缘保护层17保护源漏极层16避免进入干刻机台干刻时遭到刻蚀而损伤,从而达到更好的器件性能一致性、工艺简单、稳定性佳、可见光透过率高等优点,且不影响后续制程。
综上所述,虽然本发明结合其具体实施例而被描述,应该理解的是,许多替代、修改及变化对于那些本领域的技术人员将是显而易见的。因此,其意在包含落入所附权利要求书的范围内的所有替代、修改及变化。

Claims (10)

1.一种非晶硅薄膜晶体管,包括:
基板;
栅极层,设置在所述基板上;
栅极绝缘层,设置在所述栅极层上;
有源层,设置在所述栅极绝缘层上;
源漏极层,设置在有源层上;
N+掺杂层,设置在所述有源层和所述源漏极层之间;
绝缘保护层,设置在所述源漏极层上,其中沟道开设在所述源漏极层之间并贯穿所述N+掺杂层和所述绝缘保护层;及
钝化层,覆盖所述沟道和所述绝缘保护层上,其中所述绝缘保护层与所述源漏极层在所述沟道内齐平设置。
2.如权利要求1所述非晶硅薄膜晶体管,其特征在于,还包括开设在所述钝化层的穿孔和设置在所述栅极绝缘层上的像素电极层,所述像素电极层通过所述穿孔电性连接所述源漏极层。
3.如权利要求1所述非晶硅薄膜晶体管,其特征在于,所述绝缘保护层通过铜酸刻蚀,使所述绝缘保护层与所述源漏极层在所述沟道内齐平设置。
4.如权利要求1所述非晶硅薄膜晶体管,其特征在于,所述绝缘保护层为氮化硅(SiNx),且所述绝缘保护层的厚度介于500埃至1000埃之间。
5.一种非晶硅薄膜晶体管的制作方法,包括以下步骤:
S10、提供基板,在所述基板上形成栅极层;
S20、在所述栅极层上形成栅极绝缘层;
S30、在所述栅极绝缘层上形成有源层;
S40、在所述有源层上形成源漏极层,其中所述源漏极层由含铜或铝金属制成;
S50、在所述有源层和所述源漏极层之间形成N+掺杂层;
S60、在所述源漏极层上形成绝缘保护层,其中沟道还形成在所述源漏极层之间并贯穿所述N+掺杂层和所述绝缘保护层;及
S70、在所述沟道和所述绝缘保护层上涂布钝化层,其中所述绝缘保护层与所述源漏极层在所述沟道内齐平设置。
6.如权利要求5所述非晶硅薄膜晶体管的制作方法,其特征在于,在步骤S60中,在尚未形成所述沟道前,在所述源漏极层上涂布光阻,通过含有添加剂的铜酸蚀刻所述绝缘保护层和所述源漏极层,以形成所述沟道。
7.如权利要求5所述非晶硅薄膜晶体管的制作方法,其特征在于,在步骤S60后,将去除光阻的所述非晶硅薄膜晶体管进入干刻机干蚀刻,通过等离子气体刻蚀所述绝缘保护层和所述N+掺杂层,使所述绝缘保护层和所述N+掺杂层齐平设置。
8.如权利要求6所述非晶硅薄膜晶体管的制作方法,其特征在于,所述添加剂为氟离子。
9.如权利要求7所述非晶硅薄膜晶体管的制作方法,其特征在于,所述等离子气体包括加入三氟化氮(NF3)及氦气(He),以刻蚀所述绝缘保护层至所述绝缘保护层厚度介于500埃至1000埃之间。
10.如权利要求5所述非晶硅薄膜晶体管的制作方法,其特征在于,还包括以下步骤:
S80、在所述钝化层形成穿孔;及
S90、形成在所述栅极绝缘层上的像素电极层,所述像素电极层通过所述穿孔电性连接所述源漏极层。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113658869A (zh) * 2021-08-16 2021-11-16 成都京东方光电科技有限公司 薄膜晶体管及其制作方法、显示器件

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101009251A (zh) * 2006-01-24 2007-08-01 三星电子株式会社 薄膜晶体管基板及其制造方法,以及具有其的液晶显示器
CN101526707A (zh) * 2008-03-07 2009-09-09 北京京东方光电科技有限公司 Tft-lcd阵列基板结构及其制造方法
CN102157387A (zh) * 2010-11-19 2011-08-17 友达光电股份有限公司 薄膜晶体管及其制造方法
US20120315731A1 (en) * 2004-10-26 2012-12-13 Samsung Electronics Co., Ltd. Thin film transistor array panel and manufacturing method thereof
US20130032794A1 (en) * 2011-08-04 2013-02-07 Samsung Electronics Co., Ltd. Thin film transistor and thin film transistor array panel
CN105185840A (zh) * 2015-10-28 2015-12-23 深圳市华星光电技术有限公司 一种薄膜晶体管、阵列基板及其制成方法
CN106601596A (zh) * 2016-12-30 2017-04-26 惠科股份有限公司 一种导线制程阵列蚀刻方法
CN107275343A (zh) * 2017-06-15 2017-10-20 深圳市华星光电技术有限公司 底栅型tft基板的制作方法
CN107369715A (zh) * 2017-07-13 2017-11-21 南京中电熊猫平板显示科技有限公司 一种薄膜晶体管的制造方法
CN108417579A (zh) * 2018-01-19 2018-08-17 南京中电熊猫液晶显示科技有限公司 一种显示基板及其制造方法
CN108550625A (zh) * 2018-04-18 2018-09-18 深圳市华星光电技术有限公司 一种薄膜晶体管及其制作方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100776514B1 (ko) * 2000-12-30 2007-11-16 엘지.필립스 엘시디 주식회사 액정표시장치 및 그 제조방법
CN101325181B (zh) * 2008-08-05 2010-06-09 友达光电股份有限公司 薄膜晶体管阵列基板及其制作方法
JP6227396B2 (ja) * 2013-12-20 2017-11-08 株式会社ジャパンディスプレイ 薄膜トランジスタ及びそれを用いた表示装置
CN104681626A (zh) * 2015-03-03 2015-06-03 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制作方法、阵列基板
CN106847926B (zh) * 2017-01-19 2019-12-06 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、阵列基板及显示装置

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120315731A1 (en) * 2004-10-26 2012-12-13 Samsung Electronics Co., Ltd. Thin film transistor array panel and manufacturing method thereof
CN101009251A (zh) * 2006-01-24 2007-08-01 三星电子株式会社 薄膜晶体管基板及其制造方法,以及具有其的液晶显示器
CN101526707A (zh) * 2008-03-07 2009-09-09 北京京东方光电科技有限公司 Tft-lcd阵列基板结构及其制造方法
CN102157387A (zh) * 2010-11-19 2011-08-17 友达光电股份有限公司 薄膜晶体管及其制造方法
US20130032794A1 (en) * 2011-08-04 2013-02-07 Samsung Electronics Co., Ltd. Thin film transistor and thin film transistor array panel
CN105185840A (zh) * 2015-10-28 2015-12-23 深圳市华星光电技术有限公司 一种薄膜晶体管、阵列基板及其制成方法
CN106601596A (zh) * 2016-12-30 2017-04-26 惠科股份有限公司 一种导线制程阵列蚀刻方法
CN107275343A (zh) * 2017-06-15 2017-10-20 深圳市华星光电技术有限公司 底栅型tft基板的制作方法
CN107369715A (zh) * 2017-07-13 2017-11-21 南京中电熊猫平板显示科技有限公司 一种薄膜晶体管的制造方法
CN108417579A (zh) * 2018-01-19 2018-08-17 南京中电熊猫液晶显示科技有限公司 一种显示基板及其制造方法
CN108550625A (zh) * 2018-04-18 2018-09-18 深圳市华星光电技术有限公司 一种薄膜晶体管及其制作方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113658869A (zh) * 2021-08-16 2021-11-16 成都京东方光电科技有限公司 薄膜晶体管及其制作方法、显示器件

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