CN102576692B - 具有背侧体区连接的绝缘体上半导体 - Google Patents

具有背侧体区连接的绝缘体上半导体 Download PDF

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Publication number
CN102576692B
CN102576692B CN201080031814.1A CN201080031814A CN102576692B CN 102576692 B CN102576692 B CN 102576692B CN 201080031814 A CN201080031814 A CN 201080031814A CN 102576692 B CN102576692 B CN 102576692B
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tagma
contact
active device
conductive layer
semiconductor
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CN201080031814.1A
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CN102576692A (zh
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M.A.斯图伯
S.B.莫林
P.A.尼加德
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Qualcomm Inc
Qualcomm Switch Corp
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IO Semiconductor Inc
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Priority claimed from PCT/US2010/042028 external-priority patent/WO2011008895A1/en
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    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
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Abstract

本发明实施例实现了从绝缘体上半导体(SOI)结构去除过剩载流子。在一个实施例中，公开了一种制造集成电路的方法。在一个步骤中，在绝缘体上半导体晶圆的有源层中形成有源器件。在另一个步骤中，从沉积在所述SOI晶圆的背侧上的基板层区域基板材料。在另一个步骤中，从所述绝缘体上半导体晶圆的背侧去除绝缘材料以形成挖掉的绝缘区域。导电层沉积在所述挖掉的绝缘区域上。沉积导电层使所述导电层与所述挖掉的绝缘区域的第一部分中的有源器件的体区物理接触。随后导电层将所述体区耦接至一个接触，所述接触处于所述挖掉的绝缘区域的第二隔开的部分中。

Description

具有背侧体区连接的绝缘体上半导体
相关申请的交叉引用
本申请要求2009年7月15日提交的美国临时专利No.61/225,914的权益。通过引用将美国临时专利No.61/225,914并入本文。
技术领域
所描述的本发明总体上涉及绝缘体上半导体器件及处理，更具体地涉及绝缘体上半导体器件中的浮体效应(floating-body effect)。
背景技术
绝缘体上半导体(SOI)技术最早在20世纪90年代后期被商业化。SOI技术的特色特征在于其中形成了电路的半导体区域通过电绝缘层与主体基板隔开。该绝缘层通常是二氧化硅。选择二氧化硅的原因是，可以通过使晶圆氧化而在硅晶圆上形成二氧化硅，由此适合于进行有效制造。SOI技术的有利方面直接源于绝缘层将有源层与主体基板进行电子隔离的能力。当在此处以及所附权利要求中使用时，SOI结构上的形成有信号处理电路的区域指的是SOI结构的有源层。
SOI技术由于引入对SOI结构中的有源器件进行隔离(这改进了有源器件的电特性)的绝缘层而表现出对传统主体基板技术的改进。例如，希望晶体管的阈值电压统一，并且大体上由晶体管栅极下的半导体材料的特性设定晶体管的阈值。如果该材料区域是隔离的，则进一步的处理将影响该区域并改变器件阈值电压的可能性很小。由于SOI结构的使用而得到的其它电特性改进包括：更小的短沟道效益、针对更高速度的降低的电容、以及器件作为开关时的更低的插入损耗。此外，绝缘层可用来对有源器件与有害辐射进行屏蔽。这对于用于地球大气之外的有害离子辐射盛行的空间中的集成电路是特别重要的。
图1示出了一个SOI晶圆100。晶圆包括基板层101、绝缘层102以及有源层103。基板通常是诸如硅之类的半导体材料。绝缘层102是介电的，并且通常是通过对基板层101进行氧化而形成的二氧化硅。有源层103包括在已经在其中形成了电路104之后出现的掺杂物、电介质、多晶硅、金属层、钝化物以及其它层的组合。电路104可包括：金属布线，诸如电阻器、电容器和电感器之类的无源器件，以及诸如晶体管之类的有源器件。当在此处以及所附权利要求中使用时，SOI晶圆100的“顶部”指的是顶部表面105，而SOI晶圆100的“底部”指的是底部表面106。定位方案不考虑SOI晶圆100相对于其它参考系的相对定位、以及从SOI晶圆100去除层或向SOI晶圆100添加层。因此，有源层103总是处于绝缘层102“上方”。此外，从有源层103中央起始并向底部表面106延伸的矢量总是指向SOI结构的“背侧”方向，而不考虑SOI晶圆100相对于其它参考系的相对定位、、以及从SOI晶圆100去除层或向SOI晶圆100添加层。
半导体器件可能承受被称为浮体效应的现象。绝缘体上半导体尤其容易受这一效应影响。出于示例的目的，将描述其中浮体效应通过N型场效应晶体管(NFET)呈现的情况，但是许多其它有源器件也可呈现浮体效应。图1B显示了NFET 108的侧视图。NFET 108是SOI器件，因此布置在绝缘层102上。由于体区109中的过剩载流子的存在而引起浮体效应。通过经由热或光的方式随机产生电子空穴对、通过高速电子在沟道110中的散射、通过源极111或漏极112的泄漏、通过能带至能带的隧穿、或通过沟道110中的雪崩击穿，可在体区109中建立载流子。因此，在所有半导体器件中过剩载流子的存在都是无法避免的。但是，与体区是主体基板的一部分的器件相比，在SOI器件中，体区109被隔离及限制。因此，需要远远更少的过剩载流子来改变有源器件的特性。
浮体效应对有源器件的特性造成的由于SOI结构而恶化的两个变化是扭曲效应(kink effect)以及断开状态下的有源器件所呈现的非线性电容。由于源极111和漏极112上施加的高电势所引起的雪崩击穿而在体区109中引入过剩载流子将具有显著地增大流经沟道110的电流的效应。该效应被称为扭曲效应，原因在于沟道电流相对漏源电势的曲线的相对平坦的部分将在该效应发生的点处具有向上的扭曲。曲线的相对平坦部分位于电流——对于一些应用而言——期望由栅极113处的电压所主导性地设定的区域中。该效应可能会造成问题，原因是某些模拟电路应用依赖于在该区域中工作时独立于漏-源电势的有源器件的电流。
与扭曲效应相反，器件断开状态电容的非线性不是由雪崩击穿引起的。实际上，载流子通过上述其它不太激进的方式建立。如果体区109的电势转移至明显足够的程度，则漏极112处的信号看到的电容将以非线性的方式改变。所述改变将是非线性的，这是因为过剩载流子将随时间而在体区109中建立，从而使电容成为随时间变化的。而且，电荷建立将使体区109与漏极112之间的结的电容取决于漏极112处的信号，这也是非线性系统的特点。由于某些电路设计依赖于它们所处理的信号的高度线性特征的保持，所以这一效应会造成问题。例如，如果NFET 108被用作射频(RF)应用中的开关(其中，当在连接至漏极112的线路上传输信号时NFET108很难处于断开状态)，从漏极112到体区109的电容将必须是线性的，以便防止在信号中产生不期望的谐波失真以及互调失真。
SOI器件中的浮体效应的通用解决方案包括引入从体区109到源极111的连接。该解决方案是包括使用所谓的“体区联系(body tie)”或“体区接触(body contact)”在内的通用方案系列的子集。体区接触提供了对体区109的连接，这用来去除过剩载流子。将体区109连接至源极111的具体方案由于很简单而被最经常地使用。体区109中建立的不期望电荷将能够从体区109中逃至源极111，因此不会造成扭曲效应或导致产生非线性电容。
SOI器件中的浮体效应的另一解决方案包括使用智能体区联系。智能体区联系是根据向其提供了联系的器件的状态来改变其状态的体区联系。可参考图1C来描述智能体区联系的示例。图1C包括NFET 114。NFET 114的源极接地115。NFET 114的漏极连接至漏极接触116。NFET114的栅极连接至栅极接触117和二极管118的阴极。NFET114的栅极连接至二极管118的阳极。类似的结构可通过利用PFET代替NFET 114并反转二极管118的极性来发挥功效。该结构在某些情况下具有优势，这是因为二极管118所形成的体区联系在器件断开时相对于器件导通时将更多地传导。这对于前面描述的其中FET的非线性断开状态电容将在漏极接触116上的处理信号中渗入失真的情况非常有用。当栅极接触117为低并且器件断开时，电流将从NFET 114的体区通过二极管118流向栅极接触117。但是，当栅极接触117为高时，从体区到栅极的路径将有效地切断。考虑到下述原因这是非常有利的：扭曲效应在器件导通状态电流期间提供了更高电流，从这个角度来说扭曲效应提供了优点。因此，该结构能够消除一个应用中浮体效应的缺点，同时提供浮体效应的优点。
虽然这些方案具有能够从有源器件的体区去除过剩电荷的有利方面，但是由于它们通常需要与有源层接触的另一处理层，所以有些时候会出现问题。该附加的处理可使制造工艺变复杂，并通常由于制造误差而导致制造出的有源器件不理想。而且，这些方案要求有源晶圆上的附加区域，这增大了整个设计的成本。这些方案还存在沿从体区联系到沟道最远部分的宽度上的高阻的缺点。高阻会在降低浮体效应的过程中降低体区联系的效力。最后，这些方案可能对器件节点引入寄生电容，这将限制采用这种器件的所有电路的速度。
发明内容
在本发明的一个实施例中，公开了一种绝缘体上半导体结构。该SOI结构包括导电层。该SOI结构还包括绝缘层，其位于所述导电层上方，并且与挖掉的绝缘区域中的所述导电层部分地共同垂直延伸。该SOI结构还包括有源层，其位于所述绝缘层上方，并且包括具有体区的有源器件。该SOI结构还包括体区接触，其对所述导电层和所述体区进行物理连接，并且位于所述挖掉的绝缘区域的第一部分中。所述导电层将所述体区接触耦接至所述有源层中的接触。此外，所述接触位于所述挖掉的绝缘区域的第二部分中。并且，所述第二部分与所述第一部分是隔开的。
在本发明的另一个实施例中，公开了一种制造集成电路的方法。在一个步骤中，在绝缘体上半导体晶圆的有源层中形成有源器件。在另一个步骤中，从沉积在所述绝缘体上半导体晶圆的背侧上的基板层区域基板材料。在另一个步骤中，从所述绝缘体上半导体晶圆的背侧去除绝缘材料以形成挖掉的绝缘区域。在另一个步骤中，在所述挖掉的绝缘区域上沉积导电层。沉积导电层使所述导电层与所述挖掉的绝缘区域的第一部分中的有源器件的体区物理接触。随后，导电层将所述体区耦接至一个接触，所述接触位于所述挖掉的绝缘区域的第二隔开的部分中。
在本发明的另一个实施例中，公开了一种从绝缘体上半导体有源器件的沟道去除不期望的累积的多数载流子的方法。在第一步骤中，将所述不期望的累积的多数载流子从所述沟道引导至所述有源器件的体区接触。所述体区接触对导电层和所述有源器件的体区进行物理连接。在第二步骤中，通过所述导电层中的电路分支引导所述不期望的累积的多数载流子。所述导电层位于绝缘层下方，并且与挖掉的绝缘区域中的所述绝缘层部分地共同垂直延伸。所述电路分支将所述体区接触耦接至接触。体区接触位于所述挖掉的绝缘区域的第一部分中，所述接触位于所述挖掉的绝缘区域的第二隔开的部分中。
附图说明
图1A和图1B图示了根据现有技术的容易受浮体效应影响的SOI器件的框图。
图1C图示了根据现有技术的具有智能体区接触的NFET的框图。
图2图示了根据本发明的具有背侧体区接触的SOI结构的框图。
图3图示了根据本发明的具有通过pn结耦接至栅极的背侧体区接触的SOI结构的框图。
图4图示了根据本发明的具有通过热载流子结二极管(hot-carrier-junction diode)耦接至栅极的背侧体区接触的SOI结构的框图。
图5图示了根据本发明的具有大多晶硅接触焊盘的SOI结构的背侧的框图。
图6图示了根据本发明的制造具有背侧体区接触的集成电路的方法的流程图。
具体实施方式
现在详细参考所公开的发明的实施例，附图中图示了这些实施例的一个或多个示例。以解释本发明技术的方式提供各个示例，各个示例不用于限制本发明技术。实际上，对于本领域技术人员而言明显的是，可在不脱离本发明精神和范围的情况下对本发明技术做出修改和变化。例如，作为一个实施例的一部分而图示及描述的特征可与另一实施例一起使用，从而得到又一个其它实施例。因此，本发明主题覆盖所附权利要求及其等价形式的范围内的这些修改和变化。
本发明的实施例提供了具有省空间的有效的背侧体区接触的SOI器件的产品。本发明的实施例通过利用背侧处理、去除SOI掩埋绝缘层的部分、以及沉积将有源器件的体区接触连接至与有源器件自身位于同一有源层中的第二接触的导电材料实现了该结果。
图2显示了根据本发明的SOI结构200。对于现有技术的SOI器件，有源层103在绝缘层102上方。导电层201在绝缘层102下方，并沉积在绝缘层102的背侧，从而填充了挖掉的绝缘区域202。从附图可以看出，绝缘层102与挖掉的绝缘区域202中的导电层201至少部分地共同垂直延伸。当在此处以及所附权利要求中使用时，术语“区域”并非旨在限制成单个连续区域的解释。因此，挖掉的绝缘区域202允许有源器件203的体区109与体区接触204处的导电层201之间的、以及所述导电层201与第二接触205处的所述有源层103之间的分离的物理接触。有源层103接合至操纵晶圆(handle wafer)206以便在有源层103被处理的时候为有源层103提供支撑。但是，可在处理的后续时间去除操纵晶圆206。此外，可通过其它手段来提供处理期间的稳定性，从而完全没有必要附接操纵晶圆206。
前一段中参考图2描述的本发明的实施例用于从体区109去除过剩载流子以便为有源器件203缓解浮体效应。体区109中建立的过剩载流子能够通过导电层201流出以及回到有源层103。操纵晶圆206允许从背侧处理SOI结构，这就能够很容易地接近有源器件203的体区。优选地，有源器件203可形成在不受对体区联系电路的需要的限制的有源层103中。这样，体区联系电路更不可能不利地影响制成的有源器件或妨碍开发有源器件的布局的设计人员的灵活性。而且，由于器件体区附近仅仅需要小的接触，所以可能会显著地削弱由于具有靠近的体区联系电路而产生的任何寄生电容。
可参考图2来描述本发明的具体实施例。在图2中，电路分支包括：体区接触204和与有源器件203的两个源极111相连的第二接触205、以及有源器件203的体区109。在本发明的具体实施例中，图2所示的结构允许过剩载流子流入源极111并随后沿着源极电极离开有源器件203。考虑到NFET的源极总体上处于低于体区109的电势从而p型载流子将通过该电路分支流出，这是一个方便的结构。此外，p型场效应晶体管(PFET)的源极将总体上处于高于体区109的电势，从而n型载流子将通过该电路分支流出。本发明的另一具体实施例包括包含体区接触204和第二接触205的分支。但是，与图2所示的结构相反，包含体区接触204和第二接触205的该电路分支将栅极113连接至体区109。所得到的器件通常被称为动态阈值FET(DTFET或DTMOS)。通过为载流子提供离开体区205的路径(因为载流子被吸引至栅极210的信号源)，该结构将发挥功能。当晶体管在断开(OFF)状态下偏置时，DTMOS器件提供较高的阈值电压，当晶体管处于导通(ON)状态时，DTMOS器件提供较低的阈值电压。这有利地提供了断开时的低泄漏以及变成导通时的高驱动强度。
上面参照图2讨论的背侧处理概念可应用至智能体区接触的形成，以便形成根据本发明的结构。在本发明的具体实施例中，包含体区接触204和第二接触205的可变阻抗电路分支被配置成当有源器件203处于导通状态时具有高阻抗，在有源器件203不处于导通状态时具有低阻抗。虽然下文会参考NFET器件描述这些实施例，但是通过利用PFET器件来代替所描述的NFET并同时将所有所附的二极管配置成具有相反的极性，可以获得同样的结果。
可参考图3来描述根据本发明的SOI结构300。在图3中，栅极113通过包括阳极302和阴极301的二极管电耦接至导电层201。在本发明的具体实施例中，阳极302包括有源层103的已经利用与体区109相同的掺杂分布曲线更重地掺杂的区域。在本发明的具体实施例中，例如采用薄膜硅工艺的实施例，阳极302和阴极301在有源层103并肩排布，而不是垂直层叠。包括该阳极的电路分支具有基于栅极113和体区109的相对电压的可变阻抗。在栅极113的电势下降的情况下，该可变阻抗电路分支的阻抗将下降至接近0，从而在栅极为低时将体区109锁定至栅极113。
前一段中参考图3描述的本发明的实施例用于在有源器件203用于特定应用时从浮体效应的缺点中过滤出浮体效应的优点。以上参考现有技术的智能体区接触描述这些优势已经。如之前参考图2所述，可以实现这些优点而不必干扰或改变有源器件203的布局。因此，有源器件203的设计可改变来适应与有关浮体效应的方面去耦合的其他方面。此外，在本发明的具体实施例中，可变阻抗电路分支在其低阻抗状态下的阻抗可实际上高于在一些现有技术的体区接触中并保持效力。在利用智能体区接触来防止通过断开状态RF开关上的信号的谐波失真的本发明实施例中，必须从体区去除的载流子是通过比通过雪崩击穿和碰撞电离所产生的载流子远远更慢的工艺产生的载流子。相关工艺慢几个数量级，因此甚至可以通过高阻路径来去除所产生的电荷。因此，针对采用SOI结构300的器件的总体尺寸和成本的等量最小影响，包括处于有源层中的可变阻抗路径的电路可保持最小尺寸。
可再次参考图3来描述根据本发明的具体实施例。在图3中，体区接触204是欧姆的，并且存在从体区接触204到第二接触205的可忽略电阻。而且，第二接触205直接位于包括阴极301和阳极302的二极管下面。由于有源器件203是NFET，所以栅极在其导通状态下将走高。因此，阳极302处于比阴极301低的电势，并且二极管反向偏置。这将防止载流子离开体区109，这使得作为有源器件203的NFET支持更高的电流并防止体区到源极二极管的正向偏置，这将导致高电流流入期望路径。如果有源器件203是PFET，那么栅极将在其导通状态期间走低。因此，阴极301和阳极302需要在图3中交换。如果采用了该结构，则二极管将在PFET处于其导通状态时反向偏置，并且器件206将在其导通状态下支持更高的驱动电流，并防止体区至源极二极管的正向偏置。为了避免高电流流入不期望的路径，防止该二极管的正向偏置是很重要的。
在本发明的具体实施例中，利用替换结构为体区109提供与参考图3描述的方案相同的偏置方案。例如，可通过导电层201为体区109提供独立的电压偏置源。该电压偏置源可提供取决于栅极113上的电压的可变电压，从而提供与参照图3描述相同的效果。作为另一个示例，可耦接接入FET作为可变阻抗路径的一部分，以起到与图3中的二极管所提供的功能类似的功能，即FET在晶体管不处于导通状态时提供从体区到栅极的低阻抗路径，并且在晶体管处于导通状态时提供从体区到栅极的高阻抗路径。在本发明的具体实施例中，根据图3所示的概念，提供各种其它电路和结构来去除来自体区109的电荷。
可参考图4来描述根据本发明的SOI结构400。图4类似于图2，不同之处在于从上升进入有源层103的第二接触205开始的电路分支是可变阻抗路径401。在本发明的具体实施例中，体区接触204是提供可变阻抗路径401的可变方面的热载流子二极管。在有源器件203是NFET的情况下，热载流子二极管可在栅极113上的电势为高时反向偏置，并且在栅极113上的电势为低时正向偏置。因此，这些实施例将呈现与前面参考智能体区接触所描述的一样的特征。有利地，该结构不要求在有源层201中建立任何有源器件。因此，考虑到可仅仅利用通过有源层103的单个金属线路来实现可变阻抗路径401，这将节省空间。
在本发明的具体实施例中，用于形成导电层201的金属还被用于其它目的。例如，金属可用作组装金属来提供对有源层的接触。这种接触可用来向有源层中提供功率信号。接触还可用来将信号线路路由至或路由出有源层。作为另一示例，金属可沿着SOI结构的背侧上的沟道行进，以降低体区和源极之间的以及体区和漏极之间的电容。该结构将降低这些寄生电容的原因是不会在源极或漏极硅上出现金属化，而是保持在沟道或体区上。因此，体区金属线路与源极和/或漏极之间的平板电容被最小化。考虑到器件的速度和性能固有地受到其寄生电容的尺寸的限制，这将产生有利结果。
可参考图5来描述呈现大的沟道接触的本发明的具体实施例。图5图示了SOI结构500的背部表面。制造工艺的平版印刷分辨率以及对齐能力可以以很高的成功率避免设立将被用作体区接触204的接触。如果设计中的几乎所有FET面临其漏极和源极由被用作体区接触204的导电材料短路在一起的情况，则会造成关键的设计失效。在本发明的具体实施例中，可制作沟道材料的更大的着陆焊盘(landing pad)501，从而以足以允许接触沟道同时确保源极或漏极不接触的量来增大沟道502在沟道接触位置处的宽度。从图5可以看出，沉积来形成背侧接触503从而形成体区接触204的金属具有更大的面积以在着陆焊盘501处与沟道502接触，从而降低对制造工艺的限制以及潜在地增大制造产率。可用来设立更大着陆焊盘501的一种方法包括以该形状扩宽多晶硅栅极。可用来设立更大着陆焊盘501的第二种方法包括以该形状改变源极和漏极注入布局，同时保持多晶硅形状不变。虽然这些实施例稍微妨碍了本发明在将体区接触结构与晶体管结构进行去耦方面的优势，但是通常仅仅需要稍微修改，并且与在有源层中的器件本身正下方或邻近沉积体区接触的现有技术相比修改最小。
可参考图6来描述根据本发明的制造集成电路的方法。在步骤600中，SOI结构经过处理以在SOI晶圆的有源层形成有源器件。在该步骤期间在该层中形成的电路包括但不限于诸如CMOS、BiCMOS、SiGe、GaAs、InGaAs、以及GaN之类的技术。电路可包括：诸如二极管和晶体管之类的有源器件，诸如电阻器、电容器和电感器之类的无源器件，以及诸如金属布线和通孔之类的路由电路。可执行各种光刻及化学沉积步骤来形成该电路。步骤600包括有源器件的栅极的形成。步骤600还可包括有源层中接触的形成，这些接触布置在与绝缘层垂直邻接的有源层底部。这些接触可由有源器件的沟道区域中的沟道材料制成。在本发明的具体实施例中，接触可由比沟道材料所形成的沟道的剩下部分宽的沟道材料区域形成。这些更大区域可形成用于后续连接至如上所述的从医院晶圆的背部沉积的接触的着陆焊盘。步骤600还可包括与有源器件分开的接触、以及与有源层底部上形成的分开的接触相连的电路分支的形成。该电路分支随后可连接至有源器件的源极或栅极。如参考上述器件所描述的那样，该电路分支可用来形成可变阻抗路径的一部分或一般导电路径。最后，步骤600还可包括在有源层中形成二极管的步骤。如参考上述器件所描述的那样，该二极管随后被用来形成可变阻抗路径的一部分。该二极管可直接布置在接触的上方，但是它也可放置在有源层的任意其它地方。应该形成二极管以匹配所述器件的必要极性，从而根据本发明适当产生功能。
图6所示的方法的剩下步骤包括背侧处理。这些步骤之前可将临时的操纵晶圆附接至SOI晶圆顶侧。该晶圆可在执行剩余步骤的同时为SOI晶圆提供稳定性。但是，如之前所描述的那样，晶圆的附接并非必需，因为可通过其它方式提供支撑。操纵晶圆可具有通过各种方式接合至SOI晶圆顶部的绝缘层。但是，操纵晶圆也可具有接合至SOI晶圆顶部的由半导体材料或导电材料组成的层。在步骤601中，背侧处理开始于SOI晶圆基板的去除。可单独地和组合地利用机械和化学方式去除基板。例如，机械研磨可用来将基板材料从大约800微米(μm)的原始厚度减薄成大约20μm。如果基板是硅，则可利用KOH或TMAH之类的湿法刻蚀来去除基板材料的最后厚度。还可利用干法等离子体刻蚀来去除基板材料的最后厚度。可以以高精度或高刻蚀速率比去除基板。刻蚀速率比指的是从晶圆背面去除的期望基板材料的速度与本来不应该去除却被去除的其它材料的速度之比。在本发明的具体实施例中，绝缘层是起到刻蚀停止作用的掩埋的氧化物，这是因为对于到掩埋的氧化物为止的所有基板的去除，刻蚀速率比可能极其高。
在本发明的具体实施例中，在步骤601中去除基板材料之后是沉积电介质层或钝化层。在本发明的具体实施例中，在步骤601中之后可以是沉积钝化层以防止SOI结构的离子污染。最后，在本发明的具体实施例中，在步骤601中之后可以是沉积电介质层，电介质层具有通过使导电层与有源器件远离来降低有源层中的有源器件与背侧导电层之间的耦合电容的附加优点。
在步骤602中，从SOI晶圆的背部去除绝缘材料以形成挖掉的绝缘区域。在本发明的具体实施例中，挖掉的绝缘区域位于有源层中的有源器件的体区下方，该挖掉的绝缘区域的第二部分位于有源层的单独部分下方。在本发明的具体实施例中，挖掉的绝缘区域可处于已经在步骤600中制造的已制备接触的下面。在本发明的具体实施例中，有源层的单独部分可以是步骤600中制造的二极管所处的位置。步骤602可包括其它层(包括钝化电介质)的去除。总之，绝缘体去除的图案将允许在步骤603中沉积导电层，这将实现挖掉的绝缘区域的各个部分中任意部分之间的电接触。可利用标准光刻技术以及湿法或干法刻蚀来形成这些图案。
在步骤603中，在SOI晶圆背侧沉积了导电层。可以以图案化的方式提供该层，从而实现挖掉的绝缘区域的隔开的多组部分之间的连接。该导电层将挖掉的绝缘区域的一个部分中的有源器件的体区耦接至挖掉的绝缘区域的单独部分。可利用电子束溅射、电镀、无电镀、选择性化学气相沉积以及各种其它方法来完成该导电材料的沉积。在本发明的具体实施例中，可通过沉积各种其它层以便为SOI结构提供改进的热特性来完成步骤603。在本发明的具体实施例中，可通过以提供阻挡金属层、防反射涂层和各种其它层的顺序沉积各种其它层来完成步骤603。
在本发明的具体实施例中，在SOI结构的背面图案化步骤603中沉积的导电材料。可使导电材料图案化成与有源晶圆制造的有源器件的沟道平行地或垂直地延伸。但是，也可与沟道定向独立地图案化导电材料。在其中导电材料图案化成与沟道平行地延伸的具体实施例中，有源器件所看到的总电容可减小。
在本发明的具体实施例中，步骤603中沉积的导电材料在体区接触处形成了有源层和导电材料之间的热载流子二极管结。在有源器件是NFET由此体区是p型的情况下，可采用各种材料来形成该器件。可使用的金属的非排除性列表包括：铝、钛、金、钯以及钴。如果有源器件是PFET由此体区是n型的，则同样的非排除性列表包括：铝、铂、铬、金以及铪。所得到的结构的优势如上所述。为了降低片电阻，用来产生热载流子二极管的薄层金属可首先沉积，随后放一层低电阻率的金属，例如铝或铜。
在本发明的具体实施例中，步骤603中沉积的导电材料额外地用于组装。导电层可包括焊接凸点、铜柱、或其它类型的封装材料。该组装金属可用来为SOI结构的有源层中的电路提供能量，并且可附加地将信号路由至SOI结构的有源层或从中路由出来。可在用于产生体区接触的导电层已经沉积之后在单独的沉积中沉积该组装材料。
可参考图7来描述根据本发明的SOI结构700。SOI结构700包括导电层201。导电层201包括单个连续的材料区域。导电层201至少部分地与挖掉的绝缘区域202中的绝缘层102共同垂直延伸。导电层201为体区109和源极111提供低阻挡接触。因此，体区109通过单个接触联系至源极111。可利用参考图6描述的方法，采用步骤601中基板去除所应用的具体图案来制造根据这些实施例的结构，从而暴露源极111的底部。
根据图7的本发明具体实施例表现出有利特征。参考图5，这些实施例表现出有利特征是因为，考虑到用于导电层201的单个接触将布置在体区109以及源极111上，背侧接触自然地已经具有更大的着陆焊盘以便使用。此外，在具体实施例中，联系并不占据有源层103中的任何空间，这是因为联系仅仅存在于挖掉的绝缘区域202中。在具体应用中，根据图7的实施例将比上述其它实施例更容易制造。
虽然已经参考本发明的具体实施例主要讨论了本发明的实施例，但是其它变化也是可行的。所描述的系统的各种结构可用来代替或添加至此处所呈现的结构。例如，虽然一般参考硅基板和氧化物绝缘层来讨论器件，但是对于任意形式的绝缘体上半导体晶圆、结构或器件，本发明也可以发挥效力。例如，本发明可与蓝宝石上硅(silicon-on-sapphire)结构组合使用。此外，本发明在电路采用诸如CMOS、二极管、BiCMOS、SiGe、Ga、As、InGaAs、GaN以及任意其它半导体技术或复合半导体技术的形式之类的技术形式时也可发挥效力或工作。而且，本文提到的这些层之间可布置其它层或材料。半导体处理是非常复杂的领域，并且仅仅在明确地需要层来描述本发明以避免混淆时提及这些层。例如，有源层上可沉积钝化层以防止电路与其环境反应。此外，词语“层”的使用(例如在描述有源层或绝缘层时)不排除该层由多种材料组成。例如，除了SOI结构的整个有源层下方的二氧化硅绝缘体之外，有源层中的金属线路下方可能存在玻璃层、或一些其它绝缘体。但是，术语绝缘层可覆盖整个玻璃结构以及二氧化硅绝缘体。
本领域技术人员可以理解的是，前述描述仅仅作为示例，而不是用于限制本发明。公开文本中的没有表示本发明限于需要具体形式的半导体处理或集成电路的系统。根据需要，可通过硬件或软件执行功能。总体上，所显示的示图仅仅用于表示一种可能的结构，多种变化是可行的。虽然公开文本关注本发明在FET器件上的应用，但是本发明还有助于消除SOI架构中的BJT器件的寄生问题。本领域技术人员可以理解的是，与本发明一致的方法和系统适合于在更宽范围的应用中使用，包括与电子器件的特定区域中的电荷载流子的累积相关的任何应用。
虽然已经参考本发明的具体实施例详细描述了说明书，但是本领域技术人员可以理解的是，在得到了上述理解之后，本领域技术人员可以很容易地构想出对这些实施例的替换、改变和等价形式。本领域技术人员可以在不脱离所附权利要求中更具体地阐述的本发明精神和范围的情况下实施对本发明的这些和其它修改和变化。

Claims (21)

1.一种绝缘体上半导体结构，包括:
导电层；
绝缘层，其位于所述导电层上方，并且与挖掉的绝缘区域中的所述导电层部分地共同垂直延伸；
有源层，其位于所述绝缘层上方，并且包括具有体区的有源器件；以及
体区接触，其对所述导电层和所述体区进行物理连接，并且位于所述挖掉的绝缘区域的第一部分中；
其中，所述导电层将所述体区接触耦接至所述有源层中的接触，所述接触位于所述挖掉的绝缘区域的第二部分中，所述第二部分与所述第一部分是隔开的，所述接触电连接到所述有源器件的源极或栅极。
2.根据权利要求1所述的绝缘体上半导体结构，进一步包括：
电路分支，其包括所述体区接触和所述接触；
其中所述电路分支将所述有源器件的所述源极连接至所述有源器件的体区。
3.根据权利要求1所述的绝缘体上半导体结构，进一步包括：
电路分支，其包括所述体区接触和所述接触；
其中所述电路分支将所述有源器件的所述栅极连接至所述有源器件的体区。
4.根据权利要求1所述的绝缘体上半导体结构，进一步包括：
可变阻抗电路分支，其包括所述体区接触和所述接触；
其中所述可变阻抗电路分支配置成在所述有源器件处于导通状态时具有高阻抗，并且所述可变阻抗电路分支配置成在所述有源器件不处于导通状态时具有低阻抗。
5.根据权利要求4所述的绝缘体上半导体结构，所述可变阻抗电路分支进一步包括：
所述有源器件的所述栅极；
其中所述可变阻抗电路分支在所述有源器件处于断开状态时将所述体区锁定至所述栅极上的栅极电压。
6.根据权利要求5所述的绝缘体上半导体结构，其中：
所述体区接触是欧姆的；
所述接触直接位于所述有源器件中形成的二极管下面；以及
所述二极管在所述有源器件处于导通状态时反向偏置。
7.根据权利要求5所述的绝缘体上半导体结构，其中所述体区接触是一个热载流子二极管结。
8.根据权利要求7所述的绝缘体上半导体结构，进一步包括所述有源层上的操纵晶圆。
9.根据权利要求8所述的绝缘体上半导体结构，进一步包括：
在所述体区接触上方形成的着陆焊盘；
其中所述着陆焊盘由所述体区内比所述有源器件的沟道更宽的区域组成。
10.一种从绝缘体上半导体有源器件的沟道去除不期望的累积的多数载流子的方法，包括步骤：
将所述不期望的累积的多数载流子从所述沟道引导至所述有源器件的体区接触，所述体区接触对导电层和所述有源器件的体区进行物理连接；
通过所述导电层中的电路分支引导所述不期望的累积的多数载流子，所述导电层位于绝缘层下方并且与挖掉的绝缘区域中的所述绝缘层部分地共同垂直延伸；
其中，所述电路分支将所述体区接触耦接至接触，所述体区接触位于所述挖掉的绝缘区域的第一部分中，所述接触位于所述挖掉的绝缘区域的第二隔开的部分中，所述接触电连接到所述有源器件的源极或栅极。
11.根据权利要求10所述的方法，进一步包括步骤：
在所述有源器件处于导通状态时增大所述电路分支的阻抗；以及
在所述有源器件不处于导通状态时降低所述电路分支的阻抗。
12.根据权利要求11所述的方法，进一步包括步骤：提供二极管连接将所述体区接触锁定至所述有源器件的所述栅极。
13.根据权利要求12所述的方法，其中通过所述导电层和所述体区的界面形成热载流子二极管。
14.一种制造集成电路的方法，所述方法包括步骤：
在绝缘体上半导体晶圆的有源层中形成有源器件；
从沉积在所述绝缘体上半导体晶圆的背侧上的基板层区域基板材料；
从所述绝缘体上半导体晶圆的背侧去除绝缘材料以形成挖掉的绝缘区域；以及
在所述挖掉的绝缘区域上沉积导电层；
其中所述沉积步骤使所述导电层与所述挖掉的绝缘区域的第一部分中的有源器件的体区物理接触，并且将所述体区耦接至一个接触，所述接触位于所述挖掉的绝缘区域的第二隔开的部分中，所述接触电连接到所述有源器件的源极或栅极。
15.根据权利要求14所述的方法，进一步包括步骤：形成从所述接触到所述有源器件的所述源极的电路分支。
16.根据权利要求14所述的方法，其中所述沉积步骤形成了可变阻抗电路分支的一个分段，所述可变阻抗电路分支配置成在所述有源器件处于导通状态时具有高阻抗，并且在所述有源器件不处于导通状态时具有低阻抗。
17.根据权利要求14所述的方法，进一步包括步骤：形成所述有源器件的所述栅极以及从所述栅极到所述接触的可变阻抗电路的第二分段。
18.根据权利要求14所述的方法，进一步包括步骤：在所述有源器件中形成直接位于所述接触上方的二极管，所述二极管在所述有源器件处于导通状态时反向偏置。
19.根据权利要求18所述的方法，其中所述沉积步骤形成了所述有源层和所述导电层之间的热载流子二极管。
20.根据权利要求19所述的方法，其中所述在所述有源层中形成所述有源器件还包括在所述体区接触上方形成着陆焊盘，所述着陆焊盘由所述体区内比所述有源器件的沟道更宽的区域组成。
21.一种绝缘体上半导体结构，包括:
导电层；
绝缘层，其与挖掉的绝缘区域中的所述导电层至少部分地共同垂直延伸；
有源层，其位于所述绝缘层上方，并且包括具有体区的有源器件；以及
体区接触，其对所述导电层和所述体区进行物理连接；
其中，所述导电层将所述体区接触耦接至所述有源层中的接触，所述接触电连接到所述有源器件的源极或栅极。
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